1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 30 #include "atom.h" 31 32 #include "dc_bios_types.h" 33 #include "include/gpio_service_interface.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/bios_parser_interface.h" 36 #include "include/logger_interface.h" 37 38 #include "command_table.h" 39 #include "bios_parser_helper.h" 40 #include "command_table_helper.h" 41 #include "bios_parser.h" 42 #include "bios_parser_types_internal.h" 43 #include "bios_parser_interface.h" 44 45 #include "bios_parser_common.h" 46 47 #define THREE_PERCENT_OF_10000 300 48 49 #define LAST_RECORD_TYPE 0xff 50 51 #define DC_LOGGER \ 52 bp->base.ctx->logger 53 54 #define DATA_TABLES(table) (bp->master_data_tbl->ListOfDataTables.table) 55 56 static void get_atom_data_table_revision( 57 ATOM_COMMON_TABLE_HEADER *atom_data_tbl, 58 struct atom_data_revision *tbl_revision); 59 static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object, 60 uint16_t **id_list); 61 static ATOM_OBJECT *get_bios_object(struct bios_parser *bp, 62 struct graphics_object_id id); 63 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 64 ATOM_I2C_RECORD *record, 65 struct graphics_object_i2c_info *info); 66 static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp, 67 ATOM_OBJECT *object); 68 static struct device_id device_type_from_device_id(uint16_t device_id); 69 static uint32_t signal_to_ss_id(enum as_signal_type signal); 70 static uint32_t get_support_mask_for_device_id( 71 enum dal_device_type device_type, 72 uint32_t enum_id); 73 static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record( 74 struct bios_parser *bp, 75 ATOM_OBJECT *object); 76 77 #define BIOS_IMAGE_SIZE_OFFSET 2 78 #define BIOS_IMAGE_SIZE_UNIT 512 79 80 /*****************************************************************************/ 81 static bool bios_parser_construct( 82 struct bios_parser *bp, 83 struct bp_init_data *init, 84 enum dce_version dce_version); 85 86 static uint8_t bios_parser_get_connectors_number( 87 struct dc_bios *dcb); 88 89 static enum bp_result bios_parser_get_embedded_panel_info( 90 struct dc_bios *dcb, 91 struct embedded_panel_info *info); 92 93 /*****************************************************************************/ 94 95 struct dc_bios *bios_parser_create( 96 struct bp_init_data *init, 97 enum dce_version dce_version) 98 { 99 struct bios_parser *bp; 100 101 bp = kzalloc_obj(struct bios_parser); 102 if (!bp) 103 return NULL; 104 105 if (bios_parser_construct(bp, init, dce_version)) 106 return &bp->base; 107 108 kfree(bp); 109 BREAK_TO_DEBUGGER(); 110 return NULL; 111 } 112 113 static void bios_parser_destruct(struct bios_parser *bp) 114 { 115 kfree(bp->base.bios_local_image); 116 kfree(bp->base.integrated_info); 117 } 118 119 static void bios_parser_destroy(struct dc_bios **dcb) 120 { 121 struct bios_parser *bp = BP_FROM_DCB(*dcb); 122 123 if (!bp) { 124 BREAK_TO_DEBUGGER(); 125 return; 126 } 127 128 bios_parser_destruct(bp); 129 130 kfree(bp); 131 *dcb = NULL; 132 } 133 134 static uint8_t get_number_of_objects(struct bios_parser *bp, uint32_t offset) 135 { 136 ATOM_OBJECT_TABLE *table; 137 138 uint32_t object_table_offset = bp->object_info_tbl_offset + offset; 139 140 table = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base, 141 object_table_offset, 142 struct_size(table, asObjects, 1))); 143 144 if (!table) 145 return 0; 146 else 147 return table->ucNumberOfObjects; 148 } 149 150 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb) 151 { 152 struct bios_parser *bp = BP_FROM_DCB(dcb); 153 154 return get_number_of_objects(bp, 155 le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset)); 156 } 157 158 static struct graphics_object_id bios_parser_get_connector_id( 159 struct dc_bios *dcb, 160 uint8_t i) 161 { 162 struct bios_parser *bp = BP_FROM_DCB(dcb); 163 struct graphics_object_id object_id = dal_graphics_object_id_init( 164 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN); 165 uint16_t id; 166 167 uint32_t connector_table_offset = bp->object_info_tbl_offset 168 + le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset); 169 170 ATOM_OBJECT_TABLE *tbl = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base, 171 connector_table_offset, 172 struct_size(tbl, asObjects, 1))); 173 174 if (!tbl) { 175 dm_error("Can't get connector table from atom bios.\n"); 176 return object_id; 177 } 178 179 if (tbl->ucNumberOfObjects <= i) 180 return object_id; 181 182 id = le16_to_cpu(tbl->asObjects[i].usObjectID); 183 object_id = object_id_from_bios_object_id(id); 184 return object_id; 185 } 186 187 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb, 188 struct graphics_object_id object_id, uint32_t index, 189 struct graphics_object_id *src_object_id) 190 { 191 uint32_t number; 192 uint16_t *id; 193 ATOM_OBJECT *object; 194 struct bios_parser *bp = BP_FROM_DCB(dcb); 195 196 if (!src_object_id) 197 return BP_RESULT_BADINPUT; 198 199 object = get_bios_object(bp, object_id); 200 201 if (!object) { 202 BREAK_TO_DEBUGGER(); /* Invalid object id */ 203 return BP_RESULT_BADINPUT; 204 } 205 206 number = get_src_obj_list(bp, object, &id); 207 208 if (number <= index) 209 return BP_RESULT_BADINPUT; 210 211 *src_object_id = object_id_from_bios_object_id(id[index]); 212 213 return BP_RESULT_OK; 214 } 215 216 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb, 217 struct graphics_object_id id, 218 struct graphics_object_i2c_info *info) 219 { 220 uint32_t offset; 221 ATOM_OBJECT *object; 222 ATOM_COMMON_RECORD_HEADER *header; 223 ATOM_I2C_RECORD *record; 224 struct bios_parser *bp = BP_FROM_DCB(dcb); 225 226 if (!info) 227 return BP_RESULT_BADINPUT; 228 229 object = get_bios_object(bp, id); 230 231 if (!object) 232 return BP_RESULT_BADINPUT; 233 234 offset = le16_to_cpu(object->usRecordOffset) 235 + bp->object_info_tbl_offset; 236 237 for (;;) { 238 header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset); 239 240 if (!header) 241 return BP_RESULT_BADBIOSTABLE; 242 243 if (LAST_RECORD_TYPE == header->ucRecordType || 244 !header->ucRecordSize) 245 break; 246 247 if (ATOM_I2C_RECORD_TYPE == header->ucRecordType 248 && sizeof(ATOM_I2C_RECORD) <= header->ucRecordSize) { 249 /* get the I2C info */ 250 record = (ATOM_I2C_RECORD *) header; 251 252 if (get_gpio_i2c_info(bp, record, info) == BP_RESULT_OK) 253 return BP_RESULT_OK; 254 } 255 256 offset += header->ucRecordSize; 257 } 258 259 return BP_RESULT_NORECORD; 260 } 261 262 static enum bp_result bios_parser_get_hpd_info(struct dc_bios *dcb, 263 struct graphics_object_id id, 264 struct graphics_object_hpd_info *info) 265 { 266 struct bios_parser *bp = BP_FROM_DCB(dcb); 267 ATOM_OBJECT *object; 268 ATOM_HPD_INT_RECORD *record = NULL; 269 270 if (!info) 271 return BP_RESULT_BADINPUT; 272 273 object = get_bios_object(bp, id); 274 275 if (!object) 276 return BP_RESULT_BADINPUT; 277 278 record = get_hpd_record(bp, object); 279 280 if (record != NULL) { 281 info->hpd_int_gpio_uid = record->ucHPDIntGPIOID; 282 info->hpd_active = record->ucPlugged_PinState; 283 return BP_RESULT_OK; 284 } 285 286 return BP_RESULT_NORECORD; 287 } 288 289 static enum bp_result bios_parser_get_device_tag_record( 290 struct bios_parser *bp, 291 ATOM_OBJECT *object, 292 ATOM_CONNECTOR_DEVICE_TAG_RECORD **record) 293 { 294 ATOM_COMMON_RECORD_HEADER *header; 295 uint32_t offset; 296 297 offset = le16_to_cpu(object->usRecordOffset) 298 + bp->object_info_tbl_offset; 299 300 for (;;) { 301 header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset); 302 303 if (!header) 304 return BP_RESULT_BADBIOSTABLE; 305 306 offset += header->ucRecordSize; 307 308 if (LAST_RECORD_TYPE == header->ucRecordType || 309 !header->ucRecordSize) 310 break; 311 312 if (ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE != 313 header->ucRecordType) 314 continue; 315 316 if (sizeof(ATOM_CONNECTOR_DEVICE_TAG) > header->ucRecordSize) 317 continue; 318 319 *record = (ATOM_CONNECTOR_DEVICE_TAG_RECORD *) header; 320 return BP_RESULT_OK; 321 } 322 323 return BP_RESULT_NORECORD; 324 } 325 326 static enum bp_result bios_parser_get_device_tag( 327 struct dc_bios *dcb, 328 struct graphics_object_id connector_object_id, 329 uint32_t device_tag_index, 330 struct connector_device_tag_info *info) 331 { 332 struct bios_parser *bp = BP_FROM_DCB(dcb); 333 ATOM_OBJECT *object; 334 ATOM_CONNECTOR_DEVICE_TAG_RECORD *record = NULL; 335 ATOM_CONNECTOR_DEVICE_TAG *device_tag; 336 337 if (!info) 338 return BP_RESULT_BADINPUT; 339 340 /* getBiosObject will return MXM object */ 341 object = get_bios_object(bp, connector_object_id); 342 343 if (!object) { 344 BREAK_TO_DEBUGGER(); /* Invalid object id */ 345 return BP_RESULT_BADINPUT; 346 } 347 348 if (bios_parser_get_device_tag_record(bp, object, &record) 349 != BP_RESULT_OK) 350 return BP_RESULT_NORECORD; 351 352 if (device_tag_index >= record->ucNumberOfDevice) 353 return BP_RESULT_NORECORD; 354 355 device_tag = &record->asDeviceTag[device_tag_index]; 356 357 info->acpi_device = le32_to_cpu(device_tag->ulACPIDeviceEnum); 358 info->dev_id = 359 device_type_from_device_id(le16_to_cpu(device_tag->usDeviceID)); 360 361 return BP_RESULT_OK; 362 } 363 364 static enum bp_result get_firmware_info_v1_4( 365 struct bios_parser *bp, 366 struct dc_firmware_info *info); 367 static enum bp_result get_firmware_info_v2_1( 368 struct bios_parser *bp, 369 struct dc_firmware_info *info); 370 static enum bp_result get_firmware_info_v2_2( 371 struct bios_parser *bp, 372 struct dc_firmware_info *info); 373 374 static enum bp_result bios_parser_get_firmware_info( 375 struct dc_bios *dcb, 376 struct dc_firmware_info *info) 377 { 378 struct bios_parser *bp = BP_FROM_DCB(dcb); 379 enum bp_result result = BP_RESULT_BADBIOSTABLE; 380 ATOM_COMMON_TABLE_HEADER *header; 381 struct atom_data_revision revision; 382 383 if (info && DATA_TABLES(FirmwareInfo)) { 384 header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, 385 DATA_TABLES(FirmwareInfo)); 386 get_atom_data_table_revision(header, &revision); 387 switch (revision.major) { 388 case 1: 389 switch (revision.minor) { 390 case 4: 391 result = get_firmware_info_v1_4(bp, info); 392 break; 393 default: 394 break; 395 } 396 break; 397 398 case 2: 399 switch (revision.minor) { 400 case 1: 401 result = get_firmware_info_v2_1(bp, info); 402 break; 403 case 2: 404 result = get_firmware_info_v2_2(bp, info); 405 break; 406 default: 407 break; 408 } 409 break; 410 default: 411 break; 412 } 413 } 414 415 return result; 416 } 417 418 static enum bp_result get_firmware_info_v1_4( 419 struct bios_parser *bp, 420 struct dc_firmware_info *info) 421 { 422 ATOM_FIRMWARE_INFO_V1_4 *firmware_info = 423 GET_IMAGE(ATOM_FIRMWARE_INFO_V1_4, 424 DATA_TABLES(FirmwareInfo)); 425 426 if (!info) 427 return BP_RESULT_BADINPUT; 428 429 if (!firmware_info) 430 return BP_RESULT_BADBIOSTABLE; 431 432 memset(info, 0, sizeof(*info)); 433 434 /* Pixel clock pll information. We need to convert from 10KHz units into 435 * KHz units */ 436 info->pll_info.crystal_frequency = 437 le16_to_cpu(firmware_info->usReferenceClock) * 10; 438 info->pll_info.min_input_pxl_clk_pll_frequency = 439 le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10; 440 info->pll_info.max_input_pxl_clk_pll_frequency = 441 le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10; 442 info->pll_info.min_output_pxl_clk_pll_frequency = 443 le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10; 444 info->pll_info.max_output_pxl_clk_pll_frequency = 445 le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10; 446 info->max_pixel_clock = le16_to_cpu(firmware_info->usMaxPixelClock) * 10; 447 448 if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support) 449 /* Since there is no information on the SS, report conservative 450 * value 3% for bandwidth calculation */ 451 /* unit of 0.01% */ 452 info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000; 453 454 if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support) 455 /* Since there is no information on the SS,report conservative 456 * value 3% for bandwidth calculation */ 457 /* unit of 0.01% */ 458 info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000; 459 460 return BP_RESULT_OK; 461 } 462 463 static enum bp_result get_ss_info_v3_1( 464 struct bios_parser *bp, 465 uint32_t id, 466 uint32_t index, 467 struct spread_spectrum_info *ss_info); 468 469 static enum bp_result get_firmware_info_v2_1( 470 struct bios_parser *bp, 471 struct dc_firmware_info *info) 472 { 473 ATOM_FIRMWARE_INFO_V2_1 *firmwareInfo = 474 GET_IMAGE(ATOM_FIRMWARE_INFO_V2_1, DATA_TABLES(FirmwareInfo)); 475 struct spread_spectrum_info internalSS; 476 uint32_t index; 477 478 if (!info) 479 return BP_RESULT_BADINPUT; 480 481 if (!firmwareInfo) 482 return BP_RESULT_BADBIOSTABLE; 483 484 memset(info, 0, sizeof(*info)); 485 486 /* Pixel clock pll information. We need to convert from 10KHz units into 487 * KHz units */ 488 info->pll_info.crystal_frequency = 489 le16_to_cpu(firmwareInfo->usCoreReferenceClock) * 10; 490 info->pll_info.min_input_pxl_clk_pll_frequency = 491 le16_to_cpu(firmwareInfo->usMinPixelClockPLL_Input) * 10; 492 info->pll_info.max_input_pxl_clk_pll_frequency = 493 le16_to_cpu(firmwareInfo->usMaxPixelClockPLL_Input) * 10; 494 info->pll_info.min_output_pxl_clk_pll_frequency = 495 le32_to_cpu(firmwareInfo->ulMinPixelClockPLL_Output) * 10; 496 info->pll_info.max_output_pxl_clk_pll_frequency = 497 le32_to_cpu(firmwareInfo->ulMaxPixelClockPLL_Output) * 10; 498 info->default_display_engine_pll_frequency = 499 le32_to_cpu(firmwareInfo->ulDefaultDispEngineClkFreq) * 10; 500 info->external_clock_source_frequency_for_dp = 501 le16_to_cpu(firmwareInfo->usUniphyDPModeExtClkFreq) * 10; 502 info->min_allowed_bl_level = firmwareInfo->ucMinAllowedBL_Level; 503 info->max_pixel_clock = le16_to_cpu(firmwareInfo->usMaxPixelClock) * 10; 504 505 /* There should be only one entry in the SS info table for Memory Clock 506 */ 507 index = 0; 508 if (firmwareInfo->usFirmwareCapability.sbfAccess.MemoryClockSS_Support) 509 /* Since there is no information for external SS, report 510 * conservative value 3% for bandwidth calculation */ 511 /* unit of 0.01% */ 512 info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000; 513 else if (get_ss_info_v3_1(bp, 514 ASIC_INTERNAL_MEMORY_SS, index, &internalSS) == BP_RESULT_OK) { 515 if (internalSS.spread_spectrum_percentage) { 516 info->feature.memory_clk_ss_percentage = 517 internalSS.spread_spectrum_percentage; 518 if (internalSS.type.CENTER_MODE) { 519 /* if it is centermode, the exact SS Percentage 520 * will be round up of half of the percentage 521 * reported in the SS table */ 522 ++info->feature.memory_clk_ss_percentage; 523 info->feature.memory_clk_ss_percentage /= 2; 524 } 525 } 526 } 527 528 /* There should be only one entry in the SS info table for Engine Clock 529 */ 530 index = 1; 531 if (firmwareInfo->usFirmwareCapability.sbfAccess.EngineClockSS_Support) 532 /* Since there is no information for external SS, report 533 * conservative value 3% for bandwidth calculation */ 534 /* unit of 0.01% */ 535 info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000; 536 else if (get_ss_info_v3_1(bp, 537 ASIC_INTERNAL_ENGINE_SS, index, &internalSS) == BP_RESULT_OK) { 538 if (internalSS.spread_spectrum_percentage) { 539 info->feature.engine_clk_ss_percentage = 540 internalSS.spread_spectrum_percentage; 541 if (internalSS.type.CENTER_MODE) { 542 /* if it is centermode, the exact SS Percentage 543 * will be round up of half of the percentage 544 * reported in the SS table */ 545 ++info->feature.engine_clk_ss_percentage; 546 info->feature.engine_clk_ss_percentage /= 2; 547 } 548 } 549 } 550 551 return BP_RESULT_OK; 552 } 553 554 static enum bp_result get_firmware_info_v2_2( 555 struct bios_parser *bp, 556 struct dc_firmware_info *info) 557 { 558 ATOM_FIRMWARE_INFO_V2_2 *firmware_info; 559 struct spread_spectrum_info internal_ss; 560 uint32_t index; 561 562 if (!info) 563 return BP_RESULT_BADINPUT; 564 565 firmware_info = GET_IMAGE(ATOM_FIRMWARE_INFO_V2_2, 566 DATA_TABLES(FirmwareInfo)); 567 568 if (!firmware_info) 569 return BP_RESULT_BADBIOSTABLE; 570 571 memset(info, 0, sizeof(*info)); 572 573 /* Pixel clock pll information. We need to convert from 10KHz units into 574 * KHz units */ 575 info->pll_info.crystal_frequency = 576 le16_to_cpu(firmware_info->usCoreReferenceClock) * 10; 577 info->pll_info.min_input_pxl_clk_pll_frequency = 578 le16_to_cpu(firmware_info->usMinPixelClockPLL_Input) * 10; 579 info->pll_info.max_input_pxl_clk_pll_frequency = 580 le16_to_cpu(firmware_info->usMaxPixelClockPLL_Input) * 10; 581 info->pll_info.min_output_pxl_clk_pll_frequency = 582 le32_to_cpu(firmware_info->ulMinPixelClockPLL_Output) * 10; 583 info->pll_info.max_output_pxl_clk_pll_frequency = 584 le32_to_cpu(firmware_info->ulMaxPixelClockPLL_Output) * 10; 585 info->default_display_engine_pll_frequency = 586 le32_to_cpu(firmware_info->ulDefaultDispEngineClkFreq) * 10; 587 info->external_clock_source_frequency_for_dp = 588 le16_to_cpu(firmware_info->usUniphyDPModeExtClkFreq) * 10; 589 590 /* There should be only one entry in the SS info table for Memory Clock 591 */ 592 index = 0; 593 if (firmware_info->usFirmwareCapability.sbfAccess.MemoryClockSS_Support) 594 /* Since there is no information for external SS, report 595 * conservative value 3% for bandwidth calculation */ 596 /* unit of 0.01% */ 597 info->feature.memory_clk_ss_percentage = THREE_PERCENT_OF_10000; 598 else if (get_ss_info_v3_1(bp, 599 ASIC_INTERNAL_MEMORY_SS, index, &internal_ss) == BP_RESULT_OK) { 600 if (internal_ss.spread_spectrum_percentage) { 601 info->feature.memory_clk_ss_percentage = 602 internal_ss.spread_spectrum_percentage; 603 if (internal_ss.type.CENTER_MODE) { 604 /* if it is centermode, the exact SS Percentage 605 * will be round up of half of the percentage 606 * reported in the SS table */ 607 ++info->feature.memory_clk_ss_percentage; 608 info->feature.memory_clk_ss_percentage /= 2; 609 } 610 } 611 } 612 613 /* There should be only one entry in the SS info table for Engine Clock 614 */ 615 index = 1; 616 if (firmware_info->usFirmwareCapability.sbfAccess.EngineClockSS_Support) 617 /* Since there is no information for external SS, report 618 * conservative value 3% for bandwidth calculation */ 619 /* unit of 0.01% */ 620 info->feature.engine_clk_ss_percentage = THREE_PERCENT_OF_10000; 621 else if (get_ss_info_v3_1(bp, 622 ASIC_INTERNAL_ENGINE_SS, index, &internal_ss) == BP_RESULT_OK) { 623 if (internal_ss.spread_spectrum_percentage) { 624 info->feature.engine_clk_ss_percentage = 625 internal_ss.spread_spectrum_percentage; 626 if (internal_ss.type.CENTER_MODE) { 627 /* if it is centermode, the exact SS Percentage 628 * will be round up of half of the percentage 629 * reported in the SS table */ 630 ++info->feature.engine_clk_ss_percentage; 631 info->feature.engine_clk_ss_percentage /= 2; 632 } 633 } 634 } 635 636 /* Remote Display */ 637 info->remote_display_config = firmware_info->ucRemoteDisplayConfig; 638 639 /* Is allowed minimum BL level */ 640 info->min_allowed_bl_level = firmware_info->ucMinAllowedBL_Level; 641 /* Used starting from CI */ 642 info->smu_gpu_pll_output_freq = 643 (uint32_t) (le32_to_cpu(firmware_info->ulGPUPLL_OutputFreq) * 10); 644 645 return BP_RESULT_OK; 646 } 647 648 static enum bp_result get_ss_info_v3_1( 649 struct bios_parser *bp, 650 uint32_t id, 651 uint32_t index, 652 struct spread_spectrum_info *ss_info) 653 { 654 ATOM_ASIC_INTERNAL_SS_INFO_V3 *ss_table_header_include; 655 ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl; 656 uint32_t table_size; 657 uint32_t i; 658 uint32_t table_index = 0; 659 660 if (!ss_info) 661 return BP_RESULT_BADINPUT; 662 663 if (!DATA_TABLES(ASIC_InternalSS_Info)) 664 return BP_RESULT_UNSUPPORTED; 665 666 ss_table_header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) bios_get_image(&bp->base, 667 DATA_TABLES(ASIC_InternalSS_Info), 668 struct_size(ss_table_header_include, asSpreadSpectrum, 1))); 669 if (!ss_table_header_include) 670 return BP_RESULT_UNSUPPORTED; 671 672 table_size = 673 (le16_to_cpu(ss_table_header_include->sHeader.usStructureSize) 674 - sizeof(ATOM_COMMON_TABLE_HEADER)) 675 / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 676 677 tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *) 678 &ss_table_header_include->asSpreadSpectrum[0]; 679 680 memset(ss_info, 0, sizeof(struct spread_spectrum_info)); 681 682 for (i = 0; i < table_size; i++) { 683 if (tbl[i].ucClockIndication != (uint8_t) id) 684 continue; 685 686 if (table_index != index) { 687 table_index++; 688 continue; 689 } 690 /* VBIOS introduced new defines for Version 3, same values as 691 * before, so now use these new ones for Version 3. 692 * Shouldn't affect field VBIOS's V3 as define values are still 693 * same. 694 * #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 695 * #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 696 697 * Old VBIOS defines: 698 * #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 699 * #define ATOM_EXTERNAL_SS_MASK 0x00000002 700 */ 701 702 if (SS_MODE_V3_EXTERNAL_SS_MASK & tbl[i].ucSpreadSpectrumMode) 703 ss_info->type.EXTERNAL = true; 704 705 if (SS_MODE_V3_CENTRE_SPREAD_MASK & tbl[i].ucSpreadSpectrumMode) 706 ss_info->type.CENTER_MODE = true; 707 708 /* Older VBIOS (in field) always provides SS percentage in 0.01% 709 * units set Divider to 100 */ 710 ss_info->spread_percentage_divider = 100; 711 712 /* #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 */ 713 if (SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 714 & tbl[i].ucSpreadSpectrumMode) 715 ss_info->spread_percentage_divider = 1000; 716 717 ss_info->type.STEP_AND_DELAY_INFO = false; 718 /* convert [10KHz] into [KHz] */ 719 ss_info->target_clock_range = 720 le32_to_cpu(tbl[i].ulTargetClockRange) * 10; 721 ss_info->spread_spectrum_percentage = 722 (uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage); 723 ss_info->spread_spectrum_range = 724 (uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10); 725 726 return BP_RESULT_OK; 727 } 728 return BP_RESULT_NORECORD; 729 } 730 731 static enum bp_result bios_parser_transmitter_control( 732 struct dc_bios *dcb, 733 struct bp_transmitter_control *cntl) 734 { 735 struct bios_parser *bp = BP_FROM_DCB(dcb); 736 737 if (!bp->cmd_tbl.transmitter_control) 738 return BP_RESULT_FAILURE; 739 740 return bp->cmd_tbl.transmitter_control(bp, cntl); 741 } 742 743 static enum bp_result bios_parser_select_crtc_source( 744 struct dc_bios *dcb, 745 struct bp_crtc_source_select *bp_params) 746 { 747 struct bios_parser *bp = BP_FROM_DCB(dcb); 748 749 if (!bp->cmd_tbl.select_crtc_source) 750 return BP_RESULT_FAILURE; 751 752 return bp->cmd_tbl.select_crtc_source(bp, bp_params); 753 } 754 755 static enum bp_result bios_parser_encoder_control( 756 struct dc_bios *dcb, 757 struct bp_encoder_control *cntl) 758 { 759 struct bios_parser *bp = BP_FROM_DCB(dcb); 760 761 if (cntl->engine_id == ENGINE_ID_DACA) { 762 if (!bp->cmd_tbl.dac1_encoder_control) 763 return BP_RESULT_FAILURE; 764 765 return bp->cmd_tbl.dac1_encoder_control( 766 bp, cntl->action, 767 cntl->pixel_clock, ATOM_DAC1_PS2); 768 } else if (cntl->engine_id == ENGINE_ID_DACB) { 769 if (!bp->cmd_tbl.dac2_encoder_control) 770 return BP_RESULT_FAILURE; 771 772 return bp->cmd_tbl.dac2_encoder_control( 773 bp, cntl->action, 774 cntl->pixel_clock, ATOM_DAC1_PS2); 775 } 776 777 if (!bp->cmd_tbl.dig_encoder_control) 778 return BP_RESULT_FAILURE; 779 780 return bp->cmd_tbl.dig_encoder_control(bp, cntl); 781 } 782 783 static enum bp_result bios_parser_external_encoder_control( 784 struct dc_bios *dcb, 785 struct bp_external_encoder_control *cntl) 786 { 787 struct bios_parser *bp = BP_FROM_DCB(dcb); 788 789 if (!bp->cmd_tbl.external_encoder_control) 790 return BP_RESULT_UNSUPPORTED; 791 792 return bp->cmd_tbl.external_encoder_control(bp, cntl); 793 } 794 795 static enum bp_result bios_parser_dac_load_detection( 796 struct dc_bios *dcb, 797 enum engine_id engine_id, 798 struct graphics_object_id ext_enc_id) 799 { 800 struct bios_parser *bp = BP_FROM_DCB(dcb); 801 struct dc_context *ctx = dcb->ctx; 802 struct bp_load_detection_parameters bp_params = {0}; 803 struct bp_external_encoder_control ext_cntl = {0}; 804 enum bp_result bp_result = BP_RESULT_UNSUPPORTED; 805 uint32_t bios_0_scratch; 806 uint32_t device_id_mask = 0; 807 808 bp_params.device_id = get_support_mask_for_device_id( 809 DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); 810 811 if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) 812 device_id_mask = ATOM_S0_CRT1_MASK; 813 else if (bp_params.device_id == ATOM_DEVICE_CRT2_SUPPORT) 814 device_id_mask = ATOM_S0_CRT2_MASK; 815 else 816 return BP_RESULT_UNSUPPORTED; 817 818 /* BIOS will write the detected devices to BIOS_SCRATCH_0, clear corresponding bit */ 819 bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); 820 bios_0_scratch &= ~device_id_mask; 821 dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); 822 823 if (engine_id == ENGINE_ID_DACA || engine_id == ENGINE_ID_DACB) { 824 if (!bp->cmd_tbl.dac_load_detection) 825 return BP_RESULT_UNSUPPORTED; 826 827 bp_params.engine_id = engine_id; 828 bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); 829 } else if (ext_enc_id.id) { 830 if (!bp->cmd_tbl.external_encoder_control) 831 return BP_RESULT_UNSUPPORTED; 832 833 ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT; 834 ext_cntl.encoder_id = ext_enc_id; 835 bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl); 836 } 837 838 if (bp_result != BP_RESULT_OK) 839 return bp_result; 840 841 bios_0_scratch = dm_read_reg(ctx, bp->base.regs->BIOS_SCRATCH_0); 842 843 if (bios_0_scratch & device_id_mask) 844 return BP_RESULT_OK; 845 846 return BP_RESULT_FAILURE; 847 } 848 849 static enum bp_result bios_parser_adjust_pixel_clock( 850 struct dc_bios *dcb, 851 struct bp_adjust_pixel_clock_parameters *bp_params) 852 { 853 struct bios_parser *bp = BP_FROM_DCB(dcb); 854 855 if (!bp->cmd_tbl.adjust_display_pll) 856 return BP_RESULT_FAILURE; 857 858 return bp->cmd_tbl.adjust_display_pll(bp, bp_params); 859 } 860 861 static enum bp_result bios_parser_set_pixel_clock( 862 struct dc_bios *dcb, 863 struct bp_pixel_clock_parameters *bp_params) 864 { 865 struct bios_parser *bp = BP_FROM_DCB(dcb); 866 867 if (!bp->cmd_tbl.set_pixel_clock) 868 return BP_RESULT_FAILURE; 869 870 return bp->cmd_tbl.set_pixel_clock(bp, bp_params); 871 } 872 873 static enum bp_result bios_parser_set_dce_clock( 874 struct dc_bios *dcb, 875 struct bp_set_dce_clock_parameters *bp_params) 876 { 877 struct bios_parser *bp = BP_FROM_DCB(dcb); 878 879 if (!bp->cmd_tbl.set_dce_clock) 880 return BP_RESULT_FAILURE; 881 882 return bp->cmd_tbl.set_dce_clock(bp, bp_params); 883 } 884 885 static enum bp_result bios_parser_enable_spread_spectrum_on_ppll( 886 struct dc_bios *dcb, 887 struct bp_spread_spectrum_parameters *bp_params, 888 bool enable) 889 { 890 struct bios_parser *bp = BP_FROM_DCB(dcb); 891 892 if (!bp->cmd_tbl.enable_spread_spectrum_on_ppll) 893 return BP_RESULT_FAILURE; 894 895 return bp->cmd_tbl.enable_spread_spectrum_on_ppll( 896 bp, bp_params, enable); 897 898 } 899 900 static enum bp_result bios_parser_program_crtc_timing( 901 struct dc_bios *dcb, 902 struct bp_hw_crtc_timing_parameters *bp_params) 903 { 904 struct bios_parser *bp = BP_FROM_DCB(dcb); 905 906 if (!bp->cmd_tbl.set_crtc_timing) 907 return BP_RESULT_FAILURE; 908 909 return bp->cmd_tbl.set_crtc_timing(bp, bp_params); 910 } 911 912 static enum bp_result bios_parser_program_display_engine_pll( 913 struct dc_bios *dcb, 914 struct bp_pixel_clock_parameters *bp_params) 915 { 916 struct bios_parser *bp = BP_FROM_DCB(dcb); 917 918 if (!bp->cmd_tbl.program_clock) 919 return BP_RESULT_FAILURE; 920 921 return bp->cmd_tbl.program_clock(bp, bp_params); 922 923 } 924 925 926 static enum bp_result bios_parser_enable_crtc( 927 struct dc_bios *dcb, 928 enum controller_id id, 929 bool enable) 930 { 931 struct bios_parser *bp = BP_FROM_DCB(dcb); 932 933 if (!bp->cmd_tbl.enable_crtc) 934 return BP_RESULT_FAILURE; 935 936 return bp->cmd_tbl.enable_crtc(bp, id, enable); 937 } 938 939 static enum bp_result bios_parser_enable_disp_power_gating( 940 struct dc_bios *dcb, 941 enum controller_id controller_id, 942 enum bp_pipe_control_action action) 943 { 944 struct bios_parser *bp = BP_FROM_DCB(dcb); 945 946 if (!bp->cmd_tbl.enable_disp_power_gating) 947 return BP_RESULT_FAILURE; 948 949 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id, 950 action); 951 } 952 953 static bool bios_parser_is_device_id_supported( 954 struct dc_bios *dcb, 955 struct device_id id) 956 { 957 struct bios_parser *bp = BP_FROM_DCB(dcb); 958 959 uint32_t mask = get_support_mask_for_device_id(id.device_type, id.enum_id); 960 961 return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0; 962 } 963 964 static ATOM_HPD_INT_RECORD *get_hpd_record(struct bios_parser *bp, 965 ATOM_OBJECT *object) 966 { 967 ATOM_COMMON_RECORD_HEADER *header; 968 uint32_t offset; 969 970 if (!object) { 971 BREAK_TO_DEBUGGER(); /* Invalid object */ 972 return NULL; 973 } 974 975 offset = le16_to_cpu(object->usRecordOffset) 976 + bp->object_info_tbl_offset; 977 978 for (;;) { 979 header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset); 980 981 if (!header) 982 return NULL; 983 984 if (LAST_RECORD_TYPE == header->ucRecordType || 985 !header->ucRecordSize) 986 break; 987 988 if (ATOM_HPD_INT_RECORD_TYPE == header->ucRecordType 989 && sizeof(ATOM_HPD_INT_RECORD) <= header->ucRecordSize) 990 return (ATOM_HPD_INT_RECORD *) header; 991 992 offset += header->ucRecordSize; 993 } 994 995 return NULL; 996 } 997 998 static enum bp_result get_ss_info_from_ss_info_table( 999 struct bios_parser *bp, 1000 uint32_t id, 1001 struct spread_spectrum_info *ss_info); 1002 static enum bp_result get_ss_info_from_tbl( 1003 struct bios_parser *bp, 1004 uint32_t id, 1005 struct spread_spectrum_info *ss_info); 1006 /** 1007 * bios_parser_get_spread_spectrum_info 1008 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or 1009 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info 1010 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info ver 3.1, 1011 * there is only one entry for each signal /ss id. However, there is 1012 * no planning of supporting multiple spread Sprectum entry for EverGreen 1013 * @dcb: pointer to the DC BIOS 1014 * @signal: ASSignalType to be converted to info index 1015 * @index: number of entries that match the converted info index 1016 * @ss_info: sprectrum information structure, 1017 * return: Bios parser result code 1018 */ 1019 static enum bp_result bios_parser_get_spread_spectrum_info( 1020 struct dc_bios *dcb, 1021 enum as_signal_type signal, 1022 uint32_t index, 1023 struct spread_spectrum_info *ss_info) 1024 { 1025 struct bios_parser *bp = BP_FROM_DCB(dcb); 1026 enum bp_result result = BP_RESULT_UNSUPPORTED; 1027 uint32_t clk_id_ss = 0; 1028 ATOM_COMMON_TABLE_HEADER *header; 1029 struct atom_data_revision tbl_revision; 1030 1031 if (!ss_info) /* check for bad input */ 1032 return BP_RESULT_BADINPUT; 1033 /* signal translation */ 1034 clk_id_ss = signal_to_ss_id(signal); 1035 1036 if (!DATA_TABLES(ASIC_InternalSS_Info)) 1037 if (!index) 1038 return get_ss_info_from_ss_info_table(bp, clk_id_ss, 1039 ss_info); 1040 1041 header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, 1042 DATA_TABLES(ASIC_InternalSS_Info)); 1043 get_atom_data_table_revision(header, &tbl_revision); 1044 1045 switch (tbl_revision.major) { 1046 case 2: 1047 switch (tbl_revision.minor) { 1048 case 1: 1049 /* there can not be more then one entry for Internal 1050 * SS Info table version 2.1 */ 1051 if (!index) 1052 return get_ss_info_from_tbl(bp, clk_id_ss, 1053 ss_info); 1054 break; 1055 default: 1056 break; 1057 } 1058 break; 1059 1060 case 3: 1061 switch (tbl_revision.minor) { 1062 case 1: 1063 return get_ss_info_v3_1(bp, clk_id_ss, index, ss_info); 1064 default: 1065 break; 1066 } 1067 break; 1068 default: 1069 break; 1070 } 1071 /* there can not be more then one entry for SS Info table */ 1072 return result; 1073 } 1074 1075 static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1( 1076 struct bios_parser *bp, 1077 uint32_t id, 1078 struct spread_spectrum_info *info); 1079 1080 /** 1081 * get_ss_info_from_tbl 1082 * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or 1083 * SS_Info table from the VBIOS 1084 * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or 1085 * SS_Info. 1086 * 1087 * @bp: pointer to the BIOS parser 1088 * @id: spread sprectrum info index 1089 * @ss_info: sprectrum information structure, 1090 * return: BIOS parser result code 1091 */ 1092 static enum bp_result get_ss_info_from_tbl( 1093 struct bios_parser *bp, 1094 uint32_t id, 1095 struct spread_spectrum_info *ss_info) 1096 { 1097 if (!ss_info) /* check for bad input, if ss_info is not NULL */ 1098 return BP_RESULT_BADINPUT; 1099 /* for SS_Info table only support DP and LVDS */ 1100 if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS) 1101 return get_ss_info_from_ss_info_table(bp, id, ss_info); 1102 else 1103 return get_ss_info_from_internal_ss_info_tbl_V2_1(bp, id, 1104 ss_info); 1105 } 1106 1107 /** 1108 * get_ss_info_from_internal_ss_info_tbl_V2_1 1109 * Get spread sprectrum information from the ASIC_InternalSS_Info table Ver 2.1 1110 * from the VBIOS 1111 * There will not be multiple entry for Ver 2.1 1112 * 1113 * @bp: pointer to the Bios parser 1114 * @id: spread sprectrum info index 1115 * @info: sprectrum information structure, 1116 * return: Bios parser result code 1117 */ 1118 static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1( 1119 struct bios_parser *bp, 1120 uint32_t id, 1121 struct spread_spectrum_info *info) 1122 { 1123 enum bp_result result = BP_RESULT_UNSUPPORTED; 1124 ATOM_ASIC_INTERNAL_SS_INFO_V2 *header; 1125 ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl; 1126 uint32_t tbl_size, i; 1127 1128 if (!DATA_TABLES(ASIC_InternalSS_Info)) 1129 return result; 1130 1131 header = ((ATOM_ASIC_INTERNAL_SS_INFO_V2 *) bios_get_image( 1132 &bp->base, 1133 DATA_TABLES(ASIC_InternalSS_Info), 1134 struct_size(header, asSpreadSpectrum, 1))); 1135 if (!header) 1136 return result; 1137 1138 memset(info, 0, sizeof(struct spread_spectrum_info)); 1139 1140 tbl_size = (le16_to_cpu(header->sHeader.usStructureSize) 1141 - sizeof(ATOM_COMMON_TABLE_HEADER)) 1142 / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1143 1144 tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *) 1145 &(header->asSpreadSpectrum[0]); 1146 for (i = 0; i < tbl_size; i++) { 1147 result = BP_RESULT_NORECORD; 1148 1149 if (tbl[i].ucClockIndication != (uint8_t)id) 1150 continue; 1151 1152 if (ATOM_EXTERNAL_SS_MASK 1153 & tbl[i].ucSpreadSpectrumMode) { 1154 info->type.EXTERNAL = true; 1155 } 1156 if (ATOM_SS_CENTRE_SPREAD_MODE_MASK 1157 & tbl[i].ucSpreadSpectrumMode) { 1158 info->type.CENTER_MODE = true; 1159 } 1160 info->type.STEP_AND_DELAY_INFO = false; 1161 /* convert [10KHz] into [KHz] */ 1162 info->target_clock_range = 1163 le32_to_cpu(tbl[i].ulTargetClockRange) * 10; 1164 info->spread_spectrum_percentage = 1165 (uint32_t)le16_to_cpu(tbl[i].usSpreadSpectrumPercentage); 1166 info->spread_spectrum_range = 1167 (uint32_t)(le16_to_cpu(tbl[i].usSpreadRateIn10Hz) * 10); 1168 result = BP_RESULT_OK; 1169 break; 1170 } 1171 1172 return result; 1173 1174 } 1175 1176 /** 1177 * get_ss_info_from_ss_info_table 1178 * Get spread sprectrum information from the SS_Info table from the VBIOS 1179 * if the pointer to info is NULL, indicate the caller what to know the number 1180 * of entries that matches the id 1181 * for, the SS_Info table, there should not be more than 1 entry match. 1182 * 1183 * @bp: pointer to the Bios parser 1184 * @id: spread sprectrum id 1185 * @ss_info: sprectrum information structure, 1186 * return: Bios parser result code 1187 */ 1188 static enum bp_result get_ss_info_from_ss_info_table( 1189 struct bios_parser *bp, 1190 uint32_t id, 1191 struct spread_spectrum_info *ss_info) 1192 { 1193 enum bp_result result = BP_RESULT_UNSUPPORTED; 1194 ATOM_SPREAD_SPECTRUM_INFO *tbl; 1195 ATOM_COMMON_TABLE_HEADER *header; 1196 uint32_t table_size; 1197 uint32_t i; 1198 uint32_t id_local = SS_ID_UNKNOWN; 1199 struct atom_data_revision revision; 1200 1201 /* exist of the SS_Info table */ 1202 /* check for bad input, pSSinfo can not be NULL */ 1203 if (!DATA_TABLES(SS_Info) || !ss_info) 1204 return result; 1205 1206 header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(SS_Info)); 1207 get_atom_data_table_revision(header, &revision); 1208 1209 tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, DATA_TABLES(SS_Info)); 1210 if (!tbl) 1211 return result; 1212 1213 if (1 != revision.major || 2 > revision.minor) 1214 return result; 1215 1216 /* have to convert from Internal_SS format to SS_Info format */ 1217 switch (id) { 1218 case ASIC_INTERNAL_SS_ON_DP: 1219 id_local = SS_ID_DP1; 1220 break; 1221 case ASIC_INTERNAL_SS_ON_LVDS: 1222 { 1223 struct embedded_panel_info panel_info; 1224 1225 if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info) 1226 == BP_RESULT_OK) 1227 id_local = panel_info.ss_id; 1228 break; 1229 } 1230 default: 1231 break; 1232 } 1233 1234 if (id_local == SS_ID_UNKNOWN) 1235 return result; 1236 1237 table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) - 1238 sizeof(ATOM_COMMON_TABLE_HEADER)) / 1239 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1240 1241 for (i = 0; i < table_size; i++) { 1242 if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id) 1243 continue; 1244 1245 memset(ss_info, 0, sizeof(struct spread_spectrum_info)); 1246 1247 if (ATOM_EXTERNAL_SS_MASK & 1248 tbl->asSS_Info[i].ucSpreadSpectrumType) 1249 ss_info->type.EXTERNAL = true; 1250 1251 if (ATOM_SS_CENTRE_SPREAD_MODE_MASK & 1252 tbl->asSS_Info[i].ucSpreadSpectrumType) 1253 ss_info->type.CENTER_MODE = true; 1254 1255 ss_info->type.STEP_AND_DELAY_INFO = true; 1256 ss_info->spread_spectrum_percentage = 1257 (uint32_t)le16_to_cpu(tbl->asSS_Info[i].usSpreadSpectrumPercentage); 1258 ss_info->step_and_delay_info.step = tbl->asSS_Info[i].ucSS_Step; 1259 ss_info->step_and_delay_info.delay = 1260 tbl->asSS_Info[i].ucSS_Delay; 1261 ss_info->step_and_delay_info.recommended_ref_div = 1262 tbl->asSS_Info[i].ucRecommendedRef_Div; 1263 ss_info->spread_spectrum_range = 1264 (uint32_t)tbl->asSS_Info[i].ucSS_Range * 10000; 1265 1266 /* there will be only one entry for each display type in SS_info 1267 * table */ 1268 result = BP_RESULT_OK; 1269 break; 1270 } 1271 1272 return result; 1273 } 1274 static enum bp_result get_embedded_panel_info_v1_2( 1275 struct bios_parser *bp, 1276 struct embedded_panel_info *info); 1277 static enum bp_result get_embedded_panel_info_v1_3( 1278 struct bios_parser *bp, 1279 struct embedded_panel_info *info); 1280 1281 static enum bp_result bios_parser_get_embedded_panel_info( 1282 struct dc_bios *dcb, 1283 struct embedded_panel_info *info) 1284 { 1285 struct bios_parser *bp = BP_FROM_DCB(dcb); 1286 ATOM_COMMON_TABLE_HEADER *hdr; 1287 1288 if (!DATA_TABLES(LCD_Info)) 1289 return BP_RESULT_FAILURE; 1290 1291 hdr = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, DATA_TABLES(LCD_Info)); 1292 1293 if (!hdr) 1294 return BP_RESULT_BADBIOSTABLE; 1295 1296 switch (hdr->ucTableFormatRevision) { 1297 case 1: 1298 switch (hdr->ucTableContentRevision) { 1299 case 0: 1300 case 1: 1301 case 2: 1302 return get_embedded_panel_info_v1_2(bp, info); 1303 case 3: 1304 return get_embedded_panel_info_v1_3(bp, info); 1305 default: 1306 break; 1307 } 1308 break; 1309 default: 1310 break; 1311 } 1312 1313 return BP_RESULT_FAILURE; 1314 } 1315 1316 static enum bp_result get_embedded_panel_info_v1_2( 1317 struct bios_parser *bp, 1318 struct embedded_panel_info *info) 1319 { 1320 ATOM_LVDS_INFO_V12 *lvds; 1321 1322 if (!info) 1323 return BP_RESULT_BADINPUT; 1324 1325 if (!DATA_TABLES(LVDS_Info)) 1326 return BP_RESULT_UNSUPPORTED; 1327 1328 lvds = 1329 GET_IMAGE(ATOM_LVDS_INFO_V12, DATA_TABLES(LVDS_Info)); 1330 1331 if (!lvds) 1332 return BP_RESULT_BADBIOSTABLE; 1333 1334 if (1 != lvds->sHeader.ucTableFormatRevision 1335 || 2 > lvds->sHeader.ucTableContentRevision) 1336 return BP_RESULT_UNSUPPORTED; 1337 1338 memset(info, 0, sizeof(struct embedded_panel_info)); 1339 1340 /* We need to convert from 10KHz units into KHz units*/ 1341 info->lcd_timing.pixel_clk = 1342 le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10; 1343 /* usHActive does not include borders, according to VBIOS team*/ 1344 info->lcd_timing.horizontal_addressable = 1345 le16_to_cpu(lvds->sLCDTiming.usHActive); 1346 /* usHBlanking_Time includes borders, so we should really be subtracting 1347 * borders duing this translation, but LVDS generally*/ 1348 /* doesn't have borders, so we should be okay leaving this as is for 1349 * now. May need to revisit if we ever have LVDS with borders*/ 1350 info->lcd_timing.horizontal_blanking_time = 1351 le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time); 1352 /* usVActive does not include borders, according to VBIOS team*/ 1353 info->lcd_timing.vertical_addressable = 1354 le16_to_cpu(lvds->sLCDTiming.usVActive); 1355 /* usVBlanking_Time includes borders, so we should really be subtracting 1356 * borders duing this translation, but LVDS generally*/ 1357 /* doesn't have borders, so we should be okay leaving this as is for 1358 * now. May need to revisit if we ever have LVDS with borders*/ 1359 info->lcd_timing.vertical_blanking_time = 1360 le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time); 1361 info->lcd_timing.horizontal_sync_offset = 1362 le16_to_cpu(lvds->sLCDTiming.usHSyncOffset); 1363 info->lcd_timing.horizontal_sync_width = 1364 le16_to_cpu(lvds->sLCDTiming.usHSyncWidth); 1365 info->lcd_timing.vertical_sync_offset = 1366 le16_to_cpu(lvds->sLCDTiming.usVSyncOffset); 1367 info->lcd_timing.vertical_sync_width = 1368 le16_to_cpu(lvds->sLCDTiming.usVSyncWidth); 1369 info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder; 1370 info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder; 1371 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 1372 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff; 1373 info->lcd_timing.misc_info.H_SYNC_POLARITY = 1374 ~(uint32_t) 1375 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity; 1376 info->lcd_timing.misc_info.V_SYNC_POLARITY = 1377 ~(uint32_t) 1378 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity; 1379 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 1380 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff; 1381 info->lcd_timing.misc_info.H_REPLICATION_BY2 = 1382 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2; 1383 info->lcd_timing.misc_info.V_REPLICATION_BY2 = 1384 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2; 1385 info->lcd_timing.misc_info.COMPOSITE_SYNC = 1386 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync; 1387 info->lcd_timing.misc_info.INTERLACE = 1388 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; 1389 info->lcd_timing.misc_info.DOUBLE_CLOCK = 1390 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock; 1391 info->ss_id = lvds->ucSS_Id; 1392 1393 { 1394 uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate); 1395 /* Get minimum supported refresh rate*/ 1396 if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr) 1397 info->supported_rr.REFRESH_RATE_30HZ = 1; 1398 else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr) 1399 info->supported_rr.REFRESH_RATE_40HZ = 1; 1400 else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr) 1401 info->supported_rr.REFRESH_RATE_48HZ = 1; 1402 else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr) 1403 info->supported_rr.REFRESH_RATE_50HZ = 1; 1404 else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr) 1405 info->supported_rr.REFRESH_RATE_60HZ = 1; 1406 } 1407 1408 /*Drr panel support can be reported by VBIOS*/ 1409 if (LCDPANEL_CAP_DRR_SUPPORTED 1410 & lvds->ucLCDPanel_SpecialHandlingCap) 1411 info->drr_enabled = 1; 1412 1413 if (ATOM_PANEL_MISC_DUAL & lvds->ucLVDS_Misc) 1414 info->lcd_timing.misc_info.DOUBLE_CLOCK = true; 1415 1416 if (ATOM_PANEL_MISC_888RGB & lvds->ucLVDS_Misc) 1417 info->lcd_timing.misc_info.RGB888 = true; 1418 1419 info->lcd_timing.misc_info.GREY_LEVEL = 1420 (uint32_t) (ATOM_PANEL_MISC_GREY_LEVEL & 1421 lvds->ucLVDS_Misc) >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT; 1422 1423 if (ATOM_PANEL_MISC_SPATIAL & lvds->ucLVDS_Misc) 1424 info->lcd_timing.misc_info.SPATIAL = true; 1425 1426 if (ATOM_PANEL_MISC_TEMPORAL & lvds->ucLVDS_Misc) 1427 info->lcd_timing.misc_info.TEMPORAL = true; 1428 1429 if (ATOM_PANEL_MISC_API_ENABLED & lvds->ucLVDS_Misc) 1430 info->lcd_timing.misc_info.API_ENABLED = true; 1431 1432 return BP_RESULT_OK; 1433 } 1434 1435 static enum bp_result get_embedded_panel_info_v1_3( 1436 struct bios_parser *bp, 1437 struct embedded_panel_info *info) 1438 { 1439 ATOM_LCD_INFO_V13 *lvds; 1440 1441 if (!info) 1442 return BP_RESULT_BADINPUT; 1443 1444 if (!DATA_TABLES(LCD_Info)) 1445 return BP_RESULT_UNSUPPORTED; 1446 1447 lvds = GET_IMAGE(ATOM_LCD_INFO_V13, DATA_TABLES(LCD_Info)); 1448 1449 if (!lvds) 1450 return BP_RESULT_BADBIOSTABLE; 1451 1452 if (!((1 == lvds->sHeader.ucTableFormatRevision) 1453 && (3 <= lvds->sHeader.ucTableContentRevision))) 1454 return BP_RESULT_UNSUPPORTED; 1455 1456 memset(info, 0, sizeof(struct embedded_panel_info)); 1457 1458 /* We need to convert from 10KHz units into KHz units */ 1459 info->lcd_timing.pixel_clk = 1460 le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10; 1461 /* usHActive does not include borders, according to VBIOS team */ 1462 info->lcd_timing.horizontal_addressable = 1463 le16_to_cpu(lvds->sLCDTiming.usHActive); 1464 /* usHBlanking_Time includes borders, so we should really be subtracting 1465 * borders duing this translation, but LVDS generally*/ 1466 /* doesn't have borders, so we should be okay leaving this as is for 1467 * now. May need to revisit if we ever have LVDS with borders*/ 1468 info->lcd_timing.horizontal_blanking_time = 1469 le16_to_cpu(lvds->sLCDTiming.usHBlanking_Time); 1470 /* usVActive does not include borders, according to VBIOS team*/ 1471 info->lcd_timing.vertical_addressable = 1472 le16_to_cpu(lvds->sLCDTiming.usVActive); 1473 /* usVBlanking_Time includes borders, so we should really be subtracting 1474 * borders duing this translation, but LVDS generally*/ 1475 /* doesn't have borders, so we should be okay leaving this as is for 1476 * now. May need to revisit if we ever have LVDS with borders*/ 1477 info->lcd_timing.vertical_blanking_time = 1478 le16_to_cpu(lvds->sLCDTiming.usVBlanking_Time); 1479 info->lcd_timing.horizontal_sync_offset = 1480 le16_to_cpu(lvds->sLCDTiming.usHSyncOffset); 1481 info->lcd_timing.horizontal_sync_width = 1482 le16_to_cpu(lvds->sLCDTiming.usHSyncWidth); 1483 info->lcd_timing.vertical_sync_offset = 1484 le16_to_cpu(lvds->sLCDTiming.usVSyncOffset); 1485 info->lcd_timing.vertical_sync_width = 1486 le16_to_cpu(lvds->sLCDTiming.usVSyncWidth); 1487 info->lcd_timing.horizontal_border = lvds->sLCDTiming.ucHBorder; 1488 info->lcd_timing.vertical_border = lvds->sLCDTiming.ucVBorder; 1489 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 1490 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HorizontalCutOff; 1491 info->lcd_timing.misc_info.H_SYNC_POLARITY = 1492 ~(uint32_t) 1493 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.HSyncPolarity; 1494 info->lcd_timing.misc_info.V_SYNC_POLARITY = 1495 ~(uint32_t) 1496 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VSyncPolarity; 1497 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 1498 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.VerticalCutOff; 1499 info->lcd_timing.misc_info.H_REPLICATION_BY2 = 1500 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.H_ReplicationBy2; 1501 info->lcd_timing.misc_info.V_REPLICATION_BY2 = 1502 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.V_ReplicationBy2; 1503 info->lcd_timing.misc_info.COMPOSITE_SYNC = 1504 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.CompositeSync; 1505 info->lcd_timing.misc_info.INTERLACE = 1506 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; 1507 info->lcd_timing.misc_info.DOUBLE_CLOCK = 1508 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.DoubleClock; 1509 info->ss_id = lvds->ucSS_Id; 1510 1511 /* Drr panel support can be reported by VBIOS*/ 1512 if (LCDPANEL_CAP_V13_DRR_SUPPORTED 1513 & lvds->ucLCDPanel_SpecialHandlingCap) 1514 info->drr_enabled = 1; 1515 1516 /* Get supported refresh rate*/ 1517 if (info->drr_enabled == 1) { 1518 uint8_t min_rr = 1519 lvds->sRefreshRateSupport.ucMinRefreshRateForDRR; 1520 uint8_t rr = lvds->sRefreshRateSupport.ucSupportedRefreshRate; 1521 1522 if (min_rr != 0) { 1523 if (SUPPORTED_LCD_REFRESHRATE_30Hz & min_rr) 1524 info->supported_rr.REFRESH_RATE_30HZ = 1; 1525 else if (SUPPORTED_LCD_REFRESHRATE_40Hz & min_rr) 1526 info->supported_rr.REFRESH_RATE_40HZ = 1; 1527 else if (SUPPORTED_LCD_REFRESHRATE_48Hz & min_rr) 1528 info->supported_rr.REFRESH_RATE_48HZ = 1; 1529 else if (SUPPORTED_LCD_REFRESHRATE_50Hz & min_rr) 1530 info->supported_rr.REFRESH_RATE_50HZ = 1; 1531 else if (SUPPORTED_LCD_REFRESHRATE_60Hz & min_rr) 1532 info->supported_rr.REFRESH_RATE_60HZ = 1; 1533 } else { 1534 if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr) 1535 info->supported_rr.REFRESH_RATE_30HZ = 1; 1536 else if (SUPPORTED_LCD_REFRESHRATE_40Hz & rr) 1537 info->supported_rr.REFRESH_RATE_40HZ = 1; 1538 else if (SUPPORTED_LCD_REFRESHRATE_48Hz & rr) 1539 info->supported_rr.REFRESH_RATE_48HZ = 1; 1540 else if (SUPPORTED_LCD_REFRESHRATE_50Hz & rr) 1541 info->supported_rr.REFRESH_RATE_50HZ = 1; 1542 else if (SUPPORTED_LCD_REFRESHRATE_60Hz & rr) 1543 info->supported_rr.REFRESH_RATE_60HZ = 1; 1544 } 1545 } 1546 1547 if (ATOM_PANEL_MISC_V13_DUAL & lvds->ucLCD_Misc) 1548 info->lcd_timing.misc_info.DOUBLE_CLOCK = true; 1549 1550 if (ATOM_PANEL_MISC_V13_8BIT_PER_COLOR & lvds->ucLCD_Misc) 1551 info->lcd_timing.misc_info.RGB888 = true; 1552 1553 info->lcd_timing.misc_info.GREY_LEVEL = 1554 (uint32_t) (ATOM_PANEL_MISC_V13_GREY_LEVEL & 1555 lvds->ucLCD_Misc) >> ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT; 1556 1557 return BP_RESULT_OK; 1558 } 1559 1560 /** 1561 * bios_parser_get_encoder_cap_info - get encoder capability 1562 * information of input object id 1563 * 1564 * @dcb: pointer to the DC BIOS 1565 * @object_id: object id 1566 * @info: encoder cap information structure 1567 * 1568 * return: Bios parser result code 1569 */ 1570 static enum bp_result bios_parser_get_encoder_cap_info( 1571 struct dc_bios *dcb, 1572 struct graphics_object_id object_id, 1573 struct bp_encoder_cap_info *info) 1574 { 1575 struct bios_parser *bp = BP_FROM_DCB(dcb); 1576 ATOM_OBJECT *object; 1577 ATOM_ENCODER_CAP_RECORD_V2 *record = NULL; 1578 1579 if (!info) 1580 return BP_RESULT_BADINPUT; 1581 1582 object = get_bios_object(bp, object_id); 1583 1584 if (!object) 1585 return BP_RESULT_BADINPUT; 1586 1587 record = get_encoder_cap_record(bp, object); 1588 if (!record) 1589 return BP_RESULT_NORECORD; 1590 1591 info->DP_HBR2_EN = record->usHBR2En; 1592 info->DP_HBR3_EN = record->usHBR3En; 1593 info->HDMI_6GB_EN = record->usHDMI6GEn; 1594 return BP_RESULT_OK; 1595 } 1596 1597 /** 1598 * get_encoder_cap_record - Get encoder cap record for the object 1599 * 1600 * @bp: pointer to the BIOS parser 1601 * @object: ATOM object 1602 * return: atom encoder cap record 1603 * note: search all records to find the ATOM_ENCODER_CAP_RECORD_V2 record 1604 */ 1605 static ATOM_ENCODER_CAP_RECORD_V2 *get_encoder_cap_record( 1606 struct bios_parser *bp, 1607 ATOM_OBJECT *object) 1608 { 1609 ATOM_COMMON_RECORD_HEADER *header; 1610 uint32_t offset; 1611 1612 if (!object) { 1613 BREAK_TO_DEBUGGER(); /* Invalid object */ 1614 return NULL; 1615 } 1616 1617 offset = le16_to_cpu(object->usRecordOffset) 1618 + bp->object_info_tbl_offset; 1619 1620 for (;;) { 1621 header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, offset); 1622 1623 if (!header) 1624 return NULL; 1625 1626 offset += header->ucRecordSize; 1627 1628 if (LAST_RECORD_TYPE == header->ucRecordType || 1629 !header->ucRecordSize) 1630 break; 1631 1632 if (ATOM_ENCODER_CAP_RECORD_TYPE != header->ucRecordType) 1633 continue; 1634 1635 if (sizeof(ATOM_ENCODER_CAP_RECORD_V2) <= header->ucRecordSize) 1636 return (ATOM_ENCODER_CAP_RECORD_V2 *)header; 1637 } 1638 1639 return NULL; 1640 } 1641 1642 static uint32_t get_ss_entry_number( 1643 struct bios_parser *bp, 1644 uint32_t id); 1645 static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( 1646 struct bios_parser *bp, 1647 uint32_t id); 1648 static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1( 1649 struct bios_parser *bp, 1650 uint32_t id); 1651 static uint32_t get_ss_entry_number_from_ss_info_tbl( 1652 struct bios_parser *bp, 1653 uint32_t id); 1654 1655 /** 1656 * bios_parser_get_ss_entry_number 1657 * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table from 1658 * the VBIOS that match the SSid (to be converted from signal) 1659 * 1660 * @dcb: pointer to the DC BIOS 1661 * @signal: ASSignalType to be converted to SSid 1662 * return: number of SS Entry that match the signal 1663 */ 1664 static uint32_t bios_parser_get_ss_entry_number( 1665 struct dc_bios *dcb, 1666 enum as_signal_type signal) 1667 { 1668 struct bios_parser *bp = BP_FROM_DCB(dcb); 1669 uint32_t ss_id = 0; 1670 ATOM_COMMON_TABLE_HEADER *header; 1671 struct atom_data_revision revision; 1672 1673 ss_id = signal_to_ss_id(signal); 1674 1675 if (!DATA_TABLES(ASIC_InternalSS_Info)) 1676 return get_ss_entry_number_from_ss_info_tbl(bp, ss_id); 1677 1678 header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, 1679 DATA_TABLES(ASIC_InternalSS_Info)); 1680 get_atom_data_table_revision(header, &revision); 1681 1682 switch (revision.major) { 1683 case 2: 1684 switch (revision.minor) { 1685 case 1: 1686 return get_ss_entry_number(bp, ss_id); 1687 default: 1688 break; 1689 } 1690 break; 1691 case 3: 1692 switch (revision.minor) { 1693 case 1: 1694 return 1695 get_ss_entry_number_from_internal_ss_info_tbl_V3_1( 1696 bp, ss_id); 1697 default: 1698 break; 1699 } 1700 break; 1701 default: 1702 break; 1703 } 1704 1705 return 0; 1706 } 1707 1708 /** 1709 * get_ss_entry_number_from_ss_info_tbl 1710 * Get Number of spread spectrum entry from the SS_Info table from the VBIOS. 1711 * 1712 * @bp: pointer to the BIOS parser 1713 * @id: spread spectrum id 1714 * return: number of SS Entry that match the id 1715 * note: There can only be one entry for each id for SS_Info Table 1716 */ 1717 static uint32_t get_ss_entry_number_from_ss_info_tbl( 1718 struct bios_parser *bp, 1719 uint32_t id) 1720 { 1721 ATOM_SPREAD_SPECTRUM_INFO *tbl; 1722 ATOM_COMMON_TABLE_HEADER *header; 1723 uint32_t table_size; 1724 uint32_t i; 1725 uint32_t number = 0; 1726 uint32_t id_local = SS_ID_UNKNOWN; 1727 struct atom_data_revision revision; 1728 1729 /* SS_Info table exist */ 1730 if (!DATA_TABLES(SS_Info)) 1731 return number; 1732 1733 header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, 1734 DATA_TABLES(SS_Info)); 1735 get_atom_data_table_revision(header, &revision); 1736 1737 tbl = GET_IMAGE(ATOM_SPREAD_SPECTRUM_INFO, 1738 DATA_TABLES(SS_Info)); 1739 if (!tbl) 1740 return number; 1741 1742 if (1 != revision.major || 2 > revision.minor) 1743 return number; 1744 1745 /* have to convert from Internal_SS format to SS_Info format */ 1746 switch (id) { 1747 case ASIC_INTERNAL_SS_ON_DP: 1748 id_local = SS_ID_DP1; 1749 break; 1750 case ASIC_INTERNAL_SS_ON_LVDS: { 1751 struct embedded_panel_info panel_info; 1752 1753 if (bios_parser_get_embedded_panel_info(&bp->base, &panel_info) 1754 == BP_RESULT_OK) 1755 id_local = panel_info.ss_id; 1756 break; 1757 } 1758 default: 1759 break; 1760 } 1761 1762 if (id_local == SS_ID_UNKNOWN) 1763 return number; 1764 1765 table_size = (le16_to_cpu(tbl->sHeader.usStructureSize) - 1766 sizeof(ATOM_COMMON_TABLE_HEADER)) / 1767 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1768 1769 for (i = 0; i < table_size; i++) 1770 if (id_local == (uint32_t)tbl->asSS_Info[i].ucSS_Id) { 1771 number = 1; 1772 break; 1773 } 1774 1775 return number; 1776 } 1777 1778 /** 1779 * get_ss_entry_number 1780 * Get spread sprectrum information from the ASIC_InternalSS_Info Ver 2.1 or 1781 * SS_Info table from the VBIOS 1782 * There can not be more than 1 entry for ASIC_InternalSS_Info Ver 2.1 or 1783 * SS_Info. 1784 * 1785 * @bp: pointer to the BIOS parser 1786 * @id: spread sprectrum info index 1787 * return: Bios parser result code 1788 */ 1789 static uint32_t get_ss_entry_number(struct bios_parser *bp, uint32_t id) 1790 { 1791 if (id == ASIC_INTERNAL_SS_ON_DP || id == ASIC_INTERNAL_SS_ON_LVDS) 1792 return get_ss_entry_number_from_ss_info_tbl(bp, id); 1793 1794 return get_ss_entry_number_from_internal_ss_info_tbl_v2_1(bp, id); 1795 } 1796 1797 /** 1798 * get_ss_entry_number_from_internal_ss_info_tbl_v2_1 1799 * Get NUmber of spread sprectrum entry from the ASIC_InternalSS_Info table 1800 * Ver 2.1 from the VBIOS 1801 * There will not be multiple entry for Ver 2.1 1802 * 1803 * @bp: pointer to the BIOS parser 1804 * @id: spread sprectrum info index 1805 * return: number of SS Entry that match the id 1806 */ 1807 static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_v2_1( 1808 struct bios_parser *bp, 1809 uint32_t id) 1810 { 1811 ATOM_ASIC_INTERNAL_SS_INFO_V2 *header_include; 1812 ATOM_ASIC_SS_ASSIGNMENT_V2 *tbl; 1813 uint32_t size; 1814 uint32_t i; 1815 1816 if (!DATA_TABLES(ASIC_InternalSS_Info)) 1817 return 0; 1818 1819 header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V2 *) bios_get_image( 1820 &bp->base, 1821 DATA_TABLES(ASIC_InternalSS_Info), 1822 struct_size(header_include, asSpreadSpectrum, 1))); 1823 if (!header_include) 1824 return 0; 1825 1826 size = (le16_to_cpu(header_include->sHeader.usStructureSize) 1827 - sizeof(ATOM_COMMON_TABLE_HEADER)) 1828 / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1829 1830 tbl = (ATOM_ASIC_SS_ASSIGNMENT_V2 *) 1831 &header_include->asSpreadSpectrum[0]; 1832 for (i = 0; i < size; i++) 1833 if (tbl[i].ucClockIndication == (uint8_t)id) 1834 return 1; 1835 1836 return 0; 1837 } 1838 1839 /** 1840 * get_ss_entry_number_from_internal_ss_info_tbl_V3_1 1841 * Get Number of SpreadSpectrum Entry from the ASIC_InternalSS_Info table of 1842 * the VBIOS that matches id 1843 * 1844 * @bp: pointer to the BIOS parser 1845 * @id: spread sprectrum id 1846 * return: number of SS Entry that match the id 1847 */ 1848 static uint32_t get_ss_entry_number_from_internal_ss_info_tbl_V3_1( 1849 struct bios_parser *bp, 1850 uint32_t id) 1851 { 1852 uint32_t number = 0; 1853 ATOM_ASIC_INTERNAL_SS_INFO_V3 *header_include; 1854 ATOM_ASIC_SS_ASSIGNMENT_V3 *tbl; 1855 uint32_t size; 1856 uint32_t i; 1857 1858 if (!DATA_TABLES(ASIC_InternalSS_Info)) 1859 return number; 1860 1861 header_include = ((ATOM_ASIC_INTERNAL_SS_INFO_V3 *) bios_get_image(&bp->base, 1862 DATA_TABLES(ASIC_InternalSS_Info), 1863 struct_size(header_include, asSpreadSpectrum, 1))); 1864 if (!header_include) 1865 return number; 1866 1867 size = (le16_to_cpu(header_include->sHeader.usStructureSize) - 1868 sizeof(ATOM_COMMON_TABLE_HEADER)) / 1869 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1870 1871 tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *) 1872 &header_include->asSpreadSpectrum[0]; 1873 1874 for (i = 0; i < size; i++) 1875 if (tbl[i].ucClockIndication == (uint8_t)id) 1876 number++; 1877 1878 return number; 1879 } 1880 1881 /** 1882 * bios_parser_get_gpio_pin_info 1883 * Get GpioPin information of input gpio id 1884 * 1885 * @dcb: pointer to the DC BIOS 1886 * @gpio_id: GPIO ID 1887 * @info: GpioPin information structure 1888 * return: Bios parser result code 1889 * note: 1890 * to get the GPIO PIN INFO, we need: 1891 * 1. get the GPIO_ID from other object table, see GetHPDInfo() 1892 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records, to get the registerA 1893 * offset/mask 1894 */ 1895 static enum bp_result bios_parser_get_gpio_pin_info( 1896 struct dc_bios *dcb, 1897 uint32_t gpio_id, 1898 struct gpio_pin_info *info) 1899 { 1900 struct bios_parser *bp = BP_FROM_DCB(dcb); 1901 ATOM_GPIO_PIN_LUT *header; 1902 uint32_t count = 0; 1903 uint32_t i = 0; 1904 1905 if (!DATA_TABLES(GPIO_Pin_LUT)) 1906 return BP_RESULT_BADBIOSTABLE; 1907 1908 header = ((ATOM_GPIO_PIN_LUT *) bios_get_image(&bp->base, 1909 DATA_TABLES(GPIO_Pin_LUT), 1910 struct_size(header, asGPIO_Pin, 1))); 1911 if (!header) 1912 return BP_RESULT_BADBIOSTABLE; 1913 1914 if (sizeof(ATOM_COMMON_TABLE_HEADER) + struct_size(header, asGPIO_Pin, 1) 1915 > le16_to_cpu(header->sHeader.usStructureSize)) 1916 return BP_RESULT_BADBIOSTABLE; 1917 1918 if (1 != header->sHeader.ucTableContentRevision) 1919 return BP_RESULT_UNSUPPORTED; 1920 1921 count = (le16_to_cpu(header->sHeader.usStructureSize) 1922 - sizeof(ATOM_COMMON_TABLE_HEADER)) 1923 / sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 1924 for (i = 0; i < count; ++i) { 1925 if (header->asGPIO_Pin[i].ucGPIO_ID != gpio_id) 1926 continue; 1927 1928 info->offset = 1929 (uint32_t) le16_to_cpu(header->asGPIO_Pin[i].usGpioPin_AIndex); 1930 info->offset_y = info->offset + 2; 1931 info->offset_en = info->offset + 1; 1932 info->offset_mask = info->offset - 1; 1933 1934 info->mask = (uint32_t) (1 << 1935 header->asGPIO_Pin[i].ucGpioPinBitShift); 1936 info->mask_y = info->mask + 2; 1937 info->mask_en = info->mask + 1; 1938 info->mask_mask = info->mask - 1; 1939 1940 return BP_RESULT_OK; 1941 } 1942 1943 return BP_RESULT_NORECORD; 1944 } 1945 1946 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp, 1947 ATOM_I2C_RECORD *record, 1948 struct graphics_object_i2c_info *info) 1949 { 1950 ATOM_GPIO_I2C_INFO *header; 1951 uint32_t count = 0; 1952 1953 if (!info) 1954 return BP_RESULT_BADINPUT; 1955 1956 /* get the GPIO_I2C info */ 1957 if (!DATA_TABLES(GPIO_I2C_Info)) 1958 return BP_RESULT_BADBIOSTABLE; 1959 1960 header = GET_IMAGE(ATOM_GPIO_I2C_INFO, DATA_TABLES(GPIO_I2C_Info)); 1961 if (!header) 1962 return BP_RESULT_BADBIOSTABLE; 1963 1964 if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_I2C_ASSIGMENT) 1965 > le16_to_cpu(header->sHeader.usStructureSize)) 1966 return BP_RESULT_BADBIOSTABLE; 1967 1968 if (1 != header->sHeader.ucTableContentRevision) 1969 return BP_RESULT_UNSUPPORTED; 1970 1971 /* get data count */ 1972 count = (le16_to_cpu(header->sHeader.usStructureSize) 1973 - sizeof(ATOM_COMMON_TABLE_HEADER)) 1974 / sizeof(ATOM_GPIO_I2C_ASSIGMENT); 1975 if (count < record->sucI2cId.bfI2C_LineMux) 1976 return BP_RESULT_BADBIOSTABLE; 1977 1978 /* get the GPIO_I2C_INFO */ 1979 info->i2c_hw_assist = record->sucI2cId.bfHW_Capable; 1980 info->i2c_line = record->sucI2cId.bfI2C_LineMux; 1981 info->i2c_engine_id = record->sucI2cId.bfHW_EngineID; 1982 info->i2c_slave_address = record->ucI2CAddr; 1983 1984 info->gpio_info.clk_mask_register_index = 1985 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkMaskRegisterIndex); 1986 info->gpio_info.clk_en_register_index = 1987 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkEnRegisterIndex); 1988 info->gpio_info.clk_y_register_index = 1989 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkY_RegisterIndex); 1990 info->gpio_info.clk_a_register_index = 1991 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usClkA_RegisterIndex); 1992 info->gpio_info.data_mask_register_index = 1993 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataMaskRegisterIndex); 1994 info->gpio_info.data_en_register_index = 1995 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataEnRegisterIndex); 1996 info->gpio_info.data_y_register_index = 1997 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataY_RegisterIndex); 1998 info->gpio_info.data_a_register_index = 1999 le16_to_cpu(header->asGPIO_Info[info->i2c_line].usDataA_RegisterIndex); 2000 2001 info->gpio_info.clk_mask_shift = 2002 header->asGPIO_Info[info->i2c_line].ucClkMaskShift; 2003 info->gpio_info.clk_en_shift = 2004 header->asGPIO_Info[info->i2c_line].ucClkEnShift; 2005 info->gpio_info.clk_y_shift = 2006 header->asGPIO_Info[info->i2c_line].ucClkY_Shift; 2007 info->gpio_info.clk_a_shift = 2008 header->asGPIO_Info[info->i2c_line].ucClkA_Shift; 2009 info->gpio_info.data_mask_shift = 2010 header->asGPIO_Info[info->i2c_line].ucDataMaskShift; 2011 info->gpio_info.data_en_shift = 2012 header->asGPIO_Info[info->i2c_line].ucDataEnShift; 2013 info->gpio_info.data_y_shift = 2014 header->asGPIO_Info[info->i2c_line].ucDataY_Shift; 2015 info->gpio_info.data_a_shift = 2016 header->asGPIO_Info[info->i2c_line].ucDataA_Shift; 2017 2018 return BP_RESULT_OK; 2019 } 2020 2021 static bool dal_graphics_object_id_is_valid(struct graphics_object_id id) 2022 { 2023 bool rc = true; 2024 2025 switch (id.type) { 2026 case OBJECT_TYPE_UNKNOWN: 2027 rc = false; 2028 break; 2029 case OBJECT_TYPE_GPU: 2030 case OBJECT_TYPE_ENGINE: 2031 /* do NOT check for id.id == 0 */ 2032 if (id.enum_id == ENUM_ID_UNKNOWN) 2033 rc = false; 2034 break; 2035 default: 2036 if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN) 2037 rc = false; 2038 break; 2039 } 2040 2041 return rc; 2042 } 2043 2044 static bool dal_graphics_object_id_is_equal( 2045 struct graphics_object_id id1, 2046 struct graphics_object_id id2) 2047 { 2048 if (false == dal_graphics_object_id_is_valid(id1)) { 2049 dm_output_to_console( 2050 "%s: Warning: comparing invalid object 'id1'!\n", __func__); 2051 return false; 2052 } 2053 2054 if (false == dal_graphics_object_id_is_valid(id2)) { 2055 dm_output_to_console( 2056 "%s: Warning: comparing invalid object 'id2'!\n", __func__); 2057 return false; 2058 } 2059 2060 if (id1.id == id2.id && id1.enum_id == id2.enum_id 2061 && id1.type == id2.type) 2062 return true; 2063 2064 return false; 2065 } 2066 2067 static ATOM_OBJECT *get_bios_object(struct bios_parser *bp, 2068 struct graphics_object_id id) 2069 { 2070 uint32_t offset; 2071 ATOM_OBJECT_TABLE *tbl; 2072 uint32_t i; 2073 2074 switch (id.type) { 2075 case OBJECT_TYPE_ENCODER: 2076 offset = le16_to_cpu(bp->object_info_tbl.v1_1->usEncoderObjectTableOffset); 2077 break; 2078 2079 case OBJECT_TYPE_CONNECTOR: 2080 offset = le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset); 2081 break; 2082 2083 case OBJECT_TYPE_ROUTER: 2084 offset = le16_to_cpu(bp->object_info_tbl.v1_1->usRouterObjectTableOffset); 2085 break; 2086 2087 case OBJECT_TYPE_GENERIC: 2088 if (bp->object_info_tbl.revision.minor < 3) 2089 return NULL; 2090 offset = le16_to_cpu(bp->object_info_tbl.v1_3->usMiscObjectTableOffset); 2091 break; 2092 2093 default: 2094 return NULL; 2095 } 2096 2097 offset += bp->object_info_tbl_offset; 2098 2099 tbl = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base, offset, 2100 struct_size(tbl, asObjects, 1))); 2101 if (!tbl) 2102 return NULL; 2103 2104 for (i = 0; i < tbl->ucNumberOfObjects; i++) 2105 if (dal_graphics_object_id_is_equal(id, 2106 object_id_from_bios_object_id( 2107 le16_to_cpu(tbl->asObjects[i].usObjectID)))) 2108 return &tbl->asObjects[i]; 2109 2110 return NULL; 2111 } 2112 2113 static uint32_t get_src_obj_list(struct bios_parser *bp, ATOM_OBJECT *object, 2114 uint16_t **id_list) 2115 { 2116 uint32_t offset; 2117 uint8_t *number; 2118 2119 if (!object) { 2120 BREAK_TO_DEBUGGER(); /* Invalid object id */ 2121 return 0; 2122 } 2123 2124 offset = le16_to_cpu(object->usSrcDstTableOffset) 2125 + bp->object_info_tbl_offset; 2126 2127 number = GET_IMAGE(uint8_t, offset); 2128 if (!number) 2129 return 0; 2130 2131 offset += sizeof(uint8_t); 2132 *id_list = (uint16_t *)bios_get_image(&bp->base, offset, *number * sizeof(uint16_t)); 2133 2134 if (!*id_list) 2135 return 0; 2136 2137 return *number; 2138 } 2139 2140 static struct device_id device_type_from_device_id(uint16_t device_id) 2141 { 2142 2143 struct device_id result_device_id = {0}; 2144 2145 switch (device_id) { 2146 case ATOM_DEVICE_LCD1_SUPPORT: 2147 result_device_id.device_type = DEVICE_TYPE_LCD; 2148 result_device_id.enum_id = 1; 2149 break; 2150 2151 case ATOM_DEVICE_LCD2_SUPPORT: 2152 result_device_id.device_type = DEVICE_TYPE_LCD; 2153 result_device_id.enum_id = 2; 2154 break; 2155 2156 case ATOM_DEVICE_CRT1_SUPPORT: 2157 result_device_id.device_type = DEVICE_TYPE_CRT; 2158 result_device_id.enum_id = 1; 2159 break; 2160 2161 case ATOM_DEVICE_CRT2_SUPPORT: 2162 result_device_id.device_type = DEVICE_TYPE_CRT; 2163 result_device_id.enum_id = 2; 2164 break; 2165 2166 case ATOM_DEVICE_DFP1_SUPPORT: 2167 result_device_id.device_type = DEVICE_TYPE_DFP; 2168 result_device_id.enum_id = 1; 2169 break; 2170 2171 case ATOM_DEVICE_DFP2_SUPPORT: 2172 result_device_id.device_type = DEVICE_TYPE_DFP; 2173 result_device_id.enum_id = 2; 2174 break; 2175 2176 case ATOM_DEVICE_DFP3_SUPPORT: 2177 result_device_id.device_type = DEVICE_TYPE_DFP; 2178 result_device_id.enum_id = 3; 2179 break; 2180 2181 case ATOM_DEVICE_DFP4_SUPPORT: 2182 result_device_id.device_type = DEVICE_TYPE_DFP; 2183 result_device_id.enum_id = 4; 2184 break; 2185 2186 case ATOM_DEVICE_DFP5_SUPPORT: 2187 result_device_id.device_type = DEVICE_TYPE_DFP; 2188 result_device_id.enum_id = 5; 2189 break; 2190 2191 case ATOM_DEVICE_DFP6_SUPPORT: 2192 result_device_id.device_type = DEVICE_TYPE_DFP; 2193 result_device_id.enum_id = 6; 2194 break; 2195 2196 default: 2197 BREAK_TO_DEBUGGER(); /* Invalid device Id */ 2198 result_device_id.device_type = DEVICE_TYPE_UNKNOWN; 2199 result_device_id.enum_id = 0; 2200 } 2201 return result_device_id; 2202 } 2203 2204 static void get_atom_data_table_revision( 2205 ATOM_COMMON_TABLE_HEADER *atom_data_tbl, 2206 struct atom_data_revision *tbl_revision) 2207 { 2208 if (!tbl_revision) 2209 return; 2210 2211 /* initialize the revision to 0 which is invalid revision */ 2212 tbl_revision->major = 0; 2213 tbl_revision->minor = 0; 2214 2215 if (!atom_data_tbl) 2216 return; 2217 2218 tbl_revision->major = 2219 (uint32_t) GET_DATA_TABLE_MAJOR_REVISION(atom_data_tbl); 2220 tbl_revision->minor = 2221 (uint32_t) GET_DATA_TABLE_MINOR_REVISION(atom_data_tbl); 2222 } 2223 2224 static uint32_t signal_to_ss_id(enum as_signal_type signal) 2225 { 2226 uint32_t clk_id_ss = 0; 2227 2228 switch (signal) { 2229 case AS_SIGNAL_TYPE_DVI: 2230 clk_id_ss = ASIC_INTERNAL_SS_ON_TMDS; 2231 break; 2232 case AS_SIGNAL_TYPE_HDMI: 2233 clk_id_ss = ASIC_INTERNAL_SS_ON_HDMI; 2234 break; 2235 case AS_SIGNAL_TYPE_LVDS: 2236 clk_id_ss = ASIC_INTERNAL_SS_ON_LVDS; 2237 break; 2238 case AS_SIGNAL_TYPE_DISPLAY_PORT: 2239 clk_id_ss = ASIC_INTERNAL_SS_ON_DP; 2240 break; 2241 case AS_SIGNAL_TYPE_GPU_PLL: 2242 clk_id_ss = ASIC_INTERNAL_GPUPLL_SS; 2243 break; 2244 default: 2245 break; 2246 } 2247 return clk_id_ss; 2248 } 2249 2250 static uint32_t get_support_mask_for_device_id( 2251 enum dal_device_type device_type, 2252 uint32_t enum_id) 2253 { 2254 switch (device_type) { 2255 case DEVICE_TYPE_LCD: 2256 switch (enum_id) { 2257 case 1: 2258 return ATOM_DEVICE_LCD1_SUPPORT; 2259 case 2: 2260 return ATOM_DEVICE_LCD2_SUPPORT; 2261 default: 2262 break; 2263 } 2264 break; 2265 case DEVICE_TYPE_CRT: 2266 switch (enum_id) { 2267 case 1: 2268 return ATOM_DEVICE_CRT1_SUPPORT; 2269 case 2: 2270 return ATOM_DEVICE_CRT2_SUPPORT; 2271 default: 2272 break; 2273 } 2274 break; 2275 case DEVICE_TYPE_DFP: 2276 switch (enum_id) { 2277 case 1: 2278 return ATOM_DEVICE_DFP1_SUPPORT; 2279 case 2: 2280 return ATOM_DEVICE_DFP2_SUPPORT; 2281 case 3: 2282 return ATOM_DEVICE_DFP3_SUPPORT; 2283 case 4: 2284 return ATOM_DEVICE_DFP4_SUPPORT; 2285 case 5: 2286 return ATOM_DEVICE_DFP5_SUPPORT; 2287 case 6: 2288 return ATOM_DEVICE_DFP6_SUPPORT; 2289 default: 2290 break; 2291 } 2292 break; 2293 case DEVICE_TYPE_CV: 2294 switch (enum_id) { 2295 case 1: 2296 return ATOM_DEVICE_CV_SUPPORT; 2297 default: 2298 break; 2299 } 2300 break; 2301 case DEVICE_TYPE_TV: 2302 switch (enum_id) { 2303 case 1: 2304 return ATOM_DEVICE_TV1_SUPPORT; 2305 default: 2306 break; 2307 } 2308 break; 2309 default: 2310 break; 2311 } 2312 2313 /* Unidentified device ID, return empty support mask. */ 2314 return 0; 2315 } 2316 2317 /** 2318 * bios_parser_set_scratch_critical_state - update critical state 2319 * bit in VBIOS scratch register 2320 * @dcb: pointer to the DC BIOS 2321 * @state: set or reset state 2322 */ 2323 static void bios_parser_set_scratch_critical_state( 2324 struct dc_bios *dcb, 2325 bool state) 2326 { 2327 bios_set_scratch_critical_state(dcb, state); 2328 } 2329 2330 /* 2331 * get_integrated_info_v8 2332 * 2333 * @brief 2334 * Get V8 integrated BIOS information 2335 * 2336 * @param 2337 * bios_parser *bp - [in]BIOS parser handler to get master data table 2338 * integrated_info *info - [out] store and output integrated info 2339 * 2340 * return: 2341 * enum bp_result - BP_RESULT_OK if information is available, 2342 * BP_RESULT_BADBIOSTABLE otherwise. 2343 */ 2344 static enum bp_result get_integrated_info_v8( 2345 struct bios_parser *bp, 2346 struct integrated_info *info) 2347 { 2348 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *info_v8; 2349 uint32_t i; 2350 2351 info_v8 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_8, 2352 bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo); 2353 2354 if (info_v8 == NULL) 2355 return BP_RESULT_BADBIOSTABLE; 2356 info->boot_up_engine_clock = le32_to_cpu(info_v8->ulBootUpEngineClock) * 10; 2357 info->dentist_vco_freq = le32_to_cpu(info_v8->ulDentistVCOFreq) * 10; 2358 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10; 2359 2360 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2361 /* Convert [10KHz] into [KHz] */ 2362 info->disp_clk_voltage[i].max_supported_clk = 2363 le32_to_cpu(info_v8->sDISPCLK_Voltage[i]. 2364 ulMaximumSupportedCLK) * 10; 2365 info->disp_clk_voltage[i].voltage_index = 2366 le32_to_cpu(info_v8->sDISPCLK_Voltage[i].ulVoltageIndex); 2367 } 2368 2369 info->boot_up_req_display_vector = 2370 le32_to_cpu(info_v8->ulBootUpReqDisplayVector); 2371 info->gpu_cap_info = 2372 le32_to_cpu(info_v8->ulGPUCapInfo); 2373 2374 /* 2375 * system_config: Bit[0] = 0 : PCIE power gating disabled 2376 * = 1 : PCIE power gating enabled 2377 * Bit[1] = 0 : DDR-PLL shut down disabled 2378 * = 1 : DDR-PLL shut down enabled 2379 * Bit[2] = 0 : DDR-PLL power down disabled 2380 * = 1 : DDR-PLL power down enabled 2381 */ 2382 info->system_config = le32_to_cpu(info_v8->ulSystemConfig); 2383 info->cpu_cap_info = le32_to_cpu(info_v8->ulCPUCapInfo); 2384 info->boot_up_nb_voltage = 2385 le16_to_cpu(info_v8->usBootUpNBVoltage); 2386 info->ext_disp_conn_info_offset = 2387 le16_to_cpu(info_v8->usExtDispConnInfoOffset); 2388 info->memory_type = info_v8->ucMemoryType; 2389 info->ma_channel_number = info_v8->ucUMAChannelNumber; 2390 info->gmc_restore_reset_time = 2391 le32_to_cpu(info_v8->ulGMCRestoreResetTime); 2392 2393 info->minimum_n_clk = 2394 le32_to_cpu(info_v8->ulNbpStateNClkFreq[0]); 2395 for (i = 1; i < 4; ++i) 2396 info->minimum_n_clk = 2397 info->minimum_n_clk < le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]) ? 2398 info->minimum_n_clk : le32_to_cpu(info_v8->ulNbpStateNClkFreq[i]); 2399 2400 info->idle_n_clk = le32_to_cpu(info_v8->ulIdleNClk); 2401 info->ddr_dll_power_up_time = 2402 le32_to_cpu(info_v8->ulDDR_DLL_PowerUpTime); 2403 info->ddr_pll_power_up_time = 2404 le32_to_cpu(info_v8->ulDDR_PLL_PowerUpTime); 2405 info->pcie_clk_ss_type = le16_to_cpu(info_v8->usPCIEClkSSType); 2406 info->lvds_ss_percentage = 2407 le16_to_cpu(info_v8->usLvdsSSPercentage); 2408 info->lvds_sspread_rate_in_10hz = 2409 le16_to_cpu(info_v8->usLvdsSSpreadRateIn10Hz); 2410 info->hdmi_ss_percentage = 2411 le16_to_cpu(info_v8->usHDMISSPercentage); 2412 info->hdmi_sspread_rate_in_10hz = 2413 le16_to_cpu(info_v8->usHDMISSpreadRateIn10Hz); 2414 info->dvi_ss_percentage = 2415 le16_to_cpu(info_v8->usDVISSPercentage); 2416 info->dvi_sspread_rate_in_10_hz = 2417 le16_to_cpu(info_v8->usDVISSpreadRateIn10Hz); 2418 2419 info->max_lvds_pclk_freq_in_single_link = 2420 le16_to_cpu(info_v8->usMaxLVDSPclkFreqInSingleLink); 2421 info->lvds_misc = info_v8->ucLvdsMisc; 2422 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2423 info_v8->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2424 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2425 info_v8->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2426 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2427 info_v8->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2428 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2429 info_v8->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2430 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2431 info_v8->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2432 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2433 info_v8->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2434 info->lvds_off_to_on_delay_in_4ms = 2435 info_v8->ucLVDSOffToOnDelay_in4Ms; 2436 info->lvds_bit_depth_control_val = 2437 le32_to_cpu(info_v8->ulLCDBitDepthControlVal); 2438 2439 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2440 /* Convert [10KHz] into [KHz] */ 2441 info->avail_s_clk[i].supported_s_clk = 2442 le32_to_cpu(info_v8->sAvail_SCLK[i].ulSupportedSCLK) * 10; 2443 info->avail_s_clk[i].voltage_index = 2444 le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageIndex); 2445 info->avail_s_clk[i].voltage_id = 2446 le16_to_cpu(info_v8->sAvail_SCLK[i].usVoltageID); 2447 } 2448 2449 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2450 info->ext_disp_conn_info.gu_id[i] = 2451 info_v8->sExtDispConnInfo.ucGuid[i]; 2452 } 2453 2454 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2455 info->ext_disp_conn_info.path[i].device_connector_id = 2456 object_id_from_bios_object_id( 2457 le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceConnector)); 2458 2459 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2460 object_id_from_bios_object_id( 2461 le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usExtEncoderObjId)); 2462 2463 info->ext_disp_conn_info.path[i].device_tag = 2464 le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceTag); 2465 info->ext_disp_conn_info.path[i].device_acpi_enum = 2466 le16_to_cpu(info_v8->sExtDispConnInfo.sPath[i].usDeviceACPIEnum); 2467 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2468 info_v8->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex; 2469 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2470 info_v8->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex; 2471 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2472 info_v8->sExtDispConnInfo.sPath[i].ucChannelMapping; 2473 } 2474 info->ext_disp_conn_info.checksum = 2475 info_v8->sExtDispConnInfo.ucChecksum; 2476 2477 return BP_RESULT_OK; 2478 } 2479 2480 /* 2481 * get_integrated_info_v9 2482 * 2483 * @brief 2484 * Get V9 integrated BIOS information 2485 * 2486 * @param 2487 * bios_parser *bp - [in]BIOS parser handler to get master data table 2488 * integrated_info *info - [out] store and output integrated info 2489 * 2490 * return: 2491 * enum bp_result - BP_RESULT_OK if information is available, 2492 * BP_RESULT_BADBIOSTABLE otherwise. 2493 */ 2494 static enum bp_result get_integrated_info_v9( 2495 struct bios_parser *bp, 2496 struct integrated_info *info) 2497 { 2498 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info_v9; 2499 uint32_t i; 2500 2501 info_v9 = GET_IMAGE(ATOM_INTEGRATED_SYSTEM_INFO_V1_9, 2502 bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo); 2503 2504 if (!info_v9) 2505 return BP_RESULT_BADBIOSTABLE; 2506 2507 info->boot_up_engine_clock = le32_to_cpu(info_v9->ulBootUpEngineClock) * 10; 2508 info->dentist_vco_freq = le32_to_cpu(info_v9->ulDentistVCOFreq) * 10; 2509 info->boot_up_uma_clock = le32_to_cpu(info_v9->ulBootUpUMAClock) * 10; 2510 2511 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2512 /* Convert [10KHz] into [KHz] */ 2513 info->disp_clk_voltage[i].max_supported_clk = 2514 le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulMaximumSupportedCLK) * 10; 2515 info->disp_clk_voltage[i].voltage_index = 2516 le32_to_cpu(info_v9->sDISPCLK_Voltage[i].ulVoltageIndex); 2517 } 2518 2519 info->boot_up_req_display_vector = 2520 le32_to_cpu(info_v9->ulBootUpReqDisplayVector); 2521 info->gpu_cap_info = le32_to_cpu(info_v9->ulGPUCapInfo); 2522 2523 /* 2524 * system_config: Bit[0] = 0 : PCIE power gating disabled 2525 * = 1 : PCIE power gating enabled 2526 * Bit[1] = 0 : DDR-PLL shut down disabled 2527 * = 1 : DDR-PLL shut down enabled 2528 * Bit[2] = 0 : DDR-PLL power down disabled 2529 * = 1 : DDR-PLL power down enabled 2530 */ 2531 info->system_config = le32_to_cpu(info_v9->ulSystemConfig); 2532 info->cpu_cap_info = le32_to_cpu(info_v9->ulCPUCapInfo); 2533 info->boot_up_nb_voltage = le16_to_cpu(info_v9->usBootUpNBVoltage); 2534 info->ext_disp_conn_info_offset = le16_to_cpu(info_v9->usExtDispConnInfoOffset); 2535 info->memory_type = info_v9->ucMemoryType; 2536 info->ma_channel_number = info_v9->ucUMAChannelNumber; 2537 info->gmc_restore_reset_time = le32_to_cpu(info_v9->ulGMCRestoreResetTime); 2538 2539 info->minimum_n_clk = le32_to_cpu(info_v9->ulNbpStateNClkFreq[0]); 2540 for (i = 1; i < 4; ++i) 2541 info->minimum_n_clk = 2542 info->minimum_n_clk < le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]) ? 2543 info->minimum_n_clk : le32_to_cpu(info_v9->ulNbpStateNClkFreq[i]); 2544 2545 info->idle_n_clk = le32_to_cpu(info_v9->ulIdleNClk); 2546 info->ddr_dll_power_up_time = le32_to_cpu(info_v9->ulDDR_DLL_PowerUpTime); 2547 info->ddr_pll_power_up_time = le32_to_cpu(info_v9->ulDDR_PLL_PowerUpTime); 2548 info->pcie_clk_ss_type = le16_to_cpu(info_v9->usPCIEClkSSType); 2549 info->lvds_ss_percentage = le16_to_cpu(info_v9->usLvdsSSPercentage); 2550 info->lvds_sspread_rate_in_10hz = le16_to_cpu(info_v9->usLvdsSSpreadRateIn10Hz); 2551 info->hdmi_ss_percentage = le16_to_cpu(info_v9->usHDMISSPercentage); 2552 info->hdmi_sspread_rate_in_10hz = le16_to_cpu(info_v9->usHDMISSpreadRateIn10Hz); 2553 info->dvi_ss_percentage = le16_to_cpu(info_v9->usDVISSPercentage); 2554 info->dvi_sspread_rate_in_10_hz = le16_to_cpu(info_v9->usDVISSpreadRateIn10Hz); 2555 2556 info->max_lvds_pclk_freq_in_single_link = 2557 le16_to_cpu(info_v9->usMaxLVDSPclkFreqInSingleLink); 2558 info->lvds_misc = info_v9->ucLvdsMisc; 2559 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms = 2560 info_v9->ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 2561 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms = 2562 info_v9->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 2563 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms = 2564 info_v9->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 2565 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms = 2566 info_v9->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 2567 info->lvds_pwr_off_seq_de_to_dig_on_in4ms = 2568 info_v9->ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 2569 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms = 2570 info_v9->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 2571 info->lvds_off_to_on_delay_in_4ms = 2572 info_v9->ucLVDSOffToOnDelay_in4Ms; 2573 info->lvds_bit_depth_control_val = 2574 le32_to_cpu(info_v9->ulLCDBitDepthControlVal); 2575 2576 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) { 2577 /* Convert [10KHz] into [KHz] */ 2578 info->avail_s_clk[i].supported_s_clk = 2579 le32_to_cpu(info_v9->sAvail_SCLK[i].ulSupportedSCLK) * 10; 2580 info->avail_s_clk[i].voltage_index = 2581 le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageIndex); 2582 info->avail_s_clk[i].voltage_id = 2583 le16_to_cpu(info_v9->sAvail_SCLK[i].usVoltageID); 2584 } 2585 2586 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) { 2587 info->ext_disp_conn_info.gu_id[i] = 2588 info_v9->sExtDispConnInfo.ucGuid[i]; 2589 } 2590 2591 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) { 2592 info->ext_disp_conn_info.path[i].device_connector_id = 2593 object_id_from_bios_object_id( 2594 le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceConnector)); 2595 2596 info->ext_disp_conn_info.path[i].ext_encoder_obj_id = 2597 object_id_from_bios_object_id( 2598 le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usExtEncoderObjId)); 2599 2600 info->ext_disp_conn_info.path[i].device_tag = 2601 le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceTag); 2602 info->ext_disp_conn_info.path[i].device_acpi_enum = 2603 le16_to_cpu(info_v9->sExtDispConnInfo.sPath[i].usDeviceACPIEnum); 2604 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index = 2605 info_v9->sExtDispConnInfo.sPath[i].ucExtAUXDDCLutIndex; 2606 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index = 2607 info_v9->sExtDispConnInfo.sPath[i].ucExtHPDPINLutIndex; 2608 info->ext_disp_conn_info.path[i].channel_mapping.raw = 2609 info_v9->sExtDispConnInfo.sPath[i].ucChannelMapping; 2610 } 2611 info->ext_disp_conn_info.checksum = 2612 info_v9->sExtDispConnInfo.ucChecksum; 2613 2614 return BP_RESULT_OK; 2615 } 2616 2617 /* 2618 * construct_integrated_info 2619 * 2620 * @brief 2621 * Get integrated BIOS information based on table revision 2622 * 2623 * @param 2624 * bios_parser *bp - [in]BIOS parser handler to get master data table 2625 * integrated_info *info - [out] store and output integrated info 2626 * 2627 * return: 2628 * enum bp_result - BP_RESULT_OK if information is available, 2629 * BP_RESULT_BADBIOSTABLE otherwise. 2630 */ 2631 static enum bp_result construct_integrated_info( 2632 struct bios_parser *bp, 2633 struct integrated_info *info) 2634 { 2635 enum bp_result result = BP_RESULT_BADBIOSTABLE; 2636 2637 ATOM_COMMON_TABLE_HEADER *header; 2638 struct atom_data_revision revision; 2639 2640 if (bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo) { 2641 header = GET_IMAGE(ATOM_COMMON_TABLE_HEADER, 2642 bp->master_data_tbl->ListOfDataTables.IntegratedSystemInfo); 2643 2644 get_atom_data_table_revision(header, &revision); 2645 2646 /* Don't need to check major revision as they are all 1 */ 2647 switch (revision.minor) { 2648 case 8: 2649 result = get_integrated_info_v8(bp, info); 2650 break; 2651 case 9: 2652 result = get_integrated_info_v9(bp, info); 2653 break; 2654 default: 2655 return result; 2656 2657 } 2658 } 2659 2660 /* Sort voltage table from low to high*/ 2661 if (result == BP_RESULT_OK) { 2662 int32_t i; 2663 int32_t j; 2664 2665 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 2666 for (j = i; j > 0; --j) { 2667 if ( 2668 info->disp_clk_voltage[j].max_supported_clk < 2669 info->disp_clk_voltage[j-1].max_supported_clk) { 2670 /* swap j and j - 1*/ 2671 swap(info->disp_clk_voltage[j - 1], 2672 info->disp_clk_voltage[j]); 2673 } 2674 } 2675 } 2676 2677 } 2678 2679 return result; 2680 } 2681 2682 static struct integrated_info *bios_parser_create_integrated_info( 2683 struct dc_bios *dcb) 2684 { 2685 struct bios_parser *bp = BP_FROM_DCB(dcb); 2686 struct integrated_info *info; 2687 2688 info = kzalloc_obj(struct integrated_info); 2689 2690 if (info == NULL) { 2691 ASSERT_CRITICAL(0); 2692 return NULL; 2693 } 2694 2695 if (construct_integrated_info(bp, info) == BP_RESULT_OK) 2696 return info; 2697 2698 kfree(info); 2699 2700 return NULL; 2701 } 2702 2703 static enum bp_result update_slot_layout_info(struct dc_bios *dcb, 2704 unsigned int i, 2705 struct slot_layout_info *slot_layout_info, 2706 unsigned int record_offset) 2707 { 2708 unsigned int j; 2709 struct bios_parser *bp; 2710 ATOM_BRACKET_LAYOUT_RECORD *record; 2711 ATOM_COMMON_RECORD_HEADER *record_header; 2712 enum bp_result result = BP_RESULT_NORECORD; 2713 2714 bp = BP_FROM_DCB(dcb); 2715 record = NULL; 2716 record_header = NULL; 2717 2718 for (;;) { 2719 2720 record_header = GET_IMAGE(ATOM_COMMON_RECORD_HEADER, record_offset); 2721 if (record_header == NULL) { 2722 result = BP_RESULT_BADBIOSTABLE; 2723 break; 2724 } 2725 2726 /* the end of the list */ 2727 if (record_header->ucRecordType == 0xff || 2728 record_header->ucRecordSize == 0) { 2729 break; 2730 } 2731 2732 if (record_header->ucRecordType == 2733 ATOM_BRACKET_LAYOUT_RECORD_TYPE && 2734 struct_size(record, asConnInfo, 1) 2735 <= record_header->ucRecordSize) { 2736 record = (ATOM_BRACKET_LAYOUT_RECORD *) 2737 (record_header); 2738 result = BP_RESULT_OK; 2739 break; 2740 } 2741 2742 record_offset += record_header->ucRecordSize; 2743 } 2744 2745 /* return if the record not found */ 2746 if (result != BP_RESULT_OK) 2747 return result; 2748 2749 /* get slot sizes */ 2750 slot_layout_info->length = record->ucLength; 2751 slot_layout_info->width = record->ucWidth; 2752 2753 /* get info for each connector in the slot */ 2754 slot_layout_info->num_of_connectors = record->ucConnNum; 2755 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) { 2756 slot_layout_info->connectors[j].connector_type = 2757 (enum connector_layout_type) 2758 (record->asConnInfo[j].ucConnectorType); 2759 switch (record->asConnInfo[j].ucConnectorType) { 2760 case CONNECTOR_TYPE_DVI_D: 2761 slot_layout_info->connectors[j].connector_type = 2762 CONNECTOR_LAYOUT_TYPE_DVI_D; 2763 slot_layout_info->connectors[j].length = 2764 CONNECTOR_SIZE_DVI; 2765 break; 2766 2767 case CONNECTOR_TYPE_HDMI: 2768 slot_layout_info->connectors[j].connector_type = 2769 CONNECTOR_LAYOUT_TYPE_HDMI; 2770 slot_layout_info->connectors[j].length = 2771 CONNECTOR_SIZE_HDMI; 2772 break; 2773 2774 case CONNECTOR_TYPE_DISPLAY_PORT: 2775 slot_layout_info->connectors[j].connector_type = 2776 CONNECTOR_LAYOUT_TYPE_DP; 2777 slot_layout_info->connectors[j].length = 2778 CONNECTOR_SIZE_DP; 2779 break; 2780 2781 case CONNECTOR_TYPE_MINI_DISPLAY_PORT: 2782 slot_layout_info->connectors[j].connector_type = 2783 CONNECTOR_LAYOUT_TYPE_MINI_DP; 2784 slot_layout_info->connectors[j].length = 2785 CONNECTOR_SIZE_MINI_DP; 2786 break; 2787 2788 default: 2789 slot_layout_info->connectors[j].connector_type = 2790 CONNECTOR_LAYOUT_TYPE_UNKNOWN; 2791 slot_layout_info->connectors[j].length = 2792 CONNECTOR_SIZE_UNKNOWN; 2793 } 2794 2795 slot_layout_info->connectors[j].position = 2796 record->asConnInfo[j].ucPosition; 2797 slot_layout_info->connectors[j].connector_id = 2798 object_id_from_bios_object_id( 2799 record->asConnInfo[j].usConnectorObjectId); 2800 } 2801 return result; 2802 } 2803 2804 2805 static enum bp_result get_bracket_layout_record(struct dc_bios *dcb, 2806 unsigned int bracket_layout_id, 2807 struct slot_layout_info *slot_layout_info) 2808 { 2809 unsigned int i; 2810 unsigned int record_offset; 2811 struct bios_parser *bp; 2812 enum bp_result result; 2813 ATOM_OBJECT *object; 2814 ATOM_OBJECT_TABLE *object_table; 2815 unsigned int genericTableOffset; 2816 2817 bp = BP_FROM_DCB(dcb); 2818 object = NULL; 2819 if (slot_layout_info == NULL) { 2820 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n"); 2821 return BP_RESULT_BADINPUT; 2822 } 2823 2824 2825 genericTableOffset = bp->object_info_tbl_offset + 2826 bp->object_info_tbl.v1_3->usMiscObjectTableOffset; 2827 object_table = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base, 2828 genericTableOffset, 2829 struct_size(object_table, asObjects, 1))); 2830 if (!object_table) 2831 return BP_RESULT_FAILURE; 2832 2833 result = BP_RESULT_NORECORD; 2834 for (i = 0; i < object_table->ucNumberOfObjects; ++i) { 2835 2836 if (bracket_layout_id == 2837 object_table->asObjects[i].usObjectID) { 2838 2839 object = &object_table->asObjects[i]; 2840 record_offset = object->usRecordOffset + 2841 bp->object_info_tbl_offset; 2842 2843 result = update_slot_layout_info(dcb, i, 2844 slot_layout_info, record_offset); 2845 break; 2846 } 2847 } 2848 return result; 2849 } 2850 2851 static enum bp_result bios_get_board_layout_info( 2852 struct dc_bios *dcb, 2853 struct board_layout_info *board_layout_info) 2854 { 2855 unsigned int i; 2856 struct bios_parser *bp; 2857 enum bp_result record_result; 2858 2859 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = { 2860 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1, 2861 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2, 2862 0, 0 2863 }; 2864 2865 bp = BP_FROM_DCB(dcb); 2866 2867 if (board_layout_info == NULL) { 2868 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n"); 2869 return BP_RESULT_BADINPUT; 2870 } 2871 2872 board_layout_info->num_of_slots = 0; 2873 2874 for (i = 0; i < MAX_BOARD_SLOTS; ++i) { 2875 record_result = get_bracket_layout_record(dcb, 2876 slot_index_to_vbios_id[i], 2877 &board_layout_info->slots[i]); 2878 2879 if (record_result == BP_RESULT_NORECORD && i > 0) 2880 break; /* no more slots present in bios */ 2881 else if (record_result != BP_RESULT_OK) 2882 return record_result; /* fail */ 2883 2884 ++board_layout_info->num_of_slots; 2885 } 2886 2887 /* all data is valid */ 2888 board_layout_info->is_number_of_slots_valid = 1; 2889 board_layout_info->is_slots_size_valid = 1; 2890 board_layout_info->is_connector_offsets_valid = 1; 2891 board_layout_info->is_connector_lengths_valid = 1; 2892 2893 return BP_RESULT_OK; 2894 } 2895 2896 /******************************************************************************/ 2897 2898 static const struct dc_vbios_funcs vbios_funcs = { 2899 .get_connectors_number = bios_parser_get_connectors_number, 2900 2901 .get_connector_id = bios_parser_get_connector_id, 2902 2903 .get_src_obj = bios_parser_get_src_obj, 2904 2905 .get_i2c_info = bios_parser_get_i2c_info, 2906 2907 .get_hpd_info = bios_parser_get_hpd_info, 2908 2909 .get_device_tag = bios_parser_get_device_tag, 2910 2911 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info, 2912 2913 .get_ss_entry_number = bios_parser_get_ss_entry_number, 2914 2915 .get_embedded_panel_info = bios_parser_get_embedded_panel_info, 2916 2917 .get_gpio_pin_info = bios_parser_get_gpio_pin_info, 2918 2919 .get_encoder_cap_info = bios_parser_get_encoder_cap_info, 2920 2921 /* bios scratch register communication */ 2922 .is_accelerated_mode = bios_is_accelerated_mode, 2923 2924 .set_scratch_critical_state = bios_parser_set_scratch_critical_state, 2925 2926 .is_device_id_supported = bios_parser_is_device_id_supported, 2927 2928 /* COMMANDS */ 2929 .select_crtc_source = bios_parser_select_crtc_source, 2930 2931 .encoder_control = bios_parser_encoder_control, 2932 2933 .external_encoder_control = bios_parser_external_encoder_control, 2934 2935 .dac_load_detection = bios_parser_dac_load_detection, 2936 2937 .transmitter_control = bios_parser_transmitter_control, 2938 2939 .enable_crtc = bios_parser_enable_crtc, 2940 2941 .adjust_pixel_clock = bios_parser_adjust_pixel_clock, 2942 2943 .set_pixel_clock = bios_parser_set_pixel_clock, 2944 2945 .set_dce_clock = bios_parser_set_dce_clock, 2946 2947 .enable_spread_spectrum_on_ppll = bios_parser_enable_spread_spectrum_on_ppll, 2948 2949 .program_crtc_timing = bios_parser_program_crtc_timing, /* still use. should probably retire and program directly */ 2950 2951 .program_display_engine_pll = bios_parser_program_display_engine_pll, 2952 2953 .enable_disp_power_gating = bios_parser_enable_disp_power_gating, 2954 2955 /* SW init and patch */ 2956 2957 .bios_parser_destroy = bios_parser_destroy, 2958 2959 .get_board_layout_info = bios_get_board_layout_info, 2960 2961 .get_atom_dc_golden_table = NULL 2962 }; 2963 2964 static bool bios_parser_construct( 2965 struct bios_parser *bp, 2966 struct bp_init_data *init, 2967 enum dce_version dce_version) 2968 { 2969 uint16_t *rom_header_offset = NULL; 2970 ATOM_ROM_HEADER *rom_header = NULL; 2971 ATOM_OBJECT_HEADER *object_info_tbl; 2972 struct atom_data_revision tbl_rev = {0}; 2973 2974 if (!init) 2975 return false; 2976 2977 if (!init->bios) 2978 return false; 2979 2980 bp->base.funcs = &vbios_funcs; 2981 bp->base.bios = init->bios; 2982 bp->base.bios_size = bp->base.bios[BIOS_IMAGE_SIZE_OFFSET] * BIOS_IMAGE_SIZE_UNIT; 2983 2984 bp->base.ctx = init->ctx; 2985 bp->base.bios_local_image = NULL; 2986 2987 rom_header_offset = 2988 GET_IMAGE(uint16_t, OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER); 2989 2990 if (!rom_header_offset) 2991 return false; 2992 2993 rom_header = GET_IMAGE(ATOM_ROM_HEADER, *rom_header_offset); 2994 2995 if (!rom_header) 2996 return false; 2997 2998 get_atom_data_table_revision(&rom_header->sHeader, &tbl_rev); 2999 if (tbl_rev.major >= 2 && tbl_rev.minor >= 2) 3000 return false; 3001 3002 bp->master_data_tbl = 3003 GET_IMAGE(ATOM_MASTER_DATA_TABLE, 3004 rom_header->usMasterDataTableOffset); 3005 3006 if (!bp->master_data_tbl) 3007 return false; 3008 3009 bp->object_info_tbl_offset = DATA_TABLES(Object_Header); 3010 3011 if (!bp->object_info_tbl_offset) 3012 return false; 3013 3014 object_info_tbl = 3015 GET_IMAGE(ATOM_OBJECT_HEADER, bp->object_info_tbl_offset); 3016 3017 if (!object_info_tbl) 3018 return false; 3019 3020 get_atom_data_table_revision(&object_info_tbl->sHeader, 3021 &bp->object_info_tbl.revision); 3022 3023 if (bp->object_info_tbl.revision.major == 1 3024 && bp->object_info_tbl.revision.minor >= 3) { 3025 ATOM_OBJECT_HEADER_V3 *tbl_v3; 3026 3027 tbl_v3 = GET_IMAGE(ATOM_OBJECT_HEADER_V3, 3028 bp->object_info_tbl_offset); 3029 if (!tbl_v3) 3030 return false; 3031 3032 bp->object_info_tbl.v1_3 = tbl_v3; 3033 } else if (bp->object_info_tbl.revision.major == 1 3034 && bp->object_info_tbl.revision.minor >= 1) 3035 bp->object_info_tbl.v1_1 = object_info_tbl; 3036 else 3037 return false; 3038 3039 dal_bios_parser_init_cmd_tbl(bp); 3040 dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version); 3041 3042 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); 3043 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK; 3044 3045 return true; 3046 } 3047 3048 /******************************************************************************/ 3049