1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 54 /* Forward declarations */ 55 struct amdgpu_device; 56 struct drm_device; 57 struct amdgpu_dm_irq_handler_data; 58 struct dc; 59 60 struct common_irq_params { 61 struct amdgpu_device *adev; 62 enum dc_irq_source irq_src; 63 }; 64 65 /** 66 * struct irq_list_head - Linked-list for low context IRQ handlers. 67 * 68 * @head: The list_head within &struct handler_data 69 * @work: A work_struct containing the deferred handler work 70 */ 71 struct irq_list_head { 72 struct list_head head; 73 /* In case this interrupt needs post-processing, 'work' will be queued*/ 74 struct work_struct work; 75 }; 76 77 /** 78 * struct dm_compressor_info - Buffer info used by frame buffer compression 79 * @cpu_addr: MMIO cpu addr 80 * @bo_ptr: Pointer to the buffer object 81 * @gpu_addr: MMIO gpu addr 82 */ 83 struct dm_comressor_info { 84 void *cpu_addr; 85 struct amdgpu_bo *bo_ptr; 86 uint64_t gpu_addr; 87 }; 88 89 /** 90 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 91 * @min_input_signal: minimum possible input in range 0-255 92 * @max_input_signal: maximum possible input in range 0-255 93 * @caps_valid: true if these values are from the ACPI interface 94 */ 95 struct amdgpu_dm_backlight_caps { 96 int min_input_signal; 97 int max_input_signal; 98 bool caps_valid; 99 }; 100 101 /** 102 * struct amdgpu_display_manager - Central amdgpu display manager device 103 * 104 * @dc: Display Core control structure 105 * @adev: AMDGPU base driver structure 106 * @ddev: DRM base driver structure 107 * @display_indexes_num: Max number of display streams supported 108 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 109 * @backlight_dev: Backlight control device 110 * @cached_state: Caches device atomic state for suspend/resume 111 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 112 */ 113 struct amdgpu_display_manager { 114 115 struct dc *dc; 116 117 /** 118 * @cgs_device: 119 * 120 * The Common Graphics Services device. It provides an interface for 121 * accessing registers. 122 */ 123 struct cgs_device *cgs_device; 124 125 struct amdgpu_device *adev; 126 struct drm_device *ddev; 127 u16 display_indexes_num; 128 129 /** 130 * @atomic_obj 131 * 132 * In combination with &dm_atomic_state it helps manage 133 * global atomic state that doesn't map cleanly into existing 134 * drm resources, like &dc_context. 135 */ 136 struct drm_private_obj atomic_obj; 137 138 /** 139 * @dc_lock: 140 * 141 * Guards access to DC functions that can issue register write 142 * sequences. 143 */ 144 struct mutex dc_lock; 145 146 /** 147 * @irq_handler_list_low_tab: 148 * 149 * Low priority IRQ handler table. 150 * 151 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 152 * source. Low priority IRQ handlers are deferred to a workqueue to be 153 * processed. Hence, they can sleep. 154 * 155 * Note that handlers are called in the same order as they were 156 * registered (FIFO). 157 */ 158 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 159 160 /** 161 * @irq_handler_list_high_tab: 162 * 163 * High priority IRQ handler table. 164 * 165 * It is a n*m table, same as &irq_handler_list_low_tab. However, 166 * handlers in this table are not deferred and are called immediately. 167 */ 168 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 169 170 /** 171 * @pflip_params: 172 * 173 * Page flip IRQ parameters, passed to registered handlers when 174 * triggered. 175 */ 176 struct common_irq_params 177 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 178 179 /** 180 * @vblank_params: 181 * 182 * Vertical blanking IRQ parameters, passed to registered handlers when 183 * triggered. 184 */ 185 struct common_irq_params 186 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 187 188 /** 189 * @vupdate_params: 190 * 191 * Vertical update IRQ parameters, passed to registered handlers when 192 * triggered. 193 */ 194 struct common_irq_params 195 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 196 197 spinlock_t irq_handler_list_table_lock; 198 199 struct backlight_device *backlight_dev; 200 201 const struct dc_link *backlight_link; 202 struct amdgpu_dm_backlight_caps backlight_caps; 203 204 struct mod_freesync *freesync_module; 205 206 struct drm_atomic_state *cached_state; 207 208 struct dm_comressor_info compressor; 209 210 const struct firmware *fw_dmcu; 211 uint32_t dmcu_fw_version; 212 }; 213 214 struct amdgpu_dm_connector { 215 216 struct drm_connector base; 217 uint32_t connector_id; 218 219 /* we need to mind the EDID between detect 220 and get modes due to analog/digital/tvencoder */ 221 struct edid *edid; 222 223 /* shared with amdgpu */ 224 struct amdgpu_hpd hpd; 225 226 /* number of modes generated from EDID at 'dc_sink' */ 227 int num_modes; 228 229 /* The 'old' sink - before an HPD. 230 * The 'current' sink is in dc_link->sink. */ 231 struct dc_sink *dc_sink; 232 struct dc_link *dc_link; 233 struct dc_sink *dc_em_sink; 234 235 /* DM only */ 236 struct drm_dp_mst_topology_mgr mst_mgr; 237 struct amdgpu_dm_dp_aux dm_dp_aux; 238 struct drm_dp_mst_port *port; 239 struct amdgpu_dm_connector *mst_port; 240 struct amdgpu_encoder *mst_encoder; 241 242 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 243 struct amdgpu_i2c_adapter *i2c; 244 245 /* Monitor range limits */ 246 int min_vfreq ; 247 int max_vfreq ; 248 int pixel_clock_mhz; 249 250 struct mutex hpd_lock; 251 252 bool fake_enable; 253 #ifdef CONFIG_DEBUG_FS 254 uint32_t debugfs_dpcd_address; 255 uint32_t debugfs_dpcd_size; 256 #endif 257 }; 258 259 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 260 261 extern const struct amdgpu_ip_block_version dm_ip_block; 262 263 struct amdgpu_framebuffer; 264 struct amdgpu_display_manager; 265 struct dc_validation_set; 266 struct dc_plane_state; 267 268 struct dm_plane_state { 269 struct drm_plane_state base; 270 struct dc_plane_state *dc_state; 271 }; 272 273 struct dm_crtc_state { 274 struct drm_crtc_state base; 275 struct dc_stream_state *stream; 276 277 int active_planes; 278 bool interrupts_enabled; 279 280 int crc_skip_count; 281 bool crc_enabled; 282 283 bool freesync_timing_changed; 284 bool freesync_vrr_info_changed; 285 286 bool vrr_supported; 287 struct mod_freesync_config freesync_config; 288 struct mod_vrr_params vrr_params; 289 struct dc_info_packet vrr_infopacket; 290 291 int abm_level; 292 }; 293 294 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 295 296 struct dm_atomic_state { 297 struct drm_private_state base; 298 299 struct dc_state *context; 300 }; 301 302 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 303 304 struct dm_connector_state { 305 struct drm_connector_state base; 306 307 enum amdgpu_rmx_type scaling; 308 uint8_t underscan_vborder; 309 uint8_t underscan_hborder; 310 bool underscan_enable; 311 bool freesync_capable; 312 uint8_t abm_level; 313 }; 314 315 #define to_dm_connector_state(x)\ 316 container_of((x), struct dm_connector_state, base) 317 318 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 319 struct drm_connector_state * 320 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 321 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 322 struct drm_connector_state *state, 323 struct drm_property *property, 324 uint64_t val); 325 326 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 327 const struct drm_connector_state *state, 328 struct drm_property *property, 329 uint64_t *val); 330 331 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 332 333 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 334 struct amdgpu_dm_connector *aconnector, 335 int connector_type, 336 struct dc_link *link, 337 int link_index); 338 339 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 340 struct drm_display_mode *mode); 341 342 void dm_restore_drm_connector_state(struct drm_device *dev, 343 struct drm_connector *connector); 344 345 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 346 struct edid *edid); 347 348 /* amdgpu_dm_crc.c */ 349 #ifdef CONFIG_DEBUG_FS 350 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); 351 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, 352 const char *src_name, 353 size_t *values_cnt); 354 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 355 #else 356 #define amdgpu_dm_crtc_set_crc_source NULL 357 #define amdgpu_dm_crtc_verify_crc_source NULL 358 #define amdgpu_dm_crtc_handle_crc_irq(x) 359 #endif 360 361 #define MAX_COLOR_LUT_ENTRIES 4096 362 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 363 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 364 365 void amdgpu_dm_init_color_mod(void); 366 int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, 367 struct dc_plane_state *dc_plane_state); 368 void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); 369 int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); 370 371 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 372 373 #endif /* __AMDGPU_DM_H__ */ 374