1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 59 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 62 /* 63 * Maximum HDMI HPD debounce delay in milliseconds 64 */ 65 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 66 /* 67 #include "include/amdgpu_dal_power_if.h" 68 #include "amdgpu_dm_irq.h" 69 */ 70 71 #include "irq_types.h" 72 #include "signal_types.h" 73 #include "amdgpu_dm_crc.h" 74 #include "mod_info_packet.h" 75 struct aux_payload; 76 struct set_config_cmd_payload; 77 enum aux_return_code_type; 78 enum set_config_status; 79 80 /* Forward declarations */ 81 struct amdgpu_device; 82 struct amdgpu_crtc; 83 struct drm_device; 84 struct dc; 85 struct amdgpu_bo; 86 struct dmub_srv; 87 struct dc_plane_state; 88 struct dmub_notification; 89 struct dmub_cmd_fused_request; 90 91 struct amd_vsdb_block { 92 unsigned char ieee_id[3]; 93 unsigned char version; 94 unsigned char feature_caps; 95 }; 96 97 struct common_irq_params { 98 struct amdgpu_device *adev; 99 enum dc_irq_source irq_src; 100 atomic64_t previous_timestamp; 101 }; 102 103 /** 104 * struct dm_compressor_info - Buffer info used by frame buffer compression 105 * @cpu_addr: MMIO cpu addr 106 * @bo_ptr: Pointer to the buffer object 107 * @gpu_addr: MMIO gpu addr 108 */ 109 struct dm_compressor_info { 110 void *cpu_addr; 111 struct amdgpu_bo *bo_ptr; 112 uint64_t gpu_addr; 113 }; 114 115 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 116 117 /** 118 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 119 * 120 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 121 * @dmub_notify: notification for callback function 122 * @adev: amdgpu_device pointer 123 */ 124 struct dmub_hpd_work { 125 struct work_struct handle_hpd_work; 126 struct dmub_notification *dmub_notify; 127 struct amdgpu_device *adev; 128 }; 129 130 /** 131 * struct vblank_control_work - Work data for vblank control 132 * @work: Kernel work data for the work event 133 * @dm: amdgpu display manager device 134 * @acrtc: amdgpu CRTC instance for which the event has occurred 135 * @stream: DC stream for which the event has occurred 136 * @enable: true if enabling vblank 137 */ 138 struct vblank_control_work { 139 struct work_struct work; 140 struct amdgpu_display_manager *dm; 141 struct amdgpu_crtc *acrtc; 142 struct dc_stream_state *stream; 143 bool enable; 144 }; 145 146 /** 147 * struct idle_workqueue - Work data for periodic action in idle 148 * @work: Kernel work data for the work event 149 * @dm: amdgpu display manager device 150 * @enable: true if idle worker is enabled 151 * @running: true if idle worker is running 152 */ 153 struct idle_workqueue { 154 struct work_struct work; 155 struct amdgpu_display_manager *dm; 156 bool enable; 157 bool running; 158 }; 159 160 /** 161 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 162 * @work: Kernel work data for the work event 163 * @adev: amdgpu_device back pointer 164 * @stream: DC stream associated with the crtc 165 * @adjust: DC CRTC timing adjust to be applied to the crtc 166 */ 167 struct vupdate_offload_work { 168 struct work_struct work; 169 struct amdgpu_device *adev; 170 struct dc_stream_state *stream; 171 struct dc_crtc_timing_adjust *adjust; 172 }; 173 174 #define MAX_LUMINANCE_DATA_POINTS 99 175 176 /** 177 * struct amdgpu_dm_luminance_data - Custom luminance data 178 * @luminance: Luminance in percent 179 * @input_signal: Input signal in range 0-255 180 */ 181 struct amdgpu_dm_luminance_data { 182 u8 luminance; 183 u8 input_signal; 184 } __packed; 185 186 /** 187 * struct amdgpu_dm_backlight_caps - Information about backlight 188 * 189 * Describe the backlight support for ACPI or eDP AUX. 190 */ 191 struct amdgpu_dm_backlight_caps { 192 /** 193 * @ext_caps: Keep the data struct with all the information about the 194 * display support for HDR. 195 */ 196 union dpcd_sink_ext_caps *ext_caps; 197 /** 198 * @aux_min_input_signal: Min brightness value supported by the display 199 */ 200 u32 aux_min_input_signal; 201 /** 202 * @aux_max_input_signal: Max brightness value supported by the display 203 * in nits. 204 */ 205 u32 aux_max_input_signal; 206 /** 207 * @min_input_signal: minimum possible input in range 0-255. 208 */ 209 int min_input_signal; 210 /** 211 * @max_input_signal: maximum possible input in range 0-255. 212 */ 213 int max_input_signal; 214 /** 215 * @caps_valid: true if these values are from the ACPI interface. 216 */ 217 bool caps_valid; 218 /** 219 * @aux_support: Describes if the display supports AUX backlight. 220 */ 221 bool aux_support; 222 /** 223 * @brightness_mask: After deriving brightness, OR it with this mask. 224 * Workaround for panels with issues with certain brightness values. 225 */ 226 u32 brightness_mask; 227 /** 228 * @ac_level: the default brightness if booted on AC 229 */ 230 u8 ac_level; 231 /** 232 * @dc_level: the default brightness if booted on DC 233 */ 234 u8 dc_level; 235 /** 236 * @data_points: the number of custom luminance data points 237 */ 238 u8 data_points; 239 /** 240 * @luminance_data: custom luminance data 241 */ 242 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 243 }; 244 245 /** 246 * struct dal_allocation - Tracks mapped FB memory for SMU communication 247 * @list: list of dal allocations 248 * @bo: GPU buffer object 249 * @cpu_ptr: CPU virtual address of the GPU buffer object 250 * @gpu_addr: GPU virtual address of the GPU buffer object 251 */ 252 struct dal_allocation { 253 struct list_head list; 254 struct amdgpu_bo *bo; 255 void *cpu_ptr; 256 u64 gpu_addr; 257 }; 258 259 /** 260 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 261 * offload work 262 */ 263 struct hpd_rx_irq_offload_work_queue { 264 /** 265 * @wq: workqueue structure to queue offload work. 266 */ 267 struct workqueue_struct *wq; 268 /** 269 * @offload_lock: To protect fields of offload work queue. 270 */ 271 spinlock_t offload_lock; 272 /** 273 * @is_handling_link_loss: Used to prevent inserting link loss event when 274 * we're handling link loss 275 */ 276 bool is_handling_link_loss; 277 /** 278 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 279 * ready event when we're already handling mst message ready event 280 */ 281 bool is_handling_mst_msg_rdy_event; 282 /** 283 * @aconnector: The aconnector that this work queue is attached to 284 */ 285 struct amdgpu_dm_connector *aconnector; 286 }; 287 288 /** 289 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 290 */ 291 struct hpd_rx_irq_offload_work { 292 /** 293 * @work: offload work 294 */ 295 struct work_struct work; 296 /** 297 * @data: reference irq data which is used while handling offload work 298 */ 299 union hpd_irq_data data; 300 /** 301 * @offload_wq: offload work queue that this work is queued to 302 */ 303 struct hpd_rx_irq_offload_work_queue *offload_wq; 304 /** 305 * @adev: amdgpu_device pointer 306 */ 307 struct amdgpu_device *adev; 308 }; 309 310 /** 311 * struct amdgpu_display_manager - Central amdgpu display manager device 312 * 313 * @dc: Display Core control structure 314 * @adev: AMDGPU base driver structure 315 * @ddev: DRM base driver structure 316 * @display_indexes_num: Max number of display streams supported 317 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 318 * @backlight_dev: Backlight control device 319 * @backlight_link: Link on which to control backlight 320 * @backlight_caps: Capabilities of the backlight device 321 * @freesync_module: Module handling freesync calculations 322 * @hdcp_workqueue: AMDGPU content protection queue 323 * @fw_dmcu: Reference to DMCU firmware 324 * @dmcu_fw_version: Version of the DMCU firmware 325 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 326 * @cached_state: Caches device atomic state for suspend/resume 327 * @cached_dc_state: Cached state of content streams 328 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 329 * @force_timing_sync: set via debugfs. When set, indicates that all connected 330 * displays will be forced to synchronize. 331 * @dmcub_trace_event_en: enable dmcub trace events 332 * @dmub_outbox_params: DMUB Outbox parameters 333 * @num_of_edps: number of backlight eDPs 334 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 335 * driver when true 336 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 337 * transfers are done 338 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 339 */ 340 struct amdgpu_display_manager { 341 342 struct dc *dc; 343 344 /** 345 * @dmub_srv: 346 * 347 * DMUB service, used for controlling the DMUB on hardware 348 * that supports it. The pointer to the dmub_srv will be 349 * NULL on hardware that does not support it. 350 */ 351 struct dmub_srv *dmub_srv; 352 353 /** 354 * @dmub_notify: 355 * 356 * Notification from DMUB. 357 */ 358 359 struct dmub_notification *dmub_notify; 360 361 /** 362 * @dmub_callback: 363 * 364 * Callback functions to handle notification from DMUB. 365 */ 366 367 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 368 369 /** 370 * @dmub_thread_offload: 371 * 372 * Flag to indicate if callback is offload. 373 */ 374 375 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 376 377 /** 378 * @dmub_fb_info: 379 * 380 * Framebuffer regions for the DMUB. 381 */ 382 struct dmub_srv_fb_info *dmub_fb_info; 383 384 /** 385 * @dmub_fw: 386 * 387 * DMUB firmware, required on hardware that has DMUB support. 388 */ 389 const struct firmware *dmub_fw; 390 391 /** 392 * @dmub_bo: 393 * 394 * Buffer object for the DMUB. 395 */ 396 struct amdgpu_bo *dmub_bo; 397 398 /** 399 * @dmub_bo_gpu_addr: 400 * 401 * GPU virtual address for the DMUB buffer object. 402 */ 403 u64 dmub_bo_gpu_addr; 404 405 /** 406 * @dmub_bo_cpu_addr: 407 * 408 * CPU address for the DMUB buffer object. 409 */ 410 void *dmub_bo_cpu_addr; 411 412 /** 413 * @dmcub_fw_version: 414 * 415 * DMCUB firmware version. 416 */ 417 uint32_t dmcub_fw_version; 418 419 /** 420 * @cgs_device: 421 * 422 * The Common Graphics Services device. It provides an interface for 423 * accessing registers. 424 */ 425 struct cgs_device *cgs_device; 426 427 struct amdgpu_device *adev; 428 struct drm_device *ddev; 429 u16 display_indexes_num; 430 431 /** 432 * @atomic_obj: 433 * 434 * In combination with &dm_atomic_state it helps manage 435 * global atomic state that doesn't map cleanly into existing 436 * drm resources, like &dc_context. 437 */ 438 struct drm_private_obj atomic_obj; 439 440 /** 441 * @dc_lock: 442 * 443 * Guards access to DC functions that can issue register write 444 * sequences. 445 */ 446 struct mutex dc_lock; 447 448 /** 449 * @audio_lock: 450 * 451 * Guards access to audio instance changes. 452 */ 453 struct mutex audio_lock; 454 455 /** 456 * @audio_component: 457 * 458 * Used to notify ELD changes to sound driver. 459 */ 460 struct drm_audio_component *audio_component; 461 462 /** 463 * @audio_registered: 464 * 465 * True if the audio component has been registered 466 * successfully, false otherwise. 467 */ 468 bool audio_registered; 469 470 /** 471 * @irq_handler_list_low_tab: 472 * 473 * Low priority IRQ handler table. 474 * 475 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 476 * source. Low priority IRQ handlers are deferred to a workqueue to be 477 * processed. Hence, they can sleep. 478 * 479 * Note that handlers are called in the same order as they were 480 * registered (FIFO). 481 */ 482 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 483 484 /** 485 * @irq_handler_list_high_tab: 486 * 487 * High priority IRQ handler table. 488 * 489 * It is a n*m table, same as &irq_handler_list_low_tab. However, 490 * handlers in this table are not deferred and are called immediately. 491 */ 492 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 493 494 /** 495 * @pflip_params: 496 * 497 * Page flip IRQ parameters, passed to registered handlers when 498 * triggered. 499 */ 500 struct common_irq_params 501 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 502 503 /** 504 * @vblank_params: 505 * 506 * Vertical blanking IRQ parameters, passed to registered handlers when 507 * triggered. 508 */ 509 struct common_irq_params 510 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 511 512 /** 513 * @vline0_params: 514 * 515 * OTG vertical interrupt0 IRQ parameters, passed to registered 516 * handlers when triggered. 517 */ 518 struct common_irq_params 519 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 520 521 /** 522 * @vupdate_params: 523 * 524 * Vertical update IRQ parameters, passed to registered handlers when 525 * triggered. 526 */ 527 struct common_irq_params 528 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 529 530 /** 531 * @dmub_trace_params: 532 * 533 * DMUB trace event IRQ parameters, passed to registered handlers when 534 * triggered. 535 */ 536 struct common_irq_params 537 dmub_trace_params[1]; 538 539 struct common_irq_params 540 dmub_outbox_params[1]; 541 542 spinlock_t irq_handler_list_table_lock; 543 544 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 545 546 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 547 548 uint8_t num_of_edps; 549 550 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 551 552 struct mod_freesync *freesync_module; 553 struct hdcp_workqueue *hdcp_workqueue; 554 555 /** 556 * @vblank_control_workqueue: 557 * 558 * Deferred work for vblank control events. 559 */ 560 struct workqueue_struct *vblank_control_workqueue; 561 562 /** 563 * @idle_workqueue: 564 * 565 * Periodic work for idle events. 566 */ 567 struct idle_workqueue *idle_workqueue; 568 569 struct drm_atomic_state *cached_state; 570 struct dc_state *cached_dc_state; 571 572 struct dm_compressor_info compressor; 573 574 const struct firmware *fw_dmcu; 575 uint32_t dmcu_fw_version; 576 /** 577 * @soc_bounding_box: 578 * 579 * gpu_info FW provided soc bounding box struct or 0 if not 580 * available in FW 581 */ 582 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 583 584 /** 585 * @active_vblank_irq_count: 586 * 587 * number of currently active vblank irqs 588 */ 589 uint32_t active_vblank_irq_count; 590 591 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 592 /** 593 * @secure_display_ctx: 594 * 595 * Store secure display relevant info. e.g. the ROI information 596 * , the work_struct to command dmub, etc. 597 */ 598 struct secure_display_context secure_display_ctx; 599 #endif 600 /** 601 * @hpd_rx_offload_wq: 602 * 603 * Work queue to offload works of hpd_rx_irq 604 */ 605 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 606 /** 607 * @mst_encoders: 608 * 609 * fake encoders used for DP MST. 610 */ 611 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 612 bool force_timing_sync; 613 bool disable_hpd_irq; 614 bool dmcub_trace_event_en; 615 /** 616 * @da_list: 617 * 618 * DAL fb memory allocation list, for communication with SMU. 619 */ 620 struct list_head da_list; 621 struct completion dmub_aux_transfer_done; 622 struct workqueue_struct *delayed_hpd_wq; 623 624 /** 625 * @brightness: 626 * 627 * cached backlight values. 628 */ 629 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 630 /** 631 * @actual_brightness: 632 * 633 * last successfully applied backlight values. 634 */ 635 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 636 637 /** 638 * @aux_hpd_discon_quirk: 639 * 640 * quirk for hpd discon while aux is on-going. 641 * occurred on certain intel platform 642 */ 643 bool aux_hpd_discon_quirk; 644 645 /** 646 * @edp0_on_dp1_quirk: 647 * 648 * quirk for platforms that put edp0 on DP1. 649 */ 650 bool edp0_on_dp1_quirk; 651 652 /** 653 * @dpia_aux_lock: 654 * 655 * Guards access to DPIA AUX 656 */ 657 struct mutex dpia_aux_lock; 658 659 /** 660 * @bb_from_dmub: 661 * 662 * Bounding box data read from dmub during early initialization for DCN4+ 663 * Data is stored as a byte array that should be casted to the appropriate bb struct 664 */ 665 void *bb_from_dmub; 666 667 /** 668 * @oem_i2c: 669 * 670 * OEM i2c bus 671 */ 672 struct amdgpu_i2c_adapter *oem_i2c; 673 674 /** 675 * @fused_io: 676 * 677 * dmub fused io interface 678 */ 679 struct fused_io_sync { 680 struct completion replied; 681 char reply_data[0x40]; // Cannot include dmub_cmd here 682 } fused_io[8]; 683 }; 684 685 enum dsc_clock_force_state { 686 DSC_CLK_FORCE_DEFAULT = 0, 687 DSC_CLK_FORCE_ENABLE, 688 DSC_CLK_FORCE_DISABLE, 689 }; 690 691 struct dsc_preferred_settings { 692 enum dsc_clock_force_state dsc_force_enable; 693 uint32_t dsc_num_slices_v; 694 uint32_t dsc_num_slices_h; 695 uint32_t dsc_bits_per_pixel; 696 bool dsc_force_disable_passthrough; 697 }; 698 699 enum mst_progress_status { 700 MST_STATUS_DEFAULT = 0, 701 MST_PROBE = BIT(0), 702 MST_REMOTE_EDID = BIT(1), 703 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 704 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 705 }; 706 707 /** 708 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 709 * 710 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 711 * struct is useful to keep track of the display-specific information about 712 * FreeSync. 713 */ 714 struct amdgpu_hdmi_vsdb_info { 715 /** 716 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 717 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 718 */ 719 unsigned int amd_vsdb_version; 720 721 /** 722 * @freesync_supported: FreeSync Supported. 723 */ 724 bool freesync_supported; 725 726 /** 727 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 728 */ 729 unsigned int min_refresh_rate_hz; 730 731 /** 732 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 733 */ 734 unsigned int max_refresh_rate_hz; 735 736 /** 737 * @replay_mode: Replay supported 738 */ 739 bool replay_mode; 740 }; 741 742 struct amdgpu_dm_connector { 743 744 struct drm_connector base; 745 uint32_t connector_id; 746 int bl_idx; 747 748 struct cec_notifier *notifier; 749 750 /* we need to mind the EDID between detect 751 and get modes due to analog/digital/tvencoder */ 752 const struct drm_edid *drm_edid; 753 754 /* shared with amdgpu */ 755 struct amdgpu_hpd hpd; 756 757 /* number of modes generated from EDID at 'dc_sink' */ 758 int num_modes; 759 760 /* The 'old' sink - before an HPD. 761 * The 'current' sink is in dc_link->sink. */ 762 struct dc_sink *dc_sink; 763 struct dc_link *dc_link; 764 765 /** 766 * @dc_em_sink: Reference to the emulated (virtual) sink. 767 */ 768 struct dc_sink *dc_em_sink; 769 770 /* DM only */ 771 struct drm_dp_mst_topology_mgr mst_mgr; 772 struct amdgpu_dm_dp_aux dm_dp_aux; 773 struct drm_dp_mst_port *mst_output_port; 774 struct amdgpu_dm_connector *mst_root; 775 struct drm_dp_aux *dsc_aux; 776 uint32_t mst_local_bw; 777 uint16_t vc_full_pbn; 778 struct mutex handle_mst_msg_ready; 779 780 /* branch device specific data */ 781 uint32_t branch_ieee_oui; 782 783 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 784 struct amdgpu_i2c_adapter *i2c; 785 786 /* Monitor range limits */ 787 /** 788 * @min_vfreq: Minimal frequency supported by the display in Hz. This 789 * value is set to zero when there is no FreeSync support. 790 */ 791 int min_vfreq; 792 793 /** 794 * @max_vfreq: Maximum frequency supported by the display in Hz. This 795 * value is set to zero when there is no FreeSync support. 796 */ 797 int max_vfreq ; 798 799 /* Audio instance - protected by audio_lock. */ 800 int audio_inst; 801 802 struct mutex hpd_lock; 803 804 bool fake_enable; 805 bool force_yuv420_output; 806 bool force_yuv422_output; 807 struct dsc_preferred_settings dsc_settings; 808 union dp_downstream_port_present mst_downstream_port_present; 809 /* Cached display modes */ 810 struct drm_display_mode freesync_vid_base; 811 812 int sr_skip_count; 813 bool disallow_edp_enter_psr; 814 815 /* Record progress status of mst*/ 816 uint8_t mst_status; 817 818 /* Automated testing */ 819 bool timing_changed; 820 struct dc_crtc_timing *timing_requested; 821 822 /* Adaptive Sync */ 823 bool pack_sdp_v1_3; 824 enum adaptive_sync_type as_type; 825 struct amdgpu_hdmi_vsdb_info vsdb_info; 826 827 /* HDMI HPD debounce support */ 828 unsigned int hdmi_hpd_debounce_delay_ms; 829 struct delayed_work hdmi_hpd_debounce_work; 830 struct dc_sink *hdmi_prev_sink; 831 }; 832 833 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 834 uint8_t flags, bool set) 835 { 836 if (set) 837 *status |= flags; 838 else 839 *status &= ~flags; 840 } 841 842 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 843 844 struct amdgpu_dm_wb_connector { 845 struct drm_writeback_connector base; 846 struct dc_link *link; 847 }; 848 849 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 850 851 extern const struct amdgpu_ip_block_version dm_ip_block; 852 853 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 854 * 855 * It includes standardized transfer functions and pure power functions. The 856 * transfer function coefficients are available at modules/color/color_gamma.c 857 */ 858 enum amdgpu_transfer_function { 859 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 860 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 861 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 862 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 863 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 864 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 865 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 866 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 867 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 868 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 869 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 870 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 871 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 872 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 873 AMDGPU_TRANSFER_FUNCTION_COUNT 874 }; 875 876 struct dm_plane_state { 877 struct drm_plane_state base; 878 struct dc_plane_state *dc_state; 879 880 /* Plane color mgmt */ 881 /** 882 * @degamma_lut: 883 * 884 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 885 * blending operations. It's usually applied to linearize input space. 886 * The blob (if not NULL) is an array of &struct drm_color_lut. 887 */ 888 struct drm_property_blob *degamma_lut; 889 /** 890 * @degamma_tf: 891 * 892 * Predefined transfer function to tell DC driver the input space to 893 * linearize. 894 */ 895 enum amdgpu_transfer_function degamma_tf; 896 /** 897 * @hdr_mult: 898 * 899 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 900 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 901 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 902 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 903 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 904 * S31.32 sign-magnitude. 905 * 906 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 907 * TF is needed for any subsequent linear-to-non-linear transforms. 908 */ 909 __u64 hdr_mult; 910 /** 911 * @ctm: 912 * 913 * Color transformation matrix. The blob (if not NULL) is a &struct 914 * drm_color_ctm_3x4. 915 */ 916 struct drm_property_blob *ctm; 917 /** 918 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 919 * array of &struct drm_color_lut. 920 */ 921 struct drm_property_blob *shaper_lut; 922 /** 923 * @shaper_tf: 924 * 925 * Predefined transfer function to delinearize color space. 926 */ 927 enum amdgpu_transfer_function shaper_tf; 928 /** 929 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 930 * &struct drm_color_lut. 931 */ 932 struct drm_property_blob *lut3d; 933 /** 934 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 935 * array of &struct drm_color_lut. 936 */ 937 struct drm_property_blob *blend_lut; 938 /** 939 * @blend_tf: 940 * 941 * Pre-defined transfer function for converting plane pixel data before 942 * applying blend LUT. 943 */ 944 enum amdgpu_transfer_function blend_tf; 945 }; 946 947 enum amdgpu_dm_cursor_mode { 948 DM_CURSOR_NATIVE_MODE = 0, 949 DM_CURSOR_OVERLAY_MODE, 950 }; 951 952 struct dm_crtc_state { 953 struct drm_crtc_state base; 954 struct dc_stream_state *stream; 955 956 bool cm_has_degamma; 957 bool cm_is_degamma_srgb; 958 959 bool mpo_requested; 960 961 int update_type; 962 int active_planes; 963 964 int crc_skip_count; 965 966 bool freesync_vrr_info_changed; 967 968 bool dsc_force_changed; 969 bool vrr_supported; 970 struct mod_freesync_config freesync_config; 971 struct dc_info_packet vrr_infopacket; 972 973 int abm_level; 974 975 /** 976 * @regamma_tf: 977 * 978 * Pre-defined transfer function for converting internal FB -> wire 979 * encoding. 980 */ 981 enum amdgpu_transfer_function regamma_tf; 982 983 enum amdgpu_dm_cursor_mode cursor_mode; 984 }; 985 986 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 987 988 struct dm_atomic_state { 989 struct drm_private_state base; 990 991 struct dc_state *context; 992 }; 993 994 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 995 996 struct dm_connector_state { 997 struct drm_connector_state base; 998 999 enum amdgpu_rmx_type scaling; 1000 uint8_t underscan_vborder; 1001 uint8_t underscan_hborder; 1002 bool underscan_enable; 1003 bool freesync_capable; 1004 bool update_hdcp; 1005 bool abm_sysfs_forbidden; 1006 uint8_t abm_level; 1007 int vcpi_slots; 1008 uint64_t pbn; 1009 }; 1010 1011 #define to_dm_connector_state(x)\ 1012 container_of((x), struct dm_connector_state, base) 1013 1014 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1015 struct drm_connector_state * 1016 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1017 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1018 struct drm_connector_state *state, 1019 struct drm_property *property, 1020 uint64_t val); 1021 1022 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1023 const struct drm_connector_state *state, 1024 struct drm_property *property, 1025 uint64_t *val); 1026 1027 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1028 1029 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1030 struct amdgpu_dm_connector *aconnector, 1031 int connector_type, 1032 struct dc_link *link, 1033 int link_index); 1034 1035 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1036 const struct drm_display_mode *mode); 1037 1038 void dm_restore_drm_connector_state(struct drm_device *dev, 1039 struct drm_connector *connector); 1040 1041 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1042 const struct drm_edid *drm_edid); 1043 1044 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1045 1046 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1047 #define MAX_COLOR_3DLUT_SIZE 17 1048 #define MAX_COLOR_3DLUT_BITDEPTH 12 1049 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1050 struct drm_plane_state *plane_state); 1051 /* 1D LUT size */ 1052 #define MAX_COLOR_LUT_ENTRIES 4096 1053 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1054 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1055 1056 void amdgpu_dm_init_color_mod(void); 1057 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1058 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1059 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1060 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1061 bool check_only); 1062 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1063 struct drm_plane_state *plane_state, 1064 struct dc_plane_state *dc_plane_state); 1065 1066 void amdgpu_dm_update_connector_after_detect( 1067 struct amdgpu_dm_connector *aconnector); 1068 1069 void populate_hdmi_info_from_connector(struct drm_hdmi_info *info, 1070 struct dc_edid_caps *edid_caps); 1071 1072 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1073 1074 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1075 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1076 1077 bool amdgpu_dm_execute_fused_io( 1078 struct amdgpu_device *dev, 1079 struct dc_link *link, 1080 union dmub_rb_cmd *commands, 1081 uint8_t count, 1082 uint32_t timeout_us 1083 ); 1084 1085 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1086 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1087 1088 struct dc_stream_state * 1089 create_validate_stream_for_sink(struct drm_connector *connector, 1090 const struct drm_display_mode *drm_mode, 1091 const struct dm_connector_state *dm_state, 1092 const struct dc_stream_state *old_stream); 1093 1094 int dm_atomic_get_state(struct drm_atomic_state *state, 1095 struct dm_atomic_state **dm_state); 1096 1097 struct drm_connector * 1098 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1099 struct drm_crtc *crtc); 1100 1101 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1102 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1103 1104 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1105 enum dc_gpu_mem_alloc_type type, 1106 size_t size, 1107 long long *addr); 1108 void dm_free_gpu_mem(struct amdgpu_device *adev, 1109 enum dc_gpu_mem_alloc_type type, 1110 void *addr); 1111 1112 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1113 1114 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1115 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1116 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1117 1118 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1119 1120 #endif /* __AMDGPU_DM_H__ */ 1121