1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 #include "link_service_types.h" 35 #include <drm/drm_writeback.h> 36 37 /* 38 * This file contains the definition for amdgpu_display_manager 39 * and its API for amdgpu driver's use. 40 * This component provides all the display related functionality 41 * and this is the only component that calls DAL API. 42 * The API contained here intended for amdgpu driver use. 43 * The API that is called directly from KMS framework is located 44 * in amdgpu_dm_kms.h file 45 */ 46 47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 48 49 #define AMDGPU_DM_MAX_CRTC 6 50 51 #define AMDGPU_DM_MAX_NUM_EDP 2 52 53 #define AMDGPU_DMUB_NOTIFICATION_MAX 7 54 55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 58 59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 60 61 /* 62 #include "include/amdgpu_dal_power_if.h" 63 #include "amdgpu_dm_irq.h" 64 */ 65 66 #include "irq_types.h" 67 #include "signal_types.h" 68 #include "amdgpu_dm_crc.h" 69 #include "mod_info_packet.h" 70 struct aux_payload; 71 struct set_config_cmd_payload; 72 enum aux_return_code_type; 73 enum set_config_status; 74 75 /* Forward declarations */ 76 struct amdgpu_device; 77 struct amdgpu_crtc; 78 struct drm_device; 79 struct dc; 80 struct amdgpu_bo; 81 struct dmub_srv; 82 struct dc_plane_state; 83 struct dmub_notification; 84 85 struct amd_vsdb_block { 86 unsigned char ieee_id[3]; 87 unsigned char version; 88 unsigned char feature_caps; 89 }; 90 91 struct common_irq_params { 92 struct amdgpu_device *adev; 93 enum dc_irq_source irq_src; 94 atomic64_t previous_timestamp; 95 }; 96 97 /** 98 * struct dm_compressor_info - Buffer info used by frame buffer compression 99 * @cpu_addr: MMIO cpu addr 100 * @bo_ptr: Pointer to the buffer object 101 * @gpu_addr: MMIO gpu addr 102 */ 103 struct dm_compressor_info { 104 void *cpu_addr; 105 struct amdgpu_bo *bo_ptr; 106 uint64_t gpu_addr; 107 }; 108 109 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 110 111 /** 112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 113 * 114 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 115 * @dmub_notify: notification for callback function 116 * @adev: amdgpu_device pointer 117 */ 118 struct dmub_hpd_work { 119 struct work_struct handle_hpd_work; 120 struct dmub_notification *dmub_notify; 121 struct amdgpu_device *adev; 122 }; 123 124 /** 125 * struct vblank_control_work - Work data for vblank control 126 * @work: Kernel work data for the work event 127 * @dm: amdgpu display manager device 128 * @acrtc: amdgpu CRTC instance for which the event has occurred 129 * @stream: DC stream for which the event has occurred 130 * @enable: true if enabling vblank 131 */ 132 struct vblank_control_work { 133 struct work_struct work; 134 struct amdgpu_display_manager *dm; 135 struct amdgpu_crtc *acrtc; 136 struct dc_stream_state *stream; 137 bool enable; 138 }; 139 140 /** 141 * struct idle_workqueue - Work data for periodic action in idle 142 * @work: Kernel work data for the work event 143 * @dm: amdgpu display manager device 144 * @enable: true if idle worker is enabled 145 * @running: true if idle worker is running 146 */ 147 struct idle_workqueue { 148 struct work_struct work; 149 struct amdgpu_display_manager *dm; 150 bool enable; 151 bool running; 152 }; 153 154 #define MAX_LUMINANCE_DATA_POINTS 99 155 156 /** 157 * struct amdgpu_dm_luminance_data - Custom luminance data 158 * @luminance: Luminance in percent 159 * @input_signal: Input signal in range 0-255 160 */ 161 struct amdgpu_dm_luminance_data { 162 u8 luminance; 163 u8 input_signal; 164 } __packed; 165 166 /** 167 * struct amdgpu_dm_backlight_caps - Information about backlight 168 * 169 * Describe the backlight support for ACPI or eDP AUX. 170 */ 171 struct amdgpu_dm_backlight_caps { 172 /** 173 * @ext_caps: Keep the data struct with all the information about the 174 * display support for HDR. 175 */ 176 union dpcd_sink_ext_caps *ext_caps; 177 /** 178 * @aux_min_input_signal: Min brightness value supported by the display 179 */ 180 u32 aux_min_input_signal; 181 /** 182 * @aux_max_input_signal: Max brightness value supported by the display 183 * in nits. 184 */ 185 u32 aux_max_input_signal; 186 /** 187 * @min_input_signal: minimum possible input in range 0-255. 188 */ 189 int min_input_signal; 190 /** 191 * @max_input_signal: maximum possible input in range 0-255. 192 */ 193 int max_input_signal; 194 /** 195 * @caps_valid: true if these values are from the ACPI interface. 196 */ 197 bool caps_valid; 198 /** 199 * @aux_support: Describes if the display supports AUX backlight. 200 */ 201 bool aux_support; 202 /** 203 * @ac_level: the default brightness if booted on AC 204 */ 205 u8 ac_level; 206 /** 207 * @dc_level: the default brightness if booted on DC 208 */ 209 u8 dc_level; 210 /** 211 * @data_points: the number of custom luminance data points 212 */ 213 u8 data_points; 214 /** 215 * @luminance_data: custom luminance data 216 */ 217 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 218 }; 219 220 /** 221 * struct dal_allocation - Tracks mapped FB memory for SMU communication 222 * @list: list of dal allocations 223 * @bo: GPU buffer object 224 * @cpu_ptr: CPU virtual address of the GPU buffer object 225 * @gpu_addr: GPU virtual address of the GPU buffer object 226 */ 227 struct dal_allocation { 228 struct list_head list; 229 struct amdgpu_bo *bo; 230 void *cpu_ptr; 231 u64 gpu_addr; 232 }; 233 234 /** 235 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 236 * offload work 237 */ 238 struct hpd_rx_irq_offload_work_queue { 239 /** 240 * @wq: workqueue structure to queue offload work. 241 */ 242 struct workqueue_struct *wq; 243 /** 244 * @offload_lock: To protect fields of offload work queue. 245 */ 246 spinlock_t offload_lock; 247 /** 248 * @is_handling_link_loss: Used to prevent inserting link loss event when 249 * we're handling link loss 250 */ 251 bool is_handling_link_loss; 252 /** 253 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 254 * ready event when we're already handling mst message ready event 255 */ 256 bool is_handling_mst_msg_rdy_event; 257 /** 258 * @aconnector: The aconnector that this work queue is attached to 259 */ 260 struct amdgpu_dm_connector *aconnector; 261 }; 262 263 /** 264 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 265 */ 266 struct hpd_rx_irq_offload_work { 267 /** 268 * @work: offload work 269 */ 270 struct work_struct work; 271 /** 272 * @data: reference irq data which is used while handling offload work 273 */ 274 union hpd_irq_data data; 275 /** 276 * @offload_wq: offload work queue that this work is queued to 277 */ 278 struct hpd_rx_irq_offload_work_queue *offload_wq; 279 /** 280 * @adev: amdgpu_device pointer 281 */ 282 struct amdgpu_device *adev; 283 }; 284 285 /** 286 * struct amdgpu_display_manager - Central amdgpu display manager device 287 * 288 * @dc: Display Core control structure 289 * @adev: AMDGPU base driver structure 290 * @ddev: DRM base driver structure 291 * @display_indexes_num: Max number of display streams supported 292 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 293 * @backlight_dev: Backlight control device 294 * @backlight_link: Link on which to control backlight 295 * @backlight_caps: Capabilities of the backlight device 296 * @freesync_module: Module handling freesync calculations 297 * @hdcp_workqueue: AMDGPU content protection queue 298 * @fw_dmcu: Reference to DMCU firmware 299 * @dmcu_fw_version: Version of the DMCU firmware 300 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 301 * @cached_state: Caches device atomic state for suspend/resume 302 * @cached_dc_state: Cached state of content streams 303 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 304 * @force_timing_sync: set via debugfs. When set, indicates that all connected 305 * displays will be forced to synchronize. 306 * @dmcub_trace_event_en: enable dmcub trace events 307 * @dmub_outbox_params: DMUB Outbox parameters 308 * @num_of_edps: number of backlight eDPs 309 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 310 * driver when true 311 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 312 * transfers are done 313 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 314 */ 315 struct amdgpu_display_manager { 316 317 struct dc *dc; 318 319 /** 320 * @dmub_srv: 321 * 322 * DMUB service, used for controlling the DMUB on hardware 323 * that supports it. The pointer to the dmub_srv will be 324 * NULL on hardware that does not support it. 325 */ 326 struct dmub_srv *dmub_srv; 327 328 /** 329 * @dmub_notify: 330 * 331 * Notification from DMUB. 332 */ 333 334 struct dmub_notification *dmub_notify; 335 336 /** 337 * @dmub_callback: 338 * 339 * Callback functions to handle notification from DMUB. 340 */ 341 342 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 343 344 /** 345 * @dmub_thread_offload: 346 * 347 * Flag to indicate if callback is offload. 348 */ 349 350 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 351 352 /** 353 * @dmub_fb_info: 354 * 355 * Framebuffer regions for the DMUB. 356 */ 357 struct dmub_srv_fb_info *dmub_fb_info; 358 359 /** 360 * @dmub_fw: 361 * 362 * DMUB firmware, required on hardware that has DMUB support. 363 */ 364 const struct firmware *dmub_fw; 365 366 /** 367 * @dmub_bo: 368 * 369 * Buffer object for the DMUB. 370 */ 371 struct amdgpu_bo *dmub_bo; 372 373 /** 374 * @dmub_bo_gpu_addr: 375 * 376 * GPU virtual address for the DMUB buffer object. 377 */ 378 u64 dmub_bo_gpu_addr; 379 380 /** 381 * @dmub_bo_cpu_addr: 382 * 383 * CPU address for the DMUB buffer object. 384 */ 385 void *dmub_bo_cpu_addr; 386 387 /** 388 * @dmcub_fw_version: 389 * 390 * DMCUB firmware version. 391 */ 392 uint32_t dmcub_fw_version; 393 394 /** 395 * @cgs_device: 396 * 397 * The Common Graphics Services device. It provides an interface for 398 * accessing registers. 399 */ 400 struct cgs_device *cgs_device; 401 402 struct amdgpu_device *adev; 403 struct drm_device *ddev; 404 u16 display_indexes_num; 405 406 /** 407 * @atomic_obj: 408 * 409 * In combination with &dm_atomic_state it helps manage 410 * global atomic state that doesn't map cleanly into existing 411 * drm resources, like &dc_context. 412 */ 413 struct drm_private_obj atomic_obj; 414 415 /** 416 * @dc_lock: 417 * 418 * Guards access to DC functions that can issue register write 419 * sequences. 420 */ 421 struct mutex dc_lock; 422 423 /** 424 * @audio_lock: 425 * 426 * Guards access to audio instance changes. 427 */ 428 struct mutex audio_lock; 429 430 /** 431 * @audio_component: 432 * 433 * Used to notify ELD changes to sound driver. 434 */ 435 struct drm_audio_component *audio_component; 436 437 /** 438 * @audio_registered: 439 * 440 * True if the audio component has been registered 441 * successfully, false otherwise. 442 */ 443 bool audio_registered; 444 445 /** 446 * @irq_handler_list_low_tab: 447 * 448 * Low priority IRQ handler table. 449 * 450 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 451 * source. Low priority IRQ handlers are deferred to a workqueue to be 452 * processed. Hence, they can sleep. 453 * 454 * Note that handlers are called in the same order as they were 455 * registered (FIFO). 456 */ 457 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 458 459 /** 460 * @irq_handler_list_high_tab: 461 * 462 * High priority IRQ handler table. 463 * 464 * It is a n*m table, same as &irq_handler_list_low_tab. However, 465 * handlers in this table are not deferred and are called immediately. 466 */ 467 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 468 469 /** 470 * @pflip_params: 471 * 472 * Page flip IRQ parameters, passed to registered handlers when 473 * triggered. 474 */ 475 struct common_irq_params 476 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 477 478 /** 479 * @vblank_params: 480 * 481 * Vertical blanking IRQ parameters, passed to registered handlers when 482 * triggered. 483 */ 484 struct common_irq_params 485 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 486 487 /** 488 * @vline0_params: 489 * 490 * OTG vertical interrupt0 IRQ parameters, passed to registered 491 * handlers when triggered. 492 */ 493 struct common_irq_params 494 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 495 496 /** 497 * @vupdate_params: 498 * 499 * Vertical update IRQ parameters, passed to registered handlers when 500 * triggered. 501 */ 502 struct common_irq_params 503 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 504 505 /** 506 * @dmub_trace_params: 507 * 508 * DMUB trace event IRQ parameters, passed to registered handlers when 509 * triggered. 510 */ 511 struct common_irq_params 512 dmub_trace_params[1]; 513 514 struct common_irq_params 515 dmub_outbox_params[1]; 516 517 spinlock_t irq_handler_list_table_lock; 518 519 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 520 521 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 522 523 uint8_t num_of_edps; 524 525 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 526 527 struct mod_freesync *freesync_module; 528 struct hdcp_workqueue *hdcp_workqueue; 529 530 /** 531 * @vblank_control_workqueue: 532 * 533 * Deferred work for vblank control events. 534 */ 535 struct workqueue_struct *vblank_control_workqueue; 536 537 /** 538 * @idle_workqueue: 539 * 540 * Periodic work for idle events. 541 */ 542 struct idle_workqueue *idle_workqueue; 543 544 struct drm_atomic_state *cached_state; 545 struct dc_state *cached_dc_state; 546 547 struct dm_compressor_info compressor; 548 549 const struct firmware *fw_dmcu; 550 uint32_t dmcu_fw_version; 551 /** 552 * @soc_bounding_box: 553 * 554 * gpu_info FW provided soc bounding box struct or 0 if not 555 * available in FW 556 */ 557 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 558 559 /** 560 * @active_vblank_irq_count: 561 * 562 * number of currently active vblank irqs 563 */ 564 uint32_t active_vblank_irq_count; 565 566 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 567 /** 568 * @secure_display_ctx: 569 * 570 * Store secure display relevant info. e.g. the ROI information 571 * , the work_struct to command dmub, etc. 572 */ 573 struct secure_display_context secure_display_ctx; 574 #endif 575 /** 576 * @hpd_rx_offload_wq: 577 * 578 * Work queue to offload works of hpd_rx_irq 579 */ 580 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 581 /** 582 * @mst_encoders: 583 * 584 * fake encoders used for DP MST. 585 */ 586 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 587 bool force_timing_sync; 588 bool disable_hpd_irq; 589 bool dmcub_trace_event_en; 590 /** 591 * @da_list: 592 * 593 * DAL fb memory allocation list, for communication with SMU. 594 */ 595 struct list_head da_list; 596 struct completion dmub_aux_transfer_done; 597 struct workqueue_struct *delayed_hpd_wq; 598 599 /** 600 * @brightness: 601 * 602 * cached backlight values. 603 */ 604 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 605 /** 606 * @actual_brightness: 607 * 608 * last successfully applied backlight values. 609 */ 610 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 611 612 /** 613 * @aux_hpd_discon_quirk: 614 * 615 * quirk for hpd discon while aux is on-going. 616 * occurred on certain intel platform 617 */ 618 bool aux_hpd_discon_quirk; 619 620 /** 621 * @dpia_aux_lock: 622 * 623 * Guards access to DPIA AUX 624 */ 625 struct mutex dpia_aux_lock; 626 627 /** 628 * @bb_from_dmub: 629 * 630 * Bounding box data read from dmub during early initialization for DCN4+ 631 */ 632 struct dml2_soc_bb *bb_from_dmub; 633 634 /** 635 * @oem_i2c: 636 * 637 * OEM i2c bus 638 */ 639 struct amdgpu_i2c_adapter *oem_i2c; 640 }; 641 642 enum dsc_clock_force_state { 643 DSC_CLK_FORCE_DEFAULT = 0, 644 DSC_CLK_FORCE_ENABLE, 645 DSC_CLK_FORCE_DISABLE, 646 }; 647 648 struct dsc_preferred_settings { 649 enum dsc_clock_force_state dsc_force_enable; 650 uint32_t dsc_num_slices_v; 651 uint32_t dsc_num_slices_h; 652 uint32_t dsc_bits_per_pixel; 653 bool dsc_force_disable_passthrough; 654 }; 655 656 enum mst_progress_status { 657 MST_STATUS_DEFAULT = 0, 658 MST_PROBE = BIT(0), 659 MST_REMOTE_EDID = BIT(1), 660 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 661 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 662 }; 663 664 /** 665 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 666 * 667 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 668 * struct is useful to keep track of the display-specific information about 669 * FreeSync. 670 */ 671 struct amdgpu_hdmi_vsdb_info { 672 /** 673 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 674 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 675 */ 676 unsigned int amd_vsdb_version; 677 678 /** 679 * @freesync_supported: FreeSync Supported. 680 */ 681 bool freesync_supported; 682 683 /** 684 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 685 */ 686 unsigned int min_refresh_rate_hz; 687 688 /** 689 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 690 */ 691 unsigned int max_refresh_rate_hz; 692 693 /** 694 * @replay_mode: Replay supported 695 */ 696 bool replay_mode; 697 }; 698 699 struct amdgpu_dm_connector { 700 701 struct drm_connector base; 702 uint32_t connector_id; 703 int bl_idx; 704 705 struct cec_notifier *notifier; 706 707 /* we need to mind the EDID between detect 708 and get modes due to analog/digital/tvencoder */ 709 const struct drm_edid *drm_edid; 710 711 /* shared with amdgpu */ 712 struct amdgpu_hpd hpd; 713 714 /* number of modes generated from EDID at 'dc_sink' */ 715 int num_modes; 716 717 /* The 'old' sink - before an HPD. 718 * The 'current' sink is in dc_link->sink. */ 719 struct dc_sink *dc_sink; 720 struct dc_link *dc_link; 721 722 /** 723 * @dc_em_sink: Reference to the emulated (virtual) sink. 724 */ 725 struct dc_sink *dc_em_sink; 726 727 /* DM only */ 728 struct drm_dp_mst_topology_mgr mst_mgr; 729 struct amdgpu_dm_dp_aux dm_dp_aux; 730 struct drm_dp_mst_port *mst_output_port; 731 struct amdgpu_dm_connector *mst_root; 732 struct drm_dp_aux *dsc_aux; 733 uint32_t mst_local_bw; 734 uint16_t vc_full_pbn; 735 struct mutex handle_mst_msg_ready; 736 737 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 738 struct amdgpu_i2c_adapter *i2c; 739 740 /* Monitor range limits */ 741 /** 742 * @min_vfreq: Minimal frequency supported by the display in Hz. This 743 * value is set to zero when there is no FreeSync support. 744 */ 745 int min_vfreq; 746 747 /** 748 * @max_vfreq: Maximum frequency supported by the display in Hz. This 749 * value is set to zero when there is no FreeSync support. 750 */ 751 int max_vfreq ; 752 753 /* Audio instance - protected by audio_lock. */ 754 int audio_inst; 755 756 struct mutex hpd_lock; 757 758 bool fake_enable; 759 bool force_yuv420_output; 760 struct dsc_preferred_settings dsc_settings; 761 union dp_downstream_port_present mst_downstream_port_present; 762 /* Cached display modes */ 763 struct drm_display_mode freesync_vid_base; 764 765 int sr_skip_count; 766 bool disallow_edp_enter_psr; 767 768 /* Record progress status of mst*/ 769 uint8_t mst_status; 770 771 /* Automated testing */ 772 bool timing_changed; 773 struct dc_crtc_timing *timing_requested; 774 775 /* Adaptive Sync */ 776 bool pack_sdp_v1_3; 777 enum adaptive_sync_type as_type; 778 struct amdgpu_hdmi_vsdb_info vsdb_info; 779 }; 780 781 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 782 uint8_t flags, bool set) 783 { 784 if (set) 785 *status |= flags; 786 else 787 *status &= ~flags; 788 } 789 790 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 791 792 struct amdgpu_dm_wb_connector { 793 struct drm_writeback_connector base; 794 struct dc_link *link; 795 }; 796 797 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 798 799 extern const struct amdgpu_ip_block_version dm_ip_block; 800 801 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 802 * 803 * It includes standardized transfer functions and pure power functions. The 804 * transfer function coefficients are available at modules/color/color_gamma.c 805 */ 806 enum amdgpu_transfer_function { 807 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 808 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 809 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 810 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 811 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 812 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 813 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 814 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 815 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 816 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 817 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 818 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 819 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 820 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 821 AMDGPU_TRANSFER_FUNCTION_COUNT 822 }; 823 824 struct dm_plane_state { 825 struct drm_plane_state base; 826 struct dc_plane_state *dc_state; 827 828 /* Plane color mgmt */ 829 /** 830 * @degamma_lut: 831 * 832 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 833 * blending operations. It's usually applied to linearize input space. 834 * The blob (if not NULL) is an array of &struct drm_color_lut. 835 */ 836 struct drm_property_blob *degamma_lut; 837 /** 838 * @degamma_tf: 839 * 840 * Predefined transfer function to tell DC driver the input space to 841 * linearize. 842 */ 843 enum amdgpu_transfer_function degamma_tf; 844 /** 845 * @hdr_mult: 846 * 847 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 848 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 849 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 850 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 851 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 852 * S31.32 sign-magnitude. 853 * 854 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 855 * TF is needed for any subsequent linear-to-non-linear transforms. 856 */ 857 __u64 hdr_mult; 858 /** 859 * @ctm: 860 * 861 * Color transformation matrix. The blob (if not NULL) is a &struct 862 * drm_color_ctm_3x4. 863 */ 864 struct drm_property_blob *ctm; 865 /** 866 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 867 * array of &struct drm_color_lut. 868 */ 869 struct drm_property_blob *shaper_lut; 870 /** 871 * @shaper_tf: 872 * 873 * Predefined transfer function to delinearize color space. 874 */ 875 enum amdgpu_transfer_function shaper_tf; 876 /** 877 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 878 * &struct drm_color_lut. 879 */ 880 struct drm_property_blob *lut3d; 881 /** 882 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 883 * array of &struct drm_color_lut. 884 */ 885 struct drm_property_blob *blend_lut; 886 /** 887 * @blend_tf: 888 * 889 * Pre-defined transfer function for converting plane pixel data before 890 * applying blend LUT. 891 */ 892 enum amdgpu_transfer_function blend_tf; 893 }; 894 895 enum amdgpu_dm_cursor_mode { 896 DM_CURSOR_NATIVE_MODE = 0, 897 DM_CURSOR_OVERLAY_MODE, 898 }; 899 900 struct dm_crtc_state { 901 struct drm_crtc_state base; 902 struct dc_stream_state *stream; 903 904 bool cm_has_degamma; 905 bool cm_is_degamma_srgb; 906 907 bool mpo_requested; 908 909 int update_type; 910 int active_planes; 911 912 int crc_skip_count; 913 914 bool freesync_vrr_info_changed; 915 916 bool dsc_force_changed; 917 bool vrr_supported; 918 struct mod_freesync_config freesync_config; 919 struct dc_info_packet vrr_infopacket; 920 921 int abm_level; 922 923 /** 924 * @regamma_tf: 925 * 926 * Pre-defined transfer function for converting internal FB -> wire 927 * encoding. 928 */ 929 enum amdgpu_transfer_function regamma_tf; 930 931 enum amdgpu_dm_cursor_mode cursor_mode; 932 }; 933 934 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 935 936 struct dm_atomic_state { 937 struct drm_private_state base; 938 939 struct dc_state *context; 940 }; 941 942 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 943 944 struct dm_connector_state { 945 struct drm_connector_state base; 946 947 enum amdgpu_rmx_type scaling; 948 uint8_t underscan_vborder; 949 uint8_t underscan_hborder; 950 bool underscan_enable; 951 bool freesync_capable; 952 bool update_hdcp; 953 uint8_t abm_level; 954 int vcpi_slots; 955 uint64_t pbn; 956 }; 957 958 #define to_dm_connector_state(x)\ 959 container_of((x), struct dm_connector_state, base) 960 961 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 962 struct drm_connector_state * 963 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 964 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 965 struct drm_connector_state *state, 966 struct drm_property *property, 967 uint64_t val); 968 969 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 970 const struct drm_connector_state *state, 971 struct drm_property *property, 972 uint64_t *val); 973 974 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 975 976 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 977 struct amdgpu_dm_connector *aconnector, 978 int connector_type, 979 struct dc_link *link, 980 int link_index); 981 982 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 983 const struct drm_display_mode *mode); 984 985 void dm_restore_drm_connector_state(struct drm_device *dev, 986 struct drm_connector *connector); 987 988 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 989 const struct drm_edid *drm_edid); 990 991 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 992 993 /* 3D LUT max size is 17x17x17 (4913 entries) */ 994 #define MAX_COLOR_3DLUT_SIZE 17 995 #define MAX_COLOR_3DLUT_BITDEPTH 12 996 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 997 struct drm_plane_state *plane_state); 998 /* 1D LUT size */ 999 #define MAX_COLOR_LUT_ENTRIES 4096 1000 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1001 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1002 1003 void amdgpu_dm_init_color_mod(void); 1004 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1005 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1006 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1007 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1008 struct drm_plane_state *plane_state, 1009 struct dc_plane_state *dc_plane_state); 1010 1011 void amdgpu_dm_update_connector_after_detect( 1012 struct amdgpu_dm_connector *aconnector); 1013 1014 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1015 1016 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1017 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1018 1019 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1020 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1021 1022 struct dc_stream_state * 1023 create_validate_stream_for_sink(struct drm_connector *connector, 1024 const struct drm_display_mode *drm_mode, 1025 const struct dm_connector_state *dm_state, 1026 const struct dc_stream_state *old_stream); 1027 1028 int dm_atomic_get_state(struct drm_atomic_state *state, 1029 struct dm_atomic_state **dm_state); 1030 1031 struct drm_connector * 1032 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1033 struct drm_crtc *crtc); 1034 1035 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1036 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1037 1038 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1039 enum dc_gpu_mem_alloc_type type, 1040 size_t size, 1041 long long *addr); 1042 void dm_free_gpu_mem(struct amdgpu_device *adev, 1043 enum dc_gpu_mem_alloc_type type, 1044 void *addr); 1045 1046 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1047 1048 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1049 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1050 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1051 1052 #endif /* __AMDGPU_DM_H__ */ 1053