1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 #include "link_service_types.h" 35 #include <drm/drm_writeback.h> 36 37 /* 38 * This file contains the definition for amdgpu_display_manager 39 * and its API for amdgpu driver's use. 40 * This component provides all the display related functionality 41 * and this is the only component that calls DAL API. 42 * The API contained here intended for amdgpu driver use. 43 * The API that is called directly from KMS framework is located 44 * in amdgpu_dm_kms.h file 45 */ 46 47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 48 49 #define AMDGPU_DM_MAX_CRTC 6 50 51 #define AMDGPU_DM_MAX_NUM_EDP 2 52 53 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 54 55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 58 59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 60 61 /* 62 #include "include/amdgpu_dal_power_if.h" 63 #include "amdgpu_dm_irq.h" 64 */ 65 66 #include "irq_types.h" 67 #include "signal_types.h" 68 #include "amdgpu_dm_crc.h" 69 #include "mod_info_packet.h" 70 struct aux_payload; 71 struct set_config_cmd_payload; 72 enum aux_return_code_type; 73 enum set_config_status; 74 75 /* Forward declarations */ 76 struct amdgpu_device; 77 struct amdgpu_crtc; 78 struct drm_device; 79 struct dc; 80 struct amdgpu_bo; 81 struct dmub_srv; 82 struct dc_plane_state; 83 struct dmub_notification; 84 struct dmub_cmd_fused_request; 85 86 struct amd_vsdb_block { 87 unsigned char ieee_id[3]; 88 unsigned char version; 89 unsigned char feature_caps; 90 }; 91 92 struct common_irq_params { 93 struct amdgpu_device *adev; 94 enum dc_irq_source irq_src; 95 atomic64_t previous_timestamp; 96 }; 97 98 /** 99 * struct dm_compressor_info - Buffer info used by frame buffer compression 100 * @cpu_addr: MMIO cpu addr 101 * @bo_ptr: Pointer to the buffer object 102 * @gpu_addr: MMIO gpu addr 103 */ 104 struct dm_compressor_info { 105 void *cpu_addr; 106 struct amdgpu_bo *bo_ptr; 107 uint64_t gpu_addr; 108 }; 109 110 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 111 112 /** 113 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 114 * 115 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 116 * @dmub_notify: notification for callback function 117 * @adev: amdgpu_device pointer 118 */ 119 struct dmub_hpd_work { 120 struct work_struct handle_hpd_work; 121 struct dmub_notification *dmub_notify; 122 struct amdgpu_device *adev; 123 }; 124 125 /** 126 * struct vblank_control_work - Work data for vblank control 127 * @work: Kernel work data for the work event 128 * @dm: amdgpu display manager device 129 * @acrtc: amdgpu CRTC instance for which the event has occurred 130 * @stream: DC stream for which the event has occurred 131 * @enable: true if enabling vblank 132 */ 133 struct vblank_control_work { 134 struct work_struct work; 135 struct amdgpu_display_manager *dm; 136 struct amdgpu_crtc *acrtc; 137 struct dc_stream_state *stream; 138 bool enable; 139 }; 140 141 /** 142 * struct idle_workqueue - Work data for periodic action in idle 143 * @work: Kernel work data for the work event 144 * @dm: amdgpu display manager device 145 * @enable: true if idle worker is enabled 146 * @running: true if idle worker is running 147 */ 148 struct idle_workqueue { 149 struct work_struct work; 150 struct amdgpu_display_manager *dm; 151 bool enable; 152 bool running; 153 }; 154 155 #define MAX_LUMINANCE_DATA_POINTS 99 156 157 /** 158 * struct amdgpu_dm_luminance_data - Custom luminance data 159 * @luminance: Luminance in percent 160 * @input_signal: Input signal in range 0-255 161 */ 162 struct amdgpu_dm_luminance_data { 163 u8 luminance; 164 u8 input_signal; 165 } __packed; 166 167 /** 168 * struct amdgpu_dm_backlight_caps - Information about backlight 169 * 170 * Describe the backlight support for ACPI or eDP AUX. 171 */ 172 struct amdgpu_dm_backlight_caps { 173 /** 174 * @ext_caps: Keep the data struct with all the information about the 175 * display support for HDR. 176 */ 177 union dpcd_sink_ext_caps *ext_caps; 178 /** 179 * @aux_min_input_signal: Min brightness value supported by the display 180 */ 181 u32 aux_min_input_signal; 182 /** 183 * @aux_max_input_signal: Max brightness value supported by the display 184 * in nits. 185 */ 186 u32 aux_max_input_signal; 187 /** 188 * @min_input_signal: minimum possible input in range 0-255. 189 */ 190 int min_input_signal; 191 /** 192 * @max_input_signal: maximum possible input in range 0-255. 193 */ 194 int max_input_signal; 195 /** 196 * @caps_valid: true if these values are from the ACPI interface. 197 */ 198 bool caps_valid; 199 /** 200 * @aux_support: Describes if the display supports AUX backlight. 201 */ 202 bool aux_support; 203 /** 204 * @ac_level: the default brightness if booted on AC 205 */ 206 u8 ac_level; 207 /** 208 * @dc_level: the default brightness if booted on DC 209 */ 210 u8 dc_level; 211 /** 212 * @data_points: the number of custom luminance data points 213 */ 214 u8 data_points; 215 /** 216 * @luminance_data: custom luminance data 217 */ 218 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 219 }; 220 221 /** 222 * struct dal_allocation - Tracks mapped FB memory for SMU communication 223 * @list: list of dal allocations 224 * @bo: GPU buffer object 225 * @cpu_ptr: CPU virtual address of the GPU buffer object 226 * @gpu_addr: GPU virtual address of the GPU buffer object 227 */ 228 struct dal_allocation { 229 struct list_head list; 230 struct amdgpu_bo *bo; 231 void *cpu_ptr; 232 u64 gpu_addr; 233 }; 234 235 /** 236 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 237 * offload work 238 */ 239 struct hpd_rx_irq_offload_work_queue { 240 /** 241 * @wq: workqueue structure to queue offload work. 242 */ 243 struct workqueue_struct *wq; 244 /** 245 * @offload_lock: To protect fields of offload work queue. 246 */ 247 spinlock_t offload_lock; 248 /** 249 * @is_handling_link_loss: Used to prevent inserting link loss event when 250 * we're handling link loss 251 */ 252 bool is_handling_link_loss; 253 /** 254 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 255 * ready event when we're already handling mst message ready event 256 */ 257 bool is_handling_mst_msg_rdy_event; 258 /** 259 * @aconnector: The aconnector that this work queue is attached to 260 */ 261 struct amdgpu_dm_connector *aconnector; 262 }; 263 264 /** 265 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 266 */ 267 struct hpd_rx_irq_offload_work { 268 /** 269 * @work: offload work 270 */ 271 struct work_struct work; 272 /** 273 * @data: reference irq data which is used while handling offload work 274 */ 275 union hpd_irq_data data; 276 /** 277 * @offload_wq: offload work queue that this work is queued to 278 */ 279 struct hpd_rx_irq_offload_work_queue *offload_wq; 280 /** 281 * @adev: amdgpu_device pointer 282 */ 283 struct amdgpu_device *adev; 284 }; 285 286 /** 287 * struct amdgpu_display_manager - Central amdgpu display manager device 288 * 289 * @dc: Display Core control structure 290 * @adev: AMDGPU base driver structure 291 * @ddev: DRM base driver structure 292 * @display_indexes_num: Max number of display streams supported 293 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 294 * @backlight_dev: Backlight control device 295 * @backlight_link: Link on which to control backlight 296 * @backlight_caps: Capabilities of the backlight device 297 * @freesync_module: Module handling freesync calculations 298 * @hdcp_workqueue: AMDGPU content protection queue 299 * @fw_dmcu: Reference to DMCU firmware 300 * @dmcu_fw_version: Version of the DMCU firmware 301 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 302 * @cached_state: Caches device atomic state for suspend/resume 303 * @cached_dc_state: Cached state of content streams 304 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 305 * @force_timing_sync: set via debugfs. When set, indicates that all connected 306 * displays will be forced to synchronize. 307 * @dmcub_trace_event_en: enable dmcub trace events 308 * @dmub_outbox_params: DMUB Outbox parameters 309 * @num_of_edps: number of backlight eDPs 310 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 311 * driver when true 312 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 313 * transfers are done 314 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 315 */ 316 struct amdgpu_display_manager { 317 318 struct dc *dc; 319 320 /** 321 * @dmub_srv: 322 * 323 * DMUB service, used for controlling the DMUB on hardware 324 * that supports it. The pointer to the dmub_srv will be 325 * NULL on hardware that does not support it. 326 */ 327 struct dmub_srv *dmub_srv; 328 329 /** 330 * @dmub_notify: 331 * 332 * Notification from DMUB. 333 */ 334 335 struct dmub_notification *dmub_notify; 336 337 /** 338 * @dmub_callback: 339 * 340 * Callback functions to handle notification from DMUB. 341 */ 342 343 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 344 345 /** 346 * @dmub_thread_offload: 347 * 348 * Flag to indicate if callback is offload. 349 */ 350 351 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 352 353 /** 354 * @dmub_fb_info: 355 * 356 * Framebuffer regions for the DMUB. 357 */ 358 struct dmub_srv_fb_info *dmub_fb_info; 359 360 /** 361 * @dmub_fw: 362 * 363 * DMUB firmware, required on hardware that has DMUB support. 364 */ 365 const struct firmware *dmub_fw; 366 367 /** 368 * @dmub_bo: 369 * 370 * Buffer object for the DMUB. 371 */ 372 struct amdgpu_bo *dmub_bo; 373 374 /** 375 * @dmub_bo_gpu_addr: 376 * 377 * GPU virtual address for the DMUB buffer object. 378 */ 379 u64 dmub_bo_gpu_addr; 380 381 /** 382 * @dmub_bo_cpu_addr: 383 * 384 * CPU address for the DMUB buffer object. 385 */ 386 void *dmub_bo_cpu_addr; 387 388 /** 389 * @dmcub_fw_version: 390 * 391 * DMCUB firmware version. 392 */ 393 uint32_t dmcub_fw_version; 394 395 /** 396 * @cgs_device: 397 * 398 * The Common Graphics Services device. It provides an interface for 399 * accessing registers. 400 */ 401 struct cgs_device *cgs_device; 402 403 struct amdgpu_device *adev; 404 struct drm_device *ddev; 405 u16 display_indexes_num; 406 407 /** 408 * @atomic_obj: 409 * 410 * In combination with &dm_atomic_state it helps manage 411 * global atomic state that doesn't map cleanly into existing 412 * drm resources, like &dc_context. 413 */ 414 struct drm_private_obj atomic_obj; 415 416 /** 417 * @dc_lock: 418 * 419 * Guards access to DC functions that can issue register write 420 * sequences. 421 */ 422 struct mutex dc_lock; 423 424 /** 425 * @audio_lock: 426 * 427 * Guards access to audio instance changes. 428 */ 429 struct mutex audio_lock; 430 431 /** 432 * @audio_component: 433 * 434 * Used to notify ELD changes to sound driver. 435 */ 436 struct drm_audio_component *audio_component; 437 438 /** 439 * @audio_registered: 440 * 441 * True if the audio component has been registered 442 * successfully, false otherwise. 443 */ 444 bool audio_registered; 445 446 /** 447 * @irq_handler_list_low_tab: 448 * 449 * Low priority IRQ handler table. 450 * 451 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 452 * source. Low priority IRQ handlers are deferred to a workqueue to be 453 * processed. Hence, they can sleep. 454 * 455 * Note that handlers are called in the same order as they were 456 * registered (FIFO). 457 */ 458 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 459 460 /** 461 * @irq_handler_list_high_tab: 462 * 463 * High priority IRQ handler table. 464 * 465 * It is a n*m table, same as &irq_handler_list_low_tab. However, 466 * handlers in this table are not deferred and are called immediately. 467 */ 468 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 469 470 /** 471 * @pflip_params: 472 * 473 * Page flip IRQ parameters, passed to registered handlers when 474 * triggered. 475 */ 476 struct common_irq_params 477 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 478 479 /** 480 * @vblank_params: 481 * 482 * Vertical blanking IRQ parameters, passed to registered handlers when 483 * triggered. 484 */ 485 struct common_irq_params 486 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 487 488 /** 489 * @vline0_params: 490 * 491 * OTG vertical interrupt0 IRQ parameters, passed to registered 492 * handlers when triggered. 493 */ 494 struct common_irq_params 495 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 496 497 /** 498 * @vupdate_params: 499 * 500 * Vertical update IRQ parameters, passed to registered handlers when 501 * triggered. 502 */ 503 struct common_irq_params 504 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 505 506 /** 507 * @dmub_trace_params: 508 * 509 * DMUB trace event IRQ parameters, passed to registered handlers when 510 * triggered. 511 */ 512 struct common_irq_params 513 dmub_trace_params[1]; 514 515 struct common_irq_params 516 dmub_outbox_params[1]; 517 518 spinlock_t irq_handler_list_table_lock; 519 520 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 521 522 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 523 524 uint8_t num_of_edps; 525 526 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 527 528 struct mod_freesync *freesync_module; 529 struct hdcp_workqueue *hdcp_workqueue; 530 531 /** 532 * @vblank_control_workqueue: 533 * 534 * Deferred work for vblank control events. 535 */ 536 struct workqueue_struct *vblank_control_workqueue; 537 538 /** 539 * @idle_workqueue: 540 * 541 * Periodic work for idle events. 542 */ 543 struct idle_workqueue *idle_workqueue; 544 545 struct drm_atomic_state *cached_state; 546 struct dc_state *cached_dc_state; 547 548 struct dm_compressor_info compressor; 549 550 const struct firmware *fw_dmcu; 551 uint32_t dmcu_fw_version; 552 /** 553 * @soc_bounding_box: 554 * 555 * gpu_info FW provided soc bounding box struct or 0 if not 556 * available in FW 557 */ 558 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 559 560 /** 561 * @active_vblank_irq_count: 562 * 563 * number of currently active vblank irqs 564 */ 565 uint32_t active_vblank_irq_count; 566 567 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 568 /** 569 * @secure_display_ctx: 570 * 571 * Store secure display relevant info. e.g. the ROI information 572 * , the work_struct to command dmub, etc. 573 */ 574 struct secure_display_context secure_display_ctx; 575 #endif 576 /** 577 * @hpd_rx_offload_wq: 578 * 579 * Work queue to offload works of hpd_rx_irq 580 */ 581 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 582 /** 583 * @mst_encoders: 584 * 585 * fake encoders used for DP MST. 586 */ 587 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 588 bool force_timing_sync; 589 bool disable_hpd_irq; 590 bool dmcub_trace_event_en; 591 /** 592 * @da_list: 593 * 594 * DAL fb memory allocation list, for communication with SMU. 595 */ 596 struct list_head da_list; 597 struct completion dmub_aux_transfer_done; 598 struct workqueue_struct *delayed_hpd_wq; 599 600 /** 601 * @brightness: 602 * 603 * cached backlight values. 604 */ 605 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 606 /** 607 * @actual_brightness: 608 * 609 * last successfully applied backlight values. 610 */ 611 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 612 613 /** 614 * @aux_hpd_discon_quirk: 615 * 616 * quirk for hpd discon while aux is on-going. 617 * occurred on certain intel platform 618 */ 619 bool aux_hpd_discon_quirk; 620 621 /** 622 * @dpia_aux_lock: 623 * 624 * Guards access to DPIA AUX 625 */ 626 struct mutex dpia_aux_lock; 627 628 /** 629 * @bb_from_dmub: 630 * 631 * Bounding box data read from dmub during early initialization for DCN4+ 632 */ 633 struct dml2_soc_bb *bb_from_dmub; 634 635 /** 636 * @oem_i2c: 637 * 638 * OEM i2c bus 639 */ 640 struct amdgpu_i2c_adapter *oem_i2c; 641 642 struct fused_io_sync { 643 struct completion replied; 644 char reply_data[0x40]; // Cannot include dmub_cmd here 645 } fused_io[8]; 646 }; 647 648 enum dsc_clock_force_state { 649 DSC_CLK_FORCE_DEFAULT = 0, 650 DSC_CLK_FORCE_ENABLE, 651 DSC_CLK_FORCE_DISABLE, 652 }; 653 654 struct dsc_preferred_settings { 655 enum dsc_clock_force_state dsc_force_enable; 656 uint32_t dsc_num_slices_v; 657 uint32_t dsc_num_slices_h; 658 uint32_t dsc_bits_per_pixel; 659 bool dsc_force_disable_passthrough; 660 }; 661 662 enum mst_progress_status { 663 MST_STATUS_DEFAULT = 0, 664 MST_PROBE = BIT(0), 665 MST_REMOTE_EDID = BIT(1), 666 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 667 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 668 }; 669 670 /** 671 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 672 * 673 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 674 * struct is useful to keep track of the display-specific information about 675 * FreeSync. 676 */ 677 struct amdgpu_hdmi_vsdb_info { 678 /** 679 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 680 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 681 */ 682 unsigned int amd_vsdb_version; 683 684 /** 685 * @freesync_supported: FreeSync Supported. 686 */ 687 bool freesync_supported; 688 689 /** 690 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 691 */ 692 unsigned int min_refresh_rate_hz; 693 694 /** 695 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 696 */ 697 unsigned int max_refresh_rate_hz; 698 699 /** 700 * @replay_mode: Replay supported 701 */ 702 bool replay_mode; 703 }; 704 705 struct amdgpu_dm_connector { 706 707 struct drm_connector base; 708 uint32_t connector_id; 709 int bl_idx; 710 711 struct cec_notifier *notifier; 712 713 /* we need to mind the EDID between detect 714 and get modes due to analog/digital/tvencoder */ 715 const struct drm_edid *drm_edid; 716 717 /* shared with amdgpu */ 718 struct amdgpu_hpd hpd; 719 720 /* number of modes generated from EDID at 'dc_sink' */ 721 int num_modes; 722 723 /* The 'old' sink - before an HPD. 724 * The 'current' sink is in dc_link->sink. */ 725 struct dc_sink *dc_sink; 726 struct dc_link *dc_link; 727 728 /** 729 * @dc_em_sink: Reference to the emulated (virtual) sink. 730 */ 731 struct dc_sink *dc_em_sink; 732 733 /* DM only */ 734 struct drm_dp_mst_topology_mgr mst_mgr; 735 struct amdgpu_dm_dp_aux dm_dp_aux; 736 struct drm_dp_mst_port *mst_output_port; 737 struct amdgpu_dm_connector *mst_root; 738 struct drm_dp_aux *dsc_aux; 739 uint32_t mst_local_bw; 740 uint16_t vc_full_pbn; 741 struct mutex handle_mst_msg_ready; 742 743 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 744 struct amdgpu_i2c_adapter *i2c; 745 746 /* Monitor range limits */ 747 /** 748 * @min_vfreq: Minimal frequency supported by the display in Hz. This 749 * value is set to zero when there is no FreeSync support. 750 */ 751 int min_vfreq; 752 753 /** 754 * @max_vfreq: Maximum frequency supported by the display in Hz. This 755 * value is set to zero when there is no FreeSync support. 756 */ 757 int max_vfreq ; 758 759 /* Audio instance - protected by audio_lock. */ 760 int audio_inst; 761 762 struct mutex hpd_lock; 763 764 bool fake_enable; 765 bool force_yuv420_output; 766 struct dsc_preferred_settings dsc_settings; 767 union dp_downstream_port_present mst_downstream_port_present; 768 /* Cached display modes */ 769 struct drm_display_mode freesync_vid_base; 770 771 int sr_skip_count; 772 bool disallow_edp_enter_psr; 773 774 /* Record progress status of mst*/ 775 uint8_t mst_status; 776 777 /* Automated testing */ 778 bool timing_changed; 779 struct dc_crtc_timing *timing_requested; 780 781 /* Adaptive Sync */ 782 bool pack_sdp_v1_3; 783 enum adaptive_sync_type as_type; 784 struct amdgpu_hdmi_vsdb_info vsdb_info; 785 }; 786 787 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 788 uint8_t flags, bool set) 789 { 790 if (set) 791 *status |= flags; 792 else 793 *status &= ~flags; 794 } 795 796 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 797 798 struct amdgpu_dm_wb_connector { 799 struct drm_writeback_connector base; 800 struct dc_link *link; 801 }; 802 803 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 804 805 extern const struct amdgpu_ip_block_version dm_ip_block; 806 807 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 808 * 809 * It includes standardized transfer functions and pure power functions. The 810 * transfer function coefficients are available at modules/color/color_gamma.c 811 */ 812 enum amdgpu_transfer_function { 813 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 814 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 815 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 816 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 817 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 818 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 819 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 820 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 821 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 822 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 823 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 824 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 825 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 826 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 827 AMDGPU_TRANSFER_FUNCTION_COUNT 828 }; 829 830 struct dm_plane_state { 831 struct drm_plane_state base; 832 struct dc_plane_state *dc_state; 833 834 /* Plane color mgmt */ 835 /** 836 * @degamma_lut: 837 * 838 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 839 * blending operations. It's usually applied to linearize input space. 840 * The blob (if not NULL) is an array of &struct drm_color_lut. 841 */ 842 struct drm_property_blob *degamma_lut; 843 /** 844 * @degamma_tf: 845 * 846 * Predefined transfer function to tell DC driver the input space to 847 * linearize. 848 */ 849 enum amdgpu_transfer_function degamma_tf; 850 /** 851 * @hdr_mult: 852 * 853 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 854 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 855 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 856 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 857 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 858 * S31.32 sign-magnitude. 859 * 860 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 861 * TF is needed for any subsequent linear-to-non-linear transforms. 862 */ 863 __u64 hdr_mult; 864 /** 865 * @ctm: 866 * 867 * Color transformation matrix. The blob (if not NULL) is a &struct 868 * drm_color_ctm_3x4. 869 */ 870 struct drm_property_blob *ctm; 871 /** 872 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 873 * array of &struct drm_color_lut. 874 */ 875 struct drm_property_blob *shaper_lut; 876 /** 877 * @shaper_tf: 878 * 879 * Predefined transfer function to delinearize color space. 880 */ 881 enum amdgpu_transfer_function shaper_tf; 882 /** 883 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 884 * &struct drm_color_lut. 885 */ 886 struct drm_property_blob *lut3d; 887 /** 888 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 889 * array of &struct drm_color_lut. 890 */ 891 struct drm_property_blob *blend_lut; 892 /** 893 * @blend_tf: 894 * 895 * Pre-defined transfer function for converting plane pixel data before 896 * applying blend LUT. 897 */ 898 enum amdgpu_transfer_function blend_tf; 899 }; 900 901 enum amdgpu_dm_cursor_mode { 902 DM_CURSOR_NATIVE_MODE = 0, 903 DM_CURSOR_OVERLAY_MODE, 904 }; 905 906 struct dm_crtc_state { 907 struct drm_crtc_state base; 908 struct dc_stream_state *stream; 909 910 bool cm_has_degamma; 911 bool cm_is_degamma_srgb; 912 913 bool mpo_requested; 914 915 int update_type; 916 int active_planes; 917 918 int crc_skip_count; 919 920 bool freesync_vrr_info_changed; 921 922 bool dsc_force_changed; 923 bool vrr_supported; 924 struct mod_freesync_config freesync_config; 925 struct dc_info_packet vrr_infopacket; 926 927 int abm_level; 928 929 /** 930 * @regamma_tf: 931 * 932 * Pre-defined transfer function for converting internal FB -> wire 933 * encoding. 934 */ 935 enum amdgpu_transfer_function regamma_tf; 936 937 enum amdgpu_dm_cursor_mode cursor_mode; 938 }; 939 940 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 941 942 struct dm_atomic_state { 943 struct drm_private_state base; 944 945 struct dc_state *context; 946 }; 947 948 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 949 950 struct dm_connector_state { 951 struct drm_connector_state base; 952 953 enum amdgpu_rmx_type scaling; 954 uint8_t underscan_vborder; 955 uint8_t underscan_hborder; 956 bool underscan_enable; 957 bool freesync_capable; 958 bool update_hdcp; 959 uint8_t abm_level; 960 int vcpi_slots; 961 uint64_t pbn; 962 }; 963 964 #define to_dm_connector_state(x)\ 965 container_of((x), struct dm_connector_state, base) 966 967 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 968 struct drm_connector_state * 969 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 970 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 971 struct drm_connector_state *state, 972 struct drm_property *property, 973 uint64_t val); 974 975 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 976 const struct drm_connector_state *state, 977 struct drm_property *property, 978 uint64_t *val); 979 980 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 981 982 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 983 struct amdgpu_dm_connector *aconnector, 984 int connector_type, 985 struct dc_link *link, 986 int link_index); 987 988 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 989 const struct drm_display_mode *mode); 990 991 void dm_restore_drm_connector_state(struct drm_device *dev, 992 struct drm_connector *connector); 993 994 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 995 const struct drm_edid *drm_edid); 996 997 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 998 999 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1000 #define MAX_COLOR_3DLUT_SIZE 17 1001 #define MAX_COLOR_3DLUT_BITDEPTH 12 1002 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1003 struct drm_plane_state *plane_state); 1004 /* 1D LUT size */ 1005 #define MAX_COLOR_LUT_ENTRIES 4096 1006 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1007 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1008 1009 void amdgpu_dm_init_color_mod(void); 1010 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1011 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1012 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1013 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1014 struct drm_plane_state *plane_state, 1015 struct dc_plane_state *dc_plane_state); 1016 1017 void amdgpu_dm_update_connector_after_detect( 1018 struct amdgpu_dm_connector *aconnector); 1019 1020 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1021 1022 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1023 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1024 1025 bool amdgpu_dm_execute_fused_io( 1026 struct amdgpu_device *dev, 1027 struct dc_link *link, 1028 union dmub_rb_cmd *commands, 1029 uint8_t count, 1030 uint32_t timeout_us 1031 ); 1032 1033 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1034 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1035 1036 struct dc_stream_state * 1037 create_validate_stream_for_sink(struct drm_connector *connector, 1038 const struct drm_display_mode *drm_mode, 1039 const struct dm_connector_state *dm_state, 1040 const struct dc_stream_state *old_stream); 1041 1042 int dm_atomic_get_state(struct drm_atomic_state *state, 1043 struct dm_atomic_state **dm_state); 1044 1045 struct drm_connector * 1046 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1047 struct drm_crtc *crtc); 1048 1049 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1050 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1051 1052 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1053 enum dc_gpu_mem_alloc_type type, 1054 size_t size, 1055 long long *addr); 1056 void dm_free_gpu_mem(struct amdgpu_device *adev, 1057 enum dc_gpu_mem_alloc_type type, 1058 void *addr); 1059 1060 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1061 1062 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1063 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1064 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1065 1066 #endif /* __AMDGPU_DM_H__ */ 1067