1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 59 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 62 /* 63 #include "include/amdgpu_dal_power_if.h" 64 #include "amdgpu_dm_irq.h" 65 */ 66 67 #include "irq_types.h" 68 #include "signal_types.h" 69 #include "amdgpu_dm_crc.h" 70 #include "mod_info_packet.h" 71 struct aux_payload; 72 struct set_config_cmd_payload; 73 enum aux_return_code_type; 74 enum set_config_status; 75 76 /* Forward declarations */ 77 struct amdgpu_device; 78 struct amdgpu_crtc; 79 struct drm_device; 80 struct dc; 81 struct amdgpu_bo; 82 struct dmub_srv; 83 struct dc_plane_state; 84 struct dmub_notification; 85 struct dmub_cmd_fused_request; 86 87 struct amd_vsdb_block { 88 unsigned char ieee_id[3]; 89 unsigned char version; 90 unsigned char feature_caps; 91 }; 92 93 struct common_irq_params { 94 struct amdgpu_device *adev; 95 enum dc_irq_source irq_src; 96 atomic64_t previous_timestamp; 97 }; 98 99 /** 100 * struct dm_compressor_info - Buffer info used by frame buffer compression 101 * @cpu_addr: MMIO cpu addr 102 * @bo_ptr: Pointer to the buffer object 103 * @gpu_addr: MMIO gpu addr 104 */ 105 struct dm_compressor_info { 106 void *cpu_addr; 107 struct amdgpu_bo *bo_ptr; 108 uint64_t gpu_addr; 109 }; 110 111 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 112 113 /** 114 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 115 * 116 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 117 * @dmub_notify: notification for callback function 118 * @adev: amdgpu_device pointer 119 */ 120 struct dmub_hpd_work { 121 struct work_struct handle_hpd_work; 122 struct dmub_notification *dmub_notify; 123 struct amdgpu_device *adev; 124 }; 125 126 /** 127 * struct vblank_control_work - Work data for vblank control 128 * @work: Kernel work data for the work event 129 * @dm: amdgpu display manager device 130 * @acrtc: amdgpu CRTC instance for which the event has occurred 131 * @stream: DC stream for which the event has occurred 132 * @enable: true if enabling vblank 133 */ 134 struct vblank_control_work { 135 struct work_struct work; 136 struct amdgpu_display_manager *dm; 137 struct amdgpu_crtc *acrtc; 138 struct dc_stream_state *stream; 139 bool enable; 140 }; 141 142 /** 143 * struct idle_workqueue - Work data for periodic action in idle 144 * @work: Kernel work data for the work event 145 * @dm: amdgpu display manager device 146 * @enable: true if idle worker is enabled 147 * @running: true if idle worker is running 148 */ 149 struct idle_workqueue { 150 struct work_struct work; 151 struct amdgpu_display_manager *dm; 152 bool enable; 153 bool running; 154 }; 155 156 #define MAX_LUMINANCE_DATA_POINTS 99 157 158 /** 159 * struct amdgpu_dm_luminance_data - Custom luminance data 160 * @luminance: Luminance in percent 161 * @input_signal: Input signal in range 0-255 162 */ 163 struct amdgpu_dm_luminance_data { 164 u8 luminance; 165 u8 input_signal; 166 } __packed; 167 168 /** 169 * struct amdgpu_dm_backlight_caps - Information about backlight 170 * 171 * Describe the backlight support for ACPI or eDP AUX. 172 */ 173 struct amdgpu_dm_backlight_caps { 174 /** 175 * @ext_caps: Keep the data struct with all the information about the 176 * display support for HDR. 177 */ 178 union dpcd_sink_ext_caps *ext_caps; 179 /** 180 * @aux_min_input_signal: Min brightness value supported by the display 181 */ 182 u32 aux_min_input_signal; 183 /** 184 * @aux_max_input_signal: Max brightness value supported by the display 185 * in nits. 186 */ 187 u32 aux_max_input_signal; 188 /** 189 * @min_input_signal: minimum possible input in range 0-255. 190 */ 191 int min_input_signal; 192 /** 193 * @max_input_signal: maximum possible input in range 0-255. 194 */ 195 int max_input_signal; 196 /** 197 * @caps_valid: true if these values are from the ACPI interface. 198 */ 199 bool caps_valid; 200 /** 201 * @aux_support: Describes if the display supports AUX backlight. 202 */ 203 bool aux_support; 204 /** 205 * @ac_level: the default brightness if booted on AC 206 */ 207 u8 ac_level; 208 /** 209 * @dc_level: the default brightness if booted on DC 210 */ 211 u8 dc_level; 212 /** 213 * @data_points: the number of custom luminance data points 214 */ 215 u8 data_points; 216 /** 217 * @luminance_data: custom luminance data 218 */ 219 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 220 }; 221 222 /** 223 * struct dal_allocation - Tracks mapped FB memory for SMU communication 224 * @list: list of dal allocations 225 * @bo: GPU buffer object 226 * @cpu_ptr: CPU virtual address of the GPU buffer object 227 * @gpu_addr: GPU virtual address of the GPU buffer object 228 */ 229 struct dal_allocation { 230 struct list_head list; 231 struct amdgpu_bo *bo; 232 void *cpu_ptr; 233 u64 gpu_addr; 234 }; 235 236 /** 237 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 238 * offload work 239 */ 240 struct hpd_rx_irq_offload_work_queue { 241 /** 242 * @wq: workqueue structure to queue offload work. 243 */ 244 struct workqueue_struct *wq; 245 /** 246 * @offload_lock: To protect fields of offload work queue. 247 */ 248 spinlock_t offload_lock; 249 /** 250 * @is_handling_link_loss: Used to prevent inserting link loss event when 251 * we're handling link loss 252 */ 253 bool is_handling_link_loss; 254 /** 255 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 256 * ready event when we're already handling mst message ready event 257 */ 258 bool is_handling_mst_msg_rdy_event; 259 /** 260 * @aconnector: The aconnector that this work queue is attached to 261 */ 262 struct amdgpu_dm_connector *aconnector; 263 }; 264 265 /** 266 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 267 */ 268 struct hpd_rx_irq_offload_work { 269 /** 270 * @work: offload work 271 */ 272 struct work_struct work; 273 /** 274 * @data: reference irq data which is used while handling offload work 275 */ 276 union hpd_irq_data data; 277 /** 278 * @offload_wq: offload work queue that this work is queued to 279 */ 280 struct hpd_rx_irq_offload_work_queue *offload_wq; 281 /** 282 * @adev: amdgpu_device pointer 283 */ 284 struct amdgpu_device *adev; 285 }; 286 287 /** 288 * struct amdgpu_display_manager - Central amdgpu display manager device 289 * 290 * @dc: Display Core control structure 291 * @adev: AMDGPU base driver structure 292 * @ddev: DRM base driver structure 293 * @display_indexes_num: Max number of display streams supported 294 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 295 * @backlight_dev: Backlight control device 296 * @backlight_link: Link on which to control backlight 297 * @backlight_caps: Capabilities of the backlight device 298 * @freesync_module: Module handling freesync calculations 299 * @hdcp_workqueue: AMDGPU content protection queue 300 * @fw_dmcu: Reference to DMCU firmware 301 * @dmcu_fw_version: Version of the DMCU firmware 302 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 303 * @cached_state: Caches device atomic state for suspend/resume 304 * @cached_dc_state: Cached state of content streams 305 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 306 * @force_timing_sync: set via debugfs. When set, indicates that all connected 307 * displays will be forced to synchronize. 308 * @dmcub_trace_event_en: enable dmcub trace events 309 * @dmub_outbox_params: DMUB Outbox parameters 310 * @num_of_edps: number of backlight eDPs 311 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 312 * driver when true 313 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 314 * transfers are done 315 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 316 */ 317 struct amdgpu_display_manager { 318 319 struct dc *dc; 320 321 /** 322 * @dmub_srv: 323 * 324 * DMUB service, used for controlling the DMUB on hardware 325 * that supports it. The pointer to the dmub_srv will be 326 * NULL on hardware that does not support it. 327 */ 328 struct dmub_srv *dmub_srv; 329 330 /** 331 * @dmub_notify: 332 * 333 * Notification from DMUB. 334 */ 335 336 struct dmub_notification *dmub_notify; 337 338 /** 339 * @dmub_callback: 340 * 341 * Callback functions to handle notification from DMUB. 342 */ 343 344 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 345 346 /** 347 * @dmub_thread_offload: 348 * 349 * Flag to indicate if callback is offload. 350 */ 351 352 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 353 354 /** 355 * @dmub_fb_info: 356 * 357 * Framebuffer regions for the DMUB. 358 */ 359 struct dmub_srv_fb_info *dmub_fb_info; 360 361 /** 362 * @dmub_fw: 363 * 364 * DMUB firmware, required on hardware that has DMUB support. 365 */ 366 const struct firmware *dmub_fw; 367 368 /** 369 * @dmub_bo: 370 * 371 * Buffer object for the DMUB. 372 */ 373 struct amdgpu_bo *dmub_bo; 374 375 /** 376 * @dmub_bo_gpu_addr: 377 * 378 * GPU virtual address for the DMUB buffer object. 379 */ 380 u64 dmub_bo_gpu_addr; 381 382 /** 383 * @dmub_bo_cpu_addr: 384 * 385 * CPU address for the DMUB buffer object. 386 */ 387 void *dmub_bo_cpu_addr; 388 389 /** 390 * @dmcub_fw_version: 391 * 392 * DMCUB firmware version. 393 */ 394 uint32_t dmcub_fw_version; 395 396 /** 397 * @cgs_device: 398 * 399 * The Common Graphics Services device. It provides an interface for 400 * accessing registers. 401 */ 402 struct cgs_device *cgs_device; 403 404 struct amdgpu_device *adev; 405 struct drm_device *ddev; 406 u16 display_indexes_num; 407 408 /** 409 * @atomic_obj: 410 * 411 * In combination with &dm_atomic_state it helps manage 412 * global atomic state that doesn't map cleanly into existing 413 * drm resources, like &dc_context. 414 */ 415 struct drm_private_obj atomic_obj; 416 417 /** 418 * @dc_lock: 419 * 420 * Guards access to DC functions that can issue register write 421 * sequences. 422 */ 423 struct mutex dc_lock; 424 425 /** 426 * @audio_lock: 427 * 428 * Guards access to audio instance changes. 429 */ 430 struct mutex audio_lock; 431 432 /** 433 * @audio_component: 434 * 435 * Used to notify ELD changes to sound driver. 436 */ 437 struct drm_audio_component *audio_component; 438 439 /** 440 * @audio_registered: 441 * 442 * True if the audio component has been registered 443 * successfully, false otherwise. 444 */ 445 bool audio_registered; 446 447 /** 448 * @irq_handler_list_low_tab: 449 * 450 * Low priority IRQ handler table. 451 * 452 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 453 * source. Low priority IRQ handlers are deferred to a workqueue to be 454 * processed. Hence, they can sleep. 455 * 456 * Note that handlers are called in the same order as they were 457 * registered (FIFO). 458 */ 459 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 460 461 /** 462 * @irq_handler_list_high_tab: 463 * 464 * High priority IRQ handler table. 465 * 466 * It is a n*m table, same as &irq_handler_list_low_tab. However, 467 * handlers in this table are not deferred and are called immediately. 468 */ 469 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 470 471 /** 472 * @pflip_params: 473 * 474 * Page flip IRQ parameters, passed to registered handlers when 475 * triggered. 476 */ 477 struct common_irq_params 478 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 479 480 /** 481 * @vblank_params: 482 * 483 * Vertical blanking IRQ parameters, passed to registered handlers when 484 * triggered. 485 */ 486 struct common_irq_params 487 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 488 489 /** 490 * @vline0_params: 491 * 492 * OTG vertical interrupt0 IRQ parameters, passed to registered 493 * handlers when triggered. 494 */ 495 struct common_irq_params 496 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 497 498 /** 499 * @vupdate_params: 500 * 501 * Vertical update IRQ parameters, passed to registered handlers when 502 * triggered. 503 */ 504 struct common_irq_params 505 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 506 507 /** 508 * @dmub_trace_params: 509 * 510 * DMUB trace event IRQ parameters, passed to registered handlers when 511 * triggered. 512 */ 513 struct common_irq_params 514 dmub_trace_params[1]; 515 516 struct common_irq_params 517 dmub_outbox_params[1]; 518 519 spinlock_t irq_handler_list_table_lock; 520 521 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 522 523 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 524 525 uint8_t num_of_edps; 526 527 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 528 529 struct mod_freesync *freesync_module; 530 struct hdcp_workqueue *hdcp_workqueue; 531 532 /** 533 * @vblank_control_workqueue: 534 * 535 * Deferred work for vblank control events. 536 */ 537 struct workqueue_struct *vblank_control_workqueue; 538 539 /** 540 * @idle_workqueue: 541 * 542 * Periodic work for idle events. 543 */ 544 struct idle_workqueue *idle_workqueue; 545 546 struct drm_atomic_state *cached_state; 547 struct dc_state *cached_dc_state; 548 549 struct dm_compressor_info compressor; 550 551 const struct firmware *fw_dmcu; 552 uint32_t dmcu_fw_version; 553 /** 554 * @soc_bounding_box: 555 * 556 * gpu_info FW provided soc bounding box struct or 0 if not 557 * available in FW 558 */ 559 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 560 561 /** 562 * @active_vblank_irq_count: 563 * 564 * number of currently active vblank irqs 565 */ 566 uint32_t active_vblank_irq_count; 567 568 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 569 /** 570 * @secure_display_ctx: 571 * 572 * Store secure display relevant info. e.g. the ROI information 573 * , the work_struct to command dmub, etc. 574 */ 575 struct secure_display_context secure_display_ctx; 576 #endif 577 /** 578 * @hpd_rx_offload_wq: 579 * 580 * Work queue to offload works of hpd_rx_irq 581 */ 582 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 583 /** 584 * @mst_encoders: 585 * 586 * fake encoders used for DP MST. 587 */ 588 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 589 bool force_timing_sync; 590 bool disable_hpd_irq; 591 bool dmcub_trace_event_en; 592 /** 593 * @da_list: 594 * 595 * DAL fb memory allocation list, for communication with SMU. 596 */ 597 struct list_head da_list; 598 struct completion dmub_aux_transfer_done; 599 struct workqueue_struct *delayed_hpd_wq; 600 601 /** 602 * @brightness: 603 * 604 * cached backlight values. 605 */ 606 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 607 /** 608 * @actual_brightness: 609 * 610 * last successfully applied backlight values. 611 */ 612 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 613 614 /** 615 * @aux_hpd_discon_quirk: 616 * 617 * quirk for hpd discon while aux is on-going. 618 * occurred on certain intel platform 619 */ 620 bool aux_hpd_discon_quirk; 621 622 /** 623 * @edp0_on_dp1_quirk: 624 * 625 * quirk for platforms that put edp0 on DP1. 626 */ 627 bool edp0_on_dp1_quirk; 628 629 /** 630 * @dpia_aux_lock: 631 * 632 * Guards access to DPIA AUX 633 */ 634 struct mutex dpia_aux_lock; 635 636 /** 637 * @bb_from_dmub: 638 * 639 * Bounding box data read from dmub during early initialization for DCN4+ 640 * Data is stored as a byte array that should be casted to the appropriate bb struct 641 */ 642 void *bb_from_dmub; 643 644 /** 645 * @oem_i2c: 646 * 647 * OEM i2c bus 648 */ 649 struct amdgpu_i2c_adapter *oem_i2c; 650 651 /** 652 * @fused_io: 653 * 654 * dmub fused io interface 655 */ 656 struct fused_io_sync { 657 struct completion replied; 658 char reply_data[0x40]; // Cannot include dmub_cmd here 659 } fused_io[8]; 660 }; 661 662 enum dsc_clock_force_state { 663 DSC_CLK_FORCE_DEFAULT = 0, 664 DSC_CLK_FORCE_ENABLE, 665 DSC_CLK_FORCE_DISABLE, 666 }; 667 668 struct dsc_preferred_settings { 669 enum dsc_clock_force_state dsc_force_enable; 670 uint32_t dsc_num_slices_v; 671 uint32_t dsc_num_slices_h; 672 uint32_t dsc_bits_per_pixel; 673 bool dsc_force_disable_passthrough; 674 }; 675 676 enum mst_progress_status { 677 MST_STATUS_DEFAULT = 0, 678 MST_PROBE = BIT(0), 679 MST_REMOTE_EDID = BIT(1), 680 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 681 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 682 }; 683 684 /** 685 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 686 * 687 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 688 * struct is useful to keep track of the display-specific information about 689 * FreeSync. 690 */ 691 struct amdgpu_hdmi_vsdb_info { 692 /** 693 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 694 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 695 */ 696 unsigned int amd_vsdb_version; 697 698 /** 699 * @freesync_supported: FreeSync Supported. 700 */ 701 bool freesync_supported; 702 703 /** 704 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 705 */ 706 unsigned int min_refresh_rate_hz; 707 708 /** 709 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 710 */ 711 unsigned int max_refresh_rate_hz; 712 713 /** 714 * @replay_mode: Replay supported 715 */ 716 bool replay_mode; 717 }; 718 719 struct amdgpu_dm_connector { 720 721 struct drm_connector base; 722 uint32_t connector_id; 723 int bl_idx; 724 725 struct cec_notifier *notifier; 726 727 /* we need to mind the EDID between detect 728 and get modes due to analog/digital/tvencoder */ 729 const struct drm_edid *drm_edid; 730 731 /* shared with amdgpu */ 732 struct amdgpu_hpd hpd; 733 734 /* number of modes generated from EDID at 'dc_sink' */ 735 int num_modes; 736 737 /* The 'old' sink - before an HPD. 738 * The 'current' sink is in dc_link->sink. */ 739 struct dc_sink *dc_sink; 740 struct dc_link *dc_link; 741 742 /** 743 * @dc_em_sink: Reference to the emulated (virtual) sink. 744 */ 745 struct dc_sink *dc_em_sink; 746 747 /* DM only */ 748 struct drm_dp_mst_topology_mgr mst_mgr; 749 struct amdgpu_dm_dp_aux dm_dp_aux; 750 struct drm_dp_mst_port *mst_output_port; 751 struct amdgpu_dm_connector *mst_root; 752 struct drm_dp_aux *dsc_aux; 753 uint32_t mst_local_bw; 754 uint16_t vc_full_pbn; 755 struct mutex handle_mst_msg_ready; 756 757 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 758 struct amdgpu_i2c_adapter *i2c; 759 760 /* Monitor range limits */ 761 /** 762 * @min_vfreq: Minimal frequency supported by the display in Hz. This 763 * value is set to zero when there is no FreeSync support. 764 */ 765 int min_vfreq; 766 767 /** 768 * @max_vfreq: Maximum frequency supported by the display in Hz. This 769 * value is set to zero when there is no FreeSync support. 770 */ 771 int max_vfreq ; 772 773 /* Audio instance - protected by audio_lock. */ 774 int audio_inst; 775 776 struct mutex hpd_lock; 777 778 bool fake_enable; 779 bool force_yuv420_output; 780 struct dsc_preferred_settings dsc_settings; 781 union dp_downstream_port_present mst_downstream_port_present; 782 /* Cached display modes */ 783 struct drm_display_mode freesync_vid_base; 784 785 int sr_skip_count; 786 bool disallow_edp_enter_psr; 787 788 /* Record progress status of mst*/ 789 uint8_t mst_status; 790 791 /* Automated testing */ 792 bool timing_changed; 793 struct dc_crtc_timing *timing_requested; 794 795 /* Adaptive Sync */ 796 bool pack_sdp_v1_3; 797 enum adaptive_sync_type as_type; 798 struct amdgpu_hdmi_vsdb_info vsdb_info; 799 }; 800 801 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 802 uint8_t flags, bool set) 803 { 804 if (set) 805 *status |= flags; 806 else 807 *status &= ~flags; 808 } 809 810 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 811 812 struct amdgpu_dm_wb_connector { 813 struct drm_writeback_connector base; 814 struct dc_link *link; 815 }; 816 817 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 818 819 extern const struct amdgpu_ip_block_version dm_ip_block; 820 821 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 822 * 823 * It includes standardized transfer functions and pure power functions. The 824 * transfer function coefficients are available at modules/color/color_gamma.c 825 */ 826 enum amdgpu_transfer_function { 827 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 828 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 829 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 830 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 831 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 832 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 833 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 834 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 835 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 836 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 837 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 838 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 839 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 840 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 841 AMDGPU_TRANSFER_FUNCTION_COUNT 842 }; 843 844 struct dm_plane_state { 845 struct drm_plane_state base; 846 struct dc_plane_state *dc_state; 847 848 /* Plane color mgmt */ 849 /** 850 * @degamma_lut: 851 * 852 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 853 * blending operations. It's usually applied to linearize input space. 854 * The blob (if not NULL) is an array of &struct drm_color_lut. 855 */ 856 struct drm_property_blob *degamma_lut; 857 /** 858 * @degamma_tf: 859 * 860 * Predefined transfer function to tell DC driver the input space to 861 * linearize. 862 */ 863 enum amdgpu_transfer_function degamma_tf; 864 /** 865 * @hdr_mult: 866 * 867 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 868 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 869 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 870 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 871 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 872 * S31.32 sign-magnitude. 873 * 874 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 875 * TF is needed for any subsequent linear-to-non-linear transforms. 876 */ 877 __u64 hdr_mult; 878 /** 879 * @ctm: 880 * 881 * Color transformation matrix. The blob (if not NULL) is a &struct 882 * drm_color_ctm_3x4. 883 */ 884 struct drm_property_blob *ctm; 885 /** 886 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 887 * array of &struct drm_color_lut. 888 */ 889 struct drm_property_blob *shaper_lut; 890 /** 891 * @shaper_tf: 892 * 893 * Predefined transfer function to delinearize color space. 894 */ 895 enum amdgpu_transfer_function shaper_tf; 896 /** 897 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 898 * &struct drm_color_lut. 899 */ 900 struct drm_property_blob *lut3d; 901 /** 902 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 903 * array of &struct drm_color_lut. 904 */ 905 struct drm_property_blob *blend_lut; 906 /** 907 * @blend_tf: 908 * 909 * Pre-defined transfer function for converting plane pixel data before 910 * applying blend LUT. 911 */ 912 enum amdgpu_transfer_function blend_tf; 913 }; 914 915 enum amdgpu_dm_cursor_mode { 916 DM_CURSOR_NATIVE_MODE = 0, 917 DM_CURSOR_OVERLAY_MODE, 918 }; 919 920 struct dm_crtc_state { 921 struct drm_crtc_state base; 922 struct dc_stream_state *stream; 923 924 bool cm_has_degamma; 925 bool cm_is_degamma_srgb; 926 927 bool mpo_requested; 928 929 int update_type; 930 int active_planes; 931 932 int crc_skip_count; 933 934 bool freesync_vrr_info_changed; 935 936 bool dsc_force_changed; 937 bool vrr_supported; 938 struct mod_freesync_config freesync_config; 939 struct dc_info_packet vrr_infopacket; 940 941 int abm_level; 942 943 /** 944 * @regamma_tf: 945 * 946 * Pre-defined transfer function for converting internal FB -> wire 947 * encoding. 948 */ 949 enum amdgpu_transfer_function regamma_tf; 950 951 enum amdgpu_dm_cursor_mode cursor_mode; 952 }; 953 954 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 955 956 struct dm_atomic_state { 957 struct drm_private_state base; 958 959 struct dc_state *context; 960 }; 961 962 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 963 964 struct dm_connector_state { 965 struct drm_connector_state base; 966 967 enum amdgpu_rmx_type scaling; 968 uint8_t underscan_vborder; 969 uint8_t underscan_hborder; 970 bool underscan_enable; 971 bool freesync_capable; 972 bool update_hdcp; 973 uint8_t abm_level; 974 int vcpi_slots; 975 uint64_t pbn; 976 }; 977 978 #define to_dm_connector_state(x)\ 979 container_of((x), struct dm_connector_state, base) 980 981 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 982 struct drm_connector_state * 983 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 984 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 985 struct drm_connector_state *state, 986 struct drm_property *property, 987 uint64_t val); 988 989 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 990 const struct drm_connector_state *state, 991 struct drm_property *property, 992 uint64_t *val); 993 994 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 995 996 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 997 struct amdgpu_dm_connector *aconnector, 998 int connector_type, 999 struct dc_link *link, 1000 int link_index); 1001 1002 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1003 const struct drm_display_mode *mode); 1004 1005 void dm_restore_drm_connector_state(struct drm_device *dev, 1006 struct drm_connector *connector); 1007 1008 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1009 const struct drm_edid *drm_edid); 1010 1011 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1012 1013 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1014 #define MAX_COLOR_3DLUT_SIZE 17 1015 #define MAX_COLOR_3DLUT_BITDEPTH 12 1016 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1017 struct drm_plane_state *plane_state); 1018 /* 1D LUT size */ 1019 #define MAX_COLOR_LUT_ENTRIES 4096 1020 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1021 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1022 1023 void amdgpu_dm_init_color_mod(void); 1024 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1025 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1026 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1027 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1028 struct drm_plane_state *plane_state, 1029 struct dc_plane_state *dc_plane_state); 1030 1031 void amdgpu_dm_update_connector_after_detect( 1032 struct amdgpu_dm_connector *aconnector); 1033 1034 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1035 1036 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1037 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1038 1039 bool amdgpu_dm_execute_fused_io( 1040 struct amdgpu_device *dev, 1041 struct dc_link *link, 1042 union dmub_rb_cmd *commands, 1043 uint8_t count, 1044 uint32_t timeout_us 1045 ); 1046 1047 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1048 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1049 1050 struct dc_stream_state * 1051 create_validate_stream_for_sink(struct drm_connector *connector, 1052 const struct drm_display_mode *drm_mode, 1053 const struct dm_connector_state *dm_state, 1054 const struct dc_stream_state *old_stream); 1055 1056 int dm_atomic_get_state(struct drm_atomic_state *state, 1057 struct dm_atomic_state **dm_state); 1058 1059 struct drm_connector * 1060 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1061 struct drm_crtc *crtc); 1062 1063 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1064 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1065 1066 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1067 enum dc_gpu_mem_alloc_type type, 1068 size_t size, 1069 long long *addr); 1070 void dm_free_gpu_mem(struct amdgpu_device *adev, 1071 enum dc_gpu_mem_alloc_type type, 1072 void *addr); 1073 1074 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1075 1076 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1077 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1078 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1079 1080 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1081 1082 #endif /* __AMDGPU_DM_H__ */ 1083