1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 enum amd_vsdb_panel_type { 57 AMD_VSDB_PANEL_TYPE_DEFAULT = 0, 58 AMD_VSDB_PANEL_TYPE_MINILED, 59 AMD_VSDB_PANEL_TYPE_OLED, 60 AMD_VSDB_PANEL_TYPE_RESERVED, 61 }; 62 63 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 64 65 /* 66 * Maximum HDMI HPD debounce delay in milliseconds 67 */ 68 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 69 /* 70 #include "include/amdgpu_dal_power_if.h" 71 #include "amdgpu_dm_irq.h" 72 */ 73 74 #include "irq_types.h" 75 #include "signal_types.h" 76 #include "amdgpu_dm_crc.h" 77 #include "mod_info_packet.h" 78 struct aux_payload; 79 struct set_config_cmd_payload; 80 enum aux_return_code_type; 81 enum set_config_status; 82 83 /* Forward declarations */ 84 struct amdgpu_device; 85 struct amdgpu_crtc; 86 struct drm_device; 87 struct dc; 88 struct amdgpu_bo; 89 struct dmub_srv; 90 struct dc_plane_state; 91 struct dmub_notification; 92 struct dmub_cmd_fused_request; 93 94 struct common_irq_params { 95 struct amdgpu_device *adev; 96 enum dc_irq_source irq_src; 97 atomic64_t previous_timestamp; 98 }; 99 100 /** 101 * struct dm_compressor_info - Buffer info used by frame buffer compression 102 * @cpu_addr: MMIO cpu addr 103 * @bo_ptr: Pointer to the buffer object 104 * @gpu_addr: MMIO gpu addr 105 */ 106 struct dm_compressor_info { 107 void *cpu_addr; 108 struct amdgpu_bo *bo_ptr; 109 uint64_t gpu_addr; 110 }; 111 112 /** 113 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC 114 * @cpu_addr: MMIO cpu addr 115 * @bo_ptr: Pointer to the buffer object 116 * @gpu_addr: MMIO gpu addr 117 * @size: Size of the buffer 118 */ 119 struct dm_boot_time_crc_info { 120 void *cpu_addr; 121 struct amdgpu_bo *bo_ptr; 122 uint64_t gpu_addr; 123 uint32_t size; 124 }; 125 126 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 127 128 /** 129 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 130 * 131 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 132 * @dmub_notify: notification for callback function 133 * @adev: amdgpu_device pointer 134 */ 135 struct dmub_hpd_work { 136 struct work_struct handle_hpd_work; 137 struct dmub_notification *dmub_notify; 138 struct amdgpu_device *adev; 139 }; 140 141 /** 142 * struct vblank_control_work - Work data for vblank control 143 * @work: Kernel work data for the work event 144 * @dm: amdgpu display manager device 145 * @acrtc: amdgpu CRTC instance for which the event has occurred 146 * @stream: DC stream for which the event has occurred 147 * @enable: true if enabling vblank 148 */ 149 struct vblank_control_work { 150 struct work_struct work; 151 struct amdgpu_display_manager *dm; 152 struct amdgpu_crtc *acrtc; 153 struct dc_stream_state *stream; 154 bool enable; 155 }; 156 157 /** 158 * struct idle_workqueue - Work data for periodic action in idle 159 * @work: Kernel work data for the work event 160 * @dm: amdgpu display manager device 161 * @enable: true if idle worker is enabled 162 * @running: true if idle worker is running 163 */ 164 struct idle_workqueue { 165 struct work_struct work; 166 struct amdgpu_display_manager *dm; 167 bool enable; 168 bool running; 169 }; 170 171 /** 172 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 173 * @work: Kernel work data for the work event 174 * @adev: amdgpu_device back pointer 175 * @stream: DC stream associated with the crtc 176 * @adjust: DC CRTC timing adjust to be applied to the crtc 177 */ 178 struct vupdate_offload_work { 179 struct work_struct work; 180 struct amdgpu_device *adev; 181 struct dc_stream_state *stream; 182 struct dc_crtc_timing_adjust *adjust; 183 }; 184 185 #define MAX_LUMINANCE_DATA_POINTS 99 186 187 /** 188 * struct amdgpu_dm_luminance_data - Custom luminance data 189 * @luminance: Luminance in percent 190 * @input_signal: Input signal in range 0-255 191 */ 192 struct amdgpu_dm_luminance_data { 193 u8 luminance; 194 u8 input_signal; 195 } __packed; 196 197 /** 198 * struct amdgpu_dm_backlight_caps - Information about backlight 199 * 200 * Describe the backlight support for ACPI or eDP AUX. 201 */ 202 struct amdgpu_dm_backlight_caps { 203 /** 204 * @ext_caps: Keep the data struct with all the information about the 205 * display support for HDR. 206 */ 207 union dpcd_sink_ext_caps *ext_caps; 208 /** 209 * @aux_min_input_signal: Min brightness value supported by the display 210 */ 211 u32 aux_min_input_signal; 212 /** 213 * @aux_max_input_signal: Max brightness value supported by the display 214 * in nits. 215 */ 216 u32 aux_max_input_signal; 217 /** 218 * @min_input_signal: minimum possible input in range 0-255. 219 */ 220 int min_input_signal; 221 /** 222 * @max_input_signal: maximum possible input in range 0-255. 223 */ 224 int max_input_signal; 225 /** 226 * @caps_valid: true if these values are from the ACPI interface. 227 */ 228 bool caps_valid; 229 /** 230 * @aux_support: Describes if the display supports AUX backlight. 231 */ 232 bool aux_support; 233 /** 234 * @brightness_mask: After deriving brightness, OR it with this mask. 235 * Workaround for panels with issues with certain brightness values. 236 */ 237 u32 brightness_mask; 238 /** 239 * @ac_level: the default brightness if booted on AC 240 */ 241 u8 ac_level; 242 /** 243 * @dc_level: the default brightness if booted on DC 244 */ 245 u8 dc_level; 246 /** 247 * @data_points: the number of custom luminance data points 248 */ 249 u8 data_points; 250 /** 251 * @luminance_data: custom luminance data 252 */ 253 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 254 }; 255 256 /** 257 * struct dal_allocation - Tracks mapped FB memory for SMU communication 258 * @list: list of dal allocations 259 * @bo: GPU buffer object 260 * @cpu_ptr: CPU virtual address of the GPU buffer object 261 * @gpu_addr: GPU virtual address of the GPU buffer object 262 */ 263 struct dal_allocation { 264 struct list_head list; 265 struct amdgpu_bo *bo; 266 void *cpu_ptr; 267 u64 gpu_addr; 268 }; 269 270 /** 271 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 272 * offload work 273 */ 274 struct hpd_rx_irq_offload_work_queue { 275 /** 276 * @wq: workqueue structure to queue offload work. 277 */ 278 struct workqueue_struct *wq; 279 /** 280 * @offload_lock: To protect fields of offload work queue. 281 */ 282 spinlock_t offload_lock; 283 /** 284 * @is_handling_link_loss: Used to prevent inserting link loss event when 285 * we're handling link loss 286 */ 287 bool is_handling_link_loss; 288 /** 289 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 290 * ready event when we're already handling mst message ready event 291 */ 292 bool is_handling_mst_msg_rdy_event; 293 /** 294 * @aconnector: The aconnector that this work queue is attached to 295 */ 296 struct amdgpu_dm_connector *aconnector; 297 }; 298 299 /** 300 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 301 */ 302 struct hpd_rx_irq_offload_work { 303 /** 304 * @work: offload work 305 */ 306 struct work_struct work; 307 /** 308 * @data: reference irq data which is used while handling offload work 309 */ 310 union hpd_irq_data data; 311 /** 312 * @offload_wq: offload work queue that this work is queued to 313 */ 314 struct hpd_rx_irq_offload_work_queue *offload_wq; 315 /** 316 * @adev: amdgpu_device pointer 317 */ 318 struct amdgpu_device *adev; 319 }; 320 321 /** 322 * struct amdgpu_display_manager - Central amdgpu display manager device 323 * 324 * @dc: Display Core control structure 325 * @adev: AMDGPU base driver structure 326 * @ddev: DRM base driver structure 327 * @display_indexes_num: Max number of display streams supported 328 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 329 * @backlight_dev: Backlight control device 330 * @backlight_link: Link on which to control backlight 331 * @backlight_caps: Capabilities of the backlight device 332 * @freesync_module: Module handling freesync calculations 333 * @hdcp_workqueue: AMDGPU content protection queue 334 * @fw_dmcu: Reference to DMCU firmware 335 * @dmcu_fw_version: Version of the DMCU firmware 336 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 337 * @cached_state: Caches device atomic state for suspend/resume 338 * @cached_dc_state: Cached state of content streams 339 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 340 * @force_timing_sync: set via debugfs. When set, indicates that all connected 341 * displays will be forced to synchronize. 342 * @dmcub_trace_event_en: enable dmcub trace events 343 * @dmub_outbox_params: DMUB Outbox parameters 344 * @num_of_edps: number of backlight eDPs 345 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 346 * driver when true 347 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 348 * transfers are done 349 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 350 */ 351 struct amdgpu_display_manager { 352 353 struct dc *dc; 354 355 /** 356 * @dmub_srv: 357 * 358 * DMUB service, used for controlling the DMUB on hardware 359 * that supports it. The pointer to the dmub_srv will be 360 * NULL on hardware that does not support it. 361 */ 362 struct dmub_srv *dmub_srv; 363 364 /** 365 * @dmub_notify: 366 * 367 * Notification from DMUB. 368 */ 369 370 struct dmub_notification *dmub_notify; 371 372 /** 373 * @dmub_callback: 374 * 375 * Callback functions to handle notification from DMUB. 376 */ 377 378 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 379 380 /** 381 * @dmub_thread_offload: 382 * 383 * Flag to indicate if callback is offload. 384 */ 385 386 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 387 388 /** 389 * @dmub_fb_info: 390 * 391 * Framebuffer regions for the DMUB. 392 */ 393 struct dmub_srv_fb_info *dmub_fb_info; 394 395 /** 396 * @dmub_fw: 397 * 398 * DMUB firmware, required on hardware that has DMUB support. 399 */ 400 const struct firmware *dmub_fw; 401 402 /** 403 * @dmub_bo: 404 * 405 * Buffer object for the DMUB. 406 */ 407 struct amdgpu_bo *dmub_bo; 408 409 /** 410 * @dmub_bo_gpu_addr: 411 * 412 * GPU virtual address for the DMUB buffer object. 413 */ 414 u64 dmub_bo_gpu_addr; 415 416 /** 417 * @dmub_bo_cpu_addr: 418 * 419 * CPU address for the DMUB buffer object. 420 */ 421 void *dmub_bo_cpu_addr; 422 423 /** 424 * @dmcub_fw_version: 425 * 426 * DMCUB firmware version. 427 */ 428 uint32_t dmcub_fw_version; 429 430 /** 431 * @fw_inst_size: 432 * 433 * Size of the firmware instruction buffer. 434 */ 435 uint32_t fw_inst_size; 436 437 /** 438 * @cgs_device: 439 * 440 * The Common Graphics Services device. It provides an interface for 441 * accessing registers. 442 */ 443 struct cgs_device *cgs_device; 444 445 struct amdgpu_device *adev; 446 struct drm_device *ddev; 447 u16 display_indexes_num; 448 449 /** 450 * @atomic_obj: 451 * 452 * In combination with &dm_atomic_state it helps manage 453 * global atomic state that doesn't map cleanly into existing 454 * drm resources, like &dc_context. 455 */ 456 struct drm_private_obj atomic_obj; 457 458 /** 459 * @dc_lock: 460 * 461 * Guards access to DC functions that can issue register write 462 * sequences. 463 */ 464 struct mutex dc_lock; 465 466 /** 467 * @dmub_lock: 468 * 469 * Guards access to DMUB command submission. 470 */ 471 spinlock_t dmub_lock; 472 473 /** 474 * @audio_lock: 475 * 476 * Guards access to audio instance changes. 477 */ 478 struct mutex audio_lock; 479 480 /** 481 * @audio_component: 482 * 483 * Used to notify ELD changes to sound driver. 484 */ 485 struct drm_audio_component *audio_component; 486 487 /** 488 * @audio_registered: 489 * 490 * True if the audio component has been registered 491 * successfully, false otherwise. 492 */ 493 bool audio_registered; 494 495 /** 496 * @irq_handler_list_low_tab: 497 * 498 * Low priority IRQ handler table. 499 * 500 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 501 * source. Low priority IRQ handlers are deferred to a workqueue to be 502 * processed. Hence, they can sleep. 503 * 504 * Note that handlers are called in the same order as they were 505 * registered (FIFO). 506 */ 507 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 508 509 /** 510 * @irq_handler_list_high_tab: 511 * 512 * High priority IRQ handler table. 513 * 514 * It is a n*m table, same as &irq_handler_list_low_tab. However, 515 * handlers in this table are not deferred and are called immediately. 516 */ 517 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 518 519 /** 520 * @pflip_params: 521 * 522 * Page flip IRQ parameters, passed to registered handlers when 523 * triggered. 524 */ 525 struct common_irq_params 526 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 527 528 /** 529 * @vblank_params: 530 * 531 * Vertical blanking IRQ parameters, passed to registered handlers when 532 * triggered. 533 */ 534 struct common_irq_params 535 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 536 537 /** 538 * @vline0_params: 539 * 540 * OTG vertical interrupt0 IRQ parameters, passed to registered 541 * handlers when triggered. 542 */ 543 struct common_irq_params 544 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 545 546 /** 547 * @vupdate_params: 548 * 549 * Vertical update IRQ parameters, passed to registered handlers when 550 * triggered. 551 */ 552 struct common_irq_params 553 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 554 555 /** 556 * @dmub_trace_params: 557 * 558 * DMUB trace event IRQ parameters, passed to registered handlers when 559 * triggered. 560 */ 561 struct common_irq_params 562 dmub_trace_params[1]; 563 564 struct common_irq_params 565 dmub_outbox_params[1]; 566 567 spinlock_t irq_handler_list_table_lock; 568 569 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 570 571 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 572 573 uint8_t num_of_edps; 574 575 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 576 577 struct mod_freesync *freesync_module; 578 struct mod_power *power_module; 579 struct hdcp_workqueue *hdcp_workqueue; 580 581 /** 582 * @vblank_control_workqueue: 583 * 584 * Deferred work for vblank control events. 585 */ 586 struct workqueue_struct *vblank_control_workqueue; 587 588 /** 589 * @idle_workqueue: 590 * 591 * Periodic work for idle events. 592 */ 593 struct idle_workqueue *idle_workqueue; 594 595 struct drm_atomic_commit *cached_state; 596 struct dc_state *cached_dc_state; 597 598 struct dm_compressor_info compressor; 599 600 const struct firmware *fw_dmcu; 601 uint32_t dmcu_fw_version; 602 /** 603 * @soc_bounding_box: 604 * 605 * gpu_info FW provided soc bounding box struct or 0 if not 606 * available in FW 607 */ 608 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 609 610 /** 611 * @active_vblank_irq_count: 612 * 613 * number of currently active vblank irqs 614 */ 615 uint32_t active_vblank_irq_count; 616 617 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 618 /** 619 * @secure_display_ctx: 620 * 621 * Store secure display relevant info. e.g. the ROI information 622 * , the work_struct to command dmub, etc. 623 */ 624 struct secure_display_context secure_display_ctx; 625 #endif 626 /** 627 * @hpd_rx_offload_wq: 628 * 629 * Work queue to offload works of hpd_rx_irq 630 */ 631 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 632 /** 633 * @mst_encoders: 634 * 635 * fake encoders used for DP MST. 636 */ 637 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 638 bool force_timing_sync; 639 bool disable_hpd_irq; 640 bool dmcub_trace_event_en; 641 /** 642 * @da_list: 643 * 644 * DAL fb memory allocation list, for communication with SMU. 645 */ 646 struct list_head da_list; 647 struct completion dmub_aux_transfer_done; 648 struct workqueue_struct *delayed_hpd_wq; 649 650 /** 651 * @brightness: 652 * 653 * cached backlight values. 654 */ 655 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 656 /** 657 * @actual_brightness: 658 * 659 * last successfully applied backlight values. 660 */ 661 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 662 663 /** 664 * @aux_hpd_discon_quirk: 665 * 666 * quirk for hpd discon while aux is on-going. 667 * occurred on certain intel platform 668 */ 669 bool aux_hpd_discon_quirk; 670 671 /** 672 * @edp0_on_dp1_quirk: 673 * 674 * quirk for platforms that put edp0 on DP1. 675 */ 676 bool edp0_on_dp1_quirk; 677 678 /** 679 * @dpia_aux_lock: 680 * 681 * Guards access to DPIA AUX 682 */ 683 struct mutex dpia_aux_lock; 684 685 /** 686 * @bb_from_dmub: 687 * 688 * Bounding box data read from dmub during early initialization for DCN4+ 689 * Data is stored as a byte array that should be casted to the appropriate bb struct 690 */ 691 void *bb_from_dmub; 692 693 /** 694 * @oem_i2c: 695 * 696 * OEM i2c bus 697 */ 698 struct amdgpu_i2c_adapter *oem_i2c; 699 700 /** 701 * @fused_io: 702 * 703 * dmub fused io interface 704 */ 705 struct fused_io_sync { 706 struct completion replied; 707 char reply_data[0x40]; // Cannot include dmub_cmd here 708 } fused_io[8]; 709 710 /** 711 * @dm_boot_time_crc_info: 712 * 713 * Buffer info for the boot time crc. 714 */ 715 struct dm_boot_time_crc_info boot_time_crc_info; 716 }; 717 718 enum dsc_clock_force_state { 719 DSC_CLK_FORCE_DEFAULT = 0, 720 DSC_CLK_FORCE_ENABLE, 721 DSC_CLK_FORCE_DISABLE, 722 }; 723 724 struct dsc_preferred_settings { 725 enum dsc_clock_force_state dsc_force_enable; 726 uint32_t dsc_num_slices_v; 727 uint32_t dsc_num_slices_h; 728 uint32_t dsc_bits_per_pixel; 729 bool dsc_force_disable_passthrough; 730 }; 731 732 enum mst_progress_status { 733 MST_STATUS_DEFAULT = 0, 734 MST_PROBE = BIT(0), 735 MST_REMOTE_EDID = BIT(1), 736 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 737 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 738 }; 739 740 /** 741 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 742 * 743 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 744 * struct is useful to keep track of the display-specific information about 745 * FreeSync. 746 */ 747 struct amdgpu_hdmi_vsdb_info { 748 /** 749 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 750 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 751 */ 752 unsigned int amd_vsdb_version; 753 754 /** 755 * @freesync_supported: FreeSync Supported. 756 */ 757 bool freesync_supported; 758 759 /** 760 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 761 */ 762 unsigned int min_refresh_rate_hz; 763 764 /** 765 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 766 */ 767 unsigned int max_refresh_rate_hz; 768 769 /** 770 * @freesync_mccs_vcp_code: MCCS VCP code for freesync state 771 */ 772 unsigned int freesync_mccs_vcp_code; 773 774 /** 775 * @replay_mode: Replay supported 776 */ 777 bool replay_mode; 778 }; 779 780 struct amdgpu_dm_connector { 781 782 struct drm_connector base; 783 uint32_t connector_id; 784 int bl_idx; 785 786 struct cec_notifier *notifier; 787 788 /* we need to mind the EDID between detect 789 and get modes due to analog/digital/tvencoder */ 790 const struct drm_edid *drm_edid; 791 792 /* shared with amdgpu */ 793 struct amdgpu_hpd hpd; 794 795 /* number of modes generated from EDID at 'dc_sink' */ 796 int num_modes; 797 798 /* The 'old' sink - before an HPD. 799 * The 'current' sink is in dc_link->sink. */ 800 struct dc_sink *dc_sink; 801 struct dc_link *dc_link; 802 803 /** 804 * @dc_em_sink: Reference to the emulated (virtual) sink. 805 */ 806 struct dc_sink *dc_em_sink; 807 808 /* DM only */ 809 struct drm_dp_mst_topology_mgr mst_mgr; 810 struct amdgpu_dm_dp_aux dm_dp_aux; 811 struct drm_dp_mst_port *mst_output_port; 812 struct amdgpu_dm_connector *mst_root; 813 struct drm_dp_aux *dsc_aux; 814 uint32_t mst_local_bw; 815 uint16_t vc_full_pbn; 816 struct mutex handle_mst_msg_ready; 817 818 /* branch device specific data */ 819 uint32_t branch_ieee_oui; 820 821 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 822 struct amdgpu_i2c_adapter *i2c; 823 824 /* Monitor range limits */ 825 /** 826 * @min_vfreq: Minimal frequency supported by the display in Hz. This 827 * value is set to zero when there is no FreeSync support. 828 */ 829 int min_vfreq; 830 831 /** 832 * @max_vfreq: Maximum frequency supported by the display in Hz. This 833 * value is set to zero when there is no FreeSync support. 834 */ 835 int max_vfreq ; 836 837 /* Audio instance - protected by audio_lock. */ 838 int audio_inst; 839 840 struct mutex hpd_lock; 841 842 bool fake_enable; 843 bool force_yuv420_output; 844 bool force_yuv422_output; 845 struct dsc_preferred_settings dsc_settings; 846 struct psr_caps psr_caps; 847 union dp_downstream_port_present mst_downstream_port_present; 848 /* Cached display modes */ 849 struct drm_display_mode freesync_vid_base; 850 851 int sr_skip_count; 852 bool disallow_edp_enter_psr; 853 bool disallow_edp_enter_replay; 854 855 /* Record progress status of mst*/ 856 uint8_t mst_status; 857 858 /* Automated testing */ 859 bool timing_changed; 860 struct dc_crtc_timing *timing_requested; 861 862 /* Adaptive Sync */ 863 bool pack_sdp_v1_3; 864 enum adaptive_sync_type as_type; 865 struct amdgpu_hdmi_vsdb_info vsdb_info; 866 867 /* HDMI HPD debounce support */ 868 unsigned int hdmi_hpd_debounce_delay_ms; 869 struct delayed_work hdmi_hpd_debounce_work; 870 struct dc_sink *hdmi_prev_sink; 871 }; 872 873 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 874 uint8_t flags, bool set) 875 { 876 if (set) 877 *status |= flags; 878 else 879 *status &= ~flags; 880 } 881 882 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 883 884 struct amdgpu_dm_wb_connector { 885 struct drm_writeback_connector base; 886 struct dc_link *link; 887 }; 888 889 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 890 891 extern const struct amdgpu_ip_block_version dm_ip_block; 892 893 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 894 * 895 * It includes standardized transfer functions and pure power functions. The 896 * transfer function coefficients are available at modules/color/color_gamma.c 897 */ 898 enum amdgpu_transfer_function { 899 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 900 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 901 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 902 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 903 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 904 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 905 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 906 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 907 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 908 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 909 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 910 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 911 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 912 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 913 AMDGPU_TRANSFER_FUNCTION_COUNT 914 }; 915 916 struct dm_plane_state { 917 struct drm_plane_state base; 918 struct dc_plane_state *dc_state; 919 920 /* Plane color mgmt */ 921 /** 922 * @degamma_lut: 923 * 924 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 925 * blending operations. It's usually applied to linearize input space. 926 * The blob (if not NULL) is an array of &struct drm_color_lut. 927 */ 928 struct drm_property_blob *degamma_lut; 929 /** 930 * @degamma_tf: 931 * 932 * Predefined transfer function to tell DC driver the input space to 933 * linearize. 934 */ 935 enum amdgpu_transfer_function degamma_tf; 936 /** 937 * @hdr_mult: 938 * 939 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 940 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 941 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 942 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 943 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 944 * S31.32 sign-magnitude. 945 * 946 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 947 * TF is needed for any subsequent linear-to-non-linear transforms. 948 */ 949 __u64 hdr_mult; 950 /** 951 * @ctm: 952 * 953 * Color transformation matrix. The blob (if not NULL) is a &struct 954 * drm_color_ctm_3x4. 955 */ 956 struct drm_property_blob *ctm; 957 /** 958 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 959 * array of &struct drm_color_lut. 960 */ 961 struct drm_property_blob *shaper_lut; 962 /** 963 * @shaper_tf: 964 * 965 * Predefined transfer function to delinearize color space. 966 */ 967 enum amdgpu_transfer_function shaper_tf; 968 /** 969 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 970 * &struct drm_color_lut. 971 */ 972 struct drm_property_blob *lut3d; 973 /** 974 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 975 * array of &struct drm_color_lut. 976 */ 977 struct drm_property_blob *blend_lut; 978 /** 979 * @blend_tf: 980 * 981 * Pre-defined transfer function for converting plane pixel data before 982 * applying blend LUT. 983 */ 984 enum amdgpu_transfer_function blend_tf; 985 }; 986 987 enum amdgpu_dm_cursor_mode { 988 DM_CURSOR_NATIVE_MODE = 0, 989 DM_CURSOR_OVERLAY_MODE, 990 }; 991 992 struct dm_crtc_state { 993 struct drm_crtc_state base; 994 struct dc_stream_state *stream; 995 996 bool cm_has_degamma; 997 bool cm_is_degamma_srgb; 998 999 bool mpo_requested; 1000 1001 int update_type; 1002 int active_planes; 1003 1004 int crc_skip_count; 1005 1006 bool freesync_vrr_info_changed; 1007 1008 bool mode_changed_independent_from_dsc; 1009 bool dsc_force_changed; 1010 bool vrr_supported; 1011 struct mod_freesync_config freesync_config; 1012 struct dc_info_packet vrr_infopacket; 1013 1014 int abm_level; 1015 1016 /** 1017 * @regamma_tf: 1018 * 1019 * Pre-defined transfer function for converting internal FB -> wire 1020 * encoding. 1021 */ 1022 enum amdgpu_transfer_function regamma_tf; 1023 1024 enum amdgpu_dm_cursor_mode cursor_mode; 1025 }; 1026 1027 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 1028 1029 struct dm_atomic_state { 1030 struct drm_private_state base; 1031 1032 struct dc_state *context; 1033 }; 1034 1035 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 1036 1037 struct dm_connector_state { 1038 struct drm_connector_state base; 1039 1040 enum amdgpu_rmx_type scaling; 1041 uint8_t underscan_vborder; 1042 uint8_t underscan_hborder; 1043 bool underscan_enable; 1044 bool freesync_capable; 1045 bool update_hdcp; 1046 bool abm_sysfs_forbidden; 1047 uint8_t abm_level; 1048 int vcpi_slots; 1049 uint64_t pbn; 1050 }; 1051 1052 #define to_dm_connector_state(x)\ 1053 container_of((x), struct dm_connector_state, base) 1054 1055 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1056 struct drm_connector_state * 1057 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1058 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1059 struct drm_connector_state *state, 1060 struct drm_property *property, 1061 uint64_t val); 1062 1063 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1064 const struct drm_connector_state *state, 1065 struct drm_property *property, 1066 uint64_t *val); 1067 1068 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1069 1070 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1071 struct amdgpu_dm_connector *aconnector, 1072 int connector_type, 1073 struct dc_link *link, 1074 int link_index); 1075 1076 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1077 const struct drm_display_mode *mode); 1078 1079 void dm_restore_drm_connector_state(struct drm_device *dev, 1080 struct drm_connector *connector); 1081 1082 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1083 const struct drm_edid *drm_edid, bool do_mccs); 1084 1085 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1086 1087 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1088 #define MAX_COLOR_3DLUT_SIZE 17 1089 #define MAX_COLOR_3DLUT_BITDEPTH 12 1090 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1091 struct drm_plane_state *plane_state); 1092 /* 1D LUT size */ 1093 #define MAX_COLOR_LUT_ENTRIES 4096 1094 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1095 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1096 1097 void amdgpu_dm_init_color_mod(void); 1098 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1099 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1100 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1101 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1102 bool check_only); 1103 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1104 struct drm_plane_state *plane_state, 1105 struct dc_plane_state *dc_plane_state); 1106 1107 void amdgpu_dm_update_connector_after_detect( 1108 struct amdgpu_dm_connector *aconnector); 1109 1110 void populate_hdmi_info_from_connector(struct drm_hdmi_info *info, 1111 struct dc_edid_caps *edid_caps); 1112 1113 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1114 1115 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1116 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1117 1118 bool amdgpu_dm_execute_fused_io( 1119 struct amdgpu_device *dev, 1120 struct dc_link *link, 1121 union dmub_rb_cmd *commands, 1122 uint8_t count, 1123 uint32_t timeout_us 1124 ); 1125 1126 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1127 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1128 1129 struct dc_stream_state * 1130 create_validate_stream_for_sink(struct drm_connector *connector, 1131 const struct drm_display_mode *drm_mode, 1132 const struct dm_connector_state *dm_state, 1133 const struct dc_stream_state *old_stream); 1134 1135 int dm_atomic_get_state(struct drm_atomic_commit *state, 1136 struct dm_atomic_state **dm_state); 1137 1138 struct drm_connector * 1139 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_commit *state, 1140 struct drm_crtc *crtc); 1141 1142 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1143 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1144 1145 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1146 enum dc_gpu_mem_alloc_type type, 1147 size_t size, 1148 long long *addr); 1149 void dm_free_gpu_mem(struct amdgpu_device *adev, 1150 enum dc_gpu_mem_alloc_type type, 1151 void *addr); 1152 1153 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1154 1155 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1156 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1157 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1158 1159 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1160 1161 void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx); 1162 #endif /* __AMDGPU_DM_H__ */ 1163