1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic.h> 31 32 /* 33 * This file contains the definition for amdgpu_display_manager 34 * and its API for amdgpu driver's use. 35 * This component provides all the display related functionality 36 * and this is the only component that calls DAL API. 37 * The API contained here intended for amdgpu driver use. 38 * The API that is called directly from KMS framework is located 39 * in amdgpu_dm_kms.h file 40 */ 41 42 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 43 /* 44 #include "include/amdgpu_dal_power_if.h" 45 #include "amdgpu_dm_irq.h" 46 */ 47 48 #include "irq_types.h" 49 #include "signal_types.h" 50 51 /* Forward declarations */ 52 struct amdgpu_device; 53 struct drm_device; 54 struct amdgpu_dm_irq_handler_data; 55 struct dc; 56 57 struct amdgpu_dm_prev_state { 58 struct drm_framebuffer *fb; 59 int32_t x; 60 int32_t y; 61 struct drm_display_mode mode; 62 }; 63 64 struct common_irq_params { 65 struct amdgpu_device *adev; 66 enum dc_irq_source irq_src; 67 }; 68 69 struct irq_list_head { 70 struct list_head head; 71 /* In case this interrupt needs post-processing, 'work' will be queued*/ 72 struct work_struct work; 73 }; 74 75 #if defined(CONFIG_DRM_AMD_DC_FBC) 76 struct dm_comressor_info { 77 void *cpu_addr; 78 struct amdgpu_bo *bo_ptr; 79 uint64_t gpu_addr; 80 }; 81 #endif 82 83 84 struct amdgpu_display_manager { 85 struct dal *dal; 86 struct dc *dc; 87 struct cgs_device *cgs_device; 88 89 struct amdgpu_device *adev; /*AMD base driver*/ 90 struct drm_device *ddev; /*DRM base driver*/ 91 u16 display_indexes_num; 92 93 struct amdgpu_dm_prev_state prev_state; 94 95 /* 96 * 'irq_source_handler_table' holds a list of handlers 97 * per (DAL) IRQ source. 98 * 99 * Each IRQ source may need to be handled at different contexts. 100 * By 'context' we mean, for example: 101 * - The ISR context, which is the direct interrupt handler. 102 * - The 'deferred' context - this is the post-processing of the 103 * interrupt, but at a lower priority. 104 * 105 * Note that handlers are called in the same order as they were 106 * registered (FIFO). 107 */ 108 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 109 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 110 111 struct common_irq_params 112 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 113 114 struct common_irq_params 115 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 116 117 /* this spin lock synchronizes access to 'irq_handler_list_table' */ 118 spinlock_t irq_handler_list_table_lock; 119 120 struct backlight_device *backlight_dev; 121 122 const struct dc_link *backlight_link; 123 124 struct work_struct mst_hotplug_work; 125 126 struct mod_freesync *freesync_module; 127 128 /** 129 * Caches device atomic state for suspend/resume 130 */ 131 struct drm_atomic_state *cached_state; 132 #if defined(CONFIG_DRM_AMD_DC_FBC) 133 struct dm_comressor_info compressor; 134 #endif 135 }; 136 137 struct amdgpu_dm_connector { 138 139 struct drm_connector base; 140 uint32_t connector_id; 141 142 /* we need to mind the EDID between detect 143 and get modes due to analog/digital/tvencoder */ 144 struct edid *edid; 145 146 /* shared with amdgpu */ 147 struct amdgpu_hpd hpd; 148 149 /* number of modes generated from EDID at 'dc_sink' */ 150 int num_modes; 151 152 /* The 'old' sink - before an HPD. 153 * The 'current' sink is in dc_link->sink. */ 154 struct dc_sink *dc_sink; 155 struct dc_link *dc_link; 156 struct dc_sink *dc_em_sink; 157 158 /* DM only */ 159 struct drm_dp_mst_topology_mgr mst_mgr; 160 struct amdgpu_dm_dp_aux dm_dp_aux; 161 struct drm_dp_mst_port *port; 162 struct amdgpu_dm_connector *mst_port; 163 struct amdgpu_encoder *mst_encoder; 164 165 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 166 struct amdgpu_i2c_adapter *i2c; 167 168 /* Monitor range limits */ 169 int min_vfreq ; 170 int max_vfreq ; 171 int pixel_clock_mhz; 172 173 /*freesync caps*/ 174 struct mod_freesync_caps caps; 175 176 struct mutex hpd_lock; 177 178 bool fake_enable; 179 180 bool mst_connected; 181 }; 182 183 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 184 185 extern const struct amdgpu_ip_block_version dm_ip_block; 186 187 struct amdgpu_framebuffer; 188 struct amdgpu_display_manager; 189 struct dc_validation_set; 190 struct dc_plane_state; 191 192 struct dm_plane_state { 193 struct drm_plane_state base; 194 struct dc_plane_state *dc_state; 195 }; 196 197 struct dm_crtc_state { 198 struct drm_crtc_state base; 199 struct dc_stream_state *stream; 200 201 int crc_skip_count; 202 bool crc_enabled; 203 }; 204 205 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 206 207 struct dm_atomic_state { 208 struct drm_atomic_state base; 209 210 struct dc_state *context; 211 }; 212 213 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 214 215 struct dm_connector_state { 216 struct drm_connector_state base; 217 218 enum amdgpu_rmx_type scaling; 219 uint8_t underscan_vborder; 220 uint8_t underscan_hborder; 221 bool underscan_enable; 222 struct mod_freesync_user_enable user_enable; 223 bool freesync_capable; 224 }; 225 226 #define to_dm_connector_state(x)\ 227 container_of((x), struct dm_connector_state, base) 228 229 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 230 struct drm_connector_state * 231 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 232 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 233 struct drm_connector_state *state, 234 struct drm_property *property, 235 uint64_t val); 236 237 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 238 const struct drm_connector_state *state, 239 struct drm_property *property, 240 uint64_t *val); 241 242 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 243 244 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 245 struct amdgpu_dm_connector *aconnector, 246 int connector_type, 247 struct dc_link *link, 248 int link_index); 249 250 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 251 struct drm_display_mode *mode); 252 253 void dm_restore_drm_connector_state(struct drm_device *dev, 254 struct drm_connector *connector); 255 256 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, 257 struct edid *edid); 258 259 void 260 amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector); 261 262 /* amdgpu_dm_crc.c */ 263 #ifdef CONFIG_DEBUG_FS 264 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name, 265 size_t *values_cnt); 266 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 267 #else 268 #define amdgpu_dm_crtc_set_crc_source NULL 269 #define amdgpu_dm_crtc_handle_crc_irq(x) 270 #endif 271 272 #define MAX_COLOR_LUT_ENTRIES 4096 273 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 274 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 275 276 void amdgpu_dm_init_color_mod(void); 277 int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, 278 struct dc_plane_state *dc_plane_state); 279 void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); 280 int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); 281 282 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 283 284 #endif /* __AMDGPU_DM_H__ */ 285