1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 #include "link_service_types.h" 35 #include <drm/drm_writeback.h> 36 37 /* 38 * This file contains the definition for amdgpu_display_manager 39 * and its API for amdgpu driver's use. 40 * This component provides all the display related functionality 41 * and this is the only component that calls DAL API. 42 * The API contained here intended for amdgpu driver use. 43 * The API that is called directly from KMS framework is located 44 * in amdgpu_dm_kms.h file 45 */ 46 47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 48 49 #define AMDGPU_DM_MAX_CRTC 6 50 51 #define AMDGPU_DM_MAX_NUM_EDP 2 52 53 #define AMDGPU_DMUB_NOTIFICATION_MAX 5 54 55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 58 59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 60 61 /* 62 #include "include/amdgpu_dal_power_if.h" 63 #include "amdgpu_dm_irq.h" 64 */ 65 66 #include "irq_types.h" 67 #include "signal_types.h" 68 #include "amdgpu_dm_crc.h" 69 #include "mod_info_packet.h" 70 struct aux_payload; 71 struct set_config_cmd_payload; 72 enum aux_return_code_type; 73 enum set_config_status; 74 75 /* Forward declarations */ 76 struct amdgpu_device; 77 struct amdgpu_crtc; 78 struct drm_device; 79 struct dc; 80 struct amdgpu_bo; 81 struct dmub_srv; 82 struct dc_plane_state; 83 struct dmub_notification; 84 85 struct amd_vsdb_block { 86 unsigned char ieee_id[3]; 87 unsigned char version; 88 unsigned char feature_caps; 89 }; 90 91 struct common_irq_params { 92 struct amdgpu_device *adev; 93 enum dc_irq_source irq_src; 94 atomic64_t previous_timestamp; 95 }; 96 97 /** 98 * struct dm_compressor_info - Buffer info used by frame buffer compression 99 * @cpu_addr: MMIO cpu addr 100 * @bo_ptr: Pointer to the buffer object 101 * @gpu_addr: MMIO gpu addr 102 */ 103 struct dm_compressor_info { 104 void *cpu_addr; 105 struct amdgpu_bo *bo_ptr; 106 uint64_t gpu_addr; 107 }; 108 109 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 110 111 /** 112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 113 * 114 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 115 * @dmub_notify: notification for callback function 116 * @adev: amdgpu_device pointer 117 */ 118 struct dmub_hpd_work { 119 struct work_struct handle_hpd_work; 120 struct dmub_notification *dmub_notify; 121 struct amdgpu_device *adev; 122 }; 123 124 /** 125 * struct vblank_control_work - Work data for vblank control 126 * @work: Kernel work data for the work event 127 * @dm: amdgpu display manager device 128 * @acrtc: amdgpu CRTC instance for which the event has occurred 129 * @stream: DC stream for which the event has occurred 130 * @enable: true if enabling vblank 131 */ 132 struct vblank_control_work { 133 struct work_struct work; 134 struct amdgpu_display_manager *dm; 135 struct amdgpu_crtc *acrtc; 136 struct dc_stream_state *stream; 137 bool enable; 138 }; 139 140 struct idle_workqueue { 141 struct work_struct work; 142 struct amdgpu_display_manager *dm; 143 bool enable; 144 bool running; 145 }; 146 147 /** 148 * struct amdgpu_dm_backlight_caps - Information about backlight 149 * 150 * Describe the backlight support for ACPI or eDP AUX. 151 */ 152 struct amdgpu_dm_backlight_caps { 153 /** 154 * @ext_caps: Keep the data struct with all the information about the 155 * display support for HDR. 156 */ 157 union dpcd_sink_ext_caps *ext_caps; 158 /** 159 * @aux_min_input_signal: Min brightness value supported by the display 160 */ 161 u32 aux_min_input_signal; 162 /** 163 * @aux_max_input_signal: Max brightness value supported by the display 164 * in nits. 165 */ 166 u32 aux_max_input_signal; 167 /** 168 * @min_input_signal: minimum possible input in range 0-255. 169 */ 170 int min_input_signal; 171 /** 172 * @max_input_signal: maximum possible input in range 0-255. 173 */ 174 int max_input_signal; 175 /** 176 * @caps_valid: true if these values are from the ACPI interface. 177 */ 178 bool caps_valid; 179 /** 180 * @aux_support: Describes if the display supports AUX backlight. 181 */ 182 bool aux_support; 183 }; 184 185 /** 186 * struct dal_allocation - Tracks mapped FB memory for SMU communication 187 * @list: list of dal allocations 188 * @bo: GPU buffer object 189 * @cpu_ptr: CPU virtual address of the GPU buffer object 190 * @gpu_addr: GPU virtual address of the GPU buffer object 191 */ 192 struct dal_allocation { 193 struct list_head list; 194 struct amdgpu_bo *bo; 195 void *cpu_ptr; 196 u64 gpu_addr; 197 }; 198 199 /** 200 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 201 * offload work 202 */ 203 struct hpd_rx_irq_offload_work_queue { 204 /** 205 * @wq: workqueue structure to queue offload work. 206 */ 207 struct workqueue_struct *wq; 208 /** 209 * @offload_lock: To protect fields of offload work queue. 210 */ 211 spinlock_t offload_lock; 212 /** 213 * @is_handling_link_loss: Used to prevent inserting link loss event when 214 * we're handling link loss 215 */ 216 bool is_handling_link_loss; 217 /** 218 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 219 * ready event when we're already handling mst message ready event 220 */ 221 bool is_handling_mst_msg_rdy_event; 222 /** 223 * @aconnector: The aconnector that this work queue is attached to 224 */ 225 struct amdgpu_dm_connector *aconnector; 226 }; 227 228 /** 229 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 230 */ 231 struct hpd_rx_irq_offload_work { 232 /** 233 * @work: offload work 234 */ 235 struct work_struct work; 236 /** 237 * @data: reference irq data which is used while handling offload work 238 */ 239 union hpd_irq_data data; 240 /** 241 * @offload_wq: offload work queue that this work is queued to 242 */ 243 struct hpd_rx_irq_offload_work_queue *offload_wq; 244 }; 245 246 /** 247 * struct amdgpu_display_manager - Central amdgpu display manager device 248 * 249 * @dc: Display Core control structure 250 * @adev: AMDGPU base driver structure 251 * @ddev: DRM base driver structure 252 * @display_indexes_num: Max number of display streams supported 253 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 254 * @backlight_dev: Backlight control device 255 * @backlight_link: Link on which to control backlight 256 * @backlight_caps: Capabilities of the backlight device 257 * @freesync_module: Module handling freesync calculations 258 * @hdcp_workqueue: AMDGPU content protection queue 259 * @fw_dmcu: Reference to DMCU firmware 260 * @dmcu_fw_version: Version of the DMCU firmware 261 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 262 * @cached_state: Caches device atomic state for suspend/resume 263 * @cached_dc_state: Cached state of content streams 264 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 265 * @force_timing_sync: set via debugfs. When set, indicates that all connected 266 * displays will be forced to synchronize. 267 * @dmcub_trace_event_en: enable dmcub trace events 268 * @dmub_outbox_params: DMUB Outbox parameters 269 * @num_of_edps: number of backlight eDPs 270 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 271 * driver when true 272 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 273 * transfers are done 274 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 275 */ 276 struct amdgpu_display_manager { 277 278 struct dc *dc; 279 280 /** 281 * @dmub_srv: 282 * 283 * DMUB service, used for controlling the DMUB on hardware 284 * that supports it. The pointer to the dmub_srv will be 285 * NULL on hardware that does not support it. 286 */ 287 struct dmub_srv *dmub_srv; 288 289 /** 290 * @dmub_notify: 291 * 292 * Notification from DMUB. 293 */ 294 295 struct dmub_notification *dmub_notify; 296 297 /** 298 * @dmub_callback: 299 * 300 * Callback functions to handle notification from DMUB. 301 */ 302 303 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 304 305 /** 306 * @dmub_thread_offload: 307 * 308 * Flag to indicate if callback is offload. 309 */ 310 311 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 312 313 /** 314 * @dmub_fb_info: 315 * 316 * Framebuffer regions for the DMUB. 317 */ 318 struct dmub_srv_fb_info *dmub_fb_info; 319 320 /** 321 * @dmub_fw: 322 * 323 * DMUB firmware, required on hardware that has DMUB support. 324 */ 325 const struct firmware *dmub_fw; 326 327 /** 328 * @dmub_bo: 329 * 330 * Buffer object for the DMUB. 331 */ 332 struct amdgpu_bo *dmub_bo; 333 334 /** 335 * @dmub_bo_gpu_addr: 336 * 337 * GPU virtual address for the DMUB buffer object. 338 */ 339 u64 dmub_bo_gpu_addr; 340 341 /** 342 * @dmub_bo_cpu_addr: 343 * 344 * CPU address for the DMUB buffer object. 345 */ 346 void *dmub_bo_cpu_addr; 347 348 /** 349 * @dmcub_fw_version: 350 * 351 * DMCUB firmware version. 352 */ 353 uint32_t dmcub_fw_version; 354 355 /** 356 * @cgs_device: 357 * 358 * The Common Graphics Services device. It provides an interface for 359 * accessing registers. 360 */ 361 struct cgs_device *cgs_device; 362 363 struct amdgpu_device *adev; 364 struct drm_device *ddev; 365 u16 display_indexes_num; 366 367 /** 368 * @atomic_obj: 369 * 370 * In combination with &dm_atomic_state it helps manage 371 * global atomic state that doesn't map cleanly into existing 372 * drm resources, like &dc_context. 373 */ 374 struct drm_private_obj atomic_obj; 375 376 /** 377 * @dc_lock: 378 * 379 * Guards access to DC functions that can issue register write 380 * sequences. 381 */ 382 struct mutex dc_lock; 383 384 /** 385 * @audio_lock: 386 * 387 * Guards access to audio instance changes. 388 */ 389 struct mutex audio_lock; 390 391 /** 392 * @audio_component: 393 * 394 * Used to notify ELD changes to sound driver. 395 */ 396 struct drm_audio_component *audio_component; 397 398 /** 399 * @audio_registered: 400 * 401 * True if the audio component has been registered 402 * successfully, false otherwise. 403 */ 404 bool audio_registered; 405 406 /** 407 * @irq_handler_list_low_tab: 408 * 409 * Low priority IRQ handler table. 410 * 411 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 412 * source. Low priority IRQ handlers are deferred to a workqueue to be 413 * processed. Hence, they can sleep. 414 * 415 * Note that handlers are called in the same order as they were 416 * registered (FIFO). 417 */ 418 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 419 420 /** 421 * @irq_handler_list_high_tab: 422 * 423 * High priority IRQ handler table. 424 * 425 * It is a n*m table, same as &irq_handler_list_low_tab. However, 426 * handlers in this table are not deferred and are called immediately. 427 */ 428 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 429 430 /** 431 * @pflip_params: 432 * 433 * Page flip IRQ parameters, passed to registered handlers when 434 * triggered. 435 */ 436 struct common_irq_params 437 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 438 439 /** 440 * @vblank_params: 441 * 442 * Vertical blanking IRQ parameters, passed to registered handlers when 443 * triggered. 444 */ 445 struct common_irq_params 446 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 447 448 /** 449 * @vline0_params: 450 * 451 * OTG vertical interrupt0 IRQ parameters, passed to registered 452 * handlers when triggered. 453 */ 454 struct common_irq_params 455 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 456 457 /** 458 * @vupdate_params: 459 * 460 * Vertical update IRQ parameters, passed to registered handlers when 461 * triggered. 462 */ 463 struct common_irq_params 464 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 465 466 /** 467 * @dmub_trace_params: 468 * 469 * DMUB trace event IRQ parameters, passed to registered handlers when 470 * triggered. 471 */ 472 struct common_irq_params 473 dmub_trace_params[1]; 474 475 struct common_irq_params 476 dmub_outbox_params[1]; 477 478 spinlock_t irq_handler_list_table_lock; 479 480 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 481 482 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 483 484 uint8_t num_of_edps; 485 486 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 487 488 struct mod_freesync *freesync_module; 489 struct hdcp_workqueue *hdcp_workqueue; 490 491 /** 492 * @vblank_control_workqueue: 493 * 494 * Deferred work for vblank control events. 495 */ 496 struct workqueue_struct *vblank_control_workqueue; 497 struct idle_workqueue *idle_workqueue; 498 499 struct drm_atomic_state *cached_state; 500 struct dc_state *cached_dc_state; 501 502 struct dm_compressor_info compressor; 503 504 const struct firmware *fw_dmcu; 505 uint32_t dmcu_fw_version; 506 /** 507 * @soc_bounding_box: 508 * 509 * gpu_info FW provided soc bounding box struct or 0 if not 510 * available in FW 511 */ 512 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 513 514 /** 515 * @active_vblank_irq_count: 516 * 517 * number of currently active vblank irqs 518 */ 519 uint32_t active_vblank_irq_count; 520 521 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 522 /** 523 * @secure_display_ctxs: 524 * 525 * Store the ROI information and the work_struct to command dmub and psp for 526 * all crtcs. 527 */ 528 struct secure_display_context *secure_display_ctxs; 529 #endif 530 /** 531 * @hpd_rx_offload_wq: 532 * 533 * Work queue to offload works of hpd_rx_irq 534 */ 535 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 536 /** 537 * @mst_encoders: 538 * 539 * fake encoders used for DP MST. 540 */ 541 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 542 bool force_timing_sync; 543 bool disable_hpd_irq; 544 bool dmcub_trace_event_en; 545 /** 546 * @da_list: 547 * 548 * DAL fb memory allocation list, for communication with SMU. 549 */ 550 struct list_head da_list; 551 struct completion dmub_aux_transfer_done; 552 struct workqueue_struct *delayed_hpd_wq; 553 554 /** 555 * @brightness: 556 * 557 * cached backlight values. 558 */ 559 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 560 /** 561 * @actual_brightness: 562 * 563 * last successfully applied backlight values. 564 */ 565 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 566 567 /** 568 * @aux_hpd_discon_quirk: 569 * 570 * quirk for hpd discon while aux is on-going. 571 * occurred on certain intel platform 572 */ 573 bool aux_hpd_discon_quirk; 574 575 /** 576 * @dpia_aux_lock: 577 * 578 * Guards access to DPIA AUX 579 */ 580 struct mutex dpia_aux_lock; 581 }; 582 583 enum dsc_clock_force_state { 584 DSC_CLK_FORCE_DEFAULT = 0, 585 DSC_CLK_FORCE_ENABLE, 586 DSC_CLK_FORCE_DISABLE, 587 }; 588 589 struct dsc_preferred_settings { 590 enum dsc_clock_force_state dsc_force_enable; 591 uint32_t dsc_num_slices_v; 592 uint32_t dsc_num_slices_h; 593 uint32_t dsc_bits_per_pixel; 594 bool dsc_force_disable_passthrough; 595 }; 596 597 enum mst_progress_status { 598 MST_STATUS_DEFAULT = 0, 599 MST_PROBE = BIT(0), 600 MST_REMOTE_EDID = BIT(1), 601 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 602 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 603 }; 604 605 /** 606 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 607 * 608 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 609 * struct is useful to keep track of the display-specific information about 610 * FreeSync. 611 */ 612 struct amdgpu_hdmi_vsdb_info { 613 /** 614 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 615 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 616 */ 617 unsigned int amd_vsdb_version; 618 619 /** 620 * @freesync_supported: FreeSync Supported. 621 */ 622 bool freesync_supported; 623 624 /** 625 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 626 */ 627 unsigned int min_refresh_rate_hz; 628 629 /** 630 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 631 */ 632 unsigned int max_refresh_rate_hz; 633 634 /** 635 * @replay_mode: Replay supported 636 */ 637 bool replay_mode; 638 }; 639 640 struct amdgpu_dm_connector { 641 642 struct drm_connector base; 643 uint32_t connector_id; 644 int bl_idx; 645 646 /* we need to mind the EDID between detect 647 and get modes due to analog/digital/tvencoder */ 648 struct edid *edid; 649 650 /* shared with amdgpu */ 651 struct amdgpu_hpd hpd; 652 653 /* number of modes generated from EDID at 'dc_sink' */ 654 int num_modes; 655 656 /* The 'old' sink - before an HPD. 657 * The 'current' sink is in dc_link->sink. */ 658 struct dc_sink *dc_sink; 659 struct dc_link *dc_link; 660 661 /** 662 * @dc_em_sink: Reference to the emulated (virtual) sink. 663 */ 664 struct dc_sink *dc_em_sink; 665 666 /* DM only */ 667 struct drm_dp_mst_topology_mgr mst_mgr; 668 struct amdgpu_dm_dp_aux dm_dp_aux; 669 struct drm_dp_mst_port *mst_output_port; 670 struct amdgpu_dm_connector *mst_root; 671 struct drm_dp_aux *dsc_aux; 672 struct mutex handle_mst_msg_ready; 673 674 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 675 struct amdgpu_i2c_adapter *i2c; 676 677 /* Monitor range limits */ 678 /** 679 * @min_vfreq: Minimal frequency supported by the display in Hz. This 680 * value is set to zero when there is no FreeSync support. 681 */ 682 int min_vfreq; 683 684 /** 685 * @max_vfreq: Maximum frequency supported by the display in Hz. This 686 * value is set to zero when there is no FreeSync support. 687 */ 688 int max_vfreq ; 689 690 /* Audio instance - protected by audio_lock. */ 691 int audio_inst; 692 693 struct mutex hpd_lock; 694 695 bool fake_enable; 696 bool force_yuv420_output; 697 struct dsc_preferred_settings dsc_settings; 698 union dp_downstream_port_present mst_downstream_port_present; 699 /* Cached display modes */ 700 struct drm_display_mode freesync_vid_base; 701 702 int psr_skip_count; 703 bool disallow_edp_enter_psr; 704 705 /* Record progress status of mst*/ 706 uint8_t mst_status; 707 708 /* Automated testing */ 709 bool timing_changed; 710 struct dc_crtc_timing *timing_requested; 711 712 /* Adaptive Sync */ 713 bool pack_sdp_v1_3; 714 enum adaptive_sync_type as_type; 715 struct amdgpu_hdmi_vsdb_info vsdb_info; 716 }; 717 718 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 719 uint8_t flags, bool set) 720 { 721 if (set) 722 *status |= flags; 723 else 724 *status &= ~flags; 725 } 726 727 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 728 729 struct amdgpu_dm_wb_connector { 730 struct drm_writeback_connector base; 731 struct dc_link *link; 732 }; 733 734 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 735 736 extern const struct amdgpu_ip_block_version dm_ip_block; 737 738 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 739 * 740 * It includes standardized transfer functions and pure power functions. The 741 * transfer function coefficients are available at modules/color/color_gamma.c 742 */ 743 enum amdgpu_transfer_function { 744 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 745 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 746 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 747 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 748 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 749 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 750 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 751 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 752 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 753 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 754 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 755 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 756 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 757 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 758 AMDGPU_TRANSFER_FUNCTION_COUNT 759 }; 760 761 struct dm_plane_state { 762 struct drm_plane_state base; 763 struct dc_plane_state *dc_state; 764 765 /* Plane color mgmt */ 766 /** 767 * @degamma_lut: 768 * 769 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 770 * blending operations. It's usually applied to linearize input space. 771 * The blob (if not NULL) is an array of &struct drm_color_lut. 772 */ 773 struct drm_property_blob *degamma_lut; 774 /** 775 * @degamma_tf: 776 * 777 * Predefined transfer function to tell DC driver the input space to 778 * linearize. 779 */ 780 enum amdgpu_transfer_function degamma_tf; 781 /** 782 * @hdr_mult: 783 * 784 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 785 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 786 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 787 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 788 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 789 * S31.32 sign-magnitude. 790 * 791 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 792 * TF is needed for any subsequent linear-to-non-linear transforms. 793 */ 794 __u64 hdr_mult; 795 /** 796 * @ctm: 797 * 798 * Color transformation matrix. The blob (if not NULL) is a &struct 799 * drm_color_ctm_3x4. 800 */ 801 struct drm_property_blob *ctm; 802 /** 803 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 804 * array of &struct drm_color_lut. 805 */ 806 struct drm_property_blob *shaper_lut; 807 /** 808 * @shaper_tf: 809 * 810 * Predefined transfer function to delinearize color space. 811 */ 812 enum amdgpu_transfer_function shaper_tf; 813 /** 814 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 815 * &struct drm_color_lut. 816 */ 817 struct drm_property_blob *lut3d; 818 /** 819 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 820 * array of &struct drm_color_lut. 821 */ 822 struct drm_property_blob *blend_lut; 823 /** 824 * @blend_tf: 825 * 826 * Pre-defined transfer function for converting plane pixel data before 827 * applying blend LUT. 828 */ 829 enum amdgpu_transfer_function blend_tf; 830 }; 831 832 struct dm_crtc_state { 833 struct drm_crtc_state base; 834 struct dc_stream_state *stream; 835 836 bool cm_has_degamma; 837 bool cm_is_degamma_srgb; 838 839 bool mpo_requested; 840 841 int update_type; 842 int active_planes; 843 844 int crc_skip_count; 845 846 bool freesync_vrr_info_changed; 847 848 bool dsc_force_changed; 849 bool vrr_supported; 850 struct mod_freesync_config freesync_config; 851 struct dc_info_packet vrr_infopacket; 852 853 int abm_level; 854 855 /** 856 * @regamma_tf: 857 * 858 * Pre-defined transfer function for converting internal FB -> wire 859 * encoding. 860 */ 861 enum amdgpu_transfer_function regamma_tf; 862 }; 863 864 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 865 866 struct dm_atomic_state { 867 struct drm_private_state base; 868 869 struct dc_state *context; 870 }; 871 872 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 873 874 struct dm_connector_state { 875 struct drm_connector_state base; 876 877 enum amdgpu_rmx_type scaling; 878 uint8_t underscan_vborder; 879 uint8_t underscan_hborder; 880 bool underscan_enable; 881 bool freesync_capable; 882 bool update_hdcp; 883 uint8_t abm_level; 884 int vcpi_slots; 885 uint64_t pbn; 886 }; 887 888 #define to_dm_connector_state(x)\ 889 container_of((x), struct dm_connector_state, base) 890 891 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 892 struct drm_connector_state * 893 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 894 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 895 struct drm_connector_state *state, 896 struct drm_property *property, 897 uint64_t val); 898 899 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 900 const struct drm_connector_state *state, 901 struct drm_property *property, 902 uint64_t *val); 903 904 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 905 906 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 907 struct amdgpu_dm_connector *aconnector, 908 int connector_type, 909 struct dc_link *link, 910 int link_index); 911 912 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 913 struct drm_display_mode *mode); 914 915 void dm_restore_drm_connector_state(struct drm_device *dev, 916 struct drm_connector *connector); 917 918 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 919 struct edid *edid); 920 921 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 922 923 /* 3D LUT max size is 17x17x17 (4913 entries) */ 924 #define MAX_COLOR_3DLUT_SIZE 17 925 #define MAX_COLOR_3DLUT_BITDEPTH 12 926 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 927 struct drm_plane_state *plane_state); 928 /* 1D LUT size */ 929 #define MAX_COLOR_LUT_ENTRIES 4096 930 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 931 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 932 933 void amdgpu_dm_init_color_mod(void); 934 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 935 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 936 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 937 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 938 struct drm_plane_state *plane_state, 939 struct dc_plane_state *dc_plane_state); 940 941 void amdgpu_dm_update_connector_after_detect( 942 struct amdgpu_dm_connector *aconnector); 943 944 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 945 946 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 947 struct aux_payload *payload, enum aux_return_code_type *operation_result); 948 949 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 950 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 951 952 struct dc_stream_state * 953 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 954 const struct drm_display_mode *drm_mode, 955 const struct dm_connector_state *dm_state, 956 const struct dc_stream_state *old_stream); 957 958 int dm_atomic_get_state(struct drm_atomic_state *state, 959 struct dm_atomic_state **dm_state); 960 961 struct drm_connector * 962 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 963 struct drm_crtc *crtc); 964 965 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 966 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 967 #endif /* __AMDGPU_DM_H__ */ 968