1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 47 #define AMDGPU_DM_MAX_CRTC 6 48 49 #define AMDGPU_DM_MAX_NUM_EDP 2 50 51 #define AMDGPU_DMUB_NOTIFICATION_MAX 5 52 53 /* 54 * DMUB Async to Sync Mechanism Status 55 */ 56 #define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1 57 #define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2 58 #define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3 59 /* 60 #include "include/amdgpu_dal_power_if.h" 61 #include "amdgpu_dm_irq.h" 62 */ 63 64 #include "irq_types.h" 65 #include "signal_types.h" 66 #include "amdgpu_dm_crc.h" 67 struct aux_payload; 68 enum aux_return_code_type; 69 70 /* Forward declarations */ 71 struct amdgpu_device; 72 struct amdgpu_crtc; 73 struct drm_device; 74 struct dc; 75 struct amdgpu_bo; 76 struct dmub_srv; 77 struct dc_plane_state; 78 struct dmub_notification; 79 80 struct common_irq_params { 81 struct amdgpu_device *adev; 82 enum dc_irq_source irq_src; 83 atomic64_t previous_timestamp; 84 }; 85 86 /** 87 * struct dm_compressor_info - Buffer info used by frame buffer compression 88 * @cpu_addr: MMIO cpu addr 89 * @bo_ptr: Pointer to the buffer object 90 * @gpu_addr: MMIO gpu addr 91 */ 92 struct dm_compressor_info { 93 void *cpu_addr; 94 struct amdgpu_bo *bo_ptr; 95 uint64_t gpu_addr; 96 }; 97 98 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 99 100 /** 101 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 102 * 103 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 104 * @dmub_notify: notification for callback function 105 * @adev: amdgpu_device pointer 106 */ 107 struct dmub_hpd_work { 108 struct work_struct handle_hpd_work; 109 struct dmub_notification *dmub_notify; 110 struct amdgpu_device *adev; 111 }; 112 113 /** 114 * struct vblank_control_work - Work data for vblank control 115 * @work: Kernel work data for the work event 116 * @dm: amdgpu display manager device 117 * @acrtc: amdgpu CRTC instance for which the event has occurred 118 * @stream: DC stream for which the event has occurred 119 * @enable: true if enabling vblank 120 */ 121 struct vblank_control_work { 122 struct work_struct work; 123 struct amdgpu_display_manager *dm; 124 struct amdgpu_crtc *acrtc; 125 struct dc_stream_state *stream; 126 bool enable; 127 }; 128 129 /** 130 * struct amdgpu_dm_backlight_caps - Information about backlight 131 * 132 * Describe the backlight support for ACPI or eDP AUX. 133 */ 134 struct amdgpu_dm_backlight_caps { 135 /** 136 * @ext_caps: Keep the data struct with all the information about the 137 * display support for HDR. 138 */ 139 union dpcd_sink_ext_caps *ext_caps; 140 /** 141 * @aux_min_input_signal: Min brightness value supported by the display 142 */ 143 u32 aux_min_input_signal; 144 /** 145 * @aux_max_input_signal: Max brightness value supported by the display 146 * in nits. 147 */ 148 u32 aux_max_input_signal; 149 /** 150 * @min_input_signal: minimum possible input in range 0-255. 151 */ 152 int min_input_signal; 153 /** 154 * @max_input_signal: maximum possible input in range 0-255. 155 */ 156 int max_input_signal; 157 /** 158 * @caps_valid: true if these values are from the ACPI interface. 159 */ 160 bool caps_valid; 161 /** 162 * @aux_support: Describes if the display supports AUX backlight. 163 */ 164 bool aux_support; 165 }; 166 167 /** 168 * struct dal_allocation - Tracks mapped FB memory for SMU communication 169 * @list: list of dal allocations 170 * @bo: GPU buffer object 171 * @cpu_ptr: CPU virtual address of the GPU buffer object 172 * @gpu_addr: GPU virtual address of the GPU buffer object 173 */ 174 struct dal_allocation { 175 struct list_head list; 176 struct amdgpu_bo *bo; 177 void *cpu_ptr; 178 u64 gpu_addr; 179 }; 180 181 /** 182 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 183 * offload work 184 */ 185 struct hpd_rx_irq_offload_work_queue { 186 /** 187 * @wq: workqueue structure to queue offload work. 188 */ 189 struct workqueue_struct *wq; 190 /** 191 * @offload_lock: To protect fields of offload work queue. 192 */ 193 spinlock_t offload_lock; 194 /** 195 * @is_handling_link_loss: Used to prevent inserting link loss event when 196 * we're handling link loss 197 */ 198 bool is_handling_link_loss; 199 /** 200 * @aconnector: The aconnector that this work queue is attached to 201 */ 202 struct amdgpu_dm_connector *aconnector; 203 }; 204 205 /** 206 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 207 */ 208 struct hpd_rx_irq_offload_work { 209 /** 210 * @work: offload work 211 */ 212 struct work_struct work; 213 /** 214 * @data: reference irq data which is used while handling offload work 215 */ 216 union hpd_irq_data data; 217 /** 218 * @offload_wq: offload work queue that this work is queued to 219 */ 220 struct hpd_rx_irq_offload_work_queue *offload_wq; 221 }; 222 223 /** 224 * struct amdgpu_display_manager - Central amdgpu display manager device 225 * 226 * @dc: Display Core control structure 227 * @adev: AMDGPU base driver structure 228 * @ddev: DRM base driver structure 229 * @display_indexes_num: Max number of display streams supported 230 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 231 * @backlight_dev: Backlight control device 232 * @backlight_link: Link on which to control backlight 233 * @backlight_caps: Capabilities of the backlight device 234 * @freesync_module: Module handling freesync calculations 235 * @hdcp_workqueue: AMDGPU content protection queue 236 * @fw_dmcu: Reference to DMCU firmware 237 * @dmcu_fw_version: Version of the DMCU firmware 238 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 239 * @cached_state: Caches device atomic state for suspend/resume 240 * @cached_dc_state: Cached state of content streams 241 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 242 * @force_timing_sync: set via debugfs. When set, indicates that all connected 243 * displays will be forced to synchronize. 244 * @dmcub_trace_event_en: enable dmcub trace events 245 */ 246 struct amdgpu_display_manager { 247 248 struct dc *dc; 249 250 /** 251 * @dmub_srv: 252 * 253 * DMUB service, used for controlling the DMUB on hardware 254 * that supports it. The pointer to the dmub_srv will be 255 * NULL on hardware that does not support it. 256 */ 257 struct dmub_srv *dmub_srv; 258 259 /** 260 * @dmub_notify: 261 * 262 * Notification from DMUB. 263 */ 264 265 struct dmub_notification *dmub_notify; 266 267 /** 268 * @dmub_callback: 269 * 270 * Callback functions to handle notification from DMUB. 271 */ 272 273 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 274 275 /** 276 * @dmub_thread_offload: 277 * 278 * Flag to indicate if callback is offload. 279 */ 280 281 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 282 283 /** 284 * @dmub_fb_info: 285 * 286 * Framebuffer regions for the DMUB. 287 */ 288 struct dmub_srv_fb_info *dmub_fb_info; 289 290 /** 291 * @dmub_fw: 292 * 293 * DMUB firmware, required on hardware that has DMUB support. 294 */ 295 const struct firmware *dmub_fw; 296 297 /** 298 * @dmub_bo: 299 * 300 * Buffer object for the DMUB. 301 */ 302 struct amdgpu_bo *dmub_bo; 303 304 /** 305 * @dmub_bo_gpu_addr: 306 * 307 * GPU virtual address for the DMUB buffer object. 308 */ 309 u64 dmub_bo_gpu_addr; 310 311 /** 312 * @dmub_bo_cpu_addr: 313 * 314 * CPU address for the DMUB buffer object. 315 */ 316 void *dmub_bo_cpu_addr; 317 318 /** 319 * @dmcub_fw_version: 320 * 321 * DMCUB firmware version. 322 */ 323 uint32_t dmcub_fw_version; 324 325 /** 326 * @cgs_device: 327 * 328 * The Common Graphics Services device. It provides an interface for 329 * accessing registers. 330 */ 331 struct cgs_device *cgs_device; 332 333 struct amdgpu_device *adev; 334 struct drm_device *ddev; 335 u16 display_indexes_num; 336 337 /** 338 * @atomic_obj: 339 * 340 * In combination with &dm_atomic_state it helps manage 341 * global atomic state that doesn't map cleanly into existing 342 * drm resources, like &dc_context. 343 */ 344 struct drm_private_obj atomic_obj; 345 346 /** 347 * @dc_lock: 348 * 349 * Guards access to DC functions that can issue register write 350 * sequences. 351 */ 352 struct mutex dc_lock; 353 354 /** 355 * @audio_lock: 356 * 357 * Guards access to audio instance changes. 358 */ 359 struct mutex audio_lock; 360 361 #if defined(CONFIG_DRM_AMD_DC_DCN) 362 /** 363 * @vblank_lock: 364 * 365 * Guards access to deferred vblank work state. 366 */ 367 spinlock_t vblank_lock; 368 #endif 369 370 /** 371 * @audio_component: 372 * 373 * Used to notify ELD changes to sound driver. 374 */ 375 struct drm_audio_component *audio_component; 376 377 /** 378 * @audio_registered: 379 * 380 * True if the audio component has been registered 381 * successfully, false otherwise. 382 */ 383 bool audio_registered; 384 385 /** 386 * @irq_handler_list_low_tab: 387 * 388 * Low priority IRQ handler table. 389 * 390 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 391 * source. Low priority IRQ handlers are deferred to a workqueue to be 392 * processed. Hence, they can sleep. 393 * 394 * Note that handlers are called in the same order as they were 395 * registered (FIFO). 396 */ 397 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 398 399 /** 400 * @irq_handler_list_high_tab: 401 * 402 * High priority IRQ handler table. 403 * 404 * It is a n*m table, same as &irq_handler_list_low_tab. However, 405 * handlers in this table are not deferred and are called immediately. 406 */ 407 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 408 409 /** 410 * @pflip_params: 411 * 412 * Page flip IRQ parameters, passed to registered handlers when 413 * triggered. 414 */ 415 struct common_irq_params 416 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 417 418 /** 419 * @vblank_params: 420 * 421 * Vertical blanking IRQ parameters, passed to registered handlers when 422 * triggered. 423 */ 424 struct common_irq_params 425 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 426 427 /** 428 * @vline0_params: 429 * 430 * OTG vertical interrupt0 IRQ parameters, passed to registered 431 * handlers when triggered. 432 */ 433 struct common_irq_params 434 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 435 436 /** 437 * @vupdate_params: 438 * 439 * Vertical update IRQ parameters, passed to registered handlers when 440 * triggered. 441 */ 442 struct common_irq_params 443 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 444 445 /** 446 * @dmub_trace_params: 447 * 448 * DMUB trace event IRQ parameters, passed to registered handlers when 449 * triggered. 450 */ 451 struct common_irq_params 452 dmub_trace_params[1]; 453 454 struct common_irq_params 455 dmub_outbox_params[1]; 456 457 spinlock_t irq_handler_list_table_lock; 458 459 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 460 461 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 462 463 uint8_t num_of_edps; 464 465 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 466 467 struct mod_freesync *freesync_module; 468 #ifdef CONFIG_DRM_AMD_DC_HDCP 469 struct hdcp_workqueue *hdcp_workqueue; 470 #endif 471 472 #if defined(CONFIG_DRM_AMD_DC_DCN) 473 /** 474 * @vblank_control_workqueue: 475 * 476 * Deferred work for vblank control events. 477 */ 478 struct workqueue_struct *vblank_control_workqueue; 479 #endif 480 481 struct drm_atomic_state *cached_state; 482 struct dc_state *cached_dc_state; 483 484 struct dm_compressor_info compressor; 485 486 const struct firmware *fw_dmcu; 487 uint32_t dmcu_fw_version; 488 /** 489 * @soc_bounding_box: 490 * 491 * gpu_info FW provided soc bounding box struct or 0 if not 492 * available in FW 493 */ 494 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 495 496 #if defined(CONFIG_DRM_AMD_DC_DCN) 497 /** 498 * @active_vblank_irq_count: 499 * 500 * number of currently active vblank irqs 501 */ 502 uint32_t active_vblank_irq_count; 503 #endif 504 505 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 506 /** 507 * @crc_rd_wrk: 508 * 509 * Work to be executed in a separate thread to communicate with PSP. 510 */ 511 struct crc_rd_work *crc_rd_wrk; 512 #endif 513 /** 514 * @hpd_rx_offload_wq: 515 * 516 * Work queue to offload works of hpd_rx_irq 517 */ 518 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 519 /** 520 * @mst_encoders: 521 * 522 * fake encoders used for DP MST. 523 */ 524 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 525 bool force_timing_sync; 526 bool disable_hpd_irq; 527 bool dmcub_trace_event_en; 528 /** 529 * @da_list: 530 * 531 * DAL fb memory allocation list, for communication with SMU. 532 */ 533 struct list_head da_list; 534 struct completion dmub_aux_transfer_done; 535 struct workqueue_struct *delayed_hpd_wq; 536 537 /** 538 * @brightness: 539 * 540 * cached backlight values. 541 */ 542 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 543 }; 544 545 enum dsc_clock_force_state { 546 DSC_CLK_FORCE_DEFAULT = 0, 547 DSC_CLK_FORCE_ENABLE, 548 DSC_CLK_FORCE_DISABLE, 549 }; 550 551 struct dsc_preferred_settings { 552 enum dsc_clock_force_state dsc_force_enable; 553 uint32_t dsc_num_slices_v; 554 uint32_t dsc_num_slices_h; 555 uint32_t dsc_bits_per_pixel; 556 bool dsc_force_disable_passthrough; 557 }; 558 559 struct amdgpu_dm_connector { 560 561 struct drm_connector base; 562 uint32_t connector_id; 563 564 /* we need to mind the EDID between detect 565 and get modes due to analog/digital/tvencoder */ 566 struct edid *edid; 567 568 /* shared with amdgpu */ 569 struct amdgpu_hpd hpd; 570 571 /* number of modes generated from EDID at 'dc_sink' */ 572 int num_modes; 573 574 /* The 'old' sink - before an HPD. 575 * The 'current' sink is in dc_link->sink. */ 576 struct dc_sink *dc_sink; 577 struct dc_link *dc_link; 578 struct dc_sink *dc_em_sink; 579 580 /* DM only */ 581 struct drm_dp_mst_topology_mgr mst_mgr; 582 struct amdgpu_dm_dp_aux dm_dp_aux; 583 struct drm_dp_mst_port *port; 584 struct amdgpu_dm_connector *mst_port; 585 struct drm_dp_aux *dsc_aux; 586 587 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 588 struct amdgpu_i2c_adapter *i2c; 589 590 /* Monitor range limits */ 591 int min_vfreq ; 592 int max_vfreq ; 593 int pixel_clock_mhz; 594 595 /* Audio instance - protected by audio_lock. */ 596 int audio_inst; 597 598 struct mutex hpd_lock; 599 600 bool fake_enable; 601 #ifdef CONFIG_DEBUG_FS 602 uint32_t debugfs_dpcd_address; 603 uint32_t debugfs_dpcd_size; 604 #endif 605 bool force_yuv420_output; 606 struct dsc_preferred_settings dsc_settings; 607 /* Cached display modes */ 608 struct drm_display_mode freesync_vid_base; 609 610 int psr_skip_count; 611 }; 612 613 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 614 615 extern const struct amdgpu_ip_block_version dm_ip_block; 616 617 struct dm_plane_state { 618 struct drm_plane_state base; 619 struct dc_plane_state *dc_state; 620 }; 621 622 struct dm_crtc_state { 623 struct drm_crtc_state base; 624 struct dc_stream_state *stream; 625 626 bool cm_has_degamma; 627 bool cm_is_degamma_srgb; 628 629 bool mpo_requested; 630 631 int update_type; 632 int active_planes; 633 634 int crc_skip_count; 635 636 bool freesync_timing_changed; 637 bool freesync_vrr_info_changed; 638 639 bool dsc_force_changed; 640 bool vrr_supported; 641 642 bool force_dpms_off; 643 struct mod_freesync_config freesync_config; 644 struct dc_info_packet vrr_infopacket; 645 646 int abm_level; 647 }; 648 649 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 650 651 struct dm_atomic_state { 652 struct drm_private_state base; 653 654 struct dc_state *context; 655 }; 656 657 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 658 659 struct dm_connector_state { 660 struct drm_connector_state base; 661 662 enum amdgpu_rmx_type scaling; 663 uint8_t underscan_vborder; 664 uint8_t underscan_hborder; 665 bool underscan_enable; 666 bool freesync_capable; 667 #ifdef CONFIG_DRM_AMD_DC_HDCP 668 bool update_hdcp; 669 #endif 670 uint8_t abm_level; 671 int vcpi_slots; 672 uint64_t pbn; 673 }; 674 675 struct amdgpu_hdmi_vsdb_info { 676 unsigned int amd_vsdb_version; /* VSDB version, should be used to determine which VSIF to send */ 677 bool freesync_supported; /* FreeSync Supported */ 678 unsigned int min_refresh_rate_hz; /* FreeSync Minimum Refresh Rate in Hz */ 679 unsigned int max_refresh_rate_hz; /* FreeSync Maximum Refresh Rate in Hz */ 680 }; 681 682 683 #define to_dm_connector_state(x)\ 684 container_of((x), struct dm_connector_state, base) 685 686 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 687 struct drm_connector_state * 688 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 689 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 690 struct drm_connector_state *state, 691 struct drm_property *property, 692 uint64_t val); 693 694 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 695 const struct drm_connector_state *state, 696 struct drm_property *property, 697 uint64_t *val); 698 699 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 700 701 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 702 struct amdgpu_dm_connector *aconnector, 703 int connector_type, 704 struct dc_link *link, 705 int link_index); 706 707 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 708 struct drm_display_mode *mode); 709 710 void dm_restore_drm_connector_state(struct drm_device *dev, 711 struct drm_connector *connector); 712 713 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 714 struct edid *edid); 715 716 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 717 718 #define MAX_COLOR_LUT_ENTRIES 4096 719 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 720 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 721 722 void amdgpu_dm_init_color_mod(void); 723 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 724 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 725 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 726 struct dc_plane_state *dc_plane_state); 727 728 void amdgpu_dm_update_connector_after_detect( 729 struct amdgpu_dm_connector *aconnector); 730 731 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 732 733 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, 734 struct dc_context *ctx, unsigned int link_index, 735 void *payload, void *operation_result); 736 737 bool check_seamless_boot_capability(struct amdgpu_device *adev); 738 739 #endif /* __AMDGPU_DM_H__ */ 740