1 /* 2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/display/drm_dp_mst_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_connector.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_plane.h> 34 #include "link_service_types.h" 35 #include <drm/drm_writeback.h> 36 37 /* 38 * This file contains the definition for amdgpu_display_manager 39 * and its API for amdgpu driver's use. 40 * This component provides all the display related functionality 41 * and this is the only component that calls DAL API. 42 * The API contained here intended for amdgpu driver use. 43 * The API that is called directly from KMS framework is located 44 * in amdgpu_dm_kms.h file 45 */ 46 47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 48 49 #define AMDGPU_DM_MAX_CRTC 6 50 51 #define AMDGPU_DM_MAX_NUM_EDP 2 52 53 #define AMDGPU_DMUB_NOTIFICATION_MAX 5 54 55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 58 /* 59 #include "include/amdgpu_dal_power_if.h" 60 #include "amdgpu_dm_irq.h" 61 */ 62 63 #include "irq_types.h" 64 #include "signal_types.h" 65 #include "amdgpu_dm_crc.h" 66 #include "mod_info_packet.h" 67 struct aux_payload; 68 struct set_config_cmd_payload; 69 enum aux_return_code_type; 70 enum set_config_status; 71 72 /* Forward declarations */ 73 struct amdgpu_device; 74 struct amdgpu_crtc; 75 struct drm_device; 76 struct dc; 77 struct amdgpu_bo; 78 struct dmub_srv; 79 struct dc_plane_state; 80 struct dmub_notification; 81 82 struct amd_vsdb_block { 83 unsigned char ieee_id[3]; 84 unsigned char version; 85 unsigned char feature_caps; 86 }; 87 88 struct common_irq_params { 89 struct amdgpu_device *adev; 90 enum dc_irq_source irq_src; 91 atomic64_t previous_timestamp; 92 }; 93 94 /** 95 * struct dm_compressor_info - Buffer info used by frame buffer compression 96 * @cpu_addr: MMIO cpu addr 97 * @bo_ptr: Pointer to the buffer object 98 * @gpu_addr: MMIO gpu addr 99 */ 100 struct dm_compressor_info { 101 void *cpu_addr; 102 struct amdgpu_bo *bo_ptr; 103 uint64_t gpu_addr; 104 }; 105 106 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 107 108 /** 109 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 110 * 111 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 112 * @dmub_notify: notification for callback function 113 * @adev: amdgpu_device pointer 114 */ 115 struct dmub_hpd_work { 116 struct work_struct handle_hpd_work; 117 struct dmub_notification *dmub_notify; 118 struct amdgpu_device *adev; 119 }; 120 121 /** 122 * struct vblank_control_work - Work data for vblank control 123 * @work: Kernel work data for the work event 124 * @dm: amdgpu display manager device 125 * @acrtc: amdgpu CRTC instance for which the event has occurred 126 * @stream: DC stream for which the event has occurred 127 * @enable: true if enabling vblank 128 */ 129 struct vblank_control_work { 130 struct work_struct work; 131 struct amdgpu_display_manager *dm; 132 struct amdgpu_crtc *acrtc; 133 struct dc_stream_state *stream; 134 bool enable; 135 }; 136 137 /** 138 * struct amdgpu_dm_backlight_caps - Information about backlight 139 * 140 * Describe the backlight support for ACPI or eDP AUX. 141 */ 142 struct amdgpu_dm_backlight_caps { 143 /** 144 * @ext_caps: Keep the data struct with all the information about the 145 * display support for HDR. 146 */ 147 union dpcd_sink_ext_caps *ext_caps; 148 /** 149 * @aux_min_input_signal: Min brightness value supported by the display 150 */ 151 u32 aux_min_input_signal; 152 /** 153 * @aux_max_input_signal: Max brightness value supported by the display 154 * in nits. 155 */ 156 u32 aux_max_input_signal; 157 /** 158 * @min_input_signal: minimum possible input in range 0-255. 159 */ 160 int min_input_signal; 161 /** 162 * @max_input_signal: maximum possible input in range 0-255. 163 */ 164 int max_input_signal; 165 /** 166 * @caps_valid: true if these values are from the ACPI interface. 167 */ 168 bool caps_valid; 169 /** 170 * @aux_support: Describes if the display supports AUX backlight. 171 */ 172 bool aux_support; 173 }; 174 175 /** 176 * struct dal_allocation - Tracks mapped FB memory for SMU communication 177 * @list: list of dal allocations 178 * @bo: GPU buffer object 179 * @cpu_ptr: CPU virtual address of the GPU buffer object 180 * @gpu_addr: GPU virtual address of the GPU buffer object 181 */ 182 struct dal_allocation { 183 struct list_head list; 184 struct amdgpu_bo *bo; 185 void *cpu_ptr; 186 u64 gpu_addr; 187 }; 188 189 /** 190 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 191 * offload work 192 */ 193 struct hpd_rx_irq_offload_work_queue { 194 /** 195 * @wq: workqueue structure to queue offload work. 196 */ 197 struct workqueue_struct *wq; 198 /** 199 * @offload_lock: To protect fields of offload work queue. 200 */ 201 spinlock_t offload_lock; 202 /** 203 * @is_handling_link_loss: Used to prevent inserting link loss event when 204 * we're handling link loss 205 */ 206 bool is_handling_link_loss; 207 /** 208 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 209 * ready event when we're already handling mst message ready event 210 */ 211 bool is_handling_mst_msg_rdy_event; 212 /** 213 * @aconnector: The aconnector that this work queue is attached to 214 */ 215 struct amdgpu_dm_connector *aconnector; 216 }; 217 218 /** 219 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 220 */ 221 struct hpd_rx_irq_offload_work { 222 /** 223 * @work: offload work 224 */ 225 struct work_struct work; 226 /** 227 * @data: reference irq data which is used while handling offload work 228 */ 229 union hpd_irq_data data; 230 /** 231 * @offload_wq: offload work queue that this work is queued to 232 */ 233 struct hpd_rx_irq_offload_work_queue *offload_wq; 234 }; 235 236 /** 237 * struct amdgpu_display_manager - Central amdgpu display manager device 238 * 239 * @dc: Display Core control structure 240 * @adev: AMDGPU base driver structure 241 * @ddev: DRM base driver structure 242 * @display_indexes_num: Max number of display streams supported 243 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 244 * @backlight_dev: Backlight control device 245 * @backlight_link: Link on which to control backlight 246 * @backlight_caps: Capabilities of the backlight device 247 * @freesync_module: Module handling freesync calculations 248 * @hdcp_workqueue: AMDGPU content protection queue 249 * @fw_dmcu: Reference to DMCU firmware 250 * @dmcu_fw_version: Version of the DMCU firmware 251 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 252 * @cached_state: Caches device atomic state for suspend/resume 253 * @cached_dc_state: Cached state of content streams 254 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 255 * @force_timing_sync: set via debugfs. When set, indicates that all connected 256 * displays will be forced to synchronize. 257 * @dmcub_trace_event_en: enable dmcub trace events 258 * @dmub_outbox_params: DMUB Outbox parameters 259 * @num_of_edps: number of backlight eDPs 260 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 261 * driver when true 262 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 263 * transfers are done 264 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 265 */ 266 struct amdgpu_display_manager { 267 268 struct dc *dc; 269 270 /** 271 * @dmub_srv: 272 * 273 * DMUB service, used for controlling the DMUB on hardware 274 * that supports it. The pointer to the dmub_srv will be 275 * NULL on hardware that does not support it. 276 */ 277 struct dmub_srv *dmub_srv; 278 279 /** 280 * @dmub_notify: 281 * 282 * Notification from DMUB. 283 */ 284 285 struct dmub_notification *dmub_notify; 286 287 /** 288 * @dmub_callback: 289 * 290 * Callback functions to handle notification from DMUB. 291 */ 292 293 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 294 295 /** 296 * @dmub_thread_offload: 297 * 298 * Flag to indicate if callback is offload. 299 */ 300 301 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 302 303 /** 304 * @dmub_fb_info: 305 * 306 * Framebuffer regions for the DMUB. 307 */ 308 struct dmub_srv_fb_info *dmub_fb_info; 309 310 /** 311 * @dmub_fw: 312 * 313 * DMUB firmware, required on hardware that has DMUB support. 314 */ 315 const struct firmware *dmub_fw; 316 317 /** 318 * @dmub_bo: 319 * 320 * Buffer object for the DMUB. 321 */ 322 struct amdgpu_bo *dmub_bo; 323 324 /** 325 * @dmub_bo_gpu_addr: 326 * 327 * GPU virtual address for the DMUB buffer object. 328 */ 329 u64 dmub_bo_gpu_addr; 330 331 /** 332 * @dmub_bo_cpu_addr: 333 * 334 * CPU address for the DMUB buffer object. 335 */ 336 void *dmub_bo_cpu_addr; 337 338 /** 339 * @dmcub_fw_version: 340 * 341 * DMCUB firmware version. 342 */ 343 uint32_t dmcub_fw_version; 344 345 /** 346 * @cgs_device: 347 * 348 * The Common Graphics Services device. It provides an interface for 349 * accessing registers. 350 */ 351 struct cgs_device *cgs_device; 352 353 struct amdgpu_device *adev; 354 struct drm_device *ddev; 355 u16 display_indexes_num; 356 357 /** 358 * @atomic_obj: 359 * 360 * In combination with &dm_atomic_state it helps manage 361 * global atomic state that doesn't map cleanly into existing 362 * drm resources, like &dc_context. 363 */ 364 struct drm_private_obj atomic_obj; 365 366 /** 367 * @dc_lock: 368 * 369 * Guards access to DC functions that can issue register write 370 * sequences. 371 */ 372 struct mutex dc_lock; 373 374 /** 375 * @audio_lock: 376 * 377 * Guards access to audio instance changes. 378 */ 379 struct mutex audio_lock; 380 381 /** 382 * @audio_component: 383 * 384 * Used to notify ELD changes to sound driver. 385 */ 386 struct drm_audio_component *audio_component; 387 388 /** 389 * @audio_registered: 390 * 391 * True if the audio component has been registered 392 * successfully, false otherwise. 393 */ 394 bool audio_registered; 395 396 /** 397 * @irq_handler_list_low_tab: 398 * 399 * Low priority IRQ handler table. 400 * 401 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 402 * source. Low priority IRQ handlers are deferred to a workqueue to be 403 * processed. Hence, they can sleep. 404 * 405 * Note that handlers are called in the same order as they were 406 * registered (FIFO). 407 */ 408 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 409 410 /** 411 * @irq_handler_list_high_tab: 412 * 413 * High priority IRQ handler table. 414 * 415 * It is a n*m table, same as &irq_handler_list_low_tab. However, 416 * handlers in this table are not deferred and are called immediately. 417 */ 418 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 419 420 /** 421 * @pflip_params: 422 * 423 * Page flip IRQ parameters, passed to registered handlers when 424 * triggered. 425 */ 426 struct common_irq_params 427 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 428 429 /** 430 * @vblank_params: 431 * 432 * Vertical blanking IRQ parameters, passed to registered handlers when 433 * triggered. 434 */ 435 struct common_irq_params 436 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 437 438 /** 439 * @vline0_params: 440 * 441 * OTG vertical interrupt0 IRQ parameters, passed to registered 442 * handlers when triggered. 443 */ 444 struct common_irq_params 445 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 446 447 /** 448 * @vupdate_params: 449 * 450 * Vertical update IRQ parameters, passed to registered handlers when 451 * triggered. 452 */ 453 struct common_irq_params 454 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 455 456 /** 457 * @dmub_trace_params: 458 * 459 * DMUB trace event IRQ parameters, passed to registered handlers when 460 * triggered. 461 */ 462 struct common_irq_params 463 dmub_trace_params[1]; 464 465 struct common_irq_params 466 dmub_outbox_params[1]; 467 468 spinlock_t irq_handler_list_table_lock; 469 470 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 471 472 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 473 474 uint8_t num_of_edps; 475 476 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 477 478 struct mod_freesync *freesync_module; 479 struct hdcp_workqueue *hdcp_workqueue; 480 481 /** 482 * @vblank_control_workqueue: 483 * 484 * Deferred work for vblank control events. 485 */ 486 struct workqueue_struct *vblank_control_workqueue; 487 488 struct drm_atomic_state *cached_state; 489 struct dc_state *cached_dc_state; 490 491 struct dm_compressor_info compressor; 492 493 const struct firmware *fw_dmcu; 494 uint32_t dmcu_fw_version; 495 /** 496 * @soc_bounding_box: 497 * 498 * gpu_info FW provided soc bounding box struct or 0 if not 499 * available in FW 500 */ 501 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 502 503 /** 504 * @active_vblank_irq_count: 505 * 506 * number of currently active vblank irqs 507 */ 508 uint32_t active_vblank_irq_count; 509 510 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 511 /** 512 * @secure_display_ctxs: 513 * 514 * Store the ROI information and the work_struct to command dmub and psp for 515 * all crtcs. 516 */ 517 struct secure_display_context *secure_display_ctxs; 518 #endif 519 /** 520 * @hpd_rx_offload_wq: 521 * 522 * Work queue to offload works of hpd_rx_irq 523 */ 524 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 525 /** 526 * @mst_encoders: 527 * 528 * fake encoders used for DP MST. 529 */ 530 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 531 bool force_timing_sync; 532 bool disable_hpd_irq; 533 bool dmcub_trace_event_en; 534 /** 535 * @da_list: 536 * 537 * DAL fb memory allocation list, for communication with SMU. 538 */ 539 struct list_head da_list; 540 struct completion dmub_aux_transfer_done; 541 struct workqueue_struct *delayed_hpd_wq; 542 543 /** 544 * @brightness: 545 * 546 * cached backlight values. 547 */ 548 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 549 /** 550 * @actual_brightness: 551 * 552 * last successfully applied backlight values. 553 */ 554 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 555 556 /** 557 * @aux_hpd_discon_quirk: 558 * 559 * quirk for hpd discon while aux is on-going. 560 * occurred on certain intel platform 561 */ 562 bool aux_hpd_discon_quirk; 563 564 /** 565 * @dpia_aux_lock: 566 * 567 * Guards access to DPIA AUX 568 */ 569 struct mutex dpia_aux_lock; 570 }; 571 572 enum dsc_clock_force_state { 573 DSC_CLK_FORCE_DEFAULT = 0, 574 DSC_CLK_FORCE_ENABLE, 575 DSC_CLK_FORCE_DISABLE, 576 }; 577 578 struct dsc_preferred_settings { 579 enum dsc_clock_force_state dsc_force_enable; 580 uint32_t dsc_num_slices_v; 581 uint32_t dsc_num_slices_h; 582 uint32_t dsc_bits_per_pixel; 583 bool dsc_force_disable_passthrough; 584 }; 585 586 enum mst_progress_status { 587 MST_STATUS_DEFAULT = 0, 588 MST_PROBE = BIT(0), 589 MST_REMOTE_EDID = BIT(1), 590 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 591 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 592 }; 593 594 /** 595 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 596 * 597 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 598 * struct is useful to keep track of the display-specific information about 599 * FreeSync. 600 */ 601 struct amdgpu_hdmi_vsdb_info { 602 /** 603 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 604 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 605 */ 606 unsigned int amd_vsdb_version; 607 608 /** 609 * @freesync_supported: FreeSync Supported. 610 */ 611 bool freesync_supported; 612 613 /** 614 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 615 */ 616 unsigned int min_refresh_rate_hz; 617 618 /** 619 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 620 */ 621 unsigned int max_refresh_rate_hz; 622 623 /** 624 * @replay_mode: Replay supported 625 */ 626 bool replay_mode; 627 }; 628 629 struct amdgpu_dm_connector { 630 631 struct drm_connector base; 632 uint32_t connector_id; 633 int bl_idx; 634 635 /* we need to mind the EDID between detect 636 and get modes due to analog/digital/tvencoder */ 637 struct edid *edid; 638 639 /* shared with amdgpu */ 640 struct amdgpu_hpd hpd; 641 642 /* number of modes generated from EDID at 'dc_sink' */ 643 int num_modes; 644 645 /* The 'old' sink - before an HPD. 646 * The 'current' sink is in dc_link->sink. */ 647 struct dc_sink *dc_sink; 648 struct dc_link *dc_link; 649 650 /** 651 * @dc_em_sink: Reference to the emulated (virtual) sink. 652 */ 653 struct dc_sink *dc_em_sink; 654 655 /* DM only */ 656 struct drm_dp_mst_topology_mgr mst_mgr; 657 struct amdgpu_dm_dp_aux dm_dp_aux; 658 struct drm_dp_mst_port *mst_output_port; 659 struct amdgpu_dm_connector *mst_root; 660 struct drm_dp_aux *dsc_aux; 661 struct mutex handle_mst_msg_ready; 662 663 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 664 struct amdgpu_i2c_adapter *i2c; 665 666 /* Monitor range limits */ 667 /** 668 * @min_vfreq: Minimal frequency supported by the display in Hz. This 669 * value is set to zero when there is no FreeSync support. 670 */ 671 int min_vfreq; 672 673 /** 674 * @max_vfreq: Maximum frequency supported by the display in Hz. This 675 * value is set to zero when there is no FreeSync support. 676 */ 677 int max_vfreq ; 678 int pixel_clock_mhz; 679 680 /* Audio instance - protected by audio_lock. */ 681 int audio_inst; 682 683 struct mutex hpd_lock; 684 685 bool fake_enable; 686 bool force_yuv420_output; 687 struct dsc_preferred_settings dsc_settings; 688 union dp_downstream_port_present mst_downstream_port_present; 689 /* Cached display modes */ 690 struct drm_display_mode freesync_vid_base; 691 692 int psr_skip_count; 693 694 /* Record progress status of mst*/ 695 uint8_t mst_status; 696 697 /* Automated testing */ 698 bool timing_changed; 699 struct dc_crtc_timing *timing_requested; 700 701 /* Adaptive Sync */ 702 bool pack_sdp_v1_3; 703 enum adaptive_sync_type as_type; 704 struct amdgpu_hdmi_vsdb_info vsdb_info; 705 }; 706 707 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 708 uint8_t flags, bool set) 709 { 710 if (set) 711 *status |= flags; 712 else 713 *status &= ~flags; 714 } 715 716 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 717 718 struct amdgpu_dm_wb_connector { 719 struct drm_writeback_connector base; 720 struct dc_link *link; 721 }; 722 723 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 724 725 extern const struct amdgpu_ip_block_version dm_ip_block; 726 727 struct dm_plane_state { 728 struct drm_plane_state base; 729 struct dc_plane_state *dc_state; 730 }; 731 732 struct dm_crtc_state { 733 struct drm_crtc_state base; 734 struct dc_stream_state *stream; 735 736 bool cm_has_degamma; 737 bool cm_is_degamma_srgb; 738 739 bool mpo_requested; 740 741 int update_type; 742 int active_planes; 743 744 int crc_skip_count; 745 746 bool freesync_vrr_info_changed; 747 748 bool dsc_force_changed; 749 bool vrr_supported; 750 struct mod_freesync_config freesync_config; 751 struct dc_info_packet vrr_infopacket; 752 753 int abm_level; 754 }; 755 756 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 757 758 struct dm_atomic_state { 759 struct drm_private_state base; 760 761 struct dc_state *context; 762 }; 763 764 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 765 766 struct dm_connector_state { 767 struct drm_connector_state base; 768 769 enum amdgpu_rmx_type scaling; 770 uint8_t underscan_vborder; 771 uint8_t underscan_hborder; 772 bool underscan_enable; 773 bool freesync_capable; 774 bool update_hdcp; 775 uint8_t abm_level; 776 int vcpi_slots; 777 uint64_t pbn; 778 }; 779 780 #define to_dm_connector_state(x)\ 781 container_of((x), struct dm_connector_state, base) 782 783 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 784 struct drm_connector_state * 785 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 786 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 787 struct drm_connector_state *state, 788 struct drm_property *property, 789 uint64_t val); 790 791 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 792 const struct drm_connector_state *state, 793 struct drm_property *property, 794 uint64_t *val); 795 796 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 797 798 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 799 struct amdgpu_dm_connector *aconnector, 800 int connector_type, 801 struct dc_link *link, 802 int link_index); 803 804 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 805 struct drm_display_mode *mode); 806 807 void dm_restore_drm_connector_state(struct drm_device *dev, 808 struct drm_connector *connector); 809 810 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 811 struct edid *edid); 812 813 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 814 815 #define MAX_COLOR_LUT_ENTRIES 4096 816 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 817 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 818 819 void amdgpu_dm_init_color_mod(void); 820 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 821 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 822 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 823 struct dc_plane_state *dc_plane_state); 824 825 void amdgpu_dm_update_connector_after_detect( 826 struct amdgpu_dm_connector *aconnector); 827 828 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 829 830 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 831 struct aux_payload *payload, enum aux_return_code_type *operation_result); 832 833 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 834 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 835 836 struct dc_stream_state * 837 create_validate_stream_for_sink(struct drm_connector *connector, 838 const struct drm_display_mode *drm_mode, 839 const struct dm_connector_state *dm_state, 840 const struct dc_stream_state *old_stream); 841 842 int dm_atomic_get_state(struct drm_atomic_state *state, 843 struct dm_atomic_state **dm_state); 844 845 struct drm_connector * 846 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 847 struct drm_crtc *crtc); 848 849 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 850 #endif /* __AMDGPU_DM_H__ */ 851