1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 59 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 62 #define AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS 1500 63 /* 64 #include "include/amdgpu_dal_power_if.h" 65 #include "amdgpu_dm_irq.h" 66 */ 67 68 #include "irq_types.h" 69 #include "signal_types.h" 70 #include "amdgpu_dm_crc.h" 71 #include "mod_info_packet.h" 72 struct aux_payload; 73 struct set_config_cmd_payload; 74 enum aux_return_code_type; 75 enum set_config_status; 76 77 /* Forward declarations */ 78 struct amdgpu_device; 79 struct amdgpu_crtc; 80 struct drm_device; 81 struct dc; 82 struct amdgpu_bo; 83 struct dmub_srv; 84 struct dc_plane_state; 85 struct dmub_notification; 86 struct dmub_cmd_fused_request; 87 88 struct amd_vsdb_block { 89 unsigned char ieee_id[3]; 90 unsigned char version; 91 unsigned char feature_caps; 92 }; 93 94 struct common_irq_params { 95 struct amdgpu_device *adev; 96 enum dc_irq_source irq_src; 97 atomic64_t previous_timestamp; 98 }; 99 100 /** 101 * struct dm_compressor_info - Buffer info used by frame buffer compression 102 * @cpu_addr: MMIO cpu addr 103 * @bo_ptr: Pointer to the buffer object 104 * @gpu_addr: MMIO gpu addr 105 */ 106 struct dm_compressor_info { 107 void *cpu_addr; 108 struct amdgpu_bo *bo_ptr; 109 uint64_t gpu_addr; 110 }; 111 112 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 113 114 /** 115 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 116 * 117 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 118 * @dmub_notify: notification for callback function 119 * @adev: amdgpu_device pointer 120 */ 121 struct dmub_hpd_work { 122 struct work_struct handle_hpd_work; 123 struct dmub_notification *dmub_notify; 124 struct amdgpu_device *adev; 125 }; 126 127 /** 128 * struct vblank_control_work - Work data for vblank control 129 * @work: Kernel work data for the work event 130 * @dm: amdgpu display manager device 131 * @acrtc: amdgpu CRTC instance for which the event has occurred 132 * @stream: DC stream for which the event has occurred 133 * @enable: true if enabling vblank 134 */ 135 struct vblank_control_work { 136 struct work_struct work; 137 struct amdgpu_display_manager *dm; 138 struct amdgpu_crtc *acrtc; 139 struct dc_stream_state *stream; 140 bool enable; 141 }; 142 143 /** 144 * struct idle_workqueue - Work data for periodic action in idle 145 * @work: Kernel work data for the work event 146 * @dm: amdgpu display manager device 147 * @enable: true if idle worker is enabled 148 * @running: true if idle worker is running 149 */ 150 struct idle_workqueue { 151 struct work_struct work; 152 struct amdgpu_display_manager *dm; 153 bool enable; 154 bool running; 155 }; 156 157 /** 158 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 159 * @work: Kernel work data for the work event 160 * @adev: amdgpu_device back pointer 161 * @stream: DC stream associated with the crtc 162 * @adjust: DC CRTC timing adjust to be applied to the crtc 163 */ 164 struct vupdate_offload_work { 165 struct work_struct work; 166 struct amdgpu_device *adev; 167 struct dc_stream_state *stream; 168 struct dc_crtc_timing_adjust *adjust; 169 }; 170 171 #define MAX_LUMINANCE_DATA_POINTS 99 172 173 /** 174 * struct amdgpu_dm_luminance_data - Custom luminance data 175 * @luminance: Luminance in percent 176 * @input_signal: Input signal in range 0-255 177 */ 178 struct amdgpu_dm_luminance_data { 179 u8 luminance; 180 u8 input_signal; 181 } __packed; 182 183 /** 184 * struct amdgpu_dm_backlight_caps - Information about backlight 185 * 186 * Describe the backlight support for ACPI or eDP AUX. 187 */ 188 struct amdgpu_dm_backlight_caps { 189 /** 190 * @ext_caps: Keep the data struct with all the information about the 191 * display support for HDR. 192 */ 193 union dpcd_sink_ext_caps *ext_caps; 194 /** 195 * @aux_min_input_signal: Min brightness value supported by the display 196 */ 197 u32 aux_min_input_signal; 198 /** 199 * @aux_max_input_signal: Max brightness value supported by the display 200 * in nits. 201 */ 202 u32 aux_max_input_signal; 203 /** 204 * @min_input_signal: minimum possible input in range 0-255. 205 */ 206 int min_input_signal; 207 /** 208 * @max_input_signal: maximum possible input in range 0-255. 209 */ 210 int max_input_signal; 211 /** 212 * @caps_valid: true if these values are from the ACPI interface. 213 */ 214 bool caps_valid; 215 /** 216 * @aux_support: Describes if the display supports AUX backlight. 217 */ 218 bool aux_support; 219 /** 220 * @brightness_mask: After deriving brightness, OR it with this mask. 221 * Workaround for panels with issues with certain brightness values. 222 */ 223 u32 brightness_mask; 224 /** 225 * @ac_level: the default brightness if booted on AC 226 */ 227 u8 ac_level; 228 /** 229 * @dc_level: the default brightness if booted on DC 230 */ 231 u8 dc_level; 232 /** 233 * @data_points: the number of custom luminance data points 234 */ 235 u8 data_points; 236 /** 237 * @luminance_data: custom luminance data 238 */ 239 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 240 }; 241 242 /** 243 * struct dal_allocation - Tracks mapped FB memory for SMU communication 244 * @list: list of dal allocations 245 * @bo: GPU buffer object 246 * @cpu_ptr: CPU virtual address of the GPU buffer object 247 * @gpu_addr: GPU virtual address of the GPU buffer object 248 */ 249 struct dal_allocation { 250 struct list_head list; 251 struct amdgpu_bo *bo; 252 void *cpu_ptr; 253 u64 gpu_addr; 254 }; 255 256 /** 257 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 258 * offload work 259 */ 260 struct hpd_rx_irq_offload_work_queue { 261 /** 262 * @wq: workqueue structure to queue offload work. 263 */ 264 struct workqueue_struct *wq; 265 /** 266 * @offload_lock: To protect fields of offload work queue. 267 */ 268 spinlock_t offload_lock; 269 /** 270 * @is_handling_link_loss: Used to prevent inserting link loss event when 271 * we're handling link loss 272 */ 273 bool is_handling_link_loss; 274 /** 275 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 276 * ready event when we're already handling mst message ready event 277 */ 278 bool is_handling_mst_msg_rdy_event; 279 /** 280 * @aconnector: The aconnector that this work queue is attached to 281 */ 282 struct amdgpu_dm_connector *aconnector; 283 }; 284 285 /** 286 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 287 */ 288 struct hpd_rx_irq_offload_work { 289 /** 290 * @work: offload work 291 */ 292 struct work_struct work; 293 /** 294 * @data: reference irq data which is used while handling offload work 295 */ 296 union hpd_irq_data data; 297 /** 298 * @offload_wq: offload work queue that this work is queued to 299 */ 300 struct hpd_rx_irq_offload_work_queue *offload_wq; 301 /** 302 * @adev: amdgpu_device pointer 303 */ 304 struct amdgpu_device *adev; 305 }; 306 307 /** 308 * struct amdgpu_display_manager - Central amdgpu display manager device 309 * 310 * @dc: Display Core control structure 311 * @adev: AMDGPU base driver structure 312 * @ddev: DRM base driver structure 313 * @display_indexes_num: Max number of display streams supported 314 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 315 * @backlight_dev: Backlight control device 316 * @backlight_link: Link on which to control backlight 317 * @backlight_caps: Capabilities of the backlight device 318 * @freesync_module: Module handling freesync calculations 319 * @hdcp_workqueue: AMDGPU content protection queue 320 * @fw_dmcu: Reference to DMCU firmware 321 * @dmcu_fw_version: Version of the DMCU firmware 322 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 323 * @cached_state: Caches device atomic state for suspend/resume 324 * @cached_dc_state: Cached state of content streams 325 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 326 * @force_timing_sync: set via debugfs. When set, indicates that all connected 327 * displays will be forced to synchronize. 328 * @dmcub_trace_event_en: enable dmcub trace events 329 * @dmub_outbox_params: DMUB Outbox parameters 330 * @num_of_edps: number of backlight eDPs 331 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 332 * driver when true 333 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 334 * transfers are done 335 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 336 */ 337 struct amdgpu_display_manager { 338 339 struct dc *dc; 340 341 /** 342 * @dmub_srv: 343 * 344 * DMUB service, used for controlling the DMUB on hardware 345 * that supports it. The pointer to the dmub_srv will be 346 * NULL on hardware that does not support it. 347 */ 348 struct dmub_srv *dmub_srv; 349 350 /** 351 * @dmub_notify: 352 * 353 * Notification from DMUB. 354 */ 355 356 struct dmub_notification *dmub_notify; 357 358 /** 359 * @dmub_callback: 360 * 361 * Callback functions to handle notification from DMUB. 362 */ 363 364 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 365 366 /** 367 * @dmub_thread_offload: 368 * 369 * Flag to indicate if callback is offload. 370 */ 371 372 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 373 374 /** 375 * @dmub_fb_info: 376 * 377 * Framebuffer regions for the DMUB. 378 */ 379 struct dmub_srv_fb_info *dmub_fb_info; 380 381 /** 382 * @dmub_fw: 383 * 384 * DMUB firmware, required on hardware that has DMUB support. 385 */ 386 const struct firmware *dmub_fw; 387 388 /** 389 * @dmub_bo: 390 * 391 * Buffer object for the DMUB. 392 */ 393 struct amdgpu_bo *dmub_bo; 394 395 /** 396 * @dmub_bo_gpu_addr: 397 * 398 * GPU virtual address for the DMUB buffer object. 399 */ 400 u64 dmub_bo_gpu_addr; 401 402 /** 403 * @dmub_bo_cpu_addr: 404 * 405 * CPU address for the DMUB buffer object. 406 */ 407 void *dmub_bo_cpu_addr; 408 409 /** 410 * @dmcub_fw_version: 411 * 412 * DMCUB firmware version. 413 */ 414 uint32_t dmcub_fw_version; 415 416 /** 417 * @fw_inst_size: 418 * 419 * Size of the firmware instruction buffer. 420 */ 421 uint32_t fw_inst_size; 422 423 /** 424 * @cgs_device: 425 * 426 * The Common Graphics Services device. It provides an interface for 427 * accessing registers. 428 */ 429 struct cgs_device *cgs_device; 430 431 struct amdgpu_device *adev; 432 struct drm_device *ddev; 433 u16 display_indexes_num; 434 435 /** 436 * @atomic_obj: 437 * 438 * In combination with &dm_atomic_state it helps manage 439 * global atomic state that doesn't map cleanly into existing 440 * drm resources, like &dc_context. 441 */ 442 struct drm_private_obj atomic_obj; 443 444 /** 445 * @dc_lock: 446 * 447 * Guards access to DC functions that can issue register write 448 * sequences. 449 */ 450 struct mutex dc_lock; 451 452 /** 453 * @audio_lock: 454 * 455 * Guards access to audio instance changes. 456 */ 457 struct mutex audio_lock; 458 459 /** 460 * @audio_component: 461 * 462 * Used to notify ELD changes to sound driver. 463 */ 464 struct drm_audio_component *audio_component; 465 466 /** 467 * @audio_registered: 468 * 469 * True if the audio component has been registered 470 * successfully, false otherwise. 471 */ 472 bool audio_registered; 473 474 /** 475 * @irq_handler_list_low_tab: 476 * 477 * Low priority IRQ handler table. 478 * 479 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 480 * source. Low priority IRQ handlers are deferred to a workqueue to be 481 * processed. Hence, they can sleep. 482 * 483 * Note that handlers are called in the same order as they were 484 * registered (FIFO). 485 */ 486 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 487 488 /** 489 * @irq_handler_list_high_tab: 490 * 491 * High priority IRQ handler table. 492 * 493 * It is a n*m table, same as &irq_handler_list_low_tab. However, 494 * handlers in this table are not deferred and are called immediately. 495 */ 496 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 497 498 /** 499 * @pflip_params: 500 * 501 * Page flip IRQ parameters, passed to registered handlers when 502 * triggered. 503 */ 504 struct common_irq_params 505 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 506 507 /** 508 * @vblank_params: 509 * 510 * Vertical blanking IRQ parameters, passed to registered handlers when 511 * triggered. 512 */ 513 struct common_irq_params 514 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 515 516 /** 517 * @vline0_params: 518 * 519 * OTG vertical interrupt0 IRQ parameters, passed to registered 520 * handlers when triggered. 521 */ 522 struct common_irq_params 523 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 524 525 /** 526 * @vupdate_params: 527 * 528 * Vertical update IRQ parameters, passed to registered handlers when 529 * triggered. 530 */ 531 struct common_irq_params 532 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 533 534 /** 535 * @dmub_trace_params: 536 * 537 * DMUB trace event IRQ parameters, passed to registered handlers when 538 * triggered. 539 */ 540 struct common_irq_params 541 dmub_trace_params[1]; 542 543 struct common_irq_params 544 dmub_outbox_params[1]; 545 546 spinlock_t irq_handler_list_table_lock; 547 548 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 549 550 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 551 552 uint8_t num_of_edps; 553 554 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 555 556 struct mod_freesync *freesync_module; 557 struct hdcp_workqueue *hdcp_workqueue; 558 559 /** 560 * @vblank_control_workqueue: 561 * 562 * Deferred work for vblank control events. 563 */ 564 struct workqueue_struct *vblank_control_workqueue; 565 566 /** 567 * @idle_workqueue: 568 * 569 * Periodic work for idle events. 570 */ 571 struct idle_workqueue *idle_workqueue; 572 573 struct drm_atomic_state *cached_state; 574 struct dc_state *cached_dc_state; 575 576 struct dm_compressor_info compressor; 577 578 const struct firmware *fw_dmcu; 579 uint32_t dmcu_fw_version; 580 /** 581 * @soc_bounding_box: 582 * 583 * gpu_info FW provided soc bounding box struct or 0 if not 584 * available in FW 585 */ 586 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 587 588 /** 589 * @active_vblank_irq_count: 590 * 591 * number of currently active vblank irqs 592 */ 593 uint32_t active_vblank_irq_count; 594 595 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 596 /** 597 * @secure_display_ctx: 598 * 599 * Store secure display relevant info. e.g. the ROI information 600 * , the work_struct to command dmub, etc. 601 */ 602 struct secure_display_context secure_display_ctx; 603 #endif 604 /** 605 * @hpd_rx_offload_wq: 606 * 607 * Work queue to offload works of hpd_rx_irq 608 */ 609 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 610 /** 611 * @mst_encoders: 612 * 613 * fake encoders used for DP MST. 614 */ 615 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 616 bool force_timing_sync; 617 bool disable_hpd_irq; 618 bool dmcub_trace_event_en; 619 /** 620 * @da_list: 621 * 622 * DAL fb memory allocation list, for communication with SMU. 623 */ 624 struct list_head da_list; 625 struct completion dmub_aux_transfer_done; 626 struct workqueue_struct *delayed_hpd_wq; 627 628 /** 629 * @brightness: 630 * 631 * cached backlight values. 632 */ 633 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 634 /** 635 * @actual_brightness: 636 * 637 * last successfully applied backlight values. 638 */ 639 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 640 641 /** 642 * @aux_hpd_discon_quirk: 643 * 644 * quirk for hpd discon while aux is on-going. 645 * occurred on certain intel platform 646 */ 647 bool aux_hpd_discon_quirk; 648 649 /** 650 * @edp0_on_dp1_quirk: 651 * 652 * quirk for platforms that put edp0 on DP1. 653 */ 654 bool edp0_on_dp1_quirk; 655 656 /** 657 * @dpia_aux_lock: 658 * 659 * Guards access to DPIA AUX 660 */ 661 struct mutex dpia_aux_lock; 662 663 /** 664 * @bb_from_dmub: 665 * 666 * Bounding box data read from dmub during early initialization for DCN4+ 667 * Data is stored as a byte array that should be casted to the appropriate bb struct 668 */ 669 void *bb_from_dmub; 670 671 /** 672 * @oem_i2c: 673 * 674 * OEM i2c bus 675 */ 676 struct amdgpu_i2c_adapter *oem_i2c; 677 678 /** 679 * @fused_io: 680 * 681 * dmub fused io interface 682 */ 683 struct fused_io_sync { 684 struct completion replied; 685 char reply_data[0x40]; // Cannot include dmub_cmd here 686 } fused_io[8]; 687 }; 688 689 enum dsc_clock_force_state { 690 DSC_CLK_FORCE_DEFAULT = 0, 691 DSC_CLK_FORCE_ENABLE, 692 DSC_CLK_FORCE_DISABLE, 693 }; 694 695 struct dsc_preferred_settings { 696 enum dsc_clock_force_state dsc_force_enable; 697 uint32_t dsc_num_slices_v; 698 uint32_t dsc_num_slices_h; 699 uint32_t dsc_bits_per_pixel; 700 bool dsc_force_disable_passthrough; 701 }; 702 703 enum mst_progress_status { 704 MST_STATUS_DEFAULT = 0, 705 MST_PROBE = BIT(0), 706 MST_REMOTE_EDID = BIT(1), 707 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 708 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 709 }; 710 711 /** 712 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 713 * 714 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 715 * struct is useful to keep track of the display-specific information about 716 * FreeSync. 717 */ 718 struct amdgpu_hdmi_vsdb_info { 719 /** 720 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 721 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 722 */ 723 unsigned int amd_vsdb_version; 724 725 /** 726 * @freesync_supported: FreeSync Supported. 727 */ 728 bool freesync_supported; 729 730 /** 731 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 732 */ 733 unsigned int min_refresh_rate_hz; 734 735 /** 736 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 737 */ 738 unsigned int max_refresh_rate_hz; 739 740 /** 741 * @replay_mode: Replay supported 742 */ 743 bool replay_mode; 744 }; 745 746 struct amdgpu_dm_connector { 747 748 struct drm_connector base; 749 uint32_t connector_id; 750 int bl_idx; 751 752 struct cec_notifier *notifier; 753 754 /* we need to mind the EDID between detect 755 and get modes due to analog/digital/tvencoder */ 756 const struct drm_edid *drm_edid; 757 758 /* shared with amdgpu */ 759 struct amdgpu_hpd hpd; 760 761 /* number of modes generated from EDID at 'dc_sink' */ 762 int num_modes; 763 764 /* The 'old' sink - before an HPD. 765 * The 'current' sink is in dc_link->sink. */ 766 struct dc_sink *dc_sink; 767 struct dc_link *dc_link; 768 769 /** 770 * @dc_em_sink: Reference to the emulated (virtual) sink. 771 */ 772 struct dc_sink *dc_em_sink; 773 774 /* DM only */ 775 struct drm_dp_mst_topology_mgr mst_mgr; 776 struct amdgpu_dm_dp_aux dm_dp_aux; 777 struct drm_dp_mst_port *mst_output_port; 778 struct amdgpu_dm_connector *mst_root; 779 struct drm_dp_aux *dsc_aux; 780 uint32_t mst_local_bw; 781 uint16_t vc_full_pbn; 782 struct mutex handle_mst_msg_ready; 783 784 /* branch device specific data */ 785 uint32_t branch_ieee_oui; 786 787 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 788 struct amdgpu_i2c_adapter *i2c; 789 790 /* Monitor range limits */ 791 /** 792 * @min_vfreq: Minimal frequency supported by the display in Hz. This 793 * value is set to zero when there is no FreeSync support. 794 */ 795 int min_vfreq; 796 797 /** 798 * @max_vfreq: Maximum frequency supported by the display in Hz. This 799 * value is set to zero when there is no FreeSync support. 800 */ 801 int max_vfreq ; 802 803 /* Audio instance - protected by audio_lock. */ 804 int audio_inst; 805 806 struct mutex hpd_lock; 807 808 bool fake_enable; 809 bool force_yuv420_output; 810 bool force_yuv422_output; 811 struct dsc_preferred_settings dsc_settings; 812 union dp_downstream_port_present mst_downstream_port_present; 813 /* Cached display modes */ 814 struct drm_display_mode freesync_vid_base; 815 816 int sr_skip_count; 817 bool disallow_edp_enter_psr; 818 bool disallow_edp_enter_replay; 819 820 /* Record progress status of mst*/ 821 uint8_t mst_status; 822 823 /* Automated testing */ 824 bool timing_changed; 825 struct dc_crtc_timing *timing_requested; 826 827 /* Adaptive Sync */ 828 bool pack_sdp_v1_3; 829 enum adaptive_sync_type as_type; 830 struct amdgpu_hdmi_vsdb_info vsdb_info; 831 832 /* HDMI HPD debounce support */ 833 unsigned int hdmi_hpd_debounce_delay_ms; 834 struct delayed_work hdmi_hpd_debounce_work; 835 struct dc_sink *hdmi_prev_sink; 836 }; 837 838 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 839 uint8_t flags, bool set) 840 { 841 if (set) 842 *status |= flags; 843 else 844 *status &= ~flags; 845 } 846 847 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 848 849 struct amdgpu_dm_wb_connector { 850 struct drm_writeback_connector base; 851 struct dc_link *link; 852 }; 853 854 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 855 856 extern const struct amdgpu_ip_block_version dm_ip_block; 857 858 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 859 * 860 * It includes standardized transfer functions and pure power functions. The 861 * transfer function coefficients are available at modules/color/color_gamma.c 862 */ 863 enum amdgpu_transfer_function { 864 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 865 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 866 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 867 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 868 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 869 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 870 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 871 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 872 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 873 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 874 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 875 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 876 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 877 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 878 AMDGPU_TRANSFER_FUNCTION_COUNT 879 }; 880 881 struct dm_plane_state { 882 struct drm_plane_state base; 883 struct dc_plane_state *dc_state; 884 885 /* Plane color mgmt */ 886 /** 887 * @degamma_lut: 888 * 889 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 890 * blending operations. It's usually applied to linearize input space. 891 * The blob (if not NULL) is an array of &struct drm_color_lut. 892 */ 893 struct drm_property_blob *degamma_lut; 894 /** 895 * @degamma_tf: 896 * 897 * Predefined transfer function to tell DC driver the input space to 898 * linearize. 899 */ 900 enum amdgpu_transfer_function degamma_tf; 901 /** 902 * @hdr_mult: 903 * 904 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 905 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 906 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 907 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 908 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 909 * S31.32 sign-magnitude. 910 * 911 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 912 * TF is needed for any subsequent linear-to-non-linear transforms. 913 */ 914 __u64 hdr_mult; 915 /** 916 * @ctm: 917 * 918 * Color transformation matrix. The blob (if not NULL) is a &struct 919 * drm_color_ctm_3x4. 920 */ 921 struct drm_property_blob *ctm; 922 /** 923 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 924 * array of &struct drm_color_lut. 925 */ 926 struct drm_property_blob *shaper_lut; 927 /** 928 * @shaper_tf: 929 * 930 * Predefined transfer function to delinearize color space. 931 */ 932 enum amdgpu_transfer_function shaper_tf; 933 /** 934 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 935 * &struct drm_color_lut. 936 */ 937 struct drm_property_blob *lut3d; 938 /** 939 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 940 * array of &struct drm_color_lut. 941 */ 942 struct drm_property_blob *blend_lut; 943 /** 944 * @blend_tf: 945 * 946 * Pre-defined transfer function for converting plane pixel data before 947 * applying blend LUT. 948 */ 949 enum amdgpu_transfer_function blend_tf; 950 }; 951 952 enum amdgpu_dm_cursor_mode { 953 DM_CURSOR_NATIVE_MODE = 0, 954 DM_CURSOR_OVERLAY_MODE, 955 }; 956 957 struct dm_crtc_state { 958 struct drm_crtc_state base; 959 struct dc_stream_state *stream; 960 961 bool cm_has_degamma; 962 bool cm_is_degamma_srgb; 963 964 bool mpo_requested; 965 966 int update_type; 967 int active_planes; 968 969 int crc_skip_count; 970 971 bool freesync_vrr_info_changed; 972 973 bool dsc_force_changed; 974 bool vrr_supported; 975 struct mod_freesync_config freesync_config; 976 struct dc_info_packet vrr_infopacket; 977 978 int abm_level; 979 980 /** 981 * @regamma_tf: 982 * 983 * Pre-defined transfer function for converting internal FB -> wire 984 * encoding. 985 */ 986 enum amdgpu_transfer_function regamma_tf; 987 988 enum amdgpu_dm_cursor_mode cursor_mode; 989 }; 990 991 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 992 993 struct dm_atomic_state { 994 struct drm_private_state base; 995 996 struct dc_state *context; 997 }; 998 999 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 1000 1001 struct dm_connector_state { 1002 struct drm_connector_state base; 1003 1004 enum amdgpu_rmx_type scaling; 1005 uint8_t underscan_vborder; 1006 uint8_t underscan_hborder; 1007 bool underscan_enable; 1008 bool freesync_capable; 1009 bool update_hdcp; 1010 bool abm_sysfs_forbidden; 1011 uint8_t abm_level; 1012 int vcpi_slots; 1013 uint64_t pbn; 1014 }; 1015 1016 #define to_dm_connector_state(x)\ 1017 container_of((x), struct dm_connector_state, base) 1018 1019 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1020 struct drm_connector_state * 1021 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1022 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1023 struct drm_connector_state *state, 1024 struct drm_property *property, 1025 uint64_t val); 1026 1027 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1028 const struct drm_connector_state *state, 1029 struct drm_property *property, 1030 uint64_t *val); 1031 1032 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1033 1034 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1035 struct amdgpu_dm_connector *aconnector, 1036 int connector_type, 1037 struct dc_link *link, 1038 int link_index); 1039 1040 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1041 const struct drm_display_mode *mode); 1042 1043 void dm_restore_drm_connector_state(struct drm_device *dev, 1044 struct drm_connector *connector); 1045 1046 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1047 const struct drm_edid *drm_edid); 1048 1049 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1050 1051 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1052 #define MAX_COLOR_3DLUT_SIZE 17 1053 #define MAX_COLOR_3DLUT_BITDEPTH 12 1054 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1055 struct drm_plane_state *plane_state); 1056 /* 1D LUT size */ 1057 #define MAX_COLOR_LUT_ENTRIES 4096 1058 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1059 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1060 1061 void amdgpu_dm_init_color_mod(void); 1062 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1063 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1064 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1065 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1066 bool check_only); 1067 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1068 struct drm_plane_state *plane_state, 1069 struct dc_plane_state *dc_plane_state); 1070 1071 void amdgpu_dm_update_connector_after_detect( 1072 struct amdgpu_dm_connector *aconnector); 1073 1074 void populate_hdmi_info_from_connector(struct drm_hdmi_info *info, 1075 struct dc_edid_caps *edid_caps); 1076 1077 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1078 1079 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1080 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1081 1082 bool amdgpu_dm_execute_fused_io( 1083 struct amdgpu_device *dev, 1084 struct dc_link *link, 1085 union dmub_rb_cmd *commands, 1086 uint8_t count, 1087 uint32_t timeout_us 1088 ); 1089 1090 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1091 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1092 1093 struct dc_stream_state * 1094 create_validate_stream_for_sink(struct drm_connector *connector, 1095 const struct drm_display_mode *drm_mode, 1096 const struct dm_connector_state *dm_state, 1097 const struct dc_stream_state *old_stream); 1098 1099 int dm_atomic_get_state(struct drm_atomic_state *state, 1100 struct dm_atomic_state **dm_state); 1101 1102 struct drm_connector * 1103 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1104 struct drm_crtc *crtc); 1105 1106 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1107 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1108 1109 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1110 enum dc_gpu_mem_alloc_type type, 1111 size_t size, 1112 long long *addr); 1113 void dm_free_gpu_mem(struct amdgpu_device *adev, 1114 enum dc_gpu_mem_alloc_type type, 1115 void *addr); 1116 1117 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1118 1119 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1120 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1121 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1122 1123 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1124 1125 #endif /* __AMDGPU_DM_H__ */ 1126