1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 59 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 62 /* 63 #include "include/amdgpu_dal_power_if.h" 64 #include "amdgpu_dm_irq.h" 65 */ 66 67 #include "irq_types.h" 68 #include "signal_types.h" 69 #include "amdgpu_dm_crc.h" 70 #include "mod_info_packet.h" 71 struct aux_payload; 72 struct set_config_cmd_payload; 73 enum aux_return_code_type; 74 enum set_config_status; 75 76 /* Forward declarations */ 77 struct amdgpu_device; 78 struct amdgpu_crtc; 79 struct drm_device; 80 struct dc; 81 struct amdgpu_bo; 82 struct dmub_srv; 83 struct dc_plane_state; 84 struct dmub_notification; 85 struct dmub_cmd_fused_request; 86 87 struct amd_vsdb_block { 88 unsigned char ieee_id[3]; 89 unsigned char version; 90 unsigned char feature_caps; 91 }; 92 93 struct common_irq_params { 94 struct amdgpu_device *adev; 95 enum dc_irq_source irq_src; 96 atomic64_t previous_timestamp; 97 }; 98 99 /** 100 * struct dm_compressor_info - Buffer info used by frame buffer compression 101 * @cpu_addr: MMIO cpu addr 102 * @bo_ptr: Pointer to the buffer object 103 * @gpu_addr: MMIO gpu addr 104 */ 105 struct dm_compressor_info { 106 void *cpu_addr; 107 struct amdgpu_bo *bo_ptr; 108 uint64_t gpu_addr; 109 }; 110 111 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 112 113 /** 114 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 115 * 116 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 117 * @dmub_notify: notification for callback function 118 * @adev: amdgpu_device pointer 119 */ 120 struct dmub_hpd_work { 121 struct work_struct handle_hpd_work; 122 struct dmub_notification *dmub_notify; 123 struct amdgpu_device *adev; 124 }; 125 126 /** 127 * struct vblank_control_work - Work data for vblank control 128 * @work: Kernel work data for the work event 129 * @dm: amdgpu display manager device 130 * @acrtc: amdgpu CRTC instance for which the event has occurred 131 * @stream: DC stream for which the event has occurred 132 * @enable: true if enabling vblank 133 */ 134 struct vblank_control_work { 135 struct work_struct work; 136 struct amdgpu_display_manager *dm; 137 struct amdgpu_crtc *acrtc; 138 struct dc_stream_state *stream; 139 bool enable; 140 }; 141 142 /** 143 * struct idle_workqueue - Work data for periodic action in idle 144 * @work: Kernel work data for the work event 145 * @dm: amdgpu display manager device 146 * @enable: true if idle worker is enabled 147 * @running: true if idle worker is running 148 */ 149 struct idle_workqueue { 150 struct work_struct work; 151 struct amdgpu_display_manager *dm; 152 bool enable; 153 bool running; 154 }; 155 156 /** 157 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 158 * @work: Kernel work data for the work event 159 * @adev: amdgpu_device back pointer 160 * @stream: DC stream associated with the crtc 161 * @adjust: DC CRTC timing adjust to be applied to the crtc 162 */ 163 struct vupdate_offload_work { 164 struct work_struct work; 165 struct amdgpu_device *adev; 166 struct dc_stream_state *stream; 167 struct dc_crtc_timing_adjust *adjust; 168 }; 169 170 #define MAX_LUMINANCE_DATA_POINTS 99 171 172 /** 173 * struct amdgpu_dm_luminance_data - Custom luminance data 174 * @luminance: Luminance in percent 175 * @input_signal: Input signal in range 0-255 176 */ 177 struct amdgpu_dm_luminance_data { 178 u8 luminance; 179 u8 input_signal; 180 } __packed; 181 182 /** 183 * struct amdgpu_dm_backlight_caps - Information about backlight 184 * 185 * Describe the backlight support for ACPI or eDP AUX. 186 */ 187 struct amdgpu_dm_backlight_caps { 188 /** 189 * @ext_caps: Keep the data struct with all the information about the 190 * display support for HDR. 191 */ 192 union dpcd_sink_ext_caps *ext_caps; 193 /** 194 * @aux_min_input_signal: Min brightness value supported by the display 195 */ 196 u32 aux_min_input_signal; 197 /** 198 * @aux_max_input_signal: Max brightness value supported by the display 199 * in nits. 200 */ 201 u32 aux_max_input_signal; 202 /** 203 * @min_input_signal: minimum possible input in range 0-255. 204 */ 205 int min_input_signal; 206 /** 207 * @max_input_signal: maximum possible input in range 0-255. 208 */ 209 int max_input_signal; 210 /** 211 * @caps_valid: true if these values are from the ACPI interface. 212 */ 213 bool caps_valid; 214 /** 215 * @aux_support: Describes if the display supports AUX backlight. 216 */ 217 bool aux_support; 218 /** 219 * @ac_level: the default brightness if booted on AC 220 */ 221 u8 ac_level; 222 /** 223 * @dc_level: the default brightness if booted on DC 224 */ 225 u8 dc_level; 226 /** 227 * @data_points: the number of custom luminance data points 228 */ 229 u8 data_points; 230 /** 231 * @luminance_data: custom luminance data 232 */ 233 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 234 }; 235 236 /** 237 * struct dal_allocation - Tracks mapped FB memory for SMU communication 238 * @list: list of dal allocations 239 * @bo: GPU buffer object 240 * @cpu_ptr: CPU virtual address of the GPU buffer object 241 * @gpu_addr: GPU virtual address of the GPU buffer object 242 */ 243 struct dal_allocation { 244 struct list_head list; 245 struct amdgpu_bo *bo; 246 void *cpu_ptr; 247 u64 gpu_addr; 248 }; 249 250 /** 251 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 252 * offload work 253 */ 254 struct hpd_rx_irq_offload_work_queue { 255 /** 256 * @wq: workqueue structure to queue offload work. 257 */ 258 struct workqueue_struct *wq; 259 /** 260 * @offload_lock: To protect fields of offload work queue. 261 */ 262 spinlock_t offload_lock; 263 /** 264 * @is_handling_link_loss: Used to prevent inserting link loss event when 265 * we're handling link loss 266 */ 267 bool is_handling_link_loss; 268 /** 269 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 270 * ready event when we're already handling mst message ready event 271 */ 272 bool is_handling_mst_msg_rdy_event; 273 /** 274 * @aconnector: The aconnector that this work queue is attached to 275 */ 276 struct amdgpu_dm_connector *aconnector; 277 }; 278 279 /** 280 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 281 */ 282 struct hpd_rx_irq_offload_work { 283 /** 284 * @work: offload work 285 */ 286 struct work_struct work; 287 /** 288 * @data: reference irq data which is used while handling offload work 289 */ 290 union hpd_irq_data data; 291 /** 292 * @offload_wq: offload work queue that this work is queued to 293 */ 294 struct hpd_rx_irq_offload_work_queue *offload_wq; 295 /** 296 * @adev: amdgpu_device pointer 297 */ 298 struct amdgpu_device *adev; 299 }; 300 301 /** 302 * struct amdgpu_display_manager - Central amdgpu display manager device 303 * 304 * @dc: Display Core control structure 305 * @adev: AMDGPU base driver structure 306 * @ddev: DRM base driver structure 307 * @display_indexes_num: Max number of display streams supported 308 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 309 * @backlight_dev: Backlight control device 310 * @backlight_link: Link on which to control backlight 311 * @backlight_caps: Capabilities of the backlight device 312 * @freesync_module: Module handling freesync calculations 313 * @hdcp_workqueue: AMDGPU content protection queue 314 * @fw_dmcu: Reference to DMCU firmware 315 * @dmcu_fw_version: Version of the DMCU firmware 316 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 317 * @cached_state: Caches device atomic state for suspend/resume 318 * @cached_dc_state: Cached state of content streams 319 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 320 * @force_timing_sync: set via debugfs. When set, indicates that all connected 321 * displays will be forced to synchronize. 322 * @dmcub_trace_event_en: enable dmcub trace events 323 * @dmub_outbox_params: DMUB Outbox parameters 324 * @num_of_edps: number of backlight eDPs 325 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 326 * driver when true 327 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 328 * transfers are done 329 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 330 */ 331 struct amdgpu_display_manager { 332 333 struct dc *dc; 334 335 /** 336 * @dmub_srv: 337 * 338 * DMUB service, used for controlling the DMUB on hardware 339 * that supports it. The pointer to the dmub_srv will be 340 * NULL on hardware that does not support it. 341 */ 342 struct dmub_srv *dmub_srv; 343 344 /** 345 * @dmub_notify: 346 * 347 * Notification from DMUB. 348 */ 349 350 struct dmub_notification *dmub_notify; 351 352 /** 353 * @dmub_callback: 354 * 355 * Callback functions to handle notification from DMUB. 356 */ 357 358 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 359 360 /** 361 * @dmub_thread_offload: 362 * 363 * Flag to indicate if callback is offload. 364 */ 365 366 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 367 368 /** 369 * @dmub_fb_info: 370 * 371 * Framebuffer regions for the DMUB. 372 */ 373 struct dmub_srv_fb_info *dmub_fb_info; 374 375 /** 376 * @dmub_fw: 377 * 378 * DMUB firmware, required on hardware that has DMUB support. 379 */ 380 const struct firmware *dmub_fw; 381 382 /** 383 * @dmub_bo: 384 * 385 * Buffer object for the DMUB. 386 */ 387 struct amdgpu_bo *dmub_bo; 388 389 /** 390 * @dmub_bo_gpu_addr: 391 * 392 * GPU virtual address for the DMUB buffer object. 393 */ 394 u64 dmub_bo_gpu_addr; 395 396 /** 397 * @dmub_bo_cpu_addr: 398 * 399 * CPU address for the DMUB buffer object. 400 */ 401 void *dmub_bo_cpu_addr; 402 403 /** 404 * @dmcub_fw_version: 405 * 406 * DMCUB firmware version. 407 */ 408 uint32_t dmcub_fw_version; 409 410 /** 411 * @cgs_device: 412 * 413 * The Common Graphics Services device. It provides an interface for 414 * accessing registers. 415 */ 416 struct cgs_device *cgs_device; 417 418 struct amdgpu_device *adev; 419 struct drm_device *ddev; 420 u16 display_indexes_num; 421 422 /** 423 * @atomic_obj: 424 * 425 * In combination with &dm_atomic_state it helps manage 426 * global atomic state that doesn't map cleanly into existing 427 * drm resources, like &dc_context. 428 */ 429 struct drm_private_obj atomic_obj; 430 431 /** 432 * @dc_lock: 433 * 434 * Guards access to DC functions that can issue register write 435 * sequences. 436 */ 437 struct mutex dc_lock; 438 439 /** 440 * @audio_lock: 441 * 442 * Guards access to audio instance changes. 443 */ 444 struct mutex audio_lock; 445 446 /** 447 * @audio_component: 448 * 449 * Used to notify ELD changes to sound driver. 450 */ 451 struct drm_audio_component *audio_component; 452 453 /** 454 * @audio_registered: 455 * 456 * True if the audio component has been registered 457 * successfully, false otherwise. 458 */ 459 bool audio_registered; 460 461 /** 462 * @irq_handler_list_low_tab: 463 * 464 * Low priority IRQ handler table. 465 * 466 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 467 * source. Low priority IRQ handlers are deferred to a workqueue to be 468 * processed. Hence, they can sleep. 469 * 470 * Note that handlers are called in the same order as they were 471 * registered (FIFO). 472 */ 473 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 474 475 /** 476 * @irq_handler_list_high_tab: 477 * 478 * High priority IRQ handler table. 479 * 480 * It is a n*m table, same as &irq_handler_list_low_tab. However, 481 * handlers in this table are not deferred and are called immediately. 482 */ 483 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 484 485 /** 486 * @pflip_params: 487 * 488 * Page flip IRQ parameters, passed to registered handlers when 489 * triggered. 490 */ 491 struct common_irq_params 492 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 493 494 /** 495 * @vblank_params: 496 * 497 * Vertical blanking IRQ parameters, passed to registered handlers when 498 * triggered. 499 */ 500 struct common_irq_params 501 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 502 503 /** 504 * @vline0_params: 505 * 506 * OTG vertical interrupt0 IRQ parameters, passed to registered 507 * handlers when triggered. 508 */ 509 struct common_irq_params 510 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 511 512 /** 513 * @vupdate_params: 514 * 515 * Vertical update IRQ parameters, passed to registered handlers when 516 * triggered. 517 */ 518 struct common_irq_params 519 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 520 521 /** 522 * @dmub_trace_params: 523 * 524 * DMUB trace event IRQ parameters, passed to registered handlers when 525 * triggered. 526 */ 527 struct common_irq_params 528 dmub_trace_params[1]; 529 530 struct common_irq_params 531 dmub_outbox_params[1]; 532 533 spinlock_t irq_handler_list_table_lock; 534 535 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 536 537 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 538 539 uint8_t num_of_edps; 540 541 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 542 543 struct mod_freesync *freesync_module; 544 struct hdcp_workqueue *hdcp_workqueue; 545 546 /** 547 * @vblank_control_workqueue: 548 * 549 * Deferred work for vblank control events. 550 */ 551 struct workqueue_struct *vblank_control_workqueue; 552 553 /** 554 * @idle_workqueue: 555 * 556 * Periodic work for idle events. 557 */ 558 struct idle_workqueue *idle_workqueue; 559 560 struct drm_atomic_state *cached_state; 561 struct dc_state *cached_dc_state; 562 563 struct dm_compressor_info compressor; 564 565 const struct firmware *fw_dmcu; 566 uint32_t dmcu_fw_version; 567 /** 568 * @soc_bounding_box: 569 * 570 * gpu_info FW provided soc bounding box struct or 0 if not 571 * available in FW 572 */ 573 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 574 575 /** 576 * @active_vblank_irq_count: 577 * 578 * number of currently active vblank irqs 579 */ 580 uint32_t active_vblank_irq_count; 581 582 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 583 /** 584 * @secure_display_ctx: 585 * 586 * Store secure display relevant info. e.g. the ROI information 587 * , the work_struct to command dmub, etc. 588 */ 589 struct secure_display_context secure_display_ctx; 590 #endif 591 /** 592 * @hpd_rx_offload_wq: 593 * 594 * Work queue to offload works of hpd_rx_irq 595 */ 596 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 597 /** 598 * @mst_encoders: 599 * 600 * fake encoders used for DP MST. 601 */ 602 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 603 bool force_timing_sync; 604 bool disable_hpd_irq; 605 bool dmcub_trace_event_en; 606 /** 607 * @da_list: 608 * 609 * DAL fb memory allocation list, for communication with SMU. 610 */ 611 struct list_head da_list; 612 struct completion dmub_aux_transfer_done; 613 struct workqueue_struct *delayed_hpd_wq; 614 615 /** 616 * @brightness: 617 * 618 * cached backlight values. 619 */ 620 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 621 /** 622 * @actual_brightness: 623 * 624 * last successfully applied backlight values. 625 */ 626 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 627 628 /** 629 * @aux_hpd_discon_quirk: 630 * 631 * quirk for hpd discon while aux is on-going. 632 * occurred on certain intel platform 633 */ 634 bool aux_hpd_discon_quirk; 635 636 /** 637 * @edp0_on_dp1_quirk: 638 * 639 * quirk for platforms that put edp0 on DP1. 640 */ 641 bool edp0_on_dp1_quirk; 642 643 /** 644 * @dpia_aux_lock: 645 * 646 * Guards access to DPIA AUX 647 */ 648 struct mutex dpia_aux_lock; 649 650 /** 651 * @bb_from_dmub: 652 * 653 * Bounding box data read from dmub during early initialization for DCN4+ 654 * Data is stored as a byte array that should be casted to the appropriate bb struct 655 */ 656 void *bb_from_dmub; 657 658 /** 659 * @oem_i2c: 660 * 661 * OEM i2c bus 662 */ 663 struct amdgpu_i2c_adapter *oem_i2c; 664 665 /** 666 * @fused_io: 667 * 668 * dmub fused io interface 669 */ 670 struct fused_io_sync { 671 struct completion replied; 672 char reply_data[0x40]; // Cannot include dmub_cmd here 673 } fused_io[8]; 674 }; 675 676 enum dsc_clock_force_state { 677 DSC_CLK_FORCE_DEFAULT = 0, 678 DSC_CLK_FORCE_ENABLE, 679 DSC_CLK_FORCE_DISABLE, 680 }; 681 682 struct dsc_preferred_settings { 683 enum dsc_clock_force_state dsc_force_enable; 684 uint32_t dsc_num_slices_v; 685 uint32_t dsc_num_slices_h; 686 uint32_t dsc_bits_per_pixel; 687 bool dsc_force_disable_passthrough; 688 }; 689 690 enum mst_progress_status { 691 MST_STATUS_DEFAULT = 0, 692 MST_PROBE = BIT(0), 693 MST_REMOTE_EDID = BIT(1), 694 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 695 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 696 }; 697 698 /** 699 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 700 * 701 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 702 * struct is useful to keep track of the display-specific information about 703 * FreeSync. 704 */ 705 struct amdgpu_hdmi_vsdb_info { 706 /** 707 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 708 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 709 */ 710 unsigned int amd_vsdb_version; 711 712 /** 713 * @freesync_supported: FreeSync Supported. 714 */ 715 bool freesync_supported; 716 717 /** 718 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 719 */ 720 unsigned int min_refresh_rate_hz; 721 722 /** 723 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 724 */ 725 unsigned int max_refresh_rate_hz; 726 727 /** 728 * @replay_mode: Replay supported 729 */ 730 bool replay_mode; 731 }; 732 733 struct amdgpu_dm_connector { 734 735 struct drm_connector base; 736 uint32_t connector_id; 737 int bl_idx; 738 739 struct cec_notifier *notifier; 740 741 /* we need to mind the EDID between detect 742 and get modes due to analog/digital/tvencoder */ 743 const struct drm_edid *drm_edid; 744 745 /* shared with amdgpu */ 746 struct amdgpu_hpd hpd; 747 748 /* number of modes generated from EDID at 'dc_sink' */ 749 int num_modes; 750 751 /* The 'old' sink - before an HPD. 752 * The 'current' sink is in dc_link->sink. */ 753 struct dc_sink *dc_sink; 754 struct dc_link *dc_link; 755 756 /** 757 * @dc_em_sink: Reference to the emulated (virtual) sink. 758 */ 759 struct dc_sink *dc_em_sink; 760 761 /* DM only */ 762 struct drm_dp_mst_topology_mgr mst_mgr; 763 struct amdgpu_dm_dp_aux dm_dp_aux; 764 struct drm_dp_mst_port *mst_output_port; 765 struct amdgpu_dm_connector *mst_root; 766 struct drm_dp_aux *dsc_aux; 767 uint32_t mst_local_bw; 768 uint16_t vc_full_pbn; 769 struct mutex handle_mst_msg_ready; 770 771 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 772 struct amdgpu_i2c_adapter *i2c; 773 774 /* Monitor range limits */ 775 /** 776 * @min_vfreq: Minimal frequency supported by the display in Hz. This 777 * value is set to zero when there is no FreeSync support. 778 */ 779 int min_vfreq; 780 781 /** 782 * @max_vfreq: Maximum frequency supported by the display in Hz. This 783 * value is set to zero when there is no FreeSync support. 784 */ 785 int max_vfreq ; 786 787 /* Audio instance - protected by audio_lock. */ 788 int audio_inst; 789 790 struct mutex hpd_lock; 791 792 bool fake_enable; 793 bool force_yuv420_output; 794 struct dsc_preferred_settings dsc_settings; 795 union dp_downstream_port_present mst_downstream_port_present; 796 /* Cached display modes */ 797 struct drm_display_mode freesync_vid_base; 798 799 int sr_skip_count; 800 bool disallow_edp_enter_psr; 801 802 /* Record progress status of mst*/ 803 uint8_t mst_status; 804 805 /* Automated testing */ 806 bool timing_changed; 807 struct dc_crtc_timing *timing_requested; 808 809 /* Adaptive Sync */ 810 bool pack_sdp_v1_3; 811 enum adaptive_sync_type as_type; 812 struct amdgpu_hdmi_vsdb_info vsdb_info; 813 }; 814 815 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 816 uint8_t flags, bool set) 817 { 818 if (set) 819 *status |= flags; 820 else 821 *status &= ~flags; 822 } 823 824 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 825 826 struct amdgpu_dm_wb_connector { 827 struct drm_writeback_connector base; 828 struct dc_link *link; 829 }; 830 831 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 832 833 extern const struct amdgpu_ip_block_version dm_ip_block; 834 835 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 836 * 837 * It includes standardized transfer functions and pure power functions. The 838 * transfer function coefficients are available at modules/color/color_gamma.c 839 */ 840 enum amdgpu_transfer_function { 841 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 842 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 843 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 844 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 845 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 846 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 847 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 848 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 849 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 850 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 851 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 852 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 853 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 854 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 855 AMDGPU_TRANSFER_FUNCTION_COUNT 856 }; 857 858 struct dm_plane_state { 859 struct drm_plane_state base; 860 struct dc_plane_state *dc_state; 861 862 /* Plane color mgmt */ 863 /** 864 * @degamma_lut: 865 * 866 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 867 * blending operations. It's usually applied to linearize input space. 868 * The blob (if not NULL) is an array of &struct drm_color_lut. 869 */ 870 struct drm_property_blob *degamma_lut; 871 /** 872 * @degamma_tf: 873 * 874 * Predefined transfer function to tell DC driver the input space to 875 * linearize. 876 */ 877 enum amdgpu_transfer_function degamma_tf; 878 /** 879 * @hdr_mult: 880 * 881 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 882 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 883 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 884 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 885 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 886 * S31.32 sign-magnitude. 887 * 888 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 889 * TF is needed for any subsequent linear-to-non-linear transforms. 890 */ 891 __u64 hdr_mult; 892 /** 893 * @ctm: 894 * 895 * Color transformation matrix. The blob (if not NULL) is a &struct 896 * drm_color_ctm_3x4. 897 */ 898 struct drm_property_blob *ctm; 899 /** 900 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 901 * array of &struct drm_color_lut. 902 */ 903 struct drm_property_blob *shaper_lut; 904 /** 905 * @shaper_tf: 906 * 907 * Predefined transfer function to delinearize color space. 908 */ 909 enum amdgpu_transfer_function shaper_tf; 910 /** 911 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 912 * &struct drm_color_lut. 913 */ 914 struct drm_property_blob *lut3d; 915 /** 916 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 917 * array of &struct drm_color_lut. 918 */ 919 struct drm_property_blob *blend_lut; 920 /** 921 * @blend_tf: 922 * 923 * Pre-defined transfer function for converting plane pixel data before 924 * applying blend LUT. 925 */ 926 enum amdgpu_transfer_function blend_tf; 927 }; 928 929 enum amdgpu_dm_cursor_mode { 930 DM_CURSOR_NATIVE_MODE = 0, 931 DM_CURSOR_OVERLAY_MODE, 932 }; 933 934 struct dm_crtc_state { 935 struct drm_crtc_state base; 936 struct dc_stream_state *stream; 937 938 bool cm_has_degamma; 939 bool cm_is_degamma_srgb; 940 941 bool mpo_requested; 942 943 int update_type; 944 int active_planes; 945 946 int crc_skip_count; 947 948 bool freesync_vrr_info_changed; 949 950 bool dsc_force_changed; 951 bool vrr_supported; 952 struct mod_freesync_config freesync_config; 953 struct dc_info_packet vrr_infopacket; 954 955 int abm_level; 956 957 /** 958 * @regamma_tf: 959 * 960 * Pre-defined transfer function for converting internal FB -> wire 961 * encoding. 962 */ 963 enum amdgpu_transfer_function regamma_tf; 964 965 enum amdgpu_dm_cursor_mode cursor_mode; 966 }; 967 968 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 969 970 struct dm_atomic_state { 971 struct drm_private_state base; 972 973 struct dc_state *context; 974 }; 975 976 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 977 978 struct dm_connector_state { 979 struct drm_connector_state base; 980 981 enum amdgpu_rmx_type scaling; 982 uint8_t underscan_vborder; 983 uint8_t underscan_hborder; 984 bool underscan_enable; 985 bool freesync_capable; 986 bool update_hdcp; 987 uint8_t abm_level; 988 int vcpi_slots; 989 uint64_t pbn; 990 }; 991 992 #define to_dm_connector_state(x)\ 993 container_of((x), struct dm_connector_state, base) 994 995 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 996 struct drm_connector_state * 997 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 998 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 999 struct drm_connector_state *state, 1000 struct drm_property *property, 1001 uint64_t val); 1002 1003 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1004 const struct drm_connector_state *state, 1005 struct drm_property *property, 1006 uint64_t *val); 1007 1008 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1009 1010 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1011 struct amdgpu_dm_connector *aconnector, 1012 int connector_type, 1013 struct dc_link *link, 1014 int link_index); 1015 1016 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1017 const struct drm_display_mode *mode); 1018 1019 void dm_restore_drm_connector_state(struct drm_device *dev, 1020 struct drm_connector *connector); 1021 1022 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1023 const struct drm_edid *drm_edid); 1024 1025 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1026 1027 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1028 #define MAX_COLOR_3DLUT_SIZE 17 1029 #define MAX_COLOR_3DLUT_BITDEPTH 12 1030 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1031 struct drm_plane_state *plane_state); 1032 /* 1D LUT size */ 1033 #define MAX_COLOR_LUT_ENTRIES 4096 1034 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1035 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1036 1037 void amdgpu_dm_init_color_mod(void); 1038 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1039 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1040 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1041 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1042 struct drm_plane_state *plane_state, 1043 struct dc_plane_state *dc_plane_state); 1044 1045 void amdgpu_dm_update_connector_after_detect( 1046 struct amdgpu_dm_connector *aconnector); 1047 1048 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1049 1050 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1051 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1052 1053 bool amdgpu_dm_execute_fused_io( 1054 struct amdgpu_device *dev, 1055 struct dc_link *link, 1056 union dmub_rb_cmd *commands, 1057 uint8_t count, 1058 uint32_t timeout_us 1059 ); 1060 1061 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1062 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1063 1064 struct dc_stream_state * 1065 create_validate_stream_for_sink(struct drm_connector *connector, 1066 const struct drm_display_mode *drm_mode, 1067 const struct dm_connector_state *dm_state, 1068 const struct dc_stream_state *old_stream); 1069 1070 int dm_atomic_get_state(struct drm_atomic_state *state, 1071 struct dm_atomic_state **dm_state); 1072 1073 struct drm_connector * 1074 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1075 struct drm_crtc *crtc); 1076 1077 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1078 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1079 1080 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1081 enum dc_gpu_mem_alloc_type type, 1082 size_t size, 1083 long long *addr); 1084 void dm_free_gpu_mem(struct amdgpu_device *adev, 1085 enum dc_gpu_mem_alloc_type type, 1086 void *addr); 1087 1088 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1089 1090 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1091 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1092 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1093 1094 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1095 1096 #endif /* __AMDGPU_DM_H__ */ 1097