1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 59 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 62 #define AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS 1500 63 /* 64 #include "include/amdgpu_dal_power_if.h" 65 #include "amdgpu_dm_irq.h" 66 */ 67 68 #include "irq_types.h" 69 #include "signal_types.h" 70 #include "amdgpu_dm_crc.h" 71 #include "mod_info_packet.h" 72 struct aux_payload; 73 struct set_config_cmd_payload; 74 enum aux_return_code_type; 75 enum set_config_status; 76 77 /* Forward declarations */ 78 struct amdgpu_device; 79 struct amdgpu_crtc; 80 struct drm_device; 81 struct dc; 82 struct amdgpu_bo; 83 struct dmub_srv; 84 struct dc_plane_state; 85 struct dmub_notification; 86 struct dmub_cmd_fused_request; 87 88 struct amd_vsdb_block { 89 unsigned char ieee_id[3]; 90 unsigned char version; 91 unsigned char feature_caps; 92 }; 93 94 struct common_irq_params { 95 struct amdgpu_device *adev; 96 enum dc_irq_source irq_src; 97 atomic64_t previous_timestamp; 98 }; 99 100 /** 101 * struct dm_compressor_info - Buffer info used by frame buffer compression 102 * @cpu_addr: MMIO cpu addr 103 * @bo_ptr: Pointer to the buffer object 104 * @gpu_addr: MMIO gpu addr 105 */ 106 struct dm_compressor_info { 107 void *cpu_addr; 108 struct amdgpu_bo *bo_ptr; 109 uint64_t gpu_addr; 110 }; 111 112 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 113 114 /** 115 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 116 * 117 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 118 * @dmub_notify: notification for callback function 119 * @adev: amdgpu_device pointer 120 */ 121 struct dmub_hpd_work { 122 struct work_struct handle_hpd_work; 123 struct dmub_notification *dmub_notify; 124 struct amdgpu_device *adev; 125 }; 126 127 /** 128 * struct vblank_control_work - Work data for vblank control 129 * @work: Kernel work data for the work event 130 * @dm: amdgpu display manager device 131 * @acrtc: amdgpu CRTC instance for which the event has occurred 132 * @stream: DC stream for which the event has occurred 133 * @enable: true if enabling vblank 134 */ 135 struct vblank_control_work { 136 struct work_struct work; 137 struct amdgpu_display_manager *dm; 138 struct amdgpu_crtc *acrtc; 139 struct dc_stream_state *stream; 140 bool enable; 141 }; 142 143 /** 144 * struct idle_workqueue - Work data for periodic action in idle 145 * @work: Kernel work data for the work event 146 * @dm: amdgpu display manager device 147 * @enable: true if idle worker is enabled 148 * @running: true if idle worker is running 149 */ 150 struct idle_workqueue { 151 struct work_struct work; 152 struct amdgpu_display_manager *dm; 153 bool enable; 154 bool running; 155 }; 156 157 /** 158 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 159 * @work: Kernel work data for the work event 160 * @adev: amdgpu_device back pointer 161 * @stream: DC stream associated with the crtc 162 * @adjust: DC CRTC timing adjust to be applied to the crtc 163 */ 164 struct vupdate_offload_work { 165 struct work_struct work; 166 struct amdgpu_device *adev; 167 struct dc_stream_state *stream; 168 struct dc_crtc_timing_adjust *adjust; 169 }; 170 171 #define MAX_LUMINANCE_DATA_POINTS 99 172 173 /** 174 * struct amdgpu_dm_luminance_data - Custom luminance data 175 * @luminance: Luminance in percent 176 * @input_signal: Input signal in range 0-255 177 */ 178 struct amdgpu_dm_luminance_data { 179 u8 luminance; 180 u8 input_signal; 181 } __packed; 182 183 /** 184 * struct amdgpu_dm_backlight_caps - Information about backlight 185 * 186 * Describe the backlight support for ACPI or eDP AUX. 187 */ 188 struct amdgpu_dm_backlight_caps { 189 /** 190 * @ext_caps: Keep the data struct with all the information about the 191 * display support for HDR. 192 */ 193 union dpcd_sink_ext_caps *ext_caps; 194 /** 195 * @aux_min_input_signal: Min brightness value supported by the display 196 */ 197 u32 aux_min_input_signal; 198 /** 199 * @aux_max_input_signal: Max brightness value supported by the display 200 * in nits. 201 */ 202 u32 aux_max_input_signal; 203 /** 204 * @min_input_signal: minimum possible input in range 0-255. 205 */ 206 int min_input_signal; 207 /** 208 * @max_input_signal: maximum possible input in range 0-255. 209 */ 210 int max_input_signal; 211 /** 212 * @caps_valid: true if these values are from the ACPI interface. 213 */ 214 bool caps_valid; 215 /** 216 * @aux_support: Describes if the display supports AUX backlight. 217 */ 218 bool aux_support; 219 /** 220 * @brightness_mask: After deriving brightness, OR it with this mask. 221 * Workaround for panels with issues with certain brightness values. 222 */ 223 u32 brightness_mask; 224 /** 225 * @ac_level: the default brightness if booted on AC 226 */ 227 u8 ac_level; 228 /** 229 * @dc_level: the default brightness if booted on DC 230 */ 231 u8 dc_level; 232 /** 233 * @data_points: the number of custom luminance data points 234 */ 235 u8 data_points; 236 /** 237 * @luminance_data: custom luminance data 238 */ 239 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 240 }; 241 242 /** 243 * struct dal_allocation - Tracks mapped FB memory for SMU communication 244 * @list: list of dal allocations 245 * @bo: GPU buffer object 246 * @cpu_ptr: CPU virtual address of the GPU buffer object 247 * @gpu_addr: GPU virtual address of the GPU buffer object 248 */ 249 struct dal_allocation { 250 struct list_head list; 251 struct amdgpu_bo *bo; 252 void *cpu_ptr; 253 u64 gpu_addr; 254 }; 255 256 /** 257 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 258 * offload work 259 */ 260 struct hpd_rx_irq_offload_work_queue { 261 /** 262 * @wq: workqueue structure to queue offload work. 263 */ 264 struct workqueue_struct *wq; 265 /** 266 * @offload_lock: To protect fields of offload work queue. 267 */ 268 spinlock_t offload_lock; 269 /** 270 * @is_handling_link_loss: Used to prevent inserting link loss event when 271 * we're handling link loss 272 */ 273 bool is_handling_link_loss; 274 /** 275 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 276 * ready event when we're already handling mst message ready event 277 */ 278 bool is_handling_mst_msg_rdy_event; 279 /** 280 * @aconnector: The aconnector that this work queue is attached to 281 */ 282 struct amdgpu_dm_connector *aconnector; 283 }; 284 285 /** 286 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 287 */ 288 struct hpd_rx_irq_offload_work { 289 /** 290 * @work: offload work 291 */ 292 struct work_struct work; 293 /** 294 * @data: reference irq data which is used while handling offload work 295 */ 296 union hpd_irq_data data; 297 /** 298 * @offload_wq: offload work queue that this work is queued to 299 */ 300 struct hpd_rx_irq_offload_work_queue *offload_wq; 301 /** 302 * @adev: amdgpu_device pointer 303 */ 304 struct amdgpu_device *adev; 305 }; 306 307 /** 308 * struct amdgpu_display_manager - Central amdgpu display manager device 309 * 310 * @dc: Display Core control structure 311 * @adev: AMDGPU base driver structure 312 * @ddev: DRM base driver structure 313 * @display_indexes_num: Max number of display streams supported 314 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 315 * @backlight_dev: Backlight control device 316 * @backlight_link: Link on which to control backlight 317 * @backlight_caps: Capabilities of the backlight device 318 * @freesync_module: Module handling freesync calculations 319 * @hdcp_workqueue: AMDGPU content protection queue 320 * @fw_dmcu: Reference to DMCU firmware 321 * @dmcu_fw_version: Version of the DMCU firmware 322 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 323 * @cached_state: Caches device atomic state for suspend/resume 324 * @cached_dc_state: Cached state of content streams 325 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 326 * @force_timing_sync: set via debugfs. When set, indicates that all connected 327 * displays will be forced to synchronize. 328 * @dmcub_trace_event_en: enable dmcub trace events 329 * @dmub_outbox_params: DMUB Outbox parameters 330 * @num_of_edps: number of backlight eDPs 331 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 332 * driver when true 333 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 334 * transfers are done 335 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 336 */ 337 struct amdgpu_display_manager { 338 339 struct dc *dc; 340 341 /** 342 * @dmub_srv: 343 * 344 * DMUB service, used for controlling the DMUB on hardware 345 * that supports it. The pointer to the dmub_srv will be 346 * NULL on hardware that does not support it. 347 */ 348 struct dmub_srv *dmub_srv; 349 350 /** 351 * @dmub_notify: 352 * 353 * Notification from DMUB. 354 */ 355 356 struct dmub_notification *dmub_notify; 357 358 /** 359 * @dmub_callback: 360 * 361 * Callback functions to handle notification from DMUB. 362 */ 363 364 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 365 366 /** 367 * @dmub_thread_offload: 368 * 369 * Flag to indicate if callback is offload. 370 */ 371 372 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 373 374 /** 375 * @dmub_fb_info: 376 * 377 * Framebuffer regions for the DMUB. 378 */ 379 struct dmub_srv_fb_info *dmub_fb_info; 380 381 /** 382 * @dmub_fw: 383 * 384 * DMUB firmware, required on hardware that has DMUB support. 385 */ 386 const struct firmware *dmub_fw; 387 388 /** 389 * @dmub_bo: 390 * 391 * Buffer object for the DMUB. 392 */ 393 struct amdgpu_bo *dmub_bo; 394 395 /** 396 * @dmub_bo_gpu_addr: 397 * 398 * GPU virtual address for the DMUB buffer object. 399 */ 400 u64 dmub_bo_gpu_addr; 401 402 /** 403 * @dmub_bo_cpu_addr: 404 * 405 * CPU address for the DMUB buffer object. 406 */ 407 void *dmub_bo_cpu_addr; 408 409 /** 410 * @dmcub_fw_version: 411 * 412 * DMCUB firmware version. 413 */ 414 uint32_t dmcub_fw_version; 415 416 /** 417 * @cgs_device: 418 * 419 * The Common Graphics Services device. It provides an interface for 420 * accessing registers. 421 */ 422 struct cgs_device *cgs_device; 423 424 struct amdgpu_device *adev; 425 struct drm_device *ddev; 426 u16 display_indexes_num; 427 428 /** 429 * @atomic_obj: 430 * 431 * In combination with &dm_atomic_state it helps manage 432 * global atomic state that doesn't map cleanly into existing 433 * drm resources, like &dc_context. 434 */ 435 struct drm_private_obj atomic_obj; 436 437 /** 438 * @dc_lock: 439 * 440 * Guards access to DC functions that can issue register write 441 * sequences. 442 */ 443 struct mutex dc_lock; 444 445 /** 446 * @audio_lock: 447 * 448 * Guards access to audio instance changes. 449 */ 450 struct mutex audio_lock; 451 452 /** 453 * @audio_component: 454 * 455 * Used to notify ELD changes to sound driver. 456 */ 457 struct drm_audio_component *audio_component; 458 459 /** 460 * @audio_registered: 461 * 462 * True if the audio component has been registered 463 * successfully, false otherwise. 464 */ 465 bool audio_registered; 466 467 /** 468 * @irq_handler_list_low_tab: 469 * 470 * Low priority IRQ handler table. 471 * 472 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 473 * source. Low priority IRQ handlers are deferred to a workqueue to be 474 * processed. Hence, they can sleep. 475 * 476 * Note that handlers are called in the same order as they were 477 * registered (FIFO). 478 */ 479 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 480 481 /** 482 * @irq_handler_list_high_tab: 483 * 484 * High priority IRQ handler table. 485 * 486 * It is a n*m table, same as &irq_handler_list_low_tab. However, 487 * handlers in this table are not deferred and are called immediately. 488 */ 489 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 490 491 /** 492 * @pflip_params: 493 * 494 * Page flip IRQ parameters, passed to registered handlers when 495 * triggered. 496 */ 497 struct common_irq_params 498 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 499 500 /** 501 * @vblank_params: 502 * 503 * Vertical blanking IRQ parameters, passed to registered handlers when 504 * triggered. 505 */ 506 struct common_irq_params 507 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 508 509 /** 510 * @vline0_params: 511 * 512 * OTG vertical interrupt0 IRQ parameters, passed to registered 513 * handlers when triggered. 514 */ 515 struct common_irq_params 516 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 517 518 /** 519 * @vupdate_params: 520 * 521 * Vertical update IRQ parameters, passed to registered handlers when 522 * triggered. 523 */ 524 struct common_irq_params 525 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 526 527 /** 528 * @dmub_trace_params: 529 * 530 * DMUB trace event IRQ parameters, passed to registered handlers when 531 * triggered. 532 */ 533 struct common_irq_params 534 dmub_trace_params[1]; 535 536 struct common_irq_params 537 dmub_outbox_params[1]; 538 539 spinlock_t irq_handler_list_table_lock; 540 541 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 542 543 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 544 545 uint8_t num_of_edps; 546 547 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 548 549 struct mod_freesync *freesync_module; 550 struct hdcp_workqueue *hdcp_workqueue; 551 552 /** 553 * @vblank_control_workqueue: 554 * 555 * Deferred work for vblank control events. 556 */ 557 struct workqueue_struct *vblank_control_workqueue; 558 559 /** 560 * @idle_workqueue: 561 * 562 * Periodic work for idle events. 563 */ 564 struct idle_workqueue *idle_workqueue; 565 566 struct drm_atomic_state *cached_state; 567 struct dc_state *cached_dc_state; 568 569 struct dm_compressor_info compressor; 570 571 const struct firmware *fw_dmcu; 572 uint32_t dmcu_fw_version; 573 /** 574 * @soc_bounding_box: 575 * 576 * gpu_info FW provided soc bounding box struct or 0 if not 577 * available in FW 578 */ 579 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 580 581 /** 582 * @active_vblank_irq_count: 583 * 584 * number of currently active vblank irqs 585 */ 586 uint32_t active_vblank_irq_count; 587 588 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 589 /** 590 * @secure_display_ctx: 591 * 592 * Store secure display relevant info. e.g. the ROI information 593 * , the work_struct to command dmub, etc. 594 */ 595 struct secure_display_context secure_display_ctx; 596 #endif 597 /** 598 * @hpd_rx_offload_wq: 599 * 600 * Work queue to offload works of hpd_rx_irq 601 */ 602 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 603 /** 604 * @mst_encoders: 605 * 606 * fake encoders used for DP MST. 607 */ 608 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 609 bool force_timing_sync; 610 bool disable_hpd_irq; 611 bool dmcub_trace_event_en; 612 /** 613 * @da_list: 614 * 615 * DAL fb memory allocation list, for communication with SMU. 616 */ 617 struct list_head da_list; 618 struct completion dmub_aux_transfer_done; 619 struct workqueue_struct *delayed_hpd_wq; 620 621 /** 622 * @brightness: 623 * 624 * cached backlight values. 625 */ 626 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 627 /** 628 * @actual_brightness: 629 * 630 * last successfully applied backlight values. 631 */ 632 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 633 634 /** 635 * @aux_hpd_discon_quirk: 636 * 637 * quirk for hpd discon while aux is on-going. 638 * occurred on certain intel platform 639 */ 640 bool aux_hpd_discon_quirk; 641 642 /** 643 * @edp0_on_dp1_quirk: 644 * 645 * quirk for platforms that put edp0 on DP1. 646 */ 647 bool edp0_on_dp1_quirk; 648 649 /** 650 * @dpia_aux_lock: 651 * 652 * Guards access to DPIA AUX 653 */ 654 struct mutex dpia_aux_lock; 655 656 /** 657 * @bb_from_dmub: 658 * 659 * Bounding box data read from dmub during early initialization for DCN4+ 660 * Data is stored as a byte array that should be casted to the appropriate bb struct 661 */ 662 void *bb_from_dmub; 663 664 /** 665 * @oem_i2c: 666 * 667 * OEM i2c bus 668 */ 669 struct amdgpu_i2c_adapter *oem_i2c; 670 671 /** 672 * @fused_io: 673 * 674 * dmub fused io interface 675 */ 676 struct fused_io_sync { 677 struct completion replied; 678 char reply_data[0x40]; // Cannot include dmub_cmd here 679 } fused_io[8]; 680 }; 681 682 enum dsc_clock_force_state { 683 DSC_CLK_FORCE_DEFAULT = 0, 684 DSC_CLK_FORCE_ENABLE, 685 DSC_CLK_FORCE_DISABLE, 686 }; 687 688 struct dsc_preferred_settings { 689 enum dsc_clock_force_state dsc_force_enable; 690 uint32_t dsc_num_slices_v; 691 uint32_t dsc_num_slices_h; 692 uint32_t dsc_bits_per_pixel; 693 bool dsc_force_disable_passthrough; 694 }; 695 696 enum mst_progress_status { 697 MST_STATUS_DEFAULT = 0, 698 MST_PROBE = BIT(0), 699 MST_REMOTE_EDID = BIT(1), 700 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 701 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 702 }; 703 704 /** 705 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 706 * 707 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 708 * struct is useful to keep track of the display-specific information about 709 * FreeSync. 710 */ 711 struct amdgpu_hdmi_vsdb_info { 712 /** 713 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 714 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 715 */ 716 unsigned int amd_vsdb_version; 717 718 /** 719 * @freesync_supported: FreeSync Supported. 720 */ 721 bool freesync_supported; 722 723 /** 724 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 725 */ 726 unsigned int min_refresh_rate_hz; 727 728 /** 729 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 730 */ 731 unsigned int max_refresh_rate_hz; 732 733 /** 734 * @replay_mode: Replay supported 735 */ 736 bool replay_mode; 737 }; 738 739 struct amdgpu_dm_connector { 740 741 struct drm_connector base; 742 uint32_t connector_id; 743 int bl_idx; 744 745 struct cec_notifier *notifier; 746 747 /* we need to mind the EDID between detect 748 and get modes due to analog/digital/tvencoder */ 749 const struct drm_edid *drm_edid; 750 751 /* shared with amdgpu */ 752 struct amdgpu_hpd hpd; 753 754 /* number of modes generated from EDID at 'dc_sink' */ 755 int num_modes; 756 757 /* The 'old' sink - before an HPD. 758 * The 'current' sink is in dc_link->sink. */ 759 struct dc_sink *dc_sink; 760 struct dc_link *dc_link; 761 762 /** 763 * @dc_em_sink: Reference to the emulated (virtual) sink. 764 */ 765 struct dc_sink *dc_em_sink; 766 767 /* DM only */ 768 struct drm_dp_mst_topology_mgr mst_mgr; 769 struct amdgpu_dm_dp_aux dm_dp_aux; 770 struct drm_dp_mst_port *mst_output_port; 771 struct amdgpu_dm_connector *mst_root; 772 struct drm_dp_aux *dsc_aux; 773 uint32_t mst_local_bw; 774 uint16_t vc_full_pbn; 775 struct mutex handle_mst_msg_ready; 776 777 /* branch device specific data */ 778 uint32_t branch_ieee_oui; 779 780 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 781 struct amdgpu_i2c_adapter *i2c; 782 783 /* Monitor range limits */ 784 /** 785 * @min_vfreq: Minimal frequency supported by the display in Hz. This 786 * value is set to zero when there is no FreeSync support. 787 */ 788 int min_vfreq; 789 790 /** 791 * @max_vfreq: Maximum frequency supported by the display in Hz. This 792 * value is set to zero when there is no FreeSync support. 793 */ 794 int max_vfreq ; 795 796 /* Audio instance - protected by audio_lock. */ 797 int audio_inst; 798 799 struct mutex hpd_lock; 800 801 bool fake_enable; 802 bool force_yuv420_output; 803 bool force_yuv422_output; 804 struct dsc_preferred_settings dsc_settings; 805 union dp_downstream_port_present mst_downstream_port_present; 806 /* Cached display modes */ 807 struct drm_display_mode freesync_vid_base; 808 809 int sr_skip_count; 810 bool disallow_edp_enter_psr; 811 812 /* Record progress status of mst*/ 813 uint8_t mst_status; 814 815 /* Automated testing */ 816 bool timing_changed; 817 struct dc_crtc_timing *timing_requested; 818 819 /* Adaptive Sync */ 820 bool pack_sdp_v1_3; 821 enum adaptive_sync_type as_type; 822 struct amdgpu_hdmi_vsdb_info vsdb_info; 823 824 /* HDMI HPD debounce support */ 825 unsigned int hdmi_hpd_debounce_delay_ms; 826 struct delayed_work hdmi_hpd_debounce_work; 827 struct dc_sink *hdmi_prev_sink; 828 }; 829 830 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 831 uint8_t flags, bool set) 832 { 833 if (set) 834 *status |= flags; 835 else 836 *status &= ~flags; 837 } 838 839 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 840 841 struct amdgpu_dm_wb_connector { 842 struct drm_writeback_connector base; 843 struct dc_link *link; 844 }; 845 846 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 847 848 extern const struct amdgpu_ip_block_version dm_ip_block; 849 850 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 851 * 852 * It includes standardized transfer functions and pure power functions. The 853 * transfer function coefficients are available at modules/color/color_gamma.c 854 */ 855 enum amdgpu_transfer_function { 856 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 857 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 858 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 859 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 860 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 861 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 862 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 863 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 864 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 865 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 866 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 867 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 868 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 869 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 870 AMDGPU_TRANSFER_FUNCTION_COUNT 871 }; 872 873 struct dm_plane_state { 874 struct drm_plane_state base; 875 struct dc_plane_state *dc_state; 876 877 /* Plane color mgmt */ 878 /** 879 * @degamma_lut: 880 * 881 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 882 * blending operations. It's usually applied to linearize input space. 883 * The blob (if not NULL) is an array of &struct drm_color_lut. 884 */ 885 struct drm_property_blob *degamma_lut; 886 /** 887 * @degamma_tf: 888 * 889 * Predefined transfer function to tell DC driver the input space to 890 * linearize. 891 */ 892 enum amdgpu_transfer_function degamma_tf; 893 /** 894 * @hdr_mult: 895 * 896 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 897 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 898 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 899 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 900 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 901 * S31.32 sign-magnitude. 902 * 903 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 904 * TF is needed for any subsequent linear-to-non-linear transforms. 905 */ 906 __u64 hdr_mult; 907 /** 908 * @ctm: 909 * 910 * Color transformation matrix. The blob (if not NULL) is a &struct 911 * drm_color_ctm_3x4. 912 */ 913 struct drm_property_blob *ctm; 914 /** 915 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 916 * array of &struct drm_color_lut. 917 */ 918 struct drm_property_blob *shaper_lut; 919 /** 920 * @shaper_tf: 921 * 922 * Predefined transfer function to delinearize color space. 923 */ 924 enum amdgpu_transfer_function shaper_tf; 925 /** 926 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 927 * &struct drm_color_lut. 928 */ 929 struct drm_property_blob *lut3d; 930 /** 931 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 932 * array of &struct drm_color_lut. 933 */ 934 struct drm_property_blob *blend_lut; 935 /** 936 * @blend_tf: 937 * 938 * Pre-defined transfer function for converting plane pixel data before 939 * applying blend LUT. 940 */ 941 enum amdgpu_transfer_function blend_tf; 942 }; 943 944 enum amdgpu_dm_cursor_mode { 945 DM_CURSOR_NATIVE_MODE = 0, 946 DM_CURSOR_OVERLAY_MODE, 947 }; 948 949 struct dm_crtc_state { 950 struct drm_crtc_state base; 951 struct dc_stream_state *stream; 952 953 bool cm_has_degamma; 954 bool cm_is_degamma_srgb; 955 956 bool mpo_requested; 957 958 int update_type; 959 int active_planes; 960 961 int crc_skip_count; 962 963 bool freesync_vrr_info_changed; 964 965 bool dsc_force_changed; 966 bool vrr_supported; 967 struct mod_freesync_config freesync_config; 968 struct dc_info_packet vrr_infopacket; 969 970 int abm_level; 971 972 /** 973 * @regamma_tf: 974 * 975 * Pre-defined transfer function for converting internal FB -> wire 976 * encoding. 977 */ 978 enum amdgpu_transfer_function regamma_tf; 979 980 enum amdgpu_dm_cursor_mode cursor_mode; 981 }; 982 983 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 984 985 struct dm_atomic_state { 986 struct drm_private_state base; 987 988 struct dc_state *context; 989 }; 990 991 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 992 993 struct dm_connector_state { 994 struct drm_connector_state base; 995 996 enum amdgpu_rmx_type scaling; 997 uint8_t underscan_vborder; 998 uint8_t underscan_hborder; 999 bool underscan_enable; 1000 bool freesync_capable; 1001 bool update_hdcp; 1002 uint8_t abm_level; 1003 int vcpi_slots; 1004 uint64_t pbn; 1005 }; 1006 1007 #define to_dm_connector_state(x)\ 1008 container_of((x), struct dm_connector_state, base) 1009 1010 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1011 struct drm_connector_state * 1012 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1013 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1014 struct drm_connector_state *state, 1015 struct drm_property *property, 1016 uint64_t val); 1017 1018 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1019 const struct drm_connector_state *state, 1020 struct drm_property *property, 1021 uint64_t *val); 1022 1023 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1024 1025 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1026 struct amdgpu_dm_connector *aconnector, 1027 int connector_type, 1028 struct dc_link *link, 1029 int link_index); 1030 1031 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1032 const struct drm_display_mode *mode); 1033 1034 void dm_restore_drm_connector_state(struct drm_device *dev, 1035 struct drm_connector *connector); 1036 1037 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1038 const struct drm_edid *drm_edid); 1039 1040 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1041 1042 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1043 #define MAX_COLOR_3DLUT_SIZE 17 1044 #define MAX_COLOR_3DLUT_BITDEPTH 12 1045 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1046 struct drm_plane_state *plane_state); 1047 /* 1D LUT size */ 1048 #define MAX_COLOR_LUT_ENTRIES 4096 1049 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1050 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1051 1052 void amdgpu_dm_init_color_mod(void); 1053 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1054 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1055 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1056 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1057 bool check_only); 1058 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1059 struct drm_plane_state *plane_state, 1060 struct dc_plane_state *dc_plane_state); 1061 1062 void amdgpu_dm_update_connector_after_detect( 1063 struct amdgpu_dm_connector *aconnector); 1064 1065 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1066 1067 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1068 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1069 1070 bool amdgpu_dm_execute_fused_io( 1071 struct amdgpu_device *dev, 1072 struct dc_link *link, 1073 union dmub_rb_cmd *commands, 1074 uint8_t count, 1075 uint32_t timeout_us 1076 ); 1077 1078 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1079 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1080 1081 struct dc_stream_state * 1082 create_validate_stream_for_sink(struct drm_connector *connector, 1083 const struct drm_display_mode *drm_mode, 1084 const struct dm_connector_state *dm_state, 1085 const struct dc_stream_state *old_stream); 1086 1087 int dm_atomic_get_state(struct drm_atomic_state *state, 1088 struct dm_atomic_state **dm_state); 1089 1090 struct drm_connector * 1091 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1092 struct drm_crtc *crtc); 1093 1094 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1095 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1096 1097 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1098 enum dc_gpu_mem_alloc_type type, 1099 size_t size, 1100 long long *addr); 1101 void dm_free_gpu_mem(struct amdgpu_device *adev, 1102 enum dc_gpu_mem_alloc_type type, 1103 void *addr); 1104 1105 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1106 1107 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1108 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1109 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1110 1111 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1112 1113 #endif /* __AMDGPU_DM_H__ */ 1114