1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_CRTC 6 49 50 #define AMDGPU_DM_MAX_NUM_EDP 2 51 52 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 53 54 enum amd_vsdb_panel_type { 55 AMD_VSDB_PANEL_TYPE_DEFAULT = 0, 56 AMD_VSDB_PANEL_TYPE_MINILED, 57 AMD_VSDB_PANEL_TYPE_OLED, 58 AMD_VSDB_PANEL_TYPE_RESERVED, 59 }; 60 61 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 62 63 /* 64 * Maximum HDMI HPD debounce delay in milliseconds 65 */ 66 #define AMDGPU_DM_MAX_HDMI_HPD_DEBOUNCE_MS 5000 67 /* 68 #include "include/amdgpu_dal_power_if.h" 69 #include "amdgpu_dm_irq.h" 70 */ 71 72 #include "irq_types.h" 73 #include "signal_types.h" 74 #include "amdgpu_dm_crc.h" 75 #include "mod_info_packet.h" 76 struct aux_payload; 77 struct set_config_cmd_payload; 78 enum aux_return_code_type; 79 enum set_config_status; 80 81 /* Forward declarations */ 82 struct amdgpu_device; 83 struct amdgpu_crtc; 84 struct drm_device; 85 struct dc; 86 struct amdgpu_bo; 87 struct dmub_srv; 88 struct dc_plane_state; 89 struct dmub_notification; 90 struct dmub_cmd_fused_request; 91 92 struct common_irq_params { 93 struct amdgpu_device *adev; 94 enum dc_irq_source irq_src; 95 atomic64_t previous_timestamp; 96 }; 97 98 /** 99 * struct dm_compressor_info - Buffer info used by frame buffer compression 100 * @cpu_addr: MMIO cpu addr 101 * @bo_ptr: Pointer to the buffer object 102 * @gpu_addr: MMIO gpu addr 103 */ 104 struct dm_compressor_info { 105 void *cpu_addr; 106 struct amdgpu_bo *bo_ptr; 107 uint64_t gpu_addr; 108 }; 109 110 /** 111 * struct dm_boot_time_crc_info - Buffer info used by boot time CRC 112 * @cpu_addr: MMIO cpu addr 113 * @bo_ptr: Pointer to the buffer object 114 * @gpu_addr: MMIO gpu addr 115 * @size: Size of the buffer 116 */ 117 struct dm_boot_time_crc_info { 118 void *cpu_addr; 119 struct amdgpu_bo *bo_ptr; 120 uint64_t gpu_addr; 121 uint32_t size; 122 }; 123 124 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 125 126 /** 127 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 128 * 129 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 130 * @dmub_notify: notification for callback function 131 * @adev: amdgpu_device pointer 132 */ 133 struct dmub_hpd_work { 134 struct work_struct handle_hpd_work; 135 struct dmub_notification *dmub_notify; 136 struct amdgpu_device *adev; 137 }; 138 139 /** 140 * struct vblank_control_work - Work data for vblank control 141 * @work: Kernel work data for the work event 142 * @dm: amdgpu display manager device 143 * @acrtc: amdgpu CRTC instance for which the event has occurred 144 * @stream: DC stream for which the event has occurred 145 * @enable: true if enabling vblank 146 */ 147 struct vblank_control_work { 148 struct work_struct work; 149 struct amdgpu_display_manager *dm; 150 struct amdgpu_crtc *acrtc; 151 struct dc_stream_state *stream; 152 bool enable; 153 }; 154 155 /** 156 * struct idle_workqueue - Work data for periodic action in idle 157 * @work: Kernel work data for the work event 158 * @dm: amdgpu display manager device 159 * @enable: true if idle worker is enabled 160 * @running: true if idle worker is running 161 */ 162 struct idle_workqueue { 163 struct work_struct work; 164 struct amdgpu_display_manager *dm; 165 bool enable; 166 bool running; 167 }; 168 169 /** 170 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 171 * @work: Kernel work data for the work event 172 * @adev: amdgpu_device back pointer 173 * @stream: DC stream associated with the crtc 174 * @adjust: DC CRTC timing adjust to be applied to the crtc 175 */ 176 struct vupdate_offload_work { 177 struct work_struct work; 178 struct amdgpu_device *adev; 179 struct dc_stream_state *stream; 180 struct dc_crtc_timing_adjust *adjust; 181 }; 182 183 #define MAX_LUMINANCE_DATA_POINTS 99 184 185 /** 186 * struct amdgpu_dm_luminance_data - Custom luminance data 187 * @luminance: Luminance in percent 188 * @input_signal: Input signal in range 0-255 189 */ 190 struct amdgpu_dm_luminance_data { 191 u8 luminance; 192 u8 input_signal; 193 } __packed; 194 195 /** 196 * struct amdgpu_dm_backlight_caps - Information about backlight 197 * 198 * Describe the backlight support for ACPI or eDP AUX. 199 */ 200 struct amdgpu_dm_backlight_caps { 201 /** 202 * @ext_caps: Keep the data struct with all the information about the 203 * display support for HDR. 204 */ 205 union dpcd_sink_ext_caps *ext_caps; 206 /** 207 * @aux_min_input_signal: Min brightness value supported by the display 208 */ 209 u32 aux_min_input_signal; 210 /** 211 * @aux_max_input_signal: Max brightness value supported by the display 212 * in nits. 213 */ 214 u32 aux_max_input_signal; 215 /** 216 * @min_input_signal: minimum possible input in range 0-255. 217 */ 218 int min_input_signal; 219 /** 220 * @max_input_signal: maximum possible input in range 0-255. 221 */ 222 int max_input_signal; 223 /** 224 * @caps_valid: true if these values are from the ACPI interface. 225 */ 226 bool caps_valid; 227 /** 228 * @aux_support: Describes if the display supports AUX backlight. 229 */ 230 bool aux_support; 231 /** 232 * @brightness_mask: After deriving brightness, OR it with this mask. 233 * Workaround for panels with issues with certain brightness values. 234 */ 235 u32 brightness_mask; 236 /** 237 * @ac_level: the default brightness if booted on AC 238 */ 239 u8 ac_level; 240 /** 241 * @dc_level: the default brightness if booted on DC 242 */ 243 u8 dc_level; 244 /** 245 * @data_points: the number of custom luminance data points 246 */ 247 u8 data_points; 248 /** 249 * @luminance_data: custom luminance data 250 */ 251 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 252 }; 253 254 /** 255 * struct dal_allocation - Tracks mapped FB memory for SMU communication 256 * @list: list of dal allocations 257 * @bo: GPU buffer object 258 * @cpu_ptr: CPU virtual address of the GPU buffer object 259 * @gpu_addr: GPU virtual address of the GPU buffer object 260 */ 261 struct dal_allocation { 262 struct list_head list; 263 struct amdgpu_bo *bo; 264 void *cpu_ptr; 265 u64 gpu_addr; 266 }; 267 268 /** 269 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 270 * offload work 271 */ 272 struct hpd_rx_irq_offload_work_queue { 273 /** 274 * @wq: workqueue structure to queue offload work. 275 */ 276 struct workqueue_struct *wq; 277 /** 278 * @offload_lock: To protect fields of offload work queue. 279 */ 280 spinlock_t offload_lock; 281 /** 282 * @is_handling_link_loss: Used to prevent inserting link loss event when 283 * we're handling link loss 284 */ 285 bool is_handling_link_loss; 286 /** 287 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 288 * ready event when we're already handling mst message ready event 289 */ 290 bool is_handling_mst_msg_rdy_event; 291 /** 292 * @aconnector: The aconnector that this work queue is attached to 293 */ 294 struct amdgpu_dm_connector *aconnector; 295 }; 296 297 /** 298 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 299 */ 300 struct hpd_rx_irq_offload_work { 301 /** 302 * @work: offload work 303 */ 304 struct work_struct work; 305 /** 306 * @data: reference irq data which is used while handling offload work 307 */ 308 union hpd_irq_data data; 309 /** 310 * @offload_wq: offload work queue that this work is queued to 311 */ 312 struct hpd_rx_irq_offload_work_queue *offload_wq; 313 /** 314 * @adev: amdgpu_device pointer 315 */ 316 struct amdgpu_device *adev; 317 }; 318 319 /** 320 * struct amdgpu_display_manager - Central amdgpu display manager device 321 * 322 * @dc: Display Core control structure 323 * @adev: AMDGPU base driver structure 324 * @ddev: DRM base driver structure 325 * @display_indexes_num: Max number of display streams supported 326 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 327 * @backlight_dev: Backlight control device 328 * @backlight_link: Link on which to control backlight 329 * @backlight_caps: Capabilities of the backlight device 330 * @freesync_module: Module handling freesync calculations 331 * @hdcp_workqueue: AMDGPU content protection queue 332 * @fw_dmcu: Reference to DMCU firmware 333 * @dmcu_fw_version: Version of the DMCU firmware 334 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 335 * @cached_state: Caches device atomic state for suspend/resume 336 * @cached_dc_state: Cached state of content streams 337 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 338 * @force_timing_sync: set via debugfs. When set, indicates that all connected 339 * displays will be forced to synchronize. 340 * @dmcub_trace_event_en: enable dmcub trace events 341 * @dmub_outbox_params: DMUB Outbox parameters 342 * @num_of_edps: number of backlight eDPs 343 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 344 * driver when true 345 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 346 * transfers are done 347 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 348 */ 349 struct amdgpu_display_manager { 350 351 struct dc *dc; 352 353 /** 354 * @dmub_srv: 355 * 356 * DMUB service, used for controlling the DMUB on hardware 357 * that supports it. The pointer to the dmub_srv will be 358 * NULL on hardware that does not support it. 359 */ 360 struct dmub_srv *dmub_srv; 361 362 /** 363 * @dmub_notify: 364 * 365 * Notification from DMUB. 366 */ 367 368 struct dmub_notification *dmub_notify; 369 370 /** 371 * @dmub_callback: 372 * 373 * Callback functions to handle notification from DMUB. 374 */ 375 376 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 377 378 /** 379 * @dmub_thread_offload: 380 * 381 * Flag to indicate if callback is offload. 382 */ 383 384 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 385 386 /** 387 * @dmub_fb_info: 388 * 389 * Framebuffer regions for the DMUB. 390 */ 391 struct dmub_srv_fb_info *dmub_fb_info; 392 393 /** 394 * @dmub_fw: 395 * 396 * DMUB firmware, required on hardware that has DMUB support. 397 */ 398 const struct firmware *dmub_fw; 399 400 /** 401 * @dmub_bo: 402 * 403 * Buffer object for the DMUB. 404 */ 405 struct amdgpu_bo *dmub_bo; 406 407 /** 408 * @dmub_bo_gpu_addr: 409 * 410 * GPU virtual address for the DMUB buffer object. 411 */ 412 u64 dmub_bo_gpu_addr; 413 414 /** 415 * @dmub_bo_cpu_addr: 416 * 417 * CPU address for the DMUB buffer object. 418 */ 419 void *dmub_bo_cpu_addr; 420 421 /** 422 * @dmcub_fw_version: 423 * 424 * DMCUB firmware version. 425 */ 426 uint32_t dmcub_fw_version; 427 428 /** 429 * @fw_inst_size: 430 * 431 * Size of the firmware instruction buffer. 432 */ 433 uint32_t fw_inst_size; 434 435 /** 436 * @cgs_device: 437 * 438 * The Common Graphics Services device. It provides an interface for 439 * accessing registers. 440 */ 441 struct cgs_device *cgs_device; 442 443 struct amdgpu_device *adev; 444 struct drm_device *ddev; 445 u16 display_indexes_num; 446 447 /** 448 * @atomic_obj: 449 * 450 * In combination with &dm_atomic_state it helps manage 451 * global atomic state that doesn't map cleanly into existing 452 * drm resources, like &dc_context. 453 */ 454 struct drm_private_obj atomic_obj; 455 456 /** 457 * @dc_lock: 458 * 459 * Guards access to DC functions that can issue register write 460 * sequences. 461 */ 462 struct mutex dc_lock; 463 464 /** 465 * @dmub_lock: 466 * 467 * Guards access to DMUB command submission. 468 */ 469 spinlock_t dmub_lock; 470 471 /** 472 * @audio_lock: 473 * 474 * Guards access to audio instance changes. 475 */ 476 struct mutex audio_lock; 477 478 /** 479 * @audio_component: 480 * 481 * Used to notify ELD changes to sound driver. 482 */ 483 struct drm_audio_component *audio_component; 484 485 /** 486 * @audio_registered: 487 * 488 * True if the audio component has been registered 489 * successfully, false otherwise. 490 */ 491 bool audio_registered; 492 493 /** 494 * @irq_handler_list_low_tab: 495 * 496 * Low priority IRQ handler table. 497 * 498 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 499 * source. Low priority IRQ handlers are deferred to a workqueue to be 500 * processed. Hence, they can sleep. 501 * 502 * Note that handlers are called in the same order as they were 503 * registered (FIFO). 504 */ 505 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 506 507 /** 508 * @irq_handler_list_high_tab: 509 * 510 * High priority IRQ handler table. 511 * 512 * It is a n*m table, same as &irq_handler_list_low_tab. However, 513 * handlers in this table are not deferred and are called immediately. 514 */ 515 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 516 517 /** 518 * @pflip_params: 519 * 520 * Page flip IRQ parameters, passed to registered handlers when 521 * triggered. 522 */ 523 struct common_irq_params 524 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 525 526 /** 527 * @vblank_params: 528 * 529 * Vertical blanking IRQ parameters, passed to registered handlers when 530 * triggered. 531 */ 532 struct common_irq_params 533 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 534 535 /** 536 * @vline0_params: 537 * 538 * OTG vertical interrupt0 IRQ parameters, passed to registered 539 * handlers when triggered. 540 */ 541 struct common_irq_params 542 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 543 544 /** 545 * @vupdate_params: 546 * 547 * Vertical update IRQ parameters, passed to registered handlers when 548 * triggered. 549 */ 550 struct common_irq_params 551 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 552 553 /** 554 * @dmub_trace_params: 555 * 556 * DMUB trace event IRQ parameters, passed to registered handlers when 557 * triggered. 558 */ 559 struct common_irq_params 560 dmub_trace_params[1]; 561 562 struct common_irq_params 563 dmub_outbox_params[1]; 564 565 spinlock_t irq_handler_list_table_lock; 566 567 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 568 569 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 570 571 uint8_t num_of_edps; 572 573 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 574 575 struct mod_freesync *freesync_module; 576 struct mod_power *power_module; 577 struct hdcp_workqueue *hdcp_workqueue; 578 579 /** 580 * @vblank_control_workqueue: 581 * 582 * Deferred work for vblank control events. 583 */ 584 struct workqueue_struct *vblank_control_workqueue; 585 586 /** 587 * @idle_workqueue: 588 * 589 * Periodic work for idle events. 590 */ 591 struct idle_workqueue *idle_workqueue; 592 593 struct drm_atomic_commit *cached_state; 594 struct dc_state *cached_dc_state; 595 596 struct dm_compressor_info compressor; 597 598 const struct firmware *fw_dmcu; 599 uint32_t dmcu_fw_version; 600 /** 601 * @soc_bounding_box: 602 * 603 * gpu_info FW provided soc bounding box struct or 0 if not 604 * available in FW 605 */ 606 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 607 608 /** 609 * @active_vblank_irq_count: 610 * 611 * number of currently active vblank irqs 612 */ 613 uint32_t active_vblank_irq_count; 614 615 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 616 /** 617 * @secure_display_ctx: 618 * 619 * Store secure display relevant info. e.g. the ROI information 620 * , the work_struct to command dmub, etc. 621 */ 622 struct secure_display_context secure_display_ctx; 623 #endif 624 /** 625 * @hpd_rx_offload_wq: 626 * 627 * Work queue to offload works of hpd_rx_irq 628 */ 629 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 630 /** 631 * @mst_encoders: 632 * 633 * fake encoders used for DP MST. 634 */ 635 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 636 bool force_timing_sync; 637 bool disable_hpd_irq; 638 bool dmcub_trace_event_en; 639 /** 640 * @da_list: 641 * 642 * DAL fb memory allocation list, for communication with SMU. 643 */ 644 struct list_head da_list; 645 struct completion dmub_aux_transfer_done; 646 struct workqueue_struct *delayed_hpd_wq; 647 648 /** 649 * @brightness: 650 * 651 * cached backlight values. 652 */ 653 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 654 /** 655 * @actual_brightness: 656 * 657 * last successfully applied backlight values. 658 */ 659 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 660 661 /** 662 * @aux_hpd_discon_quirk: 663 * 664 * quirk for hpd discon while aux is on-going. 665 * occurred on certain intel platform 666 */ 667 bool aux_hpd_discon_quirk; 668 669 /** 670 * @edp0_on_dp1_quirk: 671 * 672 * quirk for platforms that put edp0 on DP1. 673 */ 674 bool edp0_on_dp1_quirk; 675 676 /** 677 * @dpia_aux_lock: 678 * 679 * Guards access to DPIA AUX 680 */ 681 struct mutex dpia_aux_lock; 682 683 /** 684 * @bb_from_dmub: 685 * 686 * Bounding box data read from dmub during early initialization for DCN4+ 687 * Data is stored as a byte array that should be casted to the appropriate bb struct 688 */ 689 void *bb_from_dmub; 690 691 /** 692 * @i2c_devres_group: 693 * 694 * Devres group for DM i2c adapter lifetime management. 695 */ 696 void *i2c_devres_group; 697 698 /** 699 * @oem_i2c: 700 * 701 * OEM i2c bus 702 */ 703 struct amdgpu_i2c_adapter *oem_i2c; 704 705 /** 706 * @fused_io: 707 * 708 * dmub fused io interface 709 */ 710 struct fused_io_sync { 711 struct completion replied; 712 char reply_data[0x40]; // Cannot include dmub_cmd here 713 } fused_io[8]; 714 /** 715 * @hdmi_frl_status_polling_work: 716 * 717 * workqueue for 200ms frl status polling 718 */ 719 struct workqueue_struct *hdmi_frl_status_polling_wq; 720 struct delayed_work hdmi_frl_status_polling_work; 721 unsigned int hdmi_frl_status_polling_delay_ms; 722 723 /** 724 * @dm_boot_time_crc_info: 725 * 726 * Buffer info for the boot time crc. 727 */ 728 struct dm_boot_time_crc_info boot_time_crc_info; 729 }; 730 731 enum dsc_clock_force_state { 732 DSC_CLK_FORCE_DEFAULT = 0, 733 DSC_CLK_FORCE_ENABLE, 734 DSC_CLK_FORCE_DISABLE, 735 }; 736 737 struct dsc_preferred_settings { 738 enum dsc_clock_force_state dsc_force_enable; 739 uint32_t dsc_num_slices_v; 740 uint32_t dsc_num_slices_h; 741 uint32_t dsc_bits_per_pixel; 742 bool dsc_force_disable_passthrough; 743 }; 744 745 enum mst_progress_status { 746 MST_STATUS_DEFAULT = 0, 747 MST_PROBE = BIT(0), 748 MST_REMOTE_EDID = BIT(1), 749 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 750 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 751 }; 752 753 /** 754 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 755 * 756 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 757 * struct is useful to keep track of the display-specific information about 758 * FreeSync. 759 */ 760 struct amdgpu_hdmi_vsdb_info { 761 /** 762 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 763 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 764 */ 765 unsigned int amd_vsdb_version; 766 767 /** 768 * @freesync_supported: FreeSync Supported. 769 */ 770 bool freesync_supported; 771 772 /** 773 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 774 */ 775 unsigned int min_refresh_rate_hz; 776 777 /** 778 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 779 */ 780 unsigned int max_refresh_rate_hz; 781 782 /** 783 * @freesync_mccs_vcp_code: MCCS VCP code for freesync state 784 */ 785 unsigned int freesync_mccs_vcp_code; 786 787 /** 788 * @replay_mode: Replay supported 789 */ 790 bool replay_mode; 791 }; 792 793 struct amdgpu_dm_connector { 794 795 struct drm_connector base; 796 uint32_t connector_id; 797 int bl_idx; 798 799 struct cec_notifier *notifier; 800 801 /* we need to mind the EDID between detect 802 and get modes due to analog/digital/tvencoder */ 803 const struct drm_edid *drm_edid; 804 805 /* shared with amdgpu */ 806 struct amdgpu_hpd hpd; 807 808 /* number of modes generated from EDID at 'dc_sink' */ 809 int num_modes; 810 811 /* The 'old' sink - before an HPD. 812 * The 'current' sink is in dc_link->sink. */ 813 struct dc_sink *dc_sink; 814 struct dc_link *dc_link; 815 816 /** 817 * @dc_em_sink: Reference to the emulated (virtual) sink. 818 */ 819 struct dc_sink *dc_em_sink; 820 821 /* DM only */ 822 struct drm_dp_mst_topology_mgr mst_mgr; 823 struct amdgpu_dm_dp_aux dm_dp_aux; 824 struct drm_dp_mst_port *mst_output_port; 825 struct amdgpu_dm_connector *mst_root; 826 struct drm_dp_aux *dsc_aux; 827 uint32_t mst_local_bw; 828 uint16_t vc_full_pbn; 829 struct mutex handle_mst_msg_ready; 830 831 /* branch device specific data */ 832 uint32_t branch_ieee_oui; 833 834 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 835 struct amdgpu_i2c_adapter *i2c; 836 837 /* Monitor range limits */ 838 /** 839 * @min_vfreq: Minimal frequency supported by the display in Hz. This 840 * value is set to zero when there is no FreeSync support. 841 */ 842 int min_vfreq; 843 844 /** 845 * @max_vfreq: Maximum frequency supported by the display in Hz. This 846 * value is set to zero when there is no FreeSync support. 847 */ 848 int max_vfreq ; 849 850 /* Audio instance - protected by audio_lock. */ 851 int audio_inst; 852 853 struct mutex hpd_lock; 854 855 bool fake_enable; 856 bool force_yuv420_output; 857 bool force_yuv422_output; 858 uint8_t force_yuv_pixel_format; 859 struct dsc_preferred_settings dsc_settings; 860 struct psr_caps psr_caps; 861 union dp_downstream_port_present mst_downstream_port_present; 862 /* Cached display modes */ 863 struct drm_display_mode freesync_vid_base; 864 865 int sr_skip_count; 866 bool disallow_edp_enter_psr; 867 bool disallow_edp_enter_replay; 868 869 union dwnstream_portxcaps mst_downstream_port_caps; 870 871 /* Record progress status of mst*/ 872 uint8_t mst_status; 873 874 /* Automated testing */ 875 bool timing_changed; 876 struct dc_crtc_timing *timing_requested; 877 878 /* Adaptive Sync */ 879 bool pack_sdp_v1_3; 880 enum adaptive_sync_type as_type; 881 struct amdgpu_hdmi_vsdb_info vsdb_info; 882 883 /* HDMI HPD debounce support */ 884 unsigned int hdmi_hpd_debounce_delay_ms; 885 struct delayed_work hdmi_hpd_debounce_work; 886 struct dc_sink *hdmi_prev_sink; 887 888 /* HDMI compliance automation */ 889 bool hdmi_comp_auto; 890 }; 891 892 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 893 uint8_t flags, bool set) 894 { 895 if (set) 896 *status |= flags; 897 else 898 *status &= ~flags; 899 } 900 901 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 902 903 struct amdgpu_dm_wb_connector { 904 struct drm_writeback_connector base; 905 struct dc_link *link; 906 }; 907 908 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 909 910 extern const struct amdgpu_ip_block_version dm_ip_block; 911 912 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 913 * 914 * It includes standardized transfer functions and pure power functions. The 915 * transfer function coefficients are available at modules/color/color_gamma.c 916 */ 917 enum amdgpu_transfer_function { 918 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 919 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 920 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 921 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 922 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 923 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 924 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 925 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 926 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 927 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 928 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 929 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 930 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 931 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 932 AMDGPU_TRANSFER_FUNCTION_COUNT 933 }; 934 935 struct dm_plane_state { 936 struct drm_plane_state base; 937 struct dc_plane_state *dc_state; 938 939 /* Plane color mgmt */ 940 /** 941 * @degamma_lut: 942 * 943 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 944 * blending operations. It's usually applied to linearize input space. 945 * The blob (if not NULL) is an array of &struct drm_color_lut. 946 */ 947 struct drm_property_blob *degamma_lut; 948 /** 949 * @degamma_tf: 950 * 951 * Predefined transfer function to tell DC driver the input space to 952 * linearize. 953 */ 954 enum amdgpu_transfer_function degamma_tf; 955 /** 956 * @hdr_mult: 957 * 958 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 959 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 960 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 961 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 962 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 963 * S31.32 sign-magnitude. 964 * 965 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 966 * TF is needed for any subsequent linear-to-non-linear transforms. 967 */ 968 __u64 hdr_mult; 969 /** 970 * @ctm: 971 * 972 * Color transformation matrix. The blob (if not NULL) is a &struct 973 * drm_color_ctm_3x4. 974 */ 975 struct drm_property_blob *ctm; 976 /** 977 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 978 * array of &struct drm_color_lut. 979 */ 980 struct drm_property_blob *shaper_lut; 981 /** 982 * @shaper_tf: 983 * 984 * Predefined transfer function to delinearize color space. 985 */ 986 enum amdgpu_transfer_function shaper_tf; 987 /** 988 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 989 * &struct drm_color_lut. 990 */ 991 struct drm_property_blob *lut3d; 992 /** 993 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 994 * array of &struct drm_color_lut. 995 */ 996 struct drm_property_blob *blend_lut; 997 /** 998 * @blend_tf: 999 * 1000 * Pre-defined transfer function for converting plane pixel data before 1001 * applying blend LUT. 1002 */ 1003 enum amdgpu_transfer_function blend_tf; 1004 }; 1005 1006 enum amdgpu_dm_cursor_mode { 1007 DM_CURSOR_NATIVE_MODE = 0, 1008 DM_CURSOR_OVERLAY_MODE, 1009 }; 1010 1011 struct dm_crtc_state { 1012 struct drm_crtc_state base; 1013 struct dc_stream_state *stream; 1014 1015 bool cm_has_degamma; 1016 bool cm_is_degamma_srgb; 1017 1018 bool mpo_requested; 1019 1020 int update_type; 1021 int active_planes; 1022 1023 int crc_skip_count; 1024 1025 bool freesync_vrr_info_changed; 1026 1027 bool mode_changed_independent_from_dsc; 1028 bool dsc_force_changed; 1029 bool vrr_supported; 1030 struct mod_freesync_config freesync_config; 1031 struct dc_info_packet vrr_infopacket; 1032 1033 int abm_level; 1034 1035 /** 1036 * @regamma_tf: 1037 * 1038 * Pre-defined transfer function for converting internal FB -> wire 1039 * encoding. 1040 */ 1041 enum amdgpu_transfer_function regamma_tf; 1042 1043 enum amdgpu_dm_cursor_mode cursor_mode; 1044 }; 1045 1046 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 1047 1048 struct dm_atomic_state { 1049 struct drm_private_state base; 1050 1051 struct dc_state *context; 1052 }; 1053 1054 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 1055 1056 struct dm_connector_state { 1057 struct drm_connector_state base; 1058 1059 enum amdgpu_rmx_type scaling; 1060 uint8_t underscan_vborder; 1061 uint8_t underscan_hborder; 1062 bool underscan_enable; 1063 bool freesync_capable; 1064 bool update_hdcp; 1065 bool abm_sysfs_forbidden; 1066 uint8_t abm_level; 1067 int vcpi_slots; 1068 uint64_t pbn; 1069 }; 1070 1071 #define to_dm_connector_state(x)\ 1072 container_of((x), struct dm_connector_state, base) 1073 1074 #include "amdgpu_dm_connector.h" 1075 1076 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1077 1078 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1079 #define MAX_COLOR_3DLUT_SIZE 17 1080 #define MAX_COLOR_3DLUT_BITDEPTH 12 1081 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1082 struct drm_plane_state *plane_state); 1083 /* 1D LUT size */ 1084 #define MAX_COLOR_LUT_ENTRIES 4096 1085 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1086 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1087 1088 void amdgpu_dm_init_color_mod(void); 1089 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1090 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1091 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1092 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1093 bool check_only); 1094 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1095 struct drm_plane_state *plane_state, 1096 struct dc_plane_state *dc_plane_state); 1097 1098 void populate_hdmi_info_from_connector(bool enable_frl, struct drm_hdmi_info *info, 1099 struct dc_edid_caps *edid_caps); 1100 1101 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1102 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1103 1104 bool amdgpu_dm_execute_fused_io( 1105 struct amdgpu_device *dev, 1106 struct dc_link *link, 1107 union dmub_rb_cmd *commands, 1108 uint8_t count, 1109 uint32_t timeout_us 1110 ); 1111 1112 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1113 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1114 1115 int dm_atomic_get_state(struct drm_atomic_commit *state, 1116 struct dm_atomic_state **dm_state); 1117 1118 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1119 1120 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1121 enum dc_gpu_mem_alloc_type type, 1122 size_t size, 1123 long long *addr); 1124 void dm_free_gpu_mem(struct amdgpu_device *adev, 1125 enum dc_gpu_mem_alloc_type type, 1126 void *addr); 1127 1128 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1129 1130 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc); 1131 1132 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1133 1134 void amdgpu_dm_emulated_link_detect(struct dc_link *link); 1135 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1136 struct dc_sink *sink); 1137 1138 #if IS_ENABLED(CONFIG_DRM_AMD_DC_KUNIT_TEST) 1139 int dm_plane_layer_index_cmp(const void *a, const void *b); 1140 int fill_plane_color_attributes(const struct drm_plane_state *plane_state, 1141 const enum surface_pixel_format format, 1142 enum dc_color_space *color_space); 1143 bool modereset_required(struct drm_crtc_state *crtc_state); 1144 void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 1145 int *src_w, int *src_h); 1146 void dm_get_plane_scale(struct drm_plane_state *plane_state, 1147 int *out_plane_scale_w, int *out_plane_scale_h); 1148 bool is_scaling_state_different(const struct dm_connector_state *dm_state, 1149 const struct dm_connector_state *old_dm_state); 1150 bool is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 1151 struct drm_crtc_state *new_crtc_state); 1152 void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state); 1153 bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 1154 struct dm_crtc_state *new_state); 1155 void set_multisync_trigger_params(struct dc_stream_state *stream); 1156 void set_master_stream(struct dc_stream_state *stream_set[], int stream_count); 1157 #endif 1158 1159 #endif /* __AMDGPU_DM_H__ */ 1160