1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __AMDGPU_DM_H__ 28 #define __AMDGPU_DM_H__ 29 30 #include <drm/display/drm_dp_mst_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_plane.h> 35 #include "link_service_types.h" 36 #include <drm/drm_writeback.h> 37 38 /* 39 * This file contains the definition for amdgpu_display_manager 40 * and its API for amdgpu driver's use. 41 * This component provides all the display related functionality 42 * and this is the only component that calls DAL API. 43 * The API contained here intended for amdgpu driver use. 44 * The API that is called directly from KMS framework is located 45 * in amdgpu_dm_kms.h file 46 */ 47 48 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 49 50 #define AMDGPU_DM_MAX_CRTC 6 51 52 #define AMDGPU_DM_MAX_NUM_EDP 2 53 54 #define AMDGPU_DMUB_NOTIFICATION_MAX 8 55 56 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A 57 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 58 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 59 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 62 /* 63 #include "include/amdgpu_dal_power_if.h" 64 #include "amdgpu_dm_irq.h" 65 */ 66 67 #include "irq_types.h" 68 #include "signal_types.h" 69 #include "amdgpu_dm_crc.h" 70 #include "mod_info_packet.h" 71 struct aux_payload; 72 struct set_config_cmd_payload; 73 enum aux_return_code_type; 74 enum set_config_status; 75 76 /* Forward declarations */ 77 struct amdgpu_device; 78 struct amdgpu_crtc; 79 struct drm_device; 80 struct dc; 81 struct amdgpu_bo; 82 struct dmub_srv; 83 struct dc_plane_state; 84 struct dmub_notification; 85 struct dmub_cmd_fused_request; 86 87 struct amd_vsdb_block { 88 unsigned char ieee_id[3]; 89 unsigned char version; 90 unsigned char feature_caps; 91 }; 92 93 struct common_irq_params { 94 struct amdgpu_device *adev; 95 enum dc_irq_source irq_src; 96 atomic64_t previous_timestamp; 97 }; 98 99 /** 100 * struct dm_compressor_info - Buffer info used by frame buffer compression 101 * @cpu_addr: MMIO cpu addr 102 * @bo_ptr: Pointer to the buffer object 103 * @gpu_addr: MMIO gpu addr 104 */ 105 struct dm_compressor_info { 106 void *cpu_addr; 107 struct amdgpu_bo *bo_ptr; 108 uint64_t gpu_addr; 109 }; 110 111 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); 112 113 /** 114 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ 115 * 116 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq 117 * @dmub_notify: notification for callback function 118 * @adev: amdgpu_device pointer 119 */ 120 struct dmub_hpd_work { 121 struct work_struct handle_hpd_work; 122 struct dmub_notification *dmub_notify; 123 struct amdgpu_device *adev; 124 }; 125 126 /** 127 * struct vblank_control_work - Work data for vblank control 128 * @work: Kernel work data for the work event 129 * @dm: amdgpu display manager device 130 * @acrtc: amdgpu CRTC instance for which the event has occurred 131 * @stream: DC stream for which the event has occurred 132 * @enable: true if enabling vblank 133 */ 134 struct vblank_control_work { 135 struct work_struct work; 136 struct amdgpu_display_manager *dm; 137 struct amdgpu_crtc *acrtc; 138 struct dc_stream_state *stream; 139 bool enable; 140 }; 141 142 /** 143 * struct idle_workqueue - Work data for periodic action in idle 144 * @work: Kernel work data for the work event 145 * @dm: amdgpu display manager device 146 * @enable: true if idle worker is enabled 147 * @running: true if idle worker is running 148 */ 149 struct idle_workqueue { 150 struct work_struct work; 151 struct amdgpu_display_manager *dm; 152 bool enable; 153 bool running; 154 }; 155 156 /** 157 * struct vupdate_offload_work - Work data for offloading task from vupdate handler 158 * @work: Kernel work data for the work event 159 * @adev: amdgpu_device back pointer 160 * @stream: DC stream associated with the crtc 161 * @adjust: DC CRTC timing adjust to be applied to the crtc 162 */ 163 struct vupdate_offload_work { 164 struct work_struct work; 165 struct amdgpu_device *adev; 166 struct dc_stream_state *stream; 167 struct dc_crtc_timing_adjust *adjust; 168 }; 169 170 #define MAX_LUMINANCE_DATA_POINTS 99 171 172 /** 173 * struct amdgpu_dm_luminance_data - Custom luminance data 174 * @luminance: Luminance in percent 175 * @input_signal: Input signal in range 0-255 176 */ 177 struct amdgpu_dm_luminance_data { 178 u8 luminance; 179 u8 input_signal; 180 } __packed; 181 182 /** 183 * struct amdgpu_dm_backlight_caps - Information about backlight 184 * 185 * Describe the backlight support for ACPI or eDP AUX. 186 */ 187 struct amdgpu_dm_backlight_caps { 188 /** 189 * @ext_caps: Keep the data struct with all the information about the 190 * display support for HDR. 191 */ 192 union dpcd_sink_ext_caps *ext_caps; 193 /** 194 * @aux_min_input_signal: Min brightness value supported by the display 195 */ 196 u32 aux_min_input_signal; 197 /** 198 * @aux_max_input_signal: Max brightness value supported by the display 199 * in nits. 200 */ 201 u32 aux_max_input_signal; 202 /** 203 * @min_input_signal: minimum possible input in range 0-255. 204 */ 205 int min_input_signal; 206 /** 207 * @max_input_signal: maximum possible input in range 0-255. 208 */ 209 int max_input_signal; 210 /** 211 * @caps_valid: true if these values are from the ACPI interface. 212 */ 213 bool caps_valid; 214 /** 215 * @aux_support: Describes if the display supports AUX backlight. 216 */ 217 bool aux_support; 218 /** 219 * @brightness_mask: After deriving brightness, OR it with this mask. 220 * Workaround for panels with issues with certain brightness values. 221 */ 222 u32 brightness_mask; 223 /** 224 * @ac_level: the default brightness if booted on AC 225 */ 226 u8 ac_level; 227 /** 228 * @dc_level: the default brightness if booted on DC 229 */ 230 u8 dc_level; 231 /** 232 * @data_points: the number of custom luminance data points 233 */ 234 u8 data_points; 235 /** 236 * @luminance_data: custom luminance data 237 */ 238 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS]; 239 }; 240 241 /** 242 * struct dal_allocation - Tracks mapped FB memory for SMU communication 243 * @list: list of dal allocations 244 * @bo: GPU buffer object 245 * @cpu_ptr: CPU virtual address of the GPU buffer object 246 * @gpu_addr: GPU virtual address of the GPU buffer object 247 */ 248 struct dal_allocation { 249 struct list_head list; 250 struct amdgpu_bo *bo; 251 void *cpu_ptr; 252 u64 gpu_addr; 253 }; 254 255 /** 256 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq 257 * offload work 258 */ 259 struct hpd_rx_irq_offload_work_queue { 260 /** 261 * @wq: workqueue structure to queue offload work. 262 */ 263 struct workqueue_struct *wq; 264 /** 265 * @offload_lock: To protect fields of offload work queue. 266 */ 267 spinlock_t offload_lock; 268 /** 269 * @is_handling_link_loss: Used to prevent inserting link loss event when 270 * we're handling link loss 271 */ 272 bool is_handling_link_loss; 273 /** 274 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message 275 * ready event when we're already handling mst message ready event 276 */ 277 bool is_handling_mst_msg_rdy_event; 278 /** 279 * @aconnector: The aconnector that this work queue is attached to 280 */ 281 struct amdgpu_dm_connector *aconnector; 282 }; 283 284 /** 285 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure 286 */ 287 struct hpd_rx_irq_offload_work { 288 /** 289 * @work: offload work 290 */ 291 struct work_struct work; 292 /** 293 * @data: reference irq data which is used while handling offload work 294 */ 295 union hpd_irq_data data; 296 /** 297 * @offload_wq: offload work queue that this work is queued to 298 */ 299 struct hpd_rx_irq_offload_work_queue *offload_wq; 300 /** 301 * @adev: amdgpu_device pointer 302 */ 303 struct amdgpu_device *adev; 304 }; 305 306 /** 307 * struct amdgpu_display_manager - Central amdgpu display manager device 308 * 309 * @dc: Display Core control structure 310 * @adev: AMDGPU base driver structure 311 * @ddev: DRM base driver structure 312 * @display_indexes_num: Max number of display streams supported 313 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 314 * @backlight_dev: Backlight control device 315 * @backlight_link: Link on which to control backlight 316 * @backlight_caps: Capabilities of the backlight device 317 * @freesync_module: Module handling freesync calculations 318 * @hdcp_workqueue: AMDGPU content protection queue 319 * @fw_dmcu: Reference to DMCU firmware 320 * @dmcu_fw_version: Version of the DMCU firmware 321 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 322 * @cached_state: Caches device atomic state for suspend/resume 323 * @cached_dc_state: Cached state of content streams 324 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info 325 * @force_timing_sync: set via debugfs. When set, indicates that all connected 326 * displays will be forced to synchronize. 327 * @dmcub_trace_event_en: enable dmcub trace events 328 * @dmub_outbox_params: DMUB Outbox parameters 329 * @num_of_edps: number of backlight eDPs 330 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the 331 * driver when true 332 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB 333 * transfers are done 334 * @delayed_hpd_wq: work queue used to delay DMUB HPD work 335 */ 336 struct amdgpu_display_manager { 337 338 struct dc *dc; 339 340 /** 341 * @dmub_srv: 342 * 343 * DMUB service, used for controlling the DMUB on hardware 344 * that supports it. The pointer to the dmub_srv will be 345 * NULL on hardware that does not support it. 346 */ 347 struct dmub_srv *dmub_srv; 348 349 /** 350 * @dmub_notify: 351 * 352 * Notification from DMUB. 353 */ 354 355 struct dmub_notification *dmub_notify; 356 357 /** 358 * @dmub_callback: 359 * 360 * Callback functions to handle notification from DMUB. 361 */ 362 363 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX]; 364 365 /** 366 * @dmub_thread_offload: 367 * 368 * Flag to indicate if callback is offload. 369 */ 370 371 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX]; 372 373 /** 374 * @dmub_fb_info: 375 * 376 * Framebuffer regions for the DMUB. 377 */ 378 struct dmub_srv_fb_info *dmub_fb_info; 379 380 /** 381 * @dmub_fw: 382 * 383 * DMUB firmware, required on hardware that has DMUB support. 384 */ 385 const struct firmware *dmub_fw; 386 387 /** 388 * @dmub_bo: 389 * 390 * Buffer object for the DMUB. 391 */ 392 struct amdgpu_bo *dmub_bo; 393 394 /** 395 * @dmub_bo_gpu_addr: 396 * 397 * GPU virtual address for the DMUB buffer object. 398 */ 399 u64 dmub_bo_gpu_addr; 400 401 /** 402 * @dmub_bo_cpu_addr: 403 * 404 * CPU address for the DMUB buffer object. 405 */ 406 void *dmub_bo_cpu_addr; 407 408 /** 409 * @dmcub_fw_version: 410 * 411 * DMCUB firmware version. 412 */ 413 uint32_t dmcub_fw_version; 414 415 /** 416 * @cgs_device: 417 * 418 * The Common Graphics Services device. It provides an interface for 419 * accessing registers. 420 */ 421 struct cgs_device *cgs_device; 422 423 struct amdgpu_device *adev; 424 struct drm_device *ddev; 425 u16 display_indexes_num; 426 427 /** 428 * @atomic_obj: 429 * 430 * In combination with &dm_atomic_state it helps manage 431 * global atomic state that doesn't map cleanly into existing 432 * drm resources, like &dc_context. 433 */ 434 struct drm_private_obj atomic_obj; 435 436 /** 437 * @dc_lock: 438 * 439 * Guards access to DC functions that can issue register write 440 * sequences. 441 */ 442 struct mutex dc_lock; 443 444 /** 445 * @audio_lock: 446 * 447 * Guards access to audio instance changes. 448 */ 449 struct mutex audio_lock; 450 451 /** 452 * @audio_component: 453 * 454 * Used to notify ELD changes to sound driver. 455 */ 456 struct drm_audio_component *audio_component; 457 458 /** 459 * @audio_registered: 460 * 461 * True if the audio component has been registered 462 * successfully, false otherwise. 463 */ 464 bool audio_registered; 465 466 /** 467 * @irq_handler_list_low_tab: 468 * 469 * Low priority IRQ handler table. 470 * 471 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 472 * source. Low priority IRQ handlers are deferred to a workqueue to be 473 * processed. Hence, they can sleep. 474 * 475 * Note that handlers are called in the same order as they were 476 * registered (FIFO). 477 */ 478 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 479 480 /** 481 * @irq_handler_list_high_tab: 482 * 483 * High priority IRQ handler table. 484 * 485 * It is a n*m table, same as &irq_handler_list_low_tab. However, 486 * handlers in this table are not deferred and are called immediately. 487 */ 488 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 489 490 /** 491 * @pflip_params: 492 * 493 * Page flip IRQ parameters, passed to registered handlers when 494 * triggered. 495 */ 496 struct common_irq_params 497 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 498 499 /** 500 * @vblank_params: 501 * 502 * Vertical blanking IRQ parameters, passed to registered handlers when 503 * triggered. 504 */ 505 struct common_irq_params 506 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 507 508 /** 509 * @vline0_params: 510 * 511 * OTG vertical interrupt0 IRQ parameters, passed to registered 512 * handlers when triggered. 513 */ 514 struct common_irq_params 515 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1]; 516 517 /** 518 * @vupdate_params: 519 * 520 * Vertical update IRQ parameters, passed to registered handlers when 521 * triggered. 522 */ 523 struct common_irq_params 524 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 525 526 /** 527 * @dmub_trace_params: 528 * 529 * DMUB trace event IRQ parameters, passed to registered handlers when 530 * triggered. 531 */ 532 struct common_irq_params 533 dmub_trace_params[1]; 534 535 struct common_irq_params 536 dmub_outbox_params[1]; 537 538 spinlock_t irq_handler_list_table_lock; 539 540 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP]; 541 542 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP]; 543 544 uint8_t num_of_edps; 545 546 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP]; 547 548 struct mod_freesync *freesync_module; 549 struct hdcp_workqueue *hdcp_workqueue; 550 551 /** 552 * @vblank_control_workqueue: 553 * 554 * Deferred work for vblank control events. 555 */ 556 struct workqueue_struct *vblank_control_workqueue; 557 558 /** 559 * @idle_workqueue: 560 * 561 * Periodic work for idle events. 562 */ 563 struct idle_workqueue *idle_workqueue; 564 565 struct drm_atomic_state *cached_state; 566 struct dc_state *cached_dc_state; 567 568 struct dm_compressor_info compressor; 569 570 const struct firmware *fw_dmcu; 571 uint32_t dmcu_fw_version; 572 /** 573 * @soc_bounding_box: 574 * 575 * gpu_info FW provided soc bounding box struct or 0 if not 576 * available in FW 577 */ 578 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 579 580 /** 581 * @active_vblank_irq_count: 582 * 583 * number of currently active vblank irqs 584 */ 585 uint32_t active_vblank_irq_count; 586 587 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 588 /** 589 * @secure_display_ctx: 590 * 591 * Store secure display relevant info. e.g. the ROI information 592 * , the work_struct to command dmub, etc. 593 */ 594 struct secure_display_context secure_display_ctx; 595 #endif 596 /** 597 * @hpd_rx_offload_wq: 598 * 599 * Work queue to offload works of hpd_rx_irq 600 */ 601 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq; 602 /** 603 * @mst_encoders: 604 * 605 * fake encoders used for DP MST. 606 */ 607 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC]; 608 bool force_timing_sync; 609 bool disable_hpd_irq; 610 bool dmcub_trace_event_en; 611 /** 612 * @da_list: 613 * 614 * DAL fb memory allocation list, for communication with SMU. 615 */ 616 struct list_head da_list; 617 struct completion dmub_aux_transfer_done; 618 struct workqueue_struct *delayed_hpd_wq; 619 620 /** 621 * @brightness: 622 * 623 * cached backlight values. 624 */ 625 u32 brightness[AMDGPU_DM_MAX_NUM_EDP]; 626 /** 627 * @actual_brightness: 628 * 629 * last successfully applied backlight values. 630 */ 631 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP]; 632 633 /** 634 * @restore_backlight: 635 * 636 * Flag to indicate whether to restore backlight after modeset. 637 */ 638 bool restore_backlight; 639 640 /** 641 * @aux_hpd_discon_quirk: 642 * 643 * quirk for hpd discon while aux is on-going. 644 * occurred on certain intel platform 645 */ 646 bool aux_hpd_discon_quirk; 647 648 /** 649 * @edp0_on_dp1_quirk: 650 * 651 * quirk for platforms that put edp0 on DP1. 652 */ 653 bool edp0_on_dp1_quirk; 654 655 /** 656 * @dpia_aux_lock: 657 * 658 * Guards access to DPIA AUX 659 */ 660 struct mutex dpia_aux_lock; 661 662 /** 663 * @bb_from_dmub: 664 * 665 * Bounding box data read from dmub during early initialization for DCN4+ 666 * Data is stored as a byte array that should be casted to the appropriate bb struct 667 */ 668 void *bb_from_dmub; 669 670 /** 671 * @oem_i2c: 672 * 673 * OEM i2c bus 674 */ 675 struct amdgpu_i2c_adapter *oem_i2c; 676 677 /** 678 * @fused_io: 679 * 680 * dmub fused io interface 681 */ 682 struct fused_io_sync { 683 struct completion replied; 684 char reply_data[0x40]; // Cannot include dmub_cmd here 685 } fused_io[8]; 686 }; 687 688 enum dsc_clock_force_state { 689 DSC_CLK_FORCE_DEFAULT = 0, 690 DSC_CLK_FORCE_ENABLE, 691 DSC_CLK_FORCE_DISABLE, 692 }; 693 694 struct dsc_preferred_settings { 695 enum dsc_clock_force_state dsc_force_enable; 696 uint32_t dsc_num_slices_v; 697 uint32_t dsc_num_slices_h; 698 uint32_t dsc_bits_per_pixel; 699 bool dsc_force_disable_passthrough; 700 }; 701 702 enum mst_progress_status { 703 MST_STATUS_DEFAULT = 0, 704 MST_PROBE = BIT(0), 705 MST_REMOTE_EDID = BIT(1), 706 MST_ALLOCATE_NEW_PAYLOAD = BIT(2), 707 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3), 708 }; 709 710 /** 711 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info 712 * 713 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this 714 * struct is useful to keep track of the display-specific information about 715 * FreeSync. 716 */ 717 struct amdgpu_hdmi_vsdb_info { 718 /** 719 * @amd_vsdb_version: Vendor Specific Data Block Version, should be 720 * used to determine which Vendor Specific InfoFrame (VSIF) to send. 721 */ 722 unsigned int amd_vsdb_version; 723 724 /** 725 * @freesync_supported: FreeSync Supported. 726 */ 727 bool freesync_supported; 728 729 /** 730 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz. 731 */ 732 unsigned int min_refresh_rate_hz; 733 734 /** 735 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz 736 */ 737 unsigned int max_refresh_rate_hz; 738 739 /** 740 * @replay_mode: Replay supported 741 */ 742 bool replay_mode; 743 }; 744 745 struct amdgpu_dm_connector { 746 747 struct drm_connector base; 748 uint32_t connector_id; 749 int bl_idx; 750 751 struct cec_notifier *notifier; 752 753 /* we need to mind the EDID between detect 754 and get modes due to analog/digital/tvencoder */ 755 const struct drm_edid *drm_edid; 756 757 /* shared with amdgpu */ 758 struct amdgpu_hpd hpd; 759 760 /* number of modes generated from EDID at 'dc_sink' */ 761 int num_modes; 762 763 /* The 'old' sink - before an HPD. 764 * The 'current' sink is in dc_link->sink. */ 765 struct dc_sink *dc_sink; 766 struct dc_link *dc_link; 767 768 /** 769 * @dc_em_sink: Reference to the emulated (virtual) sink. 770 */ 771 struct dc_sink *dc_em_sink; 772 773 /* DM only */ 774 struct drm_dp_mst_topology_mgr mst_mgr; 775 struct amdgpu_dm_dp_aux dm_dp_aux; 776 struct drm_dp_mst_port *mst_output_port; 777 struct amdgpu_dm_connector *mst_root; 778 struct drm_dp_aux *dsc_aux; 779 uint32_t mst_local_bw; 780 uint16_t vc_full_pbn; 781 struct mutex handle_mst_msg_ready; 782 783 /* branch device specific data */ 784 uint32_t branch_ieee_oui; 785 786 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 787 struct amdgpu_i2c_adapter *i2c; 788 789 /* Monitor range limits */ 790 /** 791 * @min_vfreq: Minimal frequency supported by the display in Hz. This 792 * value is set to zero when there is no FreeSync support. 793 */ 794 int min_vfreq; 795 796 /** 797 * @max_vfreq: Maximum frequency supported by the display in Hz. This 798 * value is set to zero when there is no FreeSync support. 799 */ 800 int max_vfreq ; 801 802 /* Audio instance - protected by audio_lock. */ 803 int audio_inst; 804 805 struct mutex hpd_lock; 806 807 bool fake_enable; 808 bool force_yuv420_output; 809 bool force_yuv422_output; 810 struct dsc_preferred_settings dsc_settings; 811 union dp_downstream_port_present mst_downstream_port_present; 812 /* Cached display modes */ 813 struct drm_display_mode freesync_vid_base; 814 815 int sr_skip_count; 816 bool disallow_edp_enter_psr; 817 818 /* Record progress status of mst*/ 819 uint8_t mst_status; 820 821 /* Automated testing */ 822 bool timing_changed; 823 struct dc_crtc_timing *timing_requested; 824 825 /* Adaptive Sync */ 826 bool pack_sdp_v1_3; 827 enum adaptive_sync_type as_type; 828 struct amdgpu_hdmi_vsdb_info vsdb_info; 829 }; 830 831 static inline void amdgpu_dm_set_mst_status(uint8_t *status, 832 uint8_t flags, bool set) 833 { 834 if (set) 835 *status |= flags; 836 else 837 *status &= ~flags; 838 } 839 840 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 841 842 struct amdgpu_dm_wb_connector { 843 struct drm_writeback_connector base; 844 struct dc_link *link; 845 }; 846 847 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base) 848 849 extern const struct amdgpu_ip_block_version dm_ip_block; 850 851 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD. 852 * 853 * It includes standardized transfer functions and pure power functions. The 854 * transfer function coefficients are available at modules/color/color_gamma.c 855 */ 856 enum amdgpu_transfer_function { 857 AMDGPU_TRANSFER_FUNCTION_DEFAULT, 858 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, 859 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF, 860 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, 861 AMDGPU_TRANSFER_FUNCTION_IDENTITY, 862 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, 863 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, 864 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, 865 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, 866 AMDGPU_TRANSFER_FUNCTION_BT709_OETF, 867 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, 868 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, 869 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, 870 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, 871 AMDGPU_TRANSFER_FUNCTION_COUNT 872 }; 873 874 struct dm_plane_state { 875 struct drm_plane_state base; 876 struct dc_plane_state *dc_state; 877 878 /* Plane color mgmt */ 879 /** 880 * @degamma_lut: 881 * 882 * 1D LUT for mapping framebuffer/plane pixel data before sampling or 883 * blending operations. It's usually applied to linearize input space. 884 * The blob (if not NULL) is an array of &struct drm_color_lut. 885 */ 886 struct drm_property_blob *degamma_lut; 887 /** 888 * @degamma_tf: 889 * 890 * Predefined transfer function to tell DC driver the input space to 891 * linearize. 892 */ 893 enum amdgpu_transfer_function degamma_tf; 894 /** 895 * @hdr_mult: 896 * 897 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed 898 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on 899 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. 900 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you 901 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is 902 * S31.32 sign-magnitude. 903 * 904 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ 905 * TF is needed for any subsequent linear-to-non-linear transforms. 906 */ 907 __u64 hdr_mult; 908 /** 909 * @ctm: 910 * 911 * Color transformation matrix. The blob (if not NULL) is a &struct 912 * drm_color_ctm_3x4. 913 */ 914 struct drm_property_blob *ctm; 915 /** 916 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an 917 * array of &struct drm_color_lut. 918 */ 919 struct drm_property_blob *shaper_lut; 920 /** 921 * @shaper_tf: 922 * 923 * Predefined transfer function to delinearize color space. 924 */ 925 enum amdgpu_transfer_function shaper_tf; 926 /** 927 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of 928 * &struct drm_color_lut. 929 */ 930 struct drm_property_blob *lut3d; 931 /** 932 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an 933 * array of &struct drm_color_lut. 934 */ 935 struct drm_property_blob *blend_lut; 936 /** 937 * @blend_tf: 938 * 939 * Pre-defined transfer function for converting plane pixel data before 940 * applying blend LUT. 941 */ 942 enum amdgpu_transfer_function blend_tf; 943 }; 944 945 enum amdgpu_dm_cursor_mode { 946 DM_CURSOR_NATIVE_MODE = 0, 947 DM_CURSOR_OVERLAY_MODE, 948 }; 949 950 struct dm_crtc_state { 951 struct drm_crtc_state base; 952 struct dc_stream_state *stream; 953 954 bool cm_has_degamma; 955 bool cm_is_degamma_srgb; 956 957 bool mpo_requested; 958 959 int update_type; 960 int active_planes; 961 962 int crc_skip_count; 963 964 bool freesync_vrr_info_changed; 965 966 bool dsc_force_changed; 967 bool vrr_supported; 968 struct mod_freesync_config freesync_config; 969 struct dc_info_packet vrr_infopacket; 970 971 int abm_level; 972 973 /** 974 * @regamma_tf: 975 * 976 * Pre-defined transfer function for converting internal FB -> wire 977 * encoding. 978 */ 979 enum amdgpu_transfer_function regamma_tf; 980 981 enum amdgpu_dm_cursor_mode cursor_mode; 982 }; 983 984 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 985 986 struct dm_atomic_state { 987 struct drm_private_state base; 988 989 struct dc_state *context; 990 }; 991 992 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 993 994 struct dm_connector_state { 995 struct drm_connector_state base; 996 997 enum amdgpu_rmx_type scaling; 998 uint8_t underscan_vborder; 999 uint8_t underscan_hborder; 1000 bool underscan_enable; 1001 bool freesync_capable; 1002 bool update_hdcp; 1003 uint8_t abm_level; 1004 int vcpi_slots; 1005 uint64_t pbn; 1006 }; 1007 1008 #define to_dm_connector_state(x)\ 1009 container_of((x), struct dm_connector_state, base) 1010 1011 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 1012 struct drm_connector_state * 1013 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 1014 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 1015 struct drm_connector_state *state, 1016 struct drm_property *property, 1017 uint64_t val); 1018 1019 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 1020 const struct drm_connector_state *state, 1021 struct drm_property *property, 1022 uint64_t *val); 1023 1024 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 1025 1026 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 1027 struct amdgpu_dm_connector *aconnector, 1028 int connector_type, 1029 struct dc_link *link, 1030 int link_index); 1031 1032 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 1033 const struct drm_display_mode *mode); 1034 1035 void dm_restore_drm_connector_state(struct drm_device *dev, 1036 struct drm_connector *connector); 1037 1038 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 1039 const struct drm_edid *drm_edid); 1040 1041 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); 1042 1043 /* 3D LUT max size is 17x17x17 (4913 entries) */ 1044 #define MAX_COLOR_3DLUT_SIZE 17 1045 #define MAX_COLOR_3DLUT_BITDEPTH 12 1046 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, 1047 struct drm_plane_state *plane_state); 1048 /* 1D LUT size */ 1049 #define MAX_COLOR_LUT_ENTRIES 4096 1050 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 1051 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 1052 1053 void amdgpu_dm_init_color_mod(void); 1054 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); 1055 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); 1056 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 1057 int amdgpu_dm_check_crtc_color_mgmt(struct dm_crtc_state *crtc, 1058 bool check_only); 1059 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 1060 struct drm_plane_state *plane_state, 1061 struct dc_plane_state *dc_plane_state); 1062 1063 void amdgpu_dm_update_connector_after_detect( 1064 struct amdgpu_dm_connector *aconnector); 1065 1066 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 1067 1068 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index, 1069 struct aux_payload *payload, enum aux_return_code_type *operation_result); 1070 1071 bool amdgpu_dm_execute_fused_io( 1072 struct amdgpu_device *dev, 1073 struct dc_link *link, 1074 union dmub_rb_cmd *commands, 1075 uint8_t count, 1076 uint32_t timeout_us 1077 ); 1078 1079 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index, 1080 struct set_config_cmd_payload *payload, enum set_config_status *operation_result); 1081 1082 struct dc_stream_state * 1083 create_validate_stream_for_sink(struct drm_connector *connector, 1084 const struct drm_display_mode *drm_mode, 1085 const struct dm_connector_state *dm_state, 1086 const struct dc_stream_state *old_stream); 1087 1088 int dm_atomic_get_state(struct drm_atomic_state *state, 1089 struct dm_atomic_state **dm_state); 1090 1091 struct drm_connector * 1092 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 1093 struct drm_crtc *crtc); 1094 1095 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); 1096 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); 1097 1098 void *dm_allocate_gpu_mem(struct amdgpu_device *adev, 1099 enum dc_gpu_mem_alloc_type type, 1100 size_t size, 1101 long long *addr); 1102 void dm_free_gpu_mem(struct amdgpu_device *adev, 1103 enum dc_gpu_mem_alloc_type type, 1104 void *addr); 1105 1106 bool amdgpu_dm_is_headless(struct amdgpu_device *adev); 1107 1108 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector); 1109 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector); 1110 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector); 1111 1112 void retrieve_dmi_info(struct amdgpu_display_manager *dm); 1113 1114 #endif /* __AMDGPU_DM_H__ */ 1115