1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "dc/dc_state.h" 42 #include "amdgpu_dm_trace.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_dm_wb.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 #include "amdgpu_dm_replay.h" 69 #include "amdgpu_dm_backlight.h" 70 #include "amdgpu_dm_audio.h" 71 #include "amdgpu_dm_dmub.h" 72 #include "amdgpu_dm_connector.h" 73 74 #include "ivsrcid/ivsrcid_vislands30.h" 75 76 #include <linux/backlight.h> 77 #include <linux/module.h> 78 #include <linux/moduleparam.h> 79 #include <linux/types.h> 80 #include <linux/pm_runtime.h> 81 #include <linux/pci.h> 82 #include <linux/power_supply.h> 83 #include <linux/firmware.h> 84 #include <linux/component.h> 85 #include <linux/sort.h> 86 87 #include <drm/drm_privacy_screen_consumer.h> 88 #include <drm/display/drm_dp_mst_helper.h> 89 #include <drm/display/drm_hdmi_helper.h> 90 #include <drm/drm_atomic.h> 91 #include <drm/drm_atomic_uapi.h> 92 #include <drm/drm_atomic_helper.h> 93 #include <drm/drm_blend.h> 94 #include <drm/drm_fixed.h> 95 #include <drm/drm_fourcc.h> 96 #include <drm/drm_edid.h> 97 #include <drm/drm_eld.h> 98 #include <drm/drm_mode.h> 99 #include <drm/drm_utils.h> 100 #include <drm/drm_vblank.h> 101 #include <drm/drm_colorop.h> 102 #include <drm/drm_gem_atomic_helper.h> 103 104 #include <media/cec-notifier.h> 105 #include <acpi/video.h> 106 107 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 108 109 #include "modules/inc/mod_freesync.h" 110 #include "modules/inc/mod_power.h" 111 #include "modules/power/power_helpers.h" 112 113 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 114 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 115 116 /** 117 * DOC: overview 118 * 119 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 120 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 121 * requests into DC requests, and DC responses into DRM responses. 122 * 123 * The root control structure is &struct amdgpu_display_manager. 124 */ 125 126 /* basic init/fini API */ 127 static int amdgpu_dm_init(struct amdgpu_device *adev); 128 static void amdgpu_dm_fini(struct amdgpu_device *adev); 129 static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state); 130 131 /* 132 * initializes drm_device display related structures, based on the information 133 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 134 * drm_encoder, drm_mode_config 135 * 136 * Returns 0 on success 137 */ 138 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 139 /* removes and deallocates the drm structures, created by the above function */ 140 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 141 142 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 143 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 144 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 145 146 static int amdgpu_dm_atomic_check(struct drm_device *dev, 147 struct drm_atomic_commit *state); 148 149 STATIC_IFN_KUNIT bool 150 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 151 struct drm_crtc_state *new_crtc_state); 152 153 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 154 { 155 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 156 dc_exit_ips_for_hw_access(dc); 157 } 158 159 /* 160 * dm_vblank_get_counter 161 * 162 * @brief 163 * Get counter for number of vertical blanks 164 * 165 * @param 166 * struct amdgpu_device *adev - [in] desired amdgpu device 167 * int disp_idx - [in] which CRTC to get the counter from 168 * 169 * @return 170 * Counter for vertical blanks 171 */ 172 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 173 { 174 struct amdgpu_crtc *acrtc = NULL; 175 176 if (crtc >= adev->mode_info.num_crtc) 177 return 0; 178 179 acrtc = adev->mode_info.crtcs[crtc]; 180 181 if (!acrtc->dm_irq_params.stream) { 182 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 183 crtc); 184 return 0; 185 } 186 187 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 188 } 189 190 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 191 u32 *vbl, u32 *position) 192 { 193 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 194 struct amdgpu_crtc *acrtc = NULL; 195 struct dc *dc = adev->dm.dc; 196 197 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 198 return -EINVAL; 199 200 acrtc = adev->mode_info.crtcs[crtc]; 201 202 if (!acrtc->dm_irq_params.stream) { 203 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 204 crtc); 205 return 0; 206 } 207 208 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 209 dc_allow_idle_optimizations(dc, false); 210 211 /* 212 * TODO rework base driver to use values directly. 213 * for now parse it back into reg-format 214 */ 215 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 216 &v_blank_start, 217 &v_blank_end, 218 &h_position, 219 &v_position); 220 221 *position = v_position | (h_position << 16); 222 *vbl = v_blank_start | (v_blank_end << 16); 223 224 return 0; 225 } 226 227 static bool dm_is_idle(struct amdgpu_ip_block *ip_block) 228 { 229 /* XXX todo */ 230 return true; 231 } 232 233 static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 234 { 235 /* XXX todo */ 236 return 0; 237 } 238 239 static int dm_soft_reset(struct amdgpu_ip_block *ip_block) 240 { 241 /* XXX todo */ 242 return 0; 243 } 244 245 STATIC_IFN_KUNIT bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 246 struct dm_crtc_state *new_state) 247 { 248 if (new_state->stream->adjust.timing_adjust_pending) 249 return true; 250 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 251 return true; 252 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 253 return true; 254 else 255 return false; 256 } 257 EXPORT_IF_KUNIT(is_dc_timing_adjust_needed); 258 259 /* 260 * DC will program planes with their z-order determined by their ordering 261 * in the dc_surface_updates array. This comparator is used to sort them 262 * by descending zpos. 263 */ 264 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 265 { 266 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 267 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 268 269 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 270 return sb->surface->layer_index - sa->surface->layer_index; 271 } 272 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 273 274 /** 275 * update_planes_and_stream_adapter() - Send planes to be updated in DC 276 * 277 * DC has a generic way to update planes and stream via 278 * dc_update_planes_and_stream function; however, DM might need some 279 * adjustments and preparation before calling it. This function is a wrapper 280 * for the dc_update_planes_and_stream that does any required configuration 281 * before passing control to DC. 282 * 283 * @dc: Display Core control structure 284 * @update_type: specify whether it is FULL/MEDIUM/FAST update 285 * @planes_count: planes count to update 286 * @stream: stream state 287 * @stream_update: stream update 288 * @array_of_surface_update: dc surface update pointer 289 * 290 */ 291 static inline bool update_planes_and_stream_adapter(struct dc *dc, 292 int update_type, 293 int planes_count, 294 struct dc_stream_state *stream, 295 struct dc_stream_update *stream_update, 296 struct dc_surface_update *array_of_surface_update) 297 { 298 sort(array_of_surface_update, planes_count, 299 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 300 301 /* 302 * Previous frame finished and HW is ready for optimization. 303 */ 304 dc_post_update_surfaces_to_stream(dc); 305 306 return dc_update_planes_and_stream(dc, 307 array_of_surface_update, 308 planes_count, 309 stream, 310 stream_update); 311 } 312 313 static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 314 enum amd_clockgating_state state) 315 { 316 return 0; 317 } 318 319 static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 320 enum amd_powergating_state state) 321 { 322 return 0; 323 } 324 325 /* Prototypes of private functions */ 326 static int dm_early_init(struct amdgpu_ip_block *ip_block); 327 328 /* Allocate memory for FBC compressed data */ 329 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 330 { 331 u64 pt_base; 332 u32 logical_addr_low; 333 u32 logical_addr_high; 334 u32 agp_base, agp_bot, agp_top; 335 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 336 337 memset(pa_config, 0, sizeof(*pa_config)); 338 339 agp_base = 0; 340 agp_bot = adev->gmc.agp_start >> 24; 341 agp_top = adev->gmc.agp_end >> 24; 342 343 /* AGP aperture is disabled */ 344 if (agp_bot > agp_top) { 345 logical_addr_low = adev->gmc.fb_start >> 18; 346 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 347 AMD_APU_IS_RENOIR | 348 AMD_APU_IS_GREEN_SARDINE)) 349 /* 350 * Raven2 has a HW issue that it is unable to use the vram which 351 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 352 * workaround that increase system aperture high address (add 1) 353 * to get rid of the VM fault and hardware hang. 354 */ 355 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 356 else 357 logical_addr_high = adev->gmc.fb_end >> 18; 358 } else { 359 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 360 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 361 AMD_APU_IS_RENOIR | 362 AMD_APU_IS_GREEN_SARDINE)) 363 /* 364 * Raven2 has a HW issue that it is unable to use the vram which 365 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 366 * workaround that increase system aperture high address (add 1) 367 * to get rid of the VM fault and hardware hang. 368 */ 369 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 370 else 371 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 372 } 373 374 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 375 376 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 377 AMDGPU_GPU_PAGE_SHIFT); 378 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 379 AMDGPU_GPU_PAGE_SHIFT); 380 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 381 AMDGPU_GPU_PAGE_SHIFT); 382 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 383 AMDGPU_GPU_PAGE_SHIFT); 384 page_table_base.high_part = upper_32_bits(pt_base); 385 page_table_base.low_part = lower_32_bits(pt_base); 386 387 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 388 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 389 390 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 391 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 392 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 393 394 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 395 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 396 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 397 398 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 399 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 400 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 401 402 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 403 404 } 405 406 struct amdgpu_stutter_quirk { 407 u16 chip_vendor; 408 u16 chip_device; 409 u16 subsys_vendor; 410 u16 subsys_device; 411 u8 revision; 412 }; 413 414 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 415 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 416 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 417 { 0, 0, 0, 0, 0 }, 418 }; 419 420 static bool dm_should_disable_stutter(struct pci_dev *pdev) 421 { 422 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 423 424 while (p && p->chip_device != 0) { 425 if (pdev->vendor == p->chip_vendor && 426 pdev->device == p->chip_device && 427 pdev->subsystem_vendor == p->subsys_vendor && 428 pdev->subsystem_device == p->subsys_device && 429 pdev->revision == p->revision) { 430 return true; 431 } 432 ++p; 433 } 434 return false; 435 } 436 437 438 void* 439 dm_allocate_gpu_mem( 440 struct amdgpu_device *adev, 441 enum dc_gpu_mem_alloc_type type, 442 size_t size, 443 long long *addr) 444 { 445 struct dal_allocation *da; 446 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 447 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 448 int ret; 449 450 da = kzalloc_obj(struct dal_allocation); 451 if (!da) 452 return NULL; 453 454 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 455 domain, &da->bo, 456 &da->gpu_addr, &da->cpu_ptr); 457 458 *addr = da->gpu_addr; 459 460 if (ret) { 461 kfree(da); 462 return NULL; 463 } 464 465 /* add da to list in dm */ 466 list_add(&da->list, &adev->dm.da_list); 467 468 return da->cpu_ptr; 469 } 470 471 void 472 dm_free_gpu_mem( 473 struct amdgpu_device *adev, 474 enum dc_gpu_mem_alloc_type type, 475 void *pvMem) 476 { 477 struct dal_allocation *da; 478 479 /* walk the da list in DM */ 480 list_for_each_entry(da, &adev->dm.da_list, list) { 481 if (pvMem == da->cpu_ptr) { 482 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 483 list_del(&da->list); 484 kfree(da); 485 break; 486 } 487 } 488 489 } 490 491 static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 492 { 493 struct mod_power_init_params init_data[MAX_NUM_EDP]; 494 495 if (dm->num_of_edps == 0) { 496 drm_dbg_driver( 497 dm->ddev, 498 "amdgpu: No eDP detected, skip initializing power module\n"); 499 return 0; 500 } 501 502 /* Initialize all the power module parameters */ 503 for (int i = 0; i < dm->num_of_edps; i++) { 504 init_data[i].allow_psr_smu_optimizations = 505 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 506 init_data[i].allow_psr_multi_disp_optimizations = 507 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 508 /* See dm_late_init */ 509 init_data[i].backlight_ramping_override = false; 510 init_data[i].backlight_ramping_start = 0xCCCC; 511 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 512 init_data[i].def_varibright_level = 0; 513 init_data[i].abm_config_setting = 0; 514 init_data[i].num_backlight_levels = 101; 515 init_data[i].use_nits_based_brightness = false; 516 init_data[i].panel_max_millinits = 0; 517 init_data[i].panel_min_millinits = 0; 518 init_data[i].disable_fractional_pwm = 519 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 520 init_data[i].use_custom_backlight_caps = false; 521 init_data[i].custom_backlight_caps_config_no = 0; 522 init_data[i].use_linear_backlight_curve = false; 523 init_data[i].def_varibright_enable = 0; 524 init_data[i].varibright_level = 0; 525 /* 526 * Power module uses 16-bit backlight levels (0xFFFF max) rather 527 * than 8-bit(0XFF max) 528 */ 529 init_data[i].min_backlight_pwm = 530 dm->backlight_caps[i].min_input_signal * 0x101; 531 init_data[i].max_backlight_pwm = 532 dm->backlight_caps[i].max_input_signal * 0x101; 533 init_data[i].min_abm_backlight = 534 dm->backlight_caps[i].min_input_signal * 0x101; 535 536 /* Min backlight level after ABM reduction, Don't allow below 1% 537 * 0xFFFF x 0.01 = 0x28F 538 */ 539 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 540 0x28F : init_data[i].min_abm_backlight; 541 } 542 543 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 544 if (!dm->power_module) { 545 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 546 return -ENOMEM; 547 } 548 549 mod_power_hw_init(dm->power_module); 550 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 551 552 return 0; 553 } 554 555 static int amdgpu_dm_init(struct amdgpu_device *adev) 556 { 557 struct dc_init_data init_data; 558 struct dc_callback_init init_params; 559 int r; 560 561 adev->dm.ddev = adev_to_drm(adev); 562 adev->dm.adev = adev; 563 564 /* Zero all the fields */ 565 memset(&init_data, 0, sizeof(init_data)); 566 memset(&init_params, 0, sizeof(init_params)); 567 568 mutex_init(&adev->dm.dpia_aux_lock); 569 mutex_init(&adev->dm.dc_lock); 570 mutex_init(&adev->dm.audio_lock); 571 572 spin_lock_init(&adev->dm.dmub_lock); 573 574 if (amdgpu_dm_irq_init(adev)) { 575 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 576 goto error; 577 } 578 579 /* special handling for early revisions of GC 11.5.4 */ 580 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 581 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 582 else 583 init_data.asic_id.chip_family = adev->family; 584 585 init_data.asic_id.pci_revision_id = adev->pdev->revision; 586 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 587 init_data.asic_id.chip_id = adev->pdev->device; 588 589 init_data.asic_id.vram_width = adev->gmc.vram_width; 590 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 591 init_data.asic_id.atombios_base_address = 592 adev->mode_info.atom_context->bios; 593 594 init_data.driver = adev; 595 596 /* cgs_device was created in dm_sw_init() */ 597 init_data.cgs_device = adev->dm.cgs_device; 598 599 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 600 601 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 602 case IP_VERSION(2, 1, 0): 603 switch (adev->dm.dmcub_fw_version) { 604 case 0: /* development */ 605 case 0x1: /* linux-firmware.git hash 6d9f399 */ 606 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 607 init_data.flags.disable_dmcu = false; 608 break; 609 default: 610 init_data.flags.disable_dmcu = true; 611 } 612 break; 613 case IP_VERSION(2, 0, 3): 614 init_data.flags.disable_dmcu = true; 615 break; 616 default: 617 break; 618 } 619 620 /* APU support S/G display by default except: 621 * ASICs before Carrizo, 622 * RAVEN1 (Users reported stability issue) 623 */ 624 625 if (adev->asic_type < CHIP_CARRIZO) { 626 init_data.flags.gpu_vm_support = false; 627 } else if (adev->asic_type == CHIP_RAVEN) { 628 if (adev->apu_flags & AMD_APU_IS_RAVEN) 629 init_data.flags.gpu_vm_support = false; 630 else 631 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 632 } else { 633 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 634 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 635 else 636 init_data.flags.gpu_vm_support = 637 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 638 } 639 640 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 641 642 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 643 init_data.flags.fbc_support = true; 644 645 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 646 init_data.flags.multi_mon_pp_mclk_switch = true; 647 648 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 649 init_data.flags.disable_fractional_pwm = true; 650 651 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 652 init_data.flags.edp_no_power_sequencing = true; 653 654 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 655 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 656 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 657 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 658 659 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 660 init_data.flags.enable_frl = true; 661 662 init_data.flags.seamless_boot_edp_requested = false; 663 664 if (amdgpu_device_seamless_boot_supported(adev)) { 665 init_data.flags.seamless_boot_edp_requested = true; 666 init_data.flags.allow_seamless_boot_optimization = true; 667 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 668 } 669 670 init_data.flags.enable_mipi_converter_optimization = true; 671 672 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 673 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 674 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 675 676 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 677 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 678 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 679 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 680 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 681 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 682 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 683 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 684 else 685 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 686 687 init_data.flags.disable_ips_in_vpb = 0; 688 689 /* DCN35 and above supports dynamic DTBCLK switch */ 690 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 691 init_data.flags.allow_0_dtb_clk = true; 692 693 /* Enable DWB for tested platforms only */ 694 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 695 init_data.num_virtual_links = 1; 696 697 /* DCN42 and above dpia switch to unified link training path */ 698 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 699 init_data.flags.consolidated_dpia_dp_lt = true; 700 init_data.flags.enable_dpia_pre_training = true; 701 init_data.flags.unify_link_enc_assignment = true; 702 init_data.flags.usb4_bw_alloc_support = true; 703 } 704 retrieve_dmi_info(&adev->dm); 705 if (adev->dm.edp0_on_dp1_quirk) 706 init_data.flags.support_edp0_on_dp1 = true; 707 708 if (adev->dm.bb_from_dmub) 709 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 710 else 711 init_data.bb_from_dmub = NULL; 712 713 /* Display Core create. */ 714 adev->dm.dc = dc_create(&init_data); 715 716 if (adev->dm.dc) { 717 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 718 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 719 } else { 720 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 721 goto error; 722 } 723 724 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 725 adev->dm.dc->debug.force_single_disp_pipe_split = false; 726 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 727 } 728 729 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 730 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 731 if (dm_should_disable_stutter(adev->pdev)) 732 adev->dm.dc->debug.disable_stutter = true; 733 734 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 735 adev->dm.dc->debug.disable_stutter = true; 736 737 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 738 adev->dm.dc->debug.disable_dsc = true; 739 740 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 741 adev->dm.dc->debug.disable_clock_gate = true; 742 743 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 744 adev->dm.dc->debug.force_subvp_mclk_switch = true; 745 746 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 747 adev->dm.dc->debug.force_disable_subvp = true; 748 adev->dm.dc->debug.fams2_config.bits.enable = false; 749 } 750 751 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 752 adev->dm.dc->debug.using_dml2 = true; 753 adev->dm.dc->debug.using_dml21 = true; 754 } 755 756 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 757 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 758 759 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 760 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 761 762 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 763 adev->dm.dc->debug.skip_detection_link_training = true; 764 765 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 766 767 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 768 adev->dm.dc->debug.ignore_cable_id = true; 769 770 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 771 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 772 773 r = dm_dmub_hw_init(adev); 774 if (r) { 775 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 776 goto error; 777 } 778 779 dc_hardware_init(adev->dm.dc); 780 781 /* GOP/vBIOS may leave an OPTC enabled for a display present at power-on 782 * but no longer driven (e.g. an external DP unplugged at boot). Such a 783 * dangling pipe keeps DCN out of idle and blocks s0i3. Power it down 784 * here when nothing needs to be preserved. 785 */ 786 if (adev->flags & AMD_IS_APU) 787 dc_disable_dangling_timing_generators(adev->dm.dc); 788 789 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 790 if (!adev->dm.hpd_rx_offload_wq) { 791 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 792 goto error; 793 } 794 795 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 796 struct dc_phy_addr_space_config pa_config; 797 798 mmhub_read_system_context(adev, &pa_config); 799 800 // Call the DC init_memory func 801 dc_setup_system_context(adev->dm.dc, &pa_config); 802 } 803 804 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 805 if (!adev->dm.freesync_module) { 806 drm_err(adev_to_drm(adev), 807 "failed to initialize freesync_module.\n"); 808 } else 809 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 810 adev->dm.freesync_module); 811 812 amdgpu_dm_init_color_mod(); 813 814 if (adev->dm.dc->caps.max_links > 0) { 815 adev->dm.vblank_control_workqueue = 816 create_singlethread_workqueue("dm_vblank_control_workqueue"); 817 if (!adev->dm.vblank_control_workqueue) 818 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 819 } 820 821 if (adev->dm.dc->caps.ips_support && 822 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 823 adev->dm.idle_workqueue = idle_create_workqueue(adev); 824 825 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 826 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 827 828 if (!adev->dm.hdcp_workqueue) 829 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 830 else 831 drm_dbg_driver(adev_to_drm(adev), 832 "hdcp_workqueue init done %p.\n", 833 adev->dm.hdcp_workqueue); 834 835 dc_init_callbacks(adev->dm.dc, &init_params); 836 } 837 if (adev->dm.dc->caps.max_links > 0) { 838 adev->dm.hdmi_frl_status_polling_wq = 839 create_singlethread_workqueue("hdmi_frl_status_polling_workqueue"); 840 if (!adev->dm.hdmi_frl_status_polling_wq) 841 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_workqueue\n"); 842 } 843 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 844 init_completion(&adev->dm.dmub_aux_transfer_done); 845 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 846 if (!adev->dm.dmub_notify) { 847 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 848 goto error; 849 } 850 851 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 852 if (!adev->dm.delayed_hpd_wq) { 853 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 854 goto error; 855 } 856 857 amdgpu_dm_outbox_init(adev); 858 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 859 dm_dmub_aux_setconfig_callback, false)) { 860 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 861 goto error; 862 } 863 864 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 865 init_completion(&adev->dm.fused_io[i].replied); 866 867 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 868 dm_dmub_aux_fused_io_callback, false)) { 869 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 870 goto error; 871 } 872 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 873 * It is expected that DMUB will resend any pending notifications at this point. Note 874 * that hpd and hpd_irq handler registration are deferred to 875 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 876 * sequence. Connection status will be proactivly detected once in the 877 * amdgpu_dm_initialize_drm_device. 878 */ 879 dc_enable_dmub_outbox(adev->dm.dc); 880 881 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 882 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 883 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 884 } 885 886 if (amdgpu_dm_initialize_drm_device(adev)) { 887 drm_err(adev_to_drm(adev), 888 "failed to initialize sw for display support.\n"); 889 goto error; 890 } 891 892 if (amdgpu_dm_init_power_module(&adev->dm)) 893 goto error; 894 895 /* create fake encoders for MST */ 896 dm_dp_create_fake_mst_encoders(adev); 897 898 /* TODO: Add_display_info? */ 899 900 /* TODO use dynamic cursor width */ 901 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 902 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 903 904 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 905 drm_err(adev_to_drm(adev), 906 "failed to initialize vblank for display support.\n"); 907 goto error; 908 } 909 910 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 911 amdgpu_dm_crtc_secure_display_create_contexts(adev); 912 if (!adev->dm.secure_display_ctx.crtc_ctx) 913 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 914 915 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 916 adev->dm.secure_display_ctx.support_mul_roi = true; 917 918 #endif 919 920 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 921 922 return 0; 923 error: 924 amdgpu_dm_fini(adev); 925 926 return -EINVAL; 927 } 928 929 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 930 { 931 struct amdgpu_device *adev = ip_block->adev; 932 933 amdgpu_dm_audio_fini(adev); 934 935 return 0; 936 } 937 938 static void amdgpu_dm_fini(struct amdgpu_device *adev) 939 { 940 int i; 941 942 if (adev->dm.vblank_control_workqueue) { 943 destroy_workqueue(adev->dm.vblank_control_workqueue); 944 adev->dm.vblank_control_workqueue = NULL; 945 } 946 947 if (adev->dm.idle_workqueue) { 948 if (adev->dm.idle_workqueue->running) { 949 adev->dm.idle_workqueue->enable = false; 950 flush_work(&adev->dm.idle_workqueue->work); 951 } 952 953 kfree(adev->dm.idle_workqueue); 954 adev->dm.idle_workqueue = NULL; 955 } 956 957 /* 958 * Disable ISM before dc_destroy() invalidates dm->dc. 959 * 960 * Quiesce workers first without dc_lock (they take dc_lock 961 * themselves, so syncing under it would deadlock), then drive the 962 * FSM back to FULL_POWER_RUNNING under dc_lock. 963 */ 964 amdgpu_dm_ism_disable(&adev->dm); 965 scoped_guard(mutex, &adev->dm.dc_lock) 966 amdgpu_dm_ism_force_full_power(&adev->dm); 967 968 amdgpu_dm_destroy_drm_device(&adev->dm); 969 970 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 971 if (adev->dm.secure_display_ctx.crtc_ctx) { 972 for (i = 0; i < adev->mode_info.num_crtc; i++) { 973 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 974 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 975 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 976 } 977 } 978 kfree(adev->dm.secure_display_ctx.crtc_ctx); 979 adev->dm.secure_display_ctx.crtc_ctx = NULL; 980 } 981 #endif 982 if (adev->dm.hdcp_workqueue) { 983 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 984 adev->dm.hdcp_workqueue = NULL; 985 } 986 987 if (adev->dm.dc) { 988 dc_deinit_callbacks(adev->dm.dc); 989 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 990 if (dc_enable_dmub_notifications(adev->dm.dc)) { 991 kfree(adev->dm.dmub_notify); 992 adev->dm.dmub_notify = NULL; 993 destroy_workqueue(adev->dm.delayed_hpd_wq); 994 adev->dm.delayed_hpd_wq = NULL; 995 } 996 } 997 998 if (adev->dm.dmub_bo) 999 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1000 &adev->dm.dmub_bo_gpu_addr, 1001 &adev->dm.dmub_bo_cpu_addr); 1002 1003 if (adev->dm.boot_time_crc_info.bo_ptr) 1004 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 1005 &adev->dm.boot_time_crc_info.gpu_addr, 1006 &adev->dm.boot_time_crc_info.cpu_addr); 1007 1008 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 1009 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1010 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1011 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1012 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1013 } 1014 } 1015 1016 kfree(adev->dm.hpd_rx_offload_wq); 1017 adev->dm.hpd_rx_offload_wq = NULL; 1018 } 1019 1020 amdgpu_dm_irq_fini(adev); 1021 1022 /* DC Destroy TODO: Replace destroy DAL */ 1023 if (adev->dm.dc) 1024 dc_destroy(&adev->dm.dc); 1025 1026 if (adev->dm.cgs_device) { 1027 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1028 adev->dm.cgs_device = NULL; 1029 } 1030 if (adev->dm.freesync_module) { 1031 mod_freesync_destroy(adev->dm.freesync_module); 1032 adev->dm.freesync_module = NULL; 1033 } 1034 1035 if (adev->dm.power_module) { 1036 mod_power_destroy(adev->dm.power_module); 1037 adev->dm.power_module = NULL; 1038 } 1039 mutex_destroy(&adev->dm.audio_lock); 1040 mutex_destroy(&adev->dm.dc_lock); 1041 mutex_destroy(&adev->dm.dpia_aux_lock); 1042 } 1043 1044 static int load_dmcu_fw(struct amdgpu_device *adev) 1045 { 1046 const char *fw_name_dmcu = NULL; 1047 int r; 1048 const struct dmcu_firmware_header_v1_0 *hdr; 1049 1050 switch (adev->asic_type) { 1051 #if defined(CONFIG_DRM_AMD_DC_SI) 1052 case CHIP_TAHITI: 1053 case CHIP_PITCAIRN: 1054 case CHIP_VERDE: 1055 case CHIP_OLAND: 1056 #endif 1057 case CHIP_BONAIRE: 1058 case CHIP_HAWAII: 1059 case CHIP_KAVERI: 1060 case CHIP_KABINI: 1061 case CHIP_MULLINS: 1062 case CHIP_TONGA: 1063 case CHIP_FIJI: 1064 case CHIP_CARRIZO: 1065 case CHIP_STONEY: 1066 case CHIP_POLARIS11: 1067 case CHIP_POLARIS10: 1068 case CHIP_POLARIS12: 1069 case CHIP_VEGAM: 1070 case CHIP_VEGA10: 1071 case CHIP_VEGA12: 1072 case CHIP_VEGA20: 1073 return 0; 1074 case CHIP_NAVI12: 1075 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1076 break; 1077 case CHIP_RAVEN: 1078 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1079 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1080 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1081 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1082 else 1083 return 0; 1084 break; 1085 default: 1086 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1087 case IP_VERSION(2, 0, 2): 1088 case IP_VERSION(2, 0, 3): 1089 case IP_VERSION(2, 0, 0): 1090 case IP_VERSION(2, 1, 0): 1091 case IP_VERSION(3, 0, 0): 1092 case IP_VERSION(3, 0, 2): 1093 case IP_VERSION(3, 0, 3): 1094 case IP_VERSION(3, 0, 1): 1095 case IP_VERSION(3, 1, 2): 1096 case IP_VERSION(3, 1, 3): 1097 case IP_VERSION(3, 1, 4): 1098 case IP_VERSION(3, 1, 5): 1099 case IP_VERSION(3, 1, 6): 1100 case IP_VERSION(3, 2, 0): 1101 case IP_VERSION(3, 2, 1): 1102 case IP_VERSION(3, 5, 0): 1103 case IP_VERSION(3, 5, 1): 1104 case IP_VERSION(3, 6, 0): 1105 case IP_VERSION(4, 0, 1): 1106 case IP_VERSION(4, 2, 0): 1107 case IP_VERSION(4, 2, 1): 1108 return 0; 1109 default: 1110 break; 1111 } 1112 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1113 return -EINVAL; 1114 } 1115 1116 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1117 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1118 return 0; 1119 } 1120 1121 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1122 "%s", fw_name_dmcu); 1123 if (r == -ENODEV) { 1124 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1125 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1126 adev->dm.fw_dmcu = NULL; 1127 return 0; 1128 } 1129 if (r) { 1130 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1131 fw_name_dmcu); 1132 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1133 return r; 1134 } 1135 1136 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1137 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1138 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1139 adev->firmware.fw_size += 1140 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1141 1142 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1143 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1144 adev->firmware.fw_size += 1145 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1146 1147 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1148 1149 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1150 1151 return 0; 1152 } 1153 1154 static int dm_sw_init(struct amdgpu_ip_block *ip_block) 1155 { 1156 struct amdgpu_device *adev = ip_block->adev; 1157 int r; 1158 1159 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1160 1161 if (!adev->dm.cgs_device) { 1162 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1163 return -EINVAL; 1164 } 1165 1166 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1167 INIT_LIST_HEAD(&adev->dm.da_list); 1168 1169 r = dm_dmub_sw_init(adev); 1170 if (r) 1171 return r; 1172 1173 return load_dmcu_fw(adev); 1174 } 1175 1176 static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1177 { 1178 struct amdgpu_device *adev = ip_block->adev; 1179 struct dal_allocation *da; 1180 1181 list_for_each_entry(da, &adev->dm.da_list, list) { 1182 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1183 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1184 list_del(&da->list); 1185 kfree(da); 1186 adev->dm.bb_from_dmub = NULL; 1187 break; 1188 } 1189 } 1190 1191 1192 kfree(adev->dm.dmub_fb_info); 1193 adev->dm.dmub_fb_info = NULL; 1194 1195 if (adev->dm.dmub_srv) { 1196 dmub_srv_destroy(adev->dm.dmub_srv); 1197 kfree(adev->dm.dmub_srv); 1198 adev->dm.dmub_srv = NULL; 1199 } 1200 1201 amdgpu_ucode_release(&adev->dm.dmub_fw); 1202 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1203 1204 return 0; 1205 } 1206 1207 1208 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1209 { 1210 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1211 struct dmub_srv *dmub = NULL; 1212 union dmub_fw_boot_options option = {0}; 1213 int ret = 0; 1214 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1215 1216 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1217 !adev->dm.dc->ctx->dmub_srv) { 1218 return; 1219 } 1220 1221 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1222 bootcrc_info = &adev->dm.boot_time_crc_info; 1223 1224 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1225 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1226 return; 1227 } 1228 1229 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1230 1231 /* Return if boot time CRC is not enabled */ 1232 if (option.bits.bootcrc_en_at_S0i3 == 0) 1233 return; 1234 1235 /* Create a buffer for boot time CRC */ 1236 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1237 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1238 &bootcrc_info->bo_ptr, 1239 &bootcrc_info->gpu_addr, 1240 &bootcrc_info->cpu_addr); 1241 1242 if (ret) { 1243 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1244 } else { 1245 bootcrc_info->size = fb_size; 1246 1247 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1248 bootcrc_info->gpu_addr, bootcrc_info->size); 1249 1250 /* Send the buffer info to DMUB */ 1251 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1252 bootcrc_info->gpu_addr, bootcrc_info->size); 1253 } 1254 } 1255 1256 static int dm_late_init(struct amdgpu_ip_block *ip_block) 1257 { 1258 struct amdgpu_device *adev = ip_block->adev; 1259 1260 struct dmcu_iram_parameters params; 1261 unsigned int linear_lut[16]; 1262 int i; 1263 struct dmcu *dmcu = NULL; 1264 1265 dmcu = adev->dm.dc->res_pool->dmcu; 1266 1267 /* Init the boot time CRC (skip in resume) */ 1268 if ((adev->in_suspend == 0) && 1269 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1270 amdgpu_dm_boot_time_crc_init(adev); 1271 1272 for (i = 0; i < 16; i++) 1273 linear_lut[i] = 0xFFFF * i / 15; 1274 1275 params.set = 0; 1276 params.backlight_ramping_override = false; 1277 params.backlight_ramping_start = 0xCCCC; 1278 params.backlight_ramping_reduction = 0xCCCCCCCC; 1279 params.backlight_lut_array_size = 16; 1280 params.backlight_lut_array = linear_lut; 1281 1282 /* Min backlight level after ABM reduction, Don't allow below 1% 1283 * 0xFFFF x 0.01 = 0x28F 1284 */ 1285 params.min_abm_backlight = 0x28F; 1286 /* In the case where abm is implemented on dmcub, 1287 * dmcu object will be null. 1288 * ABM 2.4 and up are implemented on dmcub. 1289 */ 1290 if (dmcu) { 1291 if (!dmcu_load_iram(dmcu, params)) 1292 return -EINVAL; 1293 } else if (adev->dm.dc->ctx->dmub_srv) { 1294 struct dc_link *edp_links[MAX_NUM_EDP]; 1295 int edp_num; 1296 1297 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1298 for (i = 0; i < edp_num; i++) { 1299 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1300 return -EINVAL; 1301 } 1302 } 1303 1304 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1305 } 1306 1307 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1308 { 1309 u8 buf[UUID_SIZE]; 1310 guid_t guid; 1311 int ret; 1312 1313 mutex_lock(&mgr->lock); 1314 if (!mgr->mst_primary) 1315 goto out_fail; 1316 1317 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1318 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1319 goto out_fail; 1320 } 1321 1322 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1323 DP_MST_EN | 1324 DP_UP_REQ_EN | 1325 DP_UPSTREAM_IS_SRC); 1326 if (ret < 0) { 1327 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1328 goto out_fail; 1329 } 1330 1331 /* Some hubs forget their guids after they resume */ 1332 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1333 if (ret != sizeof(buf)) { 1334 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1335 goto out_fail; 1336 } 1337 1338 import_guid(&guid, buf); 1339 1340 if (guid_is_null(&guid)) { 1341 guid_gen(&guid); 1342 export_guid(buf, &guid); 1343 1344 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1345 1346 if (ret != sizeof(buf)) { 1347 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1348 goto out_fail; 1349 } 1350 } 1351 1352 guid_copy(&mgr->mst_primary->guid, &guid); 1353 1354 out_fail: 1355 mutex_unlock(&mgr->lock); 1356 } 1357 1358 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1359 { 1360 struct amdgpu_dm_connector *aconnector; 1361 struct drm_connector *connector; 1362 struct drm_connector_list_iter iter; 1363 struct drm_dp_mst_topology_mgr *mgr; 1364 1365 drm_connector_list_iter_begin(dev, &iter); 1366 drm_for_each_connector_iter(connector, &iter) { 1367 1368 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1369 continue; 1370 1371 aconnector = to_amdgpu_dm_connector(connector); 1372 if (aconnector->dc_link->type != dc_connection_mst_branch || 1373 aconnector->mst_root) 1374 continue; 1375 1376 mgr = &aconnector->mst_mgr; 1377 1378 if (suspend) { 1379 drm_dp_mst_topology_mgr_suspend(mgr); 1380 } else { 1381 /* if extended timeout is supported in hardware, 1382 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1383 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1384 */ 1385 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1386 if (!dp_is_lttpr_present(aconnector->dc_link)) 1387 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1388 1389 /* TODO: move resume_mst_branch_status() into drm mst resume again 1390 * once topology probing work is pulled out from mst resume into mst 1391 * resume 2nd step. mst resume 2nd step should be called after old 1392 * state getting restored (i.e. drm_atomic_helper_resume()). 1393 */ 1394 resume_mst_branch_status(mgr); 1395 } 1396 } 1397 drm_connector_list_iter_end(&iter); 1398 } 1399 1400 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 1401 { 1402 int ret = 0; 1403 1404 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 1405 * on window driver dc implementation. 1406 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 1407 * should be passed to smu during boot up and resume from s3. 1408 * boot up: dc calculate dcn watermark clock settings within dc_create, 1409 * dcn20_resource_construct 1410 * then call pplib functions below to pass the settings to smu: 1411 * smu_set_watermarks_for_clock_ranges 1412 * smu_set_watermarks_table 1413 * navi10_set_watermarks_table 1414 * smu_write_watermarks_table 1415 * 1416 * For Renoir, clock settings of dcn watermark are also fixed values. 1417 * dc has implemented different flow for window driver: 1418 * dc_hardware_init / dc_set_power_state 1419 * dcn10_init_hw 1420 * notify_wm_ranges 1421 * set_wm_ranges 1422 * -- Linux 1423 * smu_set_watermarks_for_clock_ranges 1424 * renoir_set_watermarks_table 1425 * smu_write_watermarks_table 1426 * 1427 * For Linux, 1428 * dc_hardware_init -> amdgpu_dm_init 1429 * dc_set_power_state --> dm_resume 1430 * 1431 * therefore, this function apply to navi10/12/14 but not Renoir 1432 * * 1433 */ 1434 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1435 case IP_VERSION(2, 0, 2): 1436 case IP_VERSION(2, 0, 0): 1437 break; 1438 default: 1439 return 0; 1440 } 1441 1442 ret = amdgpu_dpm_write_watermarks_table(adev); 1443 if (ret) { 1444 drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); 1445 return ret; 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1452 { 1453 struct amdgpu_display_manager *dm = &adev->dm; 1454 struct amdgpu_i2c_adapter *oem_i2c; 1455 struct ddc_service *oem_ddc_service; 1456 int r; 1457 1458 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1459 if (oem_ddc_service) { 1460 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1461 if (!oem_i2c) { 1462 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1463 return -ENOMEM; 1464 } 1465 1466 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1467 if (r) { 1468 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1469 kfree(oem_i2c); 1470 return r; 1471 } 1472 dm->oem_i2c = oem_i2c; 1473 } 1474 1475 return 0; 1476 } 1477 1478 /** 1479 * dm_hw_init() - Initialize DC device 1480 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1481 * 1482 * Initialize the &struct amdgpu_display_manager device. This involves calling 1483 * the initializers of each DM component, then populating the struct with them. 1484 * 1485 * Although the function implies hardware initialization, both hardware and 1486 * software are initialized here. Splitting them out to their relevant init 1487 * hooks is a future TODO item. 1488 * 1489 * Some notable things that are initialized here: 1490 * 1491 * - Display Core, both software and hardware 1492 * - DC modules that we need (freesync and color management) 1493 * - DRM software states 1494 * - Interrupt sources and handlers 1495 * - Vblank support 1496 * - Debug FS entries, if enabled 1497 */ 1498 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1499 { 1500 struct amdgpu_device *adev = ip_block->adev; 1501 int r; 1502 1503 adev->dm.i2c_devres_group = devres_open_group(adev->dev, NULL, GFP_KERNEL); 1504 if (!adev->dm.i2c_devres_group) 1505 return -ENOMEM; 1506 1507 /* Create DAL display manager */ 1508 r = amdgpu_dm_init(adev); 1509 if (r) 1510 goto err_release_i2c; 1511 amdgpu_dm_hpd_init(adev); 1512 1513 r = dm_oem_i2c_hw_init(adev); 1514 if (r) 1515 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1516 1517 devres_close_group(adev->dev, adev->dm.i2c_devres_group); 1518 return 0; 1519 1520 err_release_i2c: 1521 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1522 return r; 1523 } 1524 1525 /** 1526 * dm_hw_fini() - Teardown DC device 1527 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1528 * 1529 * Teardown components within &struct amdgpu_display_manager that require 1530 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1531 * were loaded. Also flush IRQ workqueues and disable them. 1532 */ 1533 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1534 { 1535 struct amdgpu_device *adev = ip_block->adev; 1536 1537 if (adev->dm.i2c_devres_group) 1538 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1539 1540 amdgpu_dm_hpd_fini(adev); 1541 1542 amdgpu_dm_fini(adev); 1543 return 0; 1544 } 1545 1546 1547 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1548 struct dc_state *state, bool enable) 1549 { 1550 enum dc_irq_source irq_source; 1551 struct amdgpu_crtc *acrtc; 1552 int rc = -EBUSY; 1553 int i = 0; 1554 1555 for (i = 0; i < state->stream_count; i++) { 1556 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1557 adev, state->stream_status[i].primary_otg_inst); 1558 1559 if (acrtc && state->stream_status[i].plane_count != 0 && 1560 amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 1561 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1562 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1563 if (rc) 1564 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1565 enable ? "enable" : "disable"); 1566 1567 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1568 if (enable) { 1569 if (amdgpu_dm_crtc_vrr_active( 1570 to_dm_crtc_state(acrtc->base.state))) 1571 rc = amdgpu_dm_crtc_set_vupdate_irq( 1572 &acrtc->base, true); 1573 } else 1574 rc = amdgpu_dm_crtc_set_vupdate_irq( 1575 &acrtc->base, false); 1576 1577 if (rc) 1578 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1579 enable ? "en" : "dis"); 1580 } 1581 1582 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1583 /* During gpu-reset we disable and then enable vblank irq, so 1584 * don't use amdgpu_irq_get/put() to avoid refcount change. 1585 */ 1586 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 1587 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1588 1589 } else if (acrtc && state->stream_status[i].plane_count != 0) { 1590 /* DCN only needs to toggle VUPDATE_NO_LOCK */ 1591 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, enable); 1592 if (rc) 1593 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1594 enable ? "en" : "dis"); 1595 } 1596 } 1597 1598 } 1599 1600 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 1601 1602 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1603 { 1604 struct dc_state *context __free(state_release) = NULL; 1605 int i; 1606 struct dc_stream_state *del_streams[MAX_PIPES]; 1607 int del_streams_count = 0; 1608 struct dc_commit_streams_params params = {}; 1609 1610 memset(del_streams, 0, sizeof(del_streams)); 1611 1612 context = dc_state_create_current_copy(dc); 1613 if (context == NULL) 1614 return DC_ERROR_UNEXPECTED; 1615 1616 /* First remove from context all streams */ 1617 for (i = 0; i < context->stream_count; i++) { 1618 struct dc_stream_state *stream = context->streams[i]; 1619 1620 del_streams[del_streams_count++] = stream; 1621 } 1622 1623 /* Remove all planes for removed streams and then remove the streams */ 1624 for (i = 0; i < del_streams_count; i++) { 1625 enum dc_status res; 1626 1627 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1628 return DC_FAIL_DETACH_SURFACES; 1629 1630 res = dc_state_remove_stream(dc, context, del_streams[i]); 1631 if (res != DC_OK) 1632 return res; 1633 } 1634 1635 params.streams = context->streams; 1636 params.stream_count = context->stream_count; 1637 1638 return dc_commit_streams(dc, ¶ms); 1639 } 1640 1641 static int dm_cache_state(struct amdgpu_device *adev) 1642 { 1643 int r; 1644 1645 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1646 if (IS_ERR(adev->dm.cached_state)) { 1647 r = PTR_ERR(adev->dm.cached_state); 1648 adev->dm.cached_state = NULL; 1649 } 1650 1651 return adev->dm.cached_state ? 0 : r; 1652 } 1653 1654 static void dm_destroy_cached_state(struct amdgpu_device *adev) 1655 { 1656 struct amdgpu_display_manager *dm = &adev->dm; 1657 struct drm_device *ddev = adev_to_drm(adev); 1658 struct dm_plane_state *dm_new_plane_state; 1659 struct drm_plane_state *new_plane_state; 1660 struct dm_crtc_state *dm_new_crtc_state; 1661 struct drm_crtc_state *new_crtc_state; 1662 struct drm_plane *plane; 1663 struct drm_crtc *crtc; 1664 int i; 1665 1666 if (!dm->cached_state) 1667 return; 1668 1669 /* Force mode set in atomic commit */ 1670 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1671 new_crtc_state->active_changed = true; 1672 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1673 reset_freesync_config_for_crtc(dm_new_crtc_state); 1674 } 1675 1676 /* 1677 * atomic_check is expected to create the dc states. We need to release 1678 * them here, since they were duplicated as part of the suspend 1679 * procedure. 1680 */ 1681 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1682 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1683 if (dm_new_crtc_state->stream) { 1684 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1685 dc_stream_release(dm_new_crtc_state->stream); 1686 dm_new_crtc_state->stream = NULL; 1687 } 1688 dm_new_crtc_state->base.color_mgmt_changed = true; 1689 } 1690 1691 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1692 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1693 if (dm_new_plane_state->dc_state) { 1694 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1695 dc_plane_state_release(dm_new_plane_state->dc_state); 1696 dm_new_plane_state->dc_state = NULL; 1697 } 1698 } 1699 1700 drm_atomic_helper_resume(ddev, dm->cached_state); 1701 1702 dm->cached_state = NULL; 1703 } 1704 1705 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1706 { 1707 struct amdgpu_device *adev = ip_block->adev; 1708 struct amdgpu_display_manager *dm = &adev->dm; 1709 1710 if (amdgpu_in_reset(adev)) { 1711 enum dc_status res; 1712 1713 /* Quiesce ISM workers before taking dc_lock (workers take 1714 * dc_lock themselves; syncing under it would deadlock). 1715 */ 1716 amdgpu_dm_ism_disable(dm); 1717 1718 mutex_lock(&dm->dc_lock); 1719 1720 amdgpu_dm_ism_force_full_power(dm); 1721 dc_allow_idle_optimizations(adev->dm.dc, false); 1722 1723 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1724 1725 if (dm->cached_dc_state) 1726 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1727 1728 res = amdgpu_dm_commit_zero_streams(dm->dc); 1729 if (res != DC_OK) { 1730 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1731 return -EINVAL; 1732 } 1733 1734 amdgpu_dm_irq_suspend(adev); 1735 1736 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1737 1738 return 0; 1739 } 1740 1741 if (!adev->dm.cached_state) { 1742 int r = dm_cache_state(adev); 1743 1744 if (r) 1745 return r; 1746 } 1747 1748 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1749 1750 s3_handle_mst(adev_to_drm(adev), true); 1751 1752 amdgpu_dm_irq_suspend(adev); 1753 1754 /* 1755 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1756 * themselves; syncing under it would deadlock). 1757 */ 1758 amdgpu_dm_ism_disable(dm); 1759 scoped_guard(mutex, &dm->dc_lock) 1760 amdgpu_dm_ism_force_full_power(dm); 1761 1762 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1763 1764 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1765 1766 if (dm->dc->caps.ips_support && adev->in_s0ix) 1767 dc_allow_idle_optimizations(dm->dc, true); 1768 1769 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1770 1771 return 0; 1772 } 1773 1774 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1775 { 1776 struct dc_sink_init_data sink_init_data = { 0 }; 1777 struct display_sink_capability sink_caps = { 0 }; 1778 enum dc_edid_status edid_status; 1779 struct dc_context *dc_ctx = link->ctx; 1780 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1781 struct dc_sink *sink = NULL; 1782 struct dc_sink *prev_sink = NULL; 1783 1784 link->type = dc_connection_none; 1785 prev_sink = link->local_sink; 1786 1787 if (prev_sink) 1788 dc_sink_release(prev_sink); 1789 1790 switch (link->connector_signal) { 1791 case SIGNAL_TYPE_HDMI_TYPE_A: { 1792 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1793 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1794 break; 1795 } 1796 1797 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1798 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1799 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1800 break; 1801 } 1802 1803 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1804 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1805 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1806 break; 1807 } 1808 1809 case SIGNAL_TYPE_LVDS: { 1810 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1811 sink_caps.signal = SIGNAL_TYPE_LVDS; 1812 break; 1813 } 1814 1815 case SIGNAL_TYPE_EDP: { 1816 sink_caps.transaction_type = 1817 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1818 sink_caps.signal = SIGNAL_TYPE_EDP; 1819 break; 1820 } 1821 1822 case SIGNAL_TYPE_DISPLAY_PORT: { 1823 sink_caps.transaction_type = 1824 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1825 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1826 break; 1827 } 1828 1829 default: 1830 drm_err(dev, "Invalid connector type! signal:%d\n", 1831 link->connector_signal); 1832 return; 1833 } 1834 1835 sink_init_data.link = link; 1836 sink_init_data.sink_signal = sink_caps.signal; 1837 1838 sink = dc_sink_create(&sink_init_data); 1839 if (!sink) { 1840 drm_err(dev, "Failed to create sink!\n"); 1841 return; 1842 } 1843 1844 /* dc_sink_create returns a new reference */ 1845 link->local_sink = sink; 1846 1847 edid_status = dm_helpers_read_local_edid( 1848 link->ctx, 1849 link, 1850 sink); 1851 1852 if (edid_status != EDID_OK) 1853 drm_err(dev, "Failed to read EDID\n"); 1854 1855 } 1856 1857 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1858 struct amdgpu_display_manager *dm) 1859 { 1860 struct { 1861 struct dc_surface_update surface_updates[MAX_SURFACES]; 1862 struct dc_plane_info plane_infos[MAX_SURFACES]; 1863 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1864 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1865 struct dc_stream_update stream_update; 1866 } *bundle __free(kfree); 1867 int k, m; 1868 1869 bundle = kzalloc_obj(*bundle); 1870 1871 if (!bundle) { 1872 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1873 return; 1874 } 1875 1876 for (k = 0; k < dc_state->stream_count; k++) { 1877 bundle->stream_update.stream = dc_state->streams[k]; 1878 1879 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1880 bundle->surface_updates[m].surface = 1881 dc_state->stream_status[k].plane_states[m]; 1882 bundle->surface_updates[m].surface->force_full_update = 1883 true; 1884 } 1885 1886 update_planes_and_stream_adapter(dm->dc, 1887 UPDATE_TYPE_FULL, 1888 dc_state->stream_status[k].plane_count, 1889 dc_state->streams[k], 1890 &bundle->stream_update, 1891 bundle->surface_updates); 1892 } 1893 } 1894 1895 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1896 struct dc_sink *sink) 1897 { 1898 struct dc_panel_patch *ppatch = NULL; 1899 1900 if (!sink) 1901 return; 1902 1903 ppatch = &sink->edid_caps.panel_patch; 1904 if (ppatch->wait_after_dpcd_poweroff_ms) { 1905 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1906 drm_dbg_driver(adev_to_drm(adev), 1907 "%s: adding a %ds delay as w/a for panel\n", 1908 __func__, 1909 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1910 } 1911 } 1912 1913 /** 1914 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1915 * @adev: amdgpu device pointer 1916 * 1917 * Iterates through all DC links and dumps information about local and remote 1918 * (MST) sinks. Should be called after connector detection is complete to see 1919 * the final state of all links. 1920 */ 1921 static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1922 { 1923 struct dc *dc = adev->dm.dc; 1924 struct drm_device *dev = adev_to_drm(adev); 1925 int li; 1926 1927 if (!dc) 1928 return; 1929 1930 for (li = 0; li < dc->link_count; li++) { 1931 struct dc_link *l = dc->links[li]; 1932 const char *name = NULL; 1933 int rs; 1934 1935 if (!l) 1936 continue; 1937 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1938 name = l->local_sink->edid_caps.display_name; 1939 else 1940 name = "n/a"; 1941 1942 drm_dbg_kms(dev, 1943 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1944 li, 1945 l->local_sink, 1946 l->type, 1947 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1948 l->sink_count, 1949 name, 1950 l->dpcd_caps.is_mst_capable, 1951 l->mst_stream_alloc_table.stream_count); 1952 1953 /* Dump remote (MST) sinks if any */ 1954 for (rs = 0; rs < l->sink_count; rs++) { 1955 struct dc_sink *rsink = l->remote_sinks[rs]; 1956 const char *rname = NULL; 1957 1958 if (!rsink) 1959 continue; 1960 if (rsink->edid_caps.display_name[0]) 1961 rname = rsink->edid_caps.display_name; 1962 else 1963 rname = "n/a"; 1964 drm_dbg_kms(dev, 1965 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1966 li, rs, 1967 rsink, 1968 rsink->sink_signal, 1969 rname); 1970 } 1971 } 1972 } 1973 1974 static int dm_resume(struct amdgpu_ip_block *ip_block) 1975 { 1976 struct amdgpu_device *adev = ip_block->adev; 1977 struct drm_device *ddev = adev_to_drm(adev); 1978 struct amdgpu_display_manager *dm = &adev->dm; 1979 struct amdgpu_dm_connector *aconnector; 1980 struct drm_connector *connector; 1981 struct drm_connector_list_iter iter; 1982 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1983 enum dc_connection_type new_connection_type = dc_connection_none; 1984 struct dc_state *dc_state; 1985 int i, r, j; 1986 struct dc_commit_streams_params commit_params = {}; 1987 1988 if (dm->dc->caps.ips_support) { 1989 if (!amdgpu_in_reset(adev)) 1990 mutex_lock(&dm->dc_lock); 1991 1992 /* Need to set POWER_STATE_D0 first or it will not execute 1993 * idle_power_optimizations command to DMUB. 1994 */ 1995 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1996 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 1997 1998 if (!amdgpu_in_reset(adev)) 1999 mutex_unlock(&dm->dc_lock); 2000 } 2001 2002 if (amdgpu_in_reset(adev)) { 2003 dc_state = dm->cached_dc_state; 2004 2005 /* 2006 * The dc->current_state is backed up into dm->cached_dc_state 2007 * before we commit 0 streams. 2008 * 2009 * DC will clear link encoder assignments on the real state 2010 * but the changes won't propagate over to the copy we made 2011 * before the 0 streams commit. 2012 * 2013 * DC expects that link encoder assignments are *not* valid 2014 * when committing a state, so as a workaround we can copy 2015 * off of the current state. 2016 * 2017 * We lose the previous assignments, but we had already 2018 * commit 0 streams anyway. 2019 */ 2020 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2021 2022 r = dm_dmub_hw_init(adev); 2023 if (r) { 2024 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 2025 return r; 2026 } 2027 2028 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2029 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2030 2031 dc_resume(dm->dc); 2032 2033 amdgpu_dm_ism_enable(dm); 2034 amdgpu_dm_irq_resume_early(adev); 2035 2036 for (i = 0; i < dc_state->stream_count; i++) { 2037 dc_state->streams[i]->mode_changed = true; 2038 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2039 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 2040 } 2041 } 2042 2043 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2044 amdgpu_dm_outbox_init(adev); 2045 dc_enable_dmub_outbox(adev->dm.dc); 2046 } 2047 2048 commit_params.streams = dc_state->streams; 2049 commit_params.stream_count = dc_state->stream_count; 2050 dc_exit_ips_for_hw_access(dm->dc); 2051 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 2052 2053 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2054 2055 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2056 2057 dc_state_release(dm->cached_dc_state); 2058 dm->cached_dc_state = NULL; 2059 2060 amdgpu_dm_irq_resume_late(adev); 2061 2062 mutex_unlock(&dm->dc_lock); 2063 2064 /* set the backlight after a reset */ 2065 for (i = 0; i < dm->num_of_edps; i++) { 2066 if (dm->backlight_dev[i]) 2067 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 2068 } 2069 2070 return 0; 2071 } 2072 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2073 dc_state_release(dm_state->context); 2074 dm_state->context = dc_state_create(dm->dc, NULL); 2075 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2076 2077 /* Before powering on DC we need to re-initialize DMUB. */ 2078 dm_dmub_hw_resume(adev); 2079 2080 /* Re-enable outbox interrupts for DPIA. */ 2081 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2082 amdgpu_dm_outbox_init(adev); 2083 dc_enable_dmub_outbox(adev->dm.dc); 2084 } 2085 2086 /* power on hardware */ 2087 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2088 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2089 2090 /* program HPD filter */ 2091 dc_resume(dm->dc); 2092 2093 scoped_guard(mutex, &dm->dc_lock) 2094 amdgpu_dm_ism_enable(dm); 2095 2096 /* 2097 * early enable HPD Rx IRQ, should be done before set mode as short 2098 * pulse interrupts are used for MST 2099 */ 2100 amdgpu_dm_irq_resume_early(adev); 2101 2102 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 2103 2104 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2105 s3_handle_mst(ddev, false); 2106 2107 /* Do detection*/ 2108 drm_connector_list_iter_begin(ddev, &iter); 2109 drm_for_each_connector_iter(connector, &iter) { 2110 bool ret; 2111 2112 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2113 continue; 2114 2115 aconnector = to_amdgpu_dm_connector(connector); 2116 2117 if (!aconnector->dc_link) 2118 continue; 2119 2120 /* 2121 * this is the case when traversing through already created end sink 2122 * MST connectors, should be skipped 2123 */ 2124 if (aconnector->mst_root) 2125 continue; 2126 2127 /* Skip eDP detection, when there is no sink present */ 2128 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 2129 !aconnector->dc_link->edp_sink_present) 2130 continue; 2131 2132 guard(mutex)(&aconnector->hpd_lock); 2133 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2134 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2135 2136 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2137 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 2138 } else { 2139 guard(mutex)(&dm->dc_lock); 2140 dc_exit_ips_for_hw_access(dm->dc); 2141 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 2142 if (ret) { 2143 /* w/a delay for certain panels */ 2144 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2145 } 2146 } 2147 2148 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2149 aconnector->fake_enable = false; 2150 2151 if (aconnector->dc_sink) 2152 dc_sink_release(aconnector->dc_sink); 2153 aconnector->dc_sink = NULL; 2154 amdgpu_dm_update_connector_after_detect(aconnector); 2155 } 2156 drm_connector_list_iter_end(&iter); 2157 2158 dm_destroy_cached_state(adev); 2159 2160 /* Do mst topology probing after resuming cached state*/ 2161 drm_connector_list_iter_begin(ddev, &iter); 2162 drm_for_each_connector_iter(connector, &iter) { 2163 bool init = false; 2164 2165 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2166 continue; 2167 2168 aconnector = to_amdgpu_dm_connector(connector); 2169 if (aconnector->dc_link->type != dc_connection_mst_branch || 2170 aconnector->mst_root) 2171 continue; 2172 2173 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2174 init = !aconnector->mst_mgr.mst_primary; 2175 } 2176 if (init) 2177 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2178 aconnector->dc_link, false); 2179 else 2180 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2181 } 2182 drm_connector_list_iter_end(&iter); 2183 2184 /* Debug dump: list all DC links and their associated sinks after detection 2185 * is complete for all connectors. This provides a comprehensive view of the 2186 * final state without repeating the dump for each connector. 2187 */ 2188 amdgpu_dm_dump_links_and_sinks(adev); 2189 2190 amdgpu_dm_irq_resume_late(adev); 2191 2192 amdgpu_dm_smu_write_watermarks_table(adev); 2193 2194 drm_kms_helper_hotplug_event(ddev); 2195 2196 return 0; 2197 } 2198 2199 /** 2200 * DOC: DM Lifecycle 2201 * 2202 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2203 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2204 * the base driver's device list to be initialized and torn down accordingly. 2205 * 2206 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2207 */ 2208 2209 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2210 .name = "dm", 2211 .early_init = dm_early_init, 2212 .late_init = dm_late_init, 2213 .sw_init = dm_sw_init, 2214 .sw_fini = dm_sw_fini, 2215 .early_fini = amdgpu_dm_early_fini, 2216 .hw_init = dm_hw_init, 2217 .hw_fini = dm_hw_fini, 2218 .suspend = dm_suspend, 2219 .resume = dm_resume, 2220 .is_idle = dm_is_idle, 2221 .wait_for_idle = dm_wait_for_idle, 2222 .soft_reset = dm_soft_reset, 2223 .set_clockgating_state = dm_set_clockgating_state, 2224 .set_powergating_state = dm_set_powergating_state, 2225 }; 2226 2227 const struct amdgpu_ip_block_version dm_ip_block = { 2228 .type = AMD_IP_BLOCK_TYPE_DCE, 2229 .major = 1, 2230 .minor = 0, 2231 .rev = 0, 2232 .funcs = &amdgpu_dm_funcs, 2233 }; 2234 2235 2236 /** 2237 * DOC: atomic 2238 * 2239 * *WIP* 2240 */ 2241 2242 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2243 .fb_create = amdgpu_display_user_framebuffer_create, 2244 .get_format_info = amdgpu_dm_plane_get_format_info, 2245 .atomic_check = amdgpu_dm_atomic_check, 2246 .atomic_commit = drm_atomic_helper_commit, 2247 }; 2248 2249 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2250 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2251 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2252 }; 2253 2254 /* 2255 * Acquires the lock for the atomic state object and returns 2256 * the new atomic state. 2257 * 2258 * This should only be called during atomic check. 2259 */ 2260 int dm_atomic_get_state(struct drm_atomic_commit *state, 2261 struct dm_atomic_state **dm_state) 2262 { 2263 struct drm_device *dev = state->dev; 2264 struct amdgpu_device *adev = drm_to_adev(dev); 2265 struct amdgpu_display_manager *dm = &adev->dm; 2266 struct drm_private_state *priv_state; 2267 2268 if (*dm_state) 2269 return 0; 2270 2271 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2272 if (IS_ERR(priv_state)) 2273 return PTR_ERR(priv_state); 2274 2275 *dm_state = to_dm_atomic_state(priv_state); 2276 2277 return 0; 2278 } 2279 2280 static struct dm_atomic_state * 2281 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2282 { 2283 struct drm_device *dev = state->dev; 2284 struct amdgpu_device *adev = drm_to_adev(dev); 2285 struct amdgpu_display_manager *dm = &adev->dm; 2286 struct drm_private_obj *obj; 2287 struct drm_private_state *new_obj_state; 2288 int i; 2289 2290 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2291 if (obj->funcs == dm->atomic_obj.funcs) 2292 return to_dm_atomic_state(new_obj_state); 2293 } 2294 2295 return NULL; 2296 } 2297 2298 static struct drm_private_state * 2299 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2300 { 2301 struct dm_atomic_state *old_state, *new_state; 2302 2303 new_state = kzalloc_obj(*new_state); 2304 if (!new_state) 2305 return NULL; 2306 2307 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2308 2309 old_state = to_dm_atomic_state(obj->state); 2310 2311 if (old_state && old_state->context) 2312 new_state->context = dc_state_create_copy(old_state->context); 2313 2314 if (!new_state->context) { 2315 kfree(new_state); 2316 return NULL; 2317 } 2318 2319 return &new_state->base; 2320 } 2321 2322 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 2323 struct drm_private_state *state) 2324 { 2325 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2326 2327 if (dm_state && dm_state->context) 2328 dc_state_release(dm_state->context); 2329 2330 kfree(dm_state); 2331 } 2332 2333 static struct drm_private_state * 2334 dm_atomic_create_state(struct drm_private_obj *obj) 2335 { 2336 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2337 struct dm_atomic_state *dm_state; 2338 struct dc_state *context; 2339 2340 dm_state = kzalloc_obj(*dm_state); 2341 if (!dm_state) 2342 return ERR_PTR(-ENOMEM); 2343 2344 context = dc_state_create_current_copy(adev->dm.dc); 2345 if (!context) { 2346 kfree(dm_state); 2347 return ERR_PTR(-ENOMEM); 2348 } 2349 2350 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2351 dm_state->context = context; 2352 2353 return &dm_state->base; 2354 } 2355 2356 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2357 .atomic_create_state = dm_atomic_create_state, 2358 .atomic_duplicate_state = dm_atomic_duplicate_state, 2359 .atomic_destroy_state = dm_atomic_destroy_state, 2360 }; 2361 2362 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2363 { 2364 int r; 2365 2366 adev->mode_info.mode_config_initialized = true; 2367 2368 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2369 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2370 2371 adev_to_drm(adev)->mode_config.max_width = 16384; 2372 adev_to_drm(adev)->mode_config.max_height = 16384; 2373 2374 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2375 if (adev->asic_type == CHIP_HAWAII) 2376 /* disable prefer shadow for now due to hibernation issues */ 2377 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2378 else 2379 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2380 /* indicates support for immediate flip */ 2381 adev_to_drm(adev)->mode_config.async_page_flip = true; 2382 2383 drm_atomic_private_obj_init(adev_to_drm(adev), 2384 &adev->dm.atomic_obj, 2385 &dm_atomic_state_funcs); 2386 2387 r = amdgpu_display_modeset_create_props(adev); 2388 if (r) 2389 return r; 2390 2391 #ifdef AMD_PRIVATE_COLOR 2392 if (amdgpu_dm_create_color_properties(adev)) 2393 return -ENOMEM; 2394 #endif 2395 2396 r = amdgpu_dm_audio_init(adev); 2397 if (r) 2398 return r; 2399 2400 return 0; 2401 } 2402 2403 static int initialize_plane(struct amdgpu_display_manager *dm, 2404 struct amdgpu_mode_info *mode_info, int plane_id, 2405 enum drm_plane_type plane_type, 2406 const struct dc_plane_cap *plane_cap) 2407 { 2408 struct drm_plane *plane; 2409 unsigned long possible_crtcs; 2410 int ret = 0; 2411 2412 plane = kzalloc_obj(struct drm_plane); 2413 if (!plane) { 2414 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2415 return -ENOMEM; 2416 } 2417 plane->type = plane_type; 2418 2419 /* 2420 * HACK: IGT tests expect that the primary plane for a CRTC 2421 * can only have one possible CRTC. Only expose support for 2422 * any CRTC if they're not going to be used as a primary plane 2423 * for a CRTC - like overlay or underlay planes. 2424 */ 2425 possible_crtcs = 1 << plane_id; 2426 if (plane_id >= dm->dc->caps.max_streams) 2427 possible_crtcs = 0xff; 2428 2429 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2430 2431 if (ret) { 2432 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2433 kfree(plane); 2434 return ret; 2435 } 2436 2437 if (mode_info) 2438 mode_info->planes[plane_id] = plane; 2439 2440 return ret; 2441 } 2442 2443 2444 /* 2445 * In this architecture, the association 2446 * connector -> encoder -> crtc 2447 * id not really requried. The crtc and connector will hold the 2448 * display_index as an abstraction to use with DAL component 2449 * 2450 * Returns 0 on success 2451 */ 2452 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2453 { 2454 struct amdgpu_display_manager *dm = &adev->dm; 2455 s32 i; 2456 struct amdgpu_dm_connector *aconnector = NULL; 2457 struct amdgpu_encoder *aencoder = NULL; 2458 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2459 u32 link_cnt; 2460 s32 primary_planes; 2461 enum dc_connection_type new_connection_type = dc_connection_none; 2462 const struct dc_plane_cap *plane; 2463 bool psr_feature_enabled = false; 2464 bool replay_feature_enabled = false; 2465 int max_overlay = dm->dc->caps.max_slave_planes; 2466 2467 dm->display_indexes_num = dm->dc->caps.max_streams; 2468 /* Update the actual used number of crtc */ 2469 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2470 2471 amdgpu_dm_set_irq_funcs(adev); 2472 2473 link_cnt = dm->dc->caps.max_links; 2474 if (amdgpu_dm_mode_config_init(dm->adev)) { 2475 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2476 return -EINVAL; 2477 } 2478 2479 /* There is one primary plane per CRTC */ 2480 primary_planes = dm->dc->caps.max_streams; 2481 if (primary_planes > AMDGPU_MAX_PLANES) { 2482 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2483 return -EINVAL; 2484 } 2485 2486 /* 2487 * Initialize primary planes, implicit planes for legacy IOCTLS. 2488 * Order is reversed to match iteration order in atomic check. 2489 */ 2490 for (i = (primary_planes - 1); i >= 0; i--) { 2491 plane = &dm->dc->caps.planes[i]; 2492 2493 if (initialize_plane(dm, mode_info, i, 2494 DRM_PLANE_TYPE_PRIMARY, plane)) { 2495 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2496 goto fail; 2497 } 2498 } 2499 2500 /* 2501 * Initialize overlay planes, index starting after primary planes. 2502 * These planes have a higher DRM index than the primary planes since 2503 * they should be considered as having a higher z-order. 2504 * Order is reversed to match iteration order in atomic check. 2505 * 2506 * Only support DCN for now, and only expose one so we don't encourage 2507 * userspace to use up all the pipes. 2508 */ 2509 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2510 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2511 2512 /* Do not create overlay if MPO disabled */ 2513 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2514 break; 2515 2516 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2517 continue; 2518 2519 if (!plane->pixel_format_support.argb8888) 2520 continue; 2521 2522 if (max_overlay-- == 0) 2523 break; 2524 2525 if (initialize_plane(dm, NULL, primary_planes + i, 2526 DRM_PLANE_TYPE_OVERLAY, plane)) { 2527 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2528 goto fail; 2529 } 2530 } 2531 2532 for (i = 0; i < dm->dc->caps.max_streams; i++) 2533 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2534 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2535 goto fail; 2536 } 2537 2538 /* Use Outbox interrupt */ 2539 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2540 case IP_VERSION(3, 0, 0): 2541 case IP_VERSION(3, 1, 2): 2542 case IP_VERSION(3, 1, 3): 2543 case IP_VERSION(3, 1, 4): 2544 case IP_VERSION(3, 1, 5): 2545 case IP_VERSION(3, 1, 6): 2546 case IP_VERSION(3, 2, 0): 2547 case IP_VERSION(3, 2, 1): 2548 case IP_VERSION(2, 1, 0): 2549 case IP_VERSION(3, 5, 0): 2550 case IP_VERSION(3, 5, 1): 2551 case IP_VERSION(3, 6, 0): 2552 case IP_VERSION(4, 0, 1): 2553 case IP_VERSION(4, 2, 0): 2554 case IP_VERSION(4, 2, 1): 2555 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2556 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2557 goto fail; 2558 } 2559 break; 2560 default: 2561 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2562 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2563 } 2564 2565 /* Determine whether to enable PSR support by default. */ 2566 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2567 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2568 case IP_VERSION(3, 1, 2): 2569 case IP_VERSION(3, 1, 3): 2570 case IP_VERSION(3, 1, 4): 2571 case IP_VERSION(3, 1, 5): 2572 case IP_VERSION(3, 1, 6): 2573 case IP_VERSION(3, 2, 0): 2574 case IP_VERSION(3, 2, 1): 2575 case IP_VERSION(3, 5, 0): 2576 case IP_VERSION(3, 5, 1): 2577 case IP_VERSION(3, 6, 0): 2578 case IP_VERSION(4, 0, 1): 2579 case IP_VERSION(4, 2, 0): 2580 case IP_VERSION(4, 2, 1): 2581 psr_feature_enabled = true; 2582 break; 2583 default: 2584 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2585 break; 2586 } 2587 } 2588 2589 /* Determine whether to enable Replay support by default. */ 2590 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2591 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2592 case IP_VERSION(3, 1, 4): 2593 case IP_VERSION(3, 2, 0): 2594 case IP_VERSION(3, 2, 1): 2595 case IP_VERSION(3, 5, 0): 2596 case IP_VERSION(3, 5, 1): 2597 case IP_VERSION(3, 6, 0): 2598 case IP_VERSION(4, 2, 0): 2599 case IP_VERSION(4, 2, 1): 2600 replay_feature_enabled = true; 2601 break; 2602 2603 default: 2604 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2605 break; 2606 } 2607 } 2608 2609 if (link_cnt > MAX_LINKS) { 2610 drm_err(adev_to_drm(adev), 2611 "KMS: Cannot support more than %d display indexes\n", 2612 MAX_LINKS); 2613 goto fail; 2614 } 2615 2616 /* loops over all connectors on the board */ 2617 for (i = 0; i < link_cnt; i++) { 2618 struct dc_link *link = NULL; 2619 2620 link = dc_get_link_at_index(dm->dc, i); 2621 2622 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2623 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2624 2625 if (!wbcon) { 2626 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2627 continue; 2628 } 2629 2630 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2631 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2632 kfree(wbcon); 2633 continue; 2634 } 2635 2636 link->psr_settings.psr_feature_enabled = false; 2637 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2638 2639 continue; 2640 } 2641 2642 aconnector = kzalloc_obj(*aconnector); 2643 if (!aconnector) 2644 goto fail; 2645 2646 aencoder = kzalloc_obj(*aencoder); 2647 if (!aencoder) 2648 goto fail; 2649 2650 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2651 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2652 goto fail; 2653 } 2654 2655 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2656 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2657 goto fail; 2658 } 2659 2660 if (dm->hpd_rx_offload_wq) 2661 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2662 aconnector; 2663 2664 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2665 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2666 2667 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2668 amdgpu_dm_emulated_link_detect(link); 2669 amdgpu_dm_update_connector_after_detect(aconnector); 2670 } else { 2671 bool ret = false; 2672 2673 mutex_lock(&dm->dc_lock); 2674 dc_exit_ips_for_hw_access(dm->dc); 2675 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2676 mutex_unlock(&dm->dc_lock); 2677 2678 if (ret) { 2679 amdgpu_dm_update_connector_after_detect(aconnector); 2680 amdgpu_dm_setup_backlight_device(dm, aconnector); 2681 2682 /* Disable PSR if Replay can be enabled */ 2683 if (replay_feature_enabled) 2684 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2685 psr_feature_enabled = false; 2686 2687 if (psr_feature_enabled) { 2688 amdgpu_dm_set_psr_caps(link, aconnector); 2689 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2690 aconnector->base.name, 2691 link->psr_settings.psr_feature_enabled, 2692 link->psr_settings.psr_version, 2693 link->dpcd_caps.psr_info.psr_version, 2694 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2695 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2696 } 2697 } 2698 } 2699 amdgpu_set_panel_orientation(&aconnector->base); 2700 } 2701 2702 /* Debug dump: list all DC links and their associated sinks after detection 2703 * is complete for all connectors. This provides a comprehensive view of the 2704 * final state without repeating the dump for each connector. 2705 */ 2706 amdgpu_dm_dump_links_and_sinks(adev); 2707 2708 /* Software is initialized. Now we can register interrupt handlers. */ 2709 switch (adev->asic_type) { 2710 #if defined(CONFIG_DRM_AMD_DC_SI) 2711 case CHIP_TAHITI: 2712 case CHIP_PITCAIRN: 2713 case CHIP_VERDE: 2714 case CHIP_OLAND: 2715 #endif 2716 case CHIP_BONAIRE: 2717 case CHIP_HAWAII: 2718 case CHIP_KAVERI: 2719 case CHIP_KABINI: 2720 case CHIP_MULLINS: 2721 case CHIP_TONGA: 2722 case CHIP_FIJI: 2723 case CHIP_CARRIZO: 2724 case CHIP_STONEY: 2725 case CHIP_POLARIS11: 2726 case CHIP_POLARIS10: 2727 case CHIP_POLARIS12: 2728 case CHIP_VEGAM: 2729 case CHIP_VEGA10: 2730 case CHIP_VEGA12: 2731 case CHIP_VEGA20: 2732 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2733 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2734 goto fail; 2735 } 2736 break; 2737 default: 2738 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2739 case IP_VERSION(1, 0, 0): 2740 case IP_VERSION(1, 0, 1): 2741 case IP_VERSION(2, 0, 2): 2742 case IP_VERSION(2, 0, 3): 2743 case IP_VERSION(2, 0, 0): 2744 case IP_VERSION(2, 1, 0): 2745 case IP_VERSION(3, 0, 0): 2746 case IP_VERSION(3, 0, 2): 2747 case IP_VERSION(3, 0, 3): 2748 case IP_VERSION(3, 0, 1): 2749 case IP_VERSION(3, 1, 2): 2750 case IP_VERSION(3, 1, 3): 2751 case IP_VERSION(3, 1, 4): 2752 case IP_VERSION(3, 1, 5): 2753 case IP_VERSION(3, 1, 6): 2754 case IP_VERSION(3, 2, 0): 2755 case IP_VERSION(3, 2, 1): 2756 case IP_VERSION(3, 5, 0): 2757 case IP_VERSION(3, 5, 1): 2758 case IP_VERSION(3, 6, 0): 2759 case IP_VERSION(4, 0, 1): 2760 case IP_VERSION(4, 2, 0): 2761 case IP_VERSION(4, 2, 1): 2762 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2763 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2764 goto fail; 2765 } 2766 break; 2767 default: 2768 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2769 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2770 goto fail; 2771 } 2772 break; 2773 } 2774 2775 return 0; 2776 fail: 2777 kfree(aencoder); 2778 kfree(aconnector); 2779 2780 return -EINVAL; 2781 } 2782 2783 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2784 { 2785 if (dm->atomic_obj.state) 2786 drm_atomic_private_obj_fini(&dm->atomic_obj); 2787 } 2788 2789 /****************************************************************************** 2790 * amdgpu_display_funcs functions 2791 *****************************************************************************/ 2792 2793 /* 2794 * dm_bandwidth_update - program display watermarks 2795 * 2796 * @adev: amdgpu_device pointer 2797 * 2798 * Calculate and program the display watermarks and line buffer allocation. 2799 */ 2800 static void dm_bandwidth_update(struct amdgpu_device *adev) 2801 { 2802 /* TODO: implement later */ 2803 } 2804 2805 static const struct amdgpu_display_funcs dm_display_funcs = { 2806 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2807 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2808 .backlight_set_level = NULL, /* never called for DC */ 2809 .backlight_get_level = NULL, /* never called for DC */ 2810 .hpd_sense = NULL,/* called unconditionally */ 2811 .hpd_set_polarity = NULL, /* called unconditionally */ 2812 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2813 .page_flip_get_scanoutpos = 2814 dm_crtc_get_scanoutpos,/* called unconditionally */ 2815 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2816 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2817 }; 2818 2819 #if defined(CONFIG_DEBUG_KERNEL_DC) 2820 2821 static ssize_t s3_debug_store(struct device *device, 2822 struct device_attribute *attr, 2823 const char *buf, 2824 size_t count) 2825 { 2826 int ret; 2827 int s3_state; 2828 struct drm_device *drm_dev = dev_get_drvdata(device); 2829 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2830 struct amdgpu_ip_block *ip_block; 2831 2832 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2833 if (!ip_block) 2834 return -EINVAL; 2835 2836 ret = kstrtoint(buf, 0, &s3_state); 2837 2838 if (ret == 0) { 2839 if (s3_state) { 2840 dm_resume(ip_block); 2841 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2842 } else 2843 dm_suspend(ip_block); 2844 } 2845 2846 return ret == 0 ? count : 0; 2847 } 2848 2849 DEVICE_ATTR_WO(s3_debug); 2850 2851 #endif 2852 2853 static int dm_early_init(struct amdgpu_ip_block *ip_block) 2854 { 2855 struct amdgpu_device *adev = ip_block->adev; 2856 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2857 struct atom_context *ctx = mode_info->atom_context; 2858 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2859 u16 data_offset; 2860 2861 /* if there is no object header, skip DM */ 2862 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2863 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2864 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2865 return -ENOENT; 2866 } 2867 2868 switch (adev->asic_type) { 2869 #if defined(CONFIG_DRM_AMD_DC_SI) 2870 case CHIP_TAHITI: 2871 case CHIP_PITCAIRN: 2872 case CHIP_VERDE: 2873 adev->mode_info.num_crtc = 6; 2874 adev->mode_info.num_hpd = 6; 2875 adev->mode_info.num_dig = 6; 2876 break; 2877 case CHIP_OLAND: 2878 adev->mode_info.num_crtc = 2; 2879 adev->mode_info.num_hpd = 2; 2880 adev->mode_info.num_dig = 2; 2881 break; 2882 #endif 2883 case CHIP_BONAIRE: 2884 case CHIP_HAWAII: 2885 adev->mode_info.num_crtc = 6; 2886 adev->mode_info.num_hpd = 6; 2887 adev->mode_info.num_dig = 6; 2888 break; 2889 case CHIP_KAVERI: 2890 adev->mode_info.num_crtc = 4; 2891 adev->mode_info.num_hpd = 6; 2892 adev->mode_info.num_dig = 7; 2893 break; 2894 case CHIP_KABINI: 2895 case CHIP_MULLINS: 2896 adev->mode_info.num_crtc = 2; 2897 adev->mode_info.num_hpd = 6; 2898 adev->mode_info.num_dig = 6; 2899 break; 2900 case CHIP_FIJI: 2901 case CHIP_TONGA: 2902 adev->mode_info.num_crtc = 6; 2903 adev->mode_info.num_hpd = 6; 2904 adev->mode_info.num_dig = 7; 2905 break; 2906 case CHIP_CARRIZO: 2907 adev->mode_info.num_crtc = 3; 2908 adev->mode_info.num_hpd = 6; 2909 adev->mode_info.num_dig = 9; 2910 break; 2911 case CHIP_STONEY: 2912 adev->mode_info.num_crtc = 2; 2913 adev->mode_info.num_hpd = 6; 2914 adev->mode_info.num_dig = 9; 2915 break; 2916 case CHIP_POLARIS11: 2917 case CHIP_POLARIS12: 2918 adev->mode_info.num_crtc = 5; 2919 adev->mode_info.num_hpd = 5; 2920 adev->mode_info.num_dig = 5; 2921 break; 2922 case CHIP_POLARIS10: 2923 case CHIP_VEGAM: 2924 adev->mode_info.num_crtc = 6; 2925 adev->mode_info.num_hpd = 6; 2926 adev->mode_info.num_dig = 6; 2927 break; 2928 case CHIP_VEGA10: 2929 case CHIP_VEGA12: 2930 case CHIP_VEGA20: 2931 adev->mode_info.num_crtc = 6; 2932 adev->mode_info.num_hpd = 6; 2933 adev->mode_info.num_dig = 6; 2934 break; 2935 default: 2936 2937 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2938 case IP_VERSION(2, 0, 2): 2939 case IP_VERSION(3, 0, 0): 2940 adev->mode_info.num_crtc = 6; 2941 adev->mode_info.num_hpd = 6; 2942 adev->mode_info.num_dig = 6; 2943 break; 2944 case IP_VERSION(2, 0, 0): 2945 case IP_VERSION(3, 0, 2): 2946 adev->mode_info.num_crtc = 5; 2947 adev->mode_info.num_hpd = 5; 2948 adev->mode_info.num_dig = 5; 2949 break; 2950 case IP_VERSION(2, 0, 3): 2951 case IP_VERSION(3, 0, 3): 2952 adev->mode_info.num_crtc = 2; 2953 adev->mode_info.num_hpd = 2; 2954 adev->mode_info.num_dig = 2; 2955 break; 2956 case IP_VERSION(1, 0, 0): 2957 case IP_VERSION(1, 0, 1): 2958 case IP_VERSION(3, 0, 1): 2959 case IP_VERSION(2, 1, 0): 2960 case IP_VERSION(3, 1, 2): 2961 case IP_VERSION(3, 1, 3): 2962 case IP_VERSION(3, 1, 4): 2963 case IP_VERSION(3, 1, 5): 2964 case IP_VERSION(3, 1, 6): 2965 case IP_VERSION(3, 2, 0): 2966 case IP_VERSION(3, 2, 1): 2967 case IP_VERSION(3, 5, 0): 2968 case IP_VERSION(3, 5, 1): 2969 case IP_VERSION(3, 6, 0): 2970 case IP_VERSION(4, 0, 1): 2971 case IP_VERSION(4, 2, 0): 2972 case IP_VERSION(4, 2, 1): 2973 adev->mode_info.num_crtc = 4; 2974 adev->mode_info.num_hpd = 4; 2975 adev->mode_info.num_dig = 4; 2976 break; 2977 default: 2978 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2979 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2980 return -EINVAL; 2981 } 2982 break; 2983 } 2984 2985 if (adev->mode_info.funcs == NULL) 2986 adev->mode_info.funcs = &dm_display_funcs; 2987 2988 /* 2989 * Note: Do NOT change adev->reg.audio_endpt.rreg and 2990 * adev->reg.audio_endpt.wreg because they are initialised in 2991 * amdgpu_device_init() 2992 */ 2993 #if defined(CONFIG_DEBUG_KERNEL_DC) 2994 device_create_file( 2995 adev_to_drm(adev)->dev, 2996 &dev_attr_s3_debug); 2997 #endif 2998 adev->dc_enabled = true; 2999 3000 return dm_init_microcode(adev); 3001 } 3002 3003 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 3004 { 3005 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 3006 } 3007 EXPORT_IF_KUNIT(modereset_required); 3008 3009 STATIC_IFN_KUNIT int 3010 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 3011 const enum surface_pixel_format format, 3012 enum dc_color_space *color_space) 3013 { 3014 bool full_range; 3015 3016 *color_space = COLOR_SPACE_SRGB; 3017 3018 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 3019 if (plane_state->state && plane_state->state->plane_color_pipeline) 3020 return 0; 3021 3022 /* DRM color properties only affect non-RGB formats. */ 3023 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3024 return 0; 3025 3026 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 3027 3028 switch (plane_state->color_encoding) { 3029 case DRM_COLOR_YCBCR_BT601: 3030 if (full_range) 3031 *color_space = COLOR_SPACE_YCBCR601; 3032 else 3033 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 3034 break; 3035 3036 case DRM_COLOR_YCBCR_BT709: 3037 if (full_range) 3038 *color_space = COLOR_SPACE_YCBCR709; 3039 else 3040 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 3041 break; 3042 3043 case DRM_COLOR_YCBCR_BT2020: 3044 if (full_range) 3045 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 3046 else 3047 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 3048 break; 3049 3050 default: 3051 return -EINVAL; 3052 } 3053 3054 return 0; 3055 } 3056 EXPORT_IF_KUNIT(fill_plane_color_attributes); 3057 3058 static int 3059 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 3060 const struct drm_plane_state *plane_state, 3061 const u64 tiling_flags, 3062 struct dc_plane_info *plane_info, 3063 struct dc_plane_address *address, 3064 bool tmz_surface) 3065 { 3066 const struct drm_framebuffer *fb = plane_state->fb; 3067 const struct amdgpu_framebuffer *afb = 3068 to_amdgpu_framebuffer(plane_state->fb); 3069 int ret; 3070 3071 memset(plane_info, 0, sizeof(*plane_info)); 3072 3073 switch (fb->format->format) { 3074 case DRM_FORMAT_C8: 3075 plane_info->format = 3076 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3077 break; 3078 case DRM_FORMAT_RGB565: 3079 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3080 break; 3081 case DRM_FORMAT_XRGB8888: 3082 case DRM_FORMAT_ARGB8888: 3083 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3084 break; 3085 case DRM_FORMAT_XRGB2101010: 3086 case DRM_FORMAT_ARGB2101010: 3087 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3088 break; 3089 case DRM_FORMAT_XBGR2101010: 3090 case DRM_FORMAT_ABGR2101010: 3091 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3092 break; 3093 case DRM_FORMAT_XBGR8888: 3094 case DRM_FORMAT_ABGR8888: 3095 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3096 break; 3097 case DRM_FORMAT_NV21: 3098 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3099 break; 3100 case DRM_FORMAT_NV12: 3101 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3102 break; 3103 case DRM_FORMAT_P010: 3104 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 3105 break; 3106 case DRM_FORMAT_XRGB16161616F: 3107 case DRM_FORMAT_ARGB16161616F: 3108 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 3109 break; 3110 case DRM_FORMAT_XBGR16161616F: 3111 case DRM_FORMAT_ABGR16161616F: 3112 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 3113 break; 3114 case DRM_FORMAT_XRGB16161616: 3115 case DRM_FORMAT_ARGB16161616: 3116 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 3117 break; 3118 case DRM_FORMAT_XBGR16161616: 3119 case DRM_FORMAT_ABGR16161616: 3120 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 3121 break; 3122 default: 3123 drm_err(adev_to_drm(adev), 3124 "Unsupported screen format %p4cc\n", 3125 &fb->format->format); 3126 return -EINVAL; 3127 } 3128 3129 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3130 case DRM_MODE_ROTATE_0: 3131 plane_info->rotation = ROTATION_ANGLE_0; 3132 break; 3133 case DRM_MODE_ROTATE_90: 3134 plane_info->rotation = ROTATION_ANGLE_90; 3135 break; 3136 case DRM_MODE_ROTATE_180: 3137 plane_info->rotation = ROTATION_ANGLE_180; 3138 break; 3139 case DRM_MODE_ROTATE_270: 3140 plane_info->rotation = ROTATION_ANGLE_270; 3141 break; 3142 default: 3143 plane_info->rotation = ROTATION_ANGLE_0; 3144 break; 3145 } 3146 3147 3148 plane_info->visible = true; 3149 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3150 3151 plane_info->layer_index = plane_state->normalized_zpos; 3152 3153 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3154 &plane_info->color_space); 3155 if (ret) 3156 return ret; 3157 3158 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3159 plane_info->rotation, tiling_flags, 3160 &plane_info->tiling_info, 3161 &plane_info->plane_size, 3162 &plane_info->dcc, address, 3163 tmz_surface); 3164 if (ret) 3165 return ret; 3166 3167 amdgpu_dm_plane_fill_blending_from_plane_state( 3168 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3169 &plane_info->global_alpha, &plane_info->global_alpha_value); 3170 3171 return 0; 3172 } 3173 3174 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3175 struct dc_plane_state *dc_plane_state, 3176 struct drm_plane_state *plane_state, 3177 struct drm_crtc_state *crtc_state) 3178 { 3179 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3180 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3181 struct dc_scaling_info scaling_info; 3182 struct dc_plane_info plane_info; 3183 int ret; 3184 3185 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3186 if (ret) 3187 return ret; 3188 3189 dc_plane_state->src_rect = scaling_info.src_rect; 3190 dc_plane_state->dst_rect = scaling_info.dst_rect; 3191 dc_plane_state->clip_rect = scaling_info.clip_rect; 3192 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3193 3194 ret = fill_dc_plane_info_and_addr(adev, plane_state, 3195 afb->tiling_flags, 3196 &plane_info, 3197 &dc_plane_state->address, 3198 afb->tmz_surface); 3199 if (ret) 3200 return ret; 3201 3202 dc_plane_state->format = plane_info.format; 3203 dc_plane_state->color_space = plane_info.color_space; 3204 dc_plane_state->format = plane_info.format; 3205 dc_plane_state->plane_size = plane_info.plane_size; 3206 dc_plane_state->rotation = plane_info.rotation; 3207 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3208 dc_plane_state->stereo_format = plane_info.stereo_format; 3209 dc_plane_state->tiling_info = plane_info.tiling_info; 3210 dc_plane_state->visible = plane_info.visible; 3211 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3212 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3213 dc_plane_state->global_alpha = plane_info.global_alpha; 3214 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3215 dc_plane_state->dcc = plane_info.dcc; 3216 dc_plane_state->layer_index = plane_info.layer_index; 3217 dc_plane_state->flip_int_enabled = true; 3218 3219 /* 3220 * Always set input transfer function, since plane state is refreshed 3221 * every time. 3222 */ 3223 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3224 plane_state, 3225 dc_plane_state); 3226 if (ret) 3227 return ret; 3228 3229 return 0; 3230 } 3231 3232 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3233 struct rect *dirty_rect, int32_t x, 3234 s32 y, s32 width, s32 height, 3235 int *i, bool ffu) 3236 { 3237 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3238 3239 dirty_rect->x = x; 3240 dirty_rect->y = y; 3241 dirty_rect->width = width; 3242 dirty_rect->height = height; 3243 3244 if (ffu) 3245 drm_dbg(plane->dev, 3246 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3247 plane->base.id, width, height); 3248 else 3249 drm_dbg(plane->dev, 3250 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3251 plane->base.id, x, y, width, height); 3252 3253 (*i)++; 3254 } 3255 3256 /** 3257 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3258 * 3259 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3260 * remote fb 3261 * @old_plane_state: Old state of @plane 3262 * @new_plane_state: New state of @plane 3263 * @crtc_state: New state of CRTC connected to the @plane 3264 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3265 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3266 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3267 * that have changed will be updated. If PSR SU is not enabled, 3268 * or if damage clips are not available, the entire screen will be updated. 3269 * @dirty_regions_changed: dirty regions changed 3270 * 3271 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3272 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3273 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3274 * amdgpu_dm's. 3275 * 3276 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3277 * plane with regions that require flushing to the eDP remote buffer. In 3278 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3279 * implicitly provide damage clips without any client support via the plane 3280 * bounds. 3281 */ 3282 static void fill_dc_dirty_rects(struct drm_plane *plane, 3283 struct drm_plane_state *old_plane_state, 3284 struct drm_plane_state *new_plane_state, 3285 struct drm_crtc_state *crtc_state, 3286 struct dc_flip_addrs *flip_addrs, 3287 bool is_psr_su, 3288 bool *dirty_regions_changed) 3289 { 3290 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3291 struct rect *dirty_rects = flip_addrs->dirty_rects; 3292 u32 num_clips = 0; 3293 struct drm_mode_rect *clips = NULL; 3294 bool bb_changed; 3295 bool fb_changed; 3296 u32 i = 0; 3297 *dirty_regions_changed = false; 3298 3299 /* 3300 * Cursor plane has it's own dirty rect update interface. See 3301 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3302 */ 3303 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3304 return; 3305 3306 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3307 goto ffu; 3308 3309 if (!new_plane_state->ignore_damage_clips) { 3310 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3311 clips = drm_plane_get_damage_clips(new_plane_state); 3312 } 3313 3314 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3315 is_psr_su))) 3316 goto ffu; 3317 3318 if (!dm_crtc_state->mpo_requested) { 3319 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3320 goto ffu; 3321 3322 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3323 fill_dc_dirty_rect(new_plane_state->plane, 3324 &dirty_rects[flip_addrs->dirty_rect_count], 3325 clips->x1, clips->y1, 3326 clips->x2 - clips->x1, clips->y2 - clips->y1, 3327 &flip_addrs->dirty_rect_count, 3328 false); 3329 return; 3330 } 3331 3332 /* 3333 * MPO is requested. Add entire plane bounding box to dirty rects if 3334 * flipped to or damaged. 3335 * 3336 * If plane is moved or resized, also add old bounding box to dirty 3337 * rects. 3338 */ 3339 fb_changed = old_plane_state->fb->base.id != 3340 new_plane_state->fb->base.id; 3341 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3342 old_plane_state->crtc_y != new_plane_state->crtc_y || 3343 old_plane_state->crtc_w != new_plane_state->crtc_w || 3344 old_plane_state->crtc_h != new_plane_state->crtc_h); 3345 3346 drm_dbg(plane->dev, 3347 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3348 new_plane_state->plane->base.id, 3349 bb_changed, fb_changed, num_clips); 3350 3351 *dirty_regions_changed = bb_changed; 3352 3353 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3354 goto ffu; 3355 3356 if (bb_changed) { 3357 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3358 new_plane_state->crtc_x, 3359 new_plane_state->crtc_y, 3360 new_plane_state->crtc_w, 3361 new_plane_state->crtc_h, &i, false); 3362 3363 /* Add old plane bounding-box if plane is moved or resized */ 3364 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3365 old_plane_state->crtc_x, 3366 old_plane_state->crtc_y, 3367 old_plane_state->crtc_w, 3368 old_plane_state->crtc_h, &i, false); 3369 } 3370 3371 if (num_clips) { 3372 for (; i < num_clips; clips++) 3373 fill_dc_dirty_rect(new_plane_state->plane, 3374 &dirty_rects[i], clips->x1, 3375 clips->y1, clips->x2 - clips->x1, 3376 clips->y2 - clips->y1, &i, false); 3377 } else if (fb_changed && !bb_changed) { 3378 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3379 new_plane_state->crtc_x, 3380 new_plane_state->crtc_y, 3381 new_plane_state->crtc_w, 3382 new_plane_state->crtc_h, &i, false); 3383 } 3384 3385 flip_addrs->dirty_rect_count = i; 3386 return; 3387 3388 ffu: 3389 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3390 dm_crtc_state->base.mode.crtc_hdisplay, 3391 dm_crtc_state->base.mode.crtc_vdisplay, 3392 &flip_addrs->dirty_rect_count, true); 3393 } 3394 3395 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 3396 const struct drm_display_mode *mode, 3397 const struct dm_connector_state *dm_state, 3398 struct dc_stream_state *stream) 3399 { 3400 enum amdgpu_rmx_type rmx_type; 3401 3402 struct rect src = { 0 }; /* viewport in composition space*/ 3403 struct rect dst = { 0 }; /* stream addressable area */ 3404 3405 /* no mode. nothing to be done */ 3406 if (!mode) 3407 return; 3408 3409 /* Full screen scaling by default */ 3410 src.width = mode->hdisplay; 3411 src.height = mode->vdisplay; 3412 dst.width = stream->timing.h_addressable; 3413 dst.height = stream->timing.v_addressable; 3414 3415 if (dm_state) { 3416 rmx_type = dm_state->scaling; 3417 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3418 if (src.width * dst.height < 3419 src.height * dst.width) { 3420 /* height needs less upscaling/more downscaling */ 3421 dst.width = src.width * 3422 dst.height / src.height; 3423 } else { 3424 /* width needs less upscaling/more downscaling */ 3425 dst.height = src.height * 3426 dst.width / src.width; 3427 } 3428 } else if (rmx_type == RMX_CENTER) { 3429 dst = src; 3430 } 3431 3432 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3433 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3434 3435 if (dm_state->underscan_enable) { 3436 dst.x += dm_state->underscan_hborder / 2; 3437 dst.y += dm_state->underscan_vborder / 2; 3438 dst.width -= dm_state->underscan_hborder; 3439 dst.height -= dm_state->underscan_vborder; 3440 } 3441 } 3442 3443 stream->src = src; 3444 stream->dst = dst; 3445 3446 drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 3447 dst.x, dst.y, dst.width, dst.height); 3448 3449 } 3450 3451 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3452 struct dc_state *dc_state, 3453 struct dsc_mst_fairness_vars *vars) 3454 { 3455 struct dc_stream_state *stream = NULL; 3456 struct drm_connector *connector; 3457 struct drm_connector_state *new_con_state; 3458 struct amdgpu_dm_connector *aconnector; 3459 struct dm_connector_state *dm_conn_state; 3460 int i, j, ret; 3461 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3462 3463 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3464 3465 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3466 continue; 3467 3468 aconnector = to_amdgpu_dm_connector(connector); 3469 3470 if (!aconnector->mst_output_port) 3471 continue; 3472 3473 if (!new_con_state || !new_con_state->crtc) 3474 continue; 3475 3476 dm_conn_state = to_dm_connector_state(new_con_state); 3477 3478 for (j = 0; j < dc_state->stream_count; j++) { 3479 stream = dc_state->streams[j]; 3480 if (!stream) 3481 continue; 3482 3483 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3484 break; 3485 3486 stream = NULL; 3487 } 3488 3489 if (!stream) 3490 continue; 3491 3492 pbn_div = dm_mst_get_pbn_divider(stream->link); 3493 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3494 for (j = 0; j < dc_state->stream_count; j++) { 3495 if (vars[j].aconnector == aconnector) { 3496 pbn = vars[j].pbn; 3497 break; 3498 } 3499 } 3500 3501 if (j == dc_state->stream_count || pbn_div == 0) 3502 continue; 3503 3504 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3505 3506 if (stream->timing.flags.DSC != 1) { 3507 dm_conn_state->pbn = pbn; 3508 dm_conn_state->vcpi_slots = slot_num; 3509 3510 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3511 dm_conn_state->pbn, false); 3512 if (ret < 0) 3513 return ret; 3514 3515 continue; 3516 } 3517 3518 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3519 if (vcpi < 0) 3520 return vcpi; 3521 3522 dm_conn_state->pbn = pbn; 3523 dm_conn_state->vcpi_slots = vcpi; 3524 } 3525 return 0; 3526 } 3527 3528 static void manage_dm_interrupts(struct amdgpu_device *adev, 3529 struct amdgpu_crtc *acrtc, 3530 struct dm_crtc_state *acrtc_state) 3531 { /* 3532 * We cannot be sure that the frontend index maps to the same 3533 * backend index - some even map to more than one. 3534 * So we have to go through the CRTC to find the right IRQ. 3535 */ 3536 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3537 adev, 3538 acrtc->crtc_id); 3539 struct drm_device *dev = adev_to_drm(adev); 3540 3541 struct drm_vblank_crtc_config config = {0}; 3542 struct dc_crtc_timing *timing; 3543 int offdelay; 3544 3545 if (acrtc_state) { 3546 timing = &acrtc_state->stream->timing; 3547 3548 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3549 IP_VERSION(3, 5, 0) || 3550 !(adev->flags & AMD_IS_APU)) { 3551 /* 3552 * Older HW and DGPU have issues with instant off; 3553 * use a 2 frame offdelay. 3554 */ 3555 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3556 timing->v_total * 3557 timing->h_total, 3558 timing->pix_clk_100hz); 3559 3560 config.offdelay_ms = offdelay ?: 30; 3561 } else { 3562 /* offdelay_ms = 0 will never disable vblank */ 3563 config.offdelay_ms = 1; 3564 config.disable_immediate = true; 3565 } 3566 3567 drm_crtc_vblank_on_config(&acrtc->base, 3568 &config); 3569 /* 3570 * Since pflip_high_irq is no longer registered for DCN, grab an 3571 * extra reference to vupdate irq instead to workaround this 3572 * issue: 3573 * https://gitlab.freedesktop.org/drm/amd/-/work_items/3936 3574 * 3575 * The callbacks to drm_vblank_on/off should really take care of 3576 * this though. 3577 */ 3578 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3579 case IP_VERSION(3, 0, 0): 3580 case IP_VERSION(3, 0, 2): 3581 case IP_VERSION(3, 0, 3): 3582 case IP_VERSION(3, 2, 0): 3583 if (amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type)) 3584 drm_err(dev, "DM_IRQ: Cannot get vupdate irq!\n"); 3585 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3586 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3587 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3588 #endif 3589 } 3590 3591 } else { 3592 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3593 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3594 case IP_VERSION(3, 0, 0): 3595 case IP_VERSION(3, 0, 2): 3596 case IP_VERSION(3, 0, 3): 3597 case IP_VERSION(3, 2, 0): 3598 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3599 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3600 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3601 #endif 3602 if (amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type)) 3603 drm_err(dev, "DM_IRQ: Cannot put vupdate irq!\n"); 3604 } 3605 3606 drm_crtc_vblank_off(&acrtc->base); 3607 } 3608 } 3609 3610 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3611 struct amdgpu_crtc *acrtc) 3612 { 3613 int irq_type = 3614 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3615 3616 /* GRPH_PFLIP is not used on DCN; nothing to reapply. */ 3617 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) 3618 return; 3619 3620 /** 3621 * This reads the current state for the IRQ and force reapplies 3622 * the setting to hardware. 3623 */ 3624 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3625 } 3626 3627 STATIC_IFN_KUNIT bool 3628 is_scaling_state_different(const struct dm_connector_state *dm_state, 3629 const struct dm_connector_state *old_dm_state) 3630 { 3631 if (dm_state->scaling != old_dm_state->scaling) 3632 return true; 3633 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3634 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3635 return true; 3636 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3637 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3638 return true; 3639 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3640 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3641 return true; 3642 return false; 3643 } 3644 EXPORT_IF_KUNIT(is_scaling_state_different); 3645 3646 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3647 struct drm_crtc_state *old_crtc_state, 3648 struct drm_connector_state *new_conn_state, 3649 struct drm_connector_state *old_conn_state, 3650 const struct drm_connector *connector, 3651 struct hdcp_workqueue *hdcp_w) 3652 { 3653 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3654 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3655 3656 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3657 connector->index, connector->status, connector->dpms); 3658 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3659 old_conn_state->content_protection, new_conn_state->content_protection); 3660 3661 if (old_crtc_state) 3662 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3663 old_crtc_state->enable, 3664 old_crtc_state->active, 3665 old_crtc_state->mode_changed, 3666 old_crtc_state->active_changed, 3667 old_crtc_state->connectors_changed); 3668 3669 if (new_crtc_state) 3670 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3671 new_crtc_state->enable, 3672 new_crtc_state->active, 3673 new_crtc_state->mode_changed, 3674 new_crtc_state->active_changed, 3675 new_crtc_state->connectors_changed); 3676 3677 /* hdcp content type change */ 3678 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3679 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3680 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3681 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3682 return true; 3683 } 3684 3685 /* CP is being re enabled, ignore this */ 3686 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3687 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3688 if (new_crtc_state && new_crtc_state->mode_changed) { 3689 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3690 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3691 return true; 3692 } 3693 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3694 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3695 return false; 3696 } 3697 3698 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3699 * 3700 * Handles: UNDESIRED -> ENABLED 3701 */ 3702 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3703 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3704 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3705 3706 /* Stream removed and re-enabled 3707 * 3708 * Can sometimes overlap with the HPD case, 3709 * thus set update_hdcp to false to avoid 3710 * setting HDCP multiple times. 3711 * 3712 * Handles: DESIRED -> DESIRED (Special case) 3713 */ 3714 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3715 new_conn_state->crtc && new_conn_state->crtc->enabled && 3716 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3717 dm_con_state->update_hdcp = false; 3718 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3719 __func__); 3720 return true; 3721 } 3722 3723 /* Hot-plug, headless s3, dpms 3724 * 3725 * Only start HDCP if the display is connected/enabled. 3726 * update_hdcp flag will be set to false until the next 3727 * HPD comes in. 3728 * 3729 * Handles: DESIRED -> DESIRED (Special case) 3730 */ 3731 if (dm_con_state->update_hdcp && 3732 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3733 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3734 dm_con_state->update_hdcp = false; 3735 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3736 __func__); 3737 return true; 3738 } 3739 3740 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3741 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3742 if (new_crtc_state && new_crtc_state->mode_changed) { 3743 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3744 __func__); 3745 return true; 3746 } 3747 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3748 __func__); 3749 return false; 3750 } 3751 3752 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3753 return false; 3754 } 3755 3756 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3757 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3758 __func__); 3759 return true; 3760 } 3761 3762 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3763 return false; 3764 } 3765 3766 static void remove_stream(struct amdgpu_device *adev, 3767 struct amdgpu_crtc *acrtc, 3768 struct dc_stream_state *stream) 3769 { 3770 /* this is the update mode case */ 3771 3772 acrtc->otg_inst = -1; 3773 acrtc->enabled = false; 3774 } 3775 3776 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 3777 { 3778 3779 assert_spin_locked(&acrtc->base.dev->event_lock); 3780 WARN_ON(acrtc->event); 3781 3782 acrtc->event = acrtc->base.state->event; 3783 3784 /* Set the flip status */ 3785 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3786 3787 /* Mark this event as consumed */ 3788 acrtc->base.state->event = NULL; 3789 3790 drm_dbg_state(acrtc->base.dev, 3791 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3792 acrtc->crtc_id); 3793 } 3794 3795 static void update_freesync_state_on_stream( 3796 struct amdgpu_display_manager *dm, 3797 struct dm_crtc_state *new_crtc_state, 3798 struct dc_stream_state *new_stream, 3799 struct dc_plane_state *surface, 3800 u32 flip_timestamp_in_us) 3801 { 3802 struct mod_vrr_params vrr_params; 3803 struct dc_info_packet vrr_infopacket = {0}; 3804 struct amdgpu_device *adev = dm->adev; 3805 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3806 unsigned long flags; 3807 bool pack_sdp_v1_3 = false; 3808 struct amdgpu_dm_connector *aconn; 3809 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 3810 3811 if (!new_stream) 3812 return; 3813 3814 /* 3815 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3816 * For now it's sufficient to just guard against these conditions. 3817 */ 3818 3819 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3820 return; 3821 3822 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3823 vrr_params = acrtc->dm_irq_params.vrr_params; 3824 3825 if (surface) { 3826 mod_freesync_handle_preflip( 3827 dm->freesync_module, 3828 surface, 3829 new_stream, 3830 flip_timestamp_in_us, 3831 &vrr_params); 3832 3833 if (adev->family < AMDGPU_FAMILY_AI && 3834 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 3835 mod_freesync_handle_v_update(dm->freesync_module, 3836 new_stream, &vrr_params); 3837 3838 /* Need to call this before the frame ends. */ 3839 dc_stream_adjust_vmin_vmax(dm->dc, 3840 new_crtc_state->stream, 3841 &vrr_params.adjust); 3842 } 3843 } 3844 3845 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 3846 3847 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 3848 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 3849 3850 if (aconn->vsdb_info.amd_vsdb_version == 1) 3851 packet_type = PACKET_TYPE_FS_V1; 3852 else if (aconn->vsdb_info.amd_vsdb_version == 2) 3853 packet_type = PACKET_TYPE_FS_V2; 3854 else if (aconn->vsdb_info.amd_vsdb_version == 3) 3855 packet_type = PACKET_TYPE_FS_V3; 3856 3857 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 3858 &new_stream->adaptive_sync_infopacket); 3859 } 3860 3861 mod_freesync_build_vrr_infopacket( 3862 dm->freesync_module, 3863 new_stream, 3864 &vrr_params, 3865 packet_type, 3866 TRANSFER_FUNC_UNKNOWN, 3867 &vrr_infopacket, 3868 pack_sdp_v1_3); 3869 3870 new_crtc_state->freesync_vrr_info_changed |= 3871 (memcmp(&new_crtc_state->vrr_infopacket, 3872 &vrr_infopacket, 3873 sizeof(vrr_infopacket)) != 0); 3874 3875 acrtc->dm_irq_params.vrr_params = vrr_params; 3876 new_crtc_state->vrr_infopacket = vrr_infopacket; 3877 3878 new_stream->vrr_infopacket = vrr_infopacket; 3879 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 3880 3881 if (new_crtc_state->freesync_vrr_info_changed) 3882 drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", 3883 new_crtc_state->base.crtc->base.id, 3884 (int)new_crtc_state->base.vrr_enabled, 3885 (int)vrr_params.state); 3886 3887 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3888 } 3889 3890 static void update_stream_irq_parameters( 3891 struct amdgpu_display_manager *dm, 3892 struct dm_crtc_state *new_crtc_state) 3893 { 3894 struct dc_stream_state *new_stream = new_crtc_state->stream; 3895 struct mod_vrr_params vrr_params; 3896 struct mod_freesync_config config = new_crtc_state->freesync_config; 3897 struct amdgpu_device *adev = dm->adev; 3898 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3899 unsigned long flags; 3900 3901 if (!new_stream) 3902 return; 3903 3904 /* 3905 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3906 * For now it's sufficient to just guard against these conditions. 3907 */ 3908 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3909 return; 3910 3911 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3912 vrr_params = acrtc->dm_irq_params.vrr_params; 3913 3914 if (new_crtc_state->vrr_supported && 3915 config.min_refresh_in_uhz && 3916 config.max_refresh_in_uhz) { 3917 /* 3918 * if freesync compatible mode was set, config.state will be set 3919 * in atomic check 3920 */ 3921 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 3922 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 3923 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 3924 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 3925 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 3926 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 3927 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 3928 } else { 3929 config.state = new_crtc_state->base.vrr_enabled ? 3930 VRR_STATE_ACTIVE_VARIABLE : 3931 VRR_STATE_INACTIVE; 3932 } 3933 } else { 3934 config.state = VRR_STATE_UNSUPPORTED; 3935 } 3936 3937 mod_freesync_build_vrr_params(dm->freesync_module, 3938 new_stream, 3939 &config, &vrr_params); 3940 3941 new_crtc_state->freesync_config = config; 3942 /* Copy state for access from DM IRQ handler */ 3943 acrtc->dm_irq_params.freesync_config = config; 3944 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 3945 acrtc->dm_irq_params.vrr_params = vrr_params; 3946 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3947 } 3948 3949 static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, 3950 struct dm_crtc_state *old_state, 3951 struct dm_crtc_state *new_state) 3952 { 3953 struct amdgpu_device *adev = dm->adev; 3954 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 3955 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 3956 3957 /* Only DCE gates vupdate on VRR, keep it enabled for DCN */ 3958 bool vrr_gates_vupdate = amdgpu_ip_version(adev, DCE_HWIP, 0) == 0; 3959 3960 if (!old_vrr_active && new_vrr_active) { 3961 /* Transition VRR inactive -> active: 3962 * While VRR is active, we must not disable vblank irq, as a 3963 * reenable after disable would compute bogus vblank/pflip 3964 * timestamps if it likely happened inside display front-porch. 3965 * 3966 * We also need vupdate irq for the actual core vblank handling 3967 * at end of vblank. 3968 */ 3969 if (vrr_gates_vupdate) 3970 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 3971 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 3972 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", 3973 __func__, new_state->base.crtc->base.id); 3974 3975 scoped_guard(mutex, &dm->dc_lock) { 3976 dc_exit_ips_for_hw_access(dm->dc); 3977 amdgpu_dm_psr_set_event(dm, new_state->stream, true, 3978 psr_event_vrr_transition, true); 3979 amdgpu_dm_replay_set_event(dm, new_state->stream, true, 3980 replay_event_vrr, true); 3981 } 3982 } else if (old_vrr_active && !new_vrr_active) { 3983 /* Transition VRR active -> inactive: 3984 * Allow vblank irq disable again for fixed refresh rate. 3985 */ 3986 if (vrr_gates_vupdate) 3987 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 3988 drm_crtc_vblank_put(new_state->base.crtc); 3989 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", 3990 __func__, new_state->base.crtc->base.id); 3991 3992 scoped_guard(mutex, &dm->dc_lock) { 3993 dc_exit_ips_for_hw_access(dm->dc); 3994 amdgpu_dm_psr_set_event(dm, new_state->stream, false, 3995 psr_event_vrr_transition, false); 3996 amdgpu_dm_replay_set_event(dm, new_state->stream, false, 3997 replay_event_vrr, false); 3998 } 3999 } 4000 } 4001 4002 static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 4003 { 4004 struct drm_plane *plane; 4005 struct drm_plane_state *old_plane_state; 4006 int i; 4007 4008 /* 4009 * TODO: Make this per-stream so we don't issue redundant updates for 4010 * commits with multiple streams. 4011 */ 4012 for_each_old_plane_in_state(state, plane, old_plane_state, i) 4013 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4014 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 4015 } 4016 4017 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 4018 { 4019 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 4020 4021 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 4022 } 4023 4024 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 4025 struct drm_plane_state *old_plane_state, 4026 struct dc_stream_update *update) 4027 { 4028 struct amdgpu_device *adev = drm_to_adev(plane->dev); 4029 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4030 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4031 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4032 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4033 uint64_t address = afb ? afb->address : 0; 4034 struct dc_cursor_position position = {0}; 4035 struct dc_cursor_attributes attributes; 4036 int ret; 4037 4038 if (!plane->state->fb && !old_plane_state->fb) 4039 return; 4040 4041 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 4042 amdgpu_crtc->crtc_id, plane->state->crtc_w, 4043 plane->state->crtc_h); 4044 4045 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 4046 if (ret) 4047 return; 4048 4049 if (!position.enable) { 4050 /* turn off cursor */ 4051 if (crtc_state && crtc_state->stream) { 4052 dc_stream_set_cursor_position(crtc_state->stream, 4053 &position); 4054 update->cursor_position = &crtc_state->stream->cursor_position; 4055 } 4056 return; 4057 } 4058 4059 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4060 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4061 4062 memset(&attributes, 0, sizeof(attributes)); 4063 attributes.address.high_part = upper_32_bits(address); 4064 attributes.address.low_part = lower_32_bits(address); 4065 attributes.width = plane->state->crtc_w; 4066 attributes.height = plane->state->crtc_h; 4067 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4068 attributes.rotation_angle = 0; 4069 attributes.attribute_flags.value = 0; 4070 4071 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 4072 * legacy gamma setup. 4073 */ 4074 if (crtc_state->cm_is_degamma_srgb && 4075 adev->dm.dc->caps.color.dpp.gamma_corr) 4076 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 4077 4078 if (afb) 4079 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 4080 4081 if (crtc_state->stream) { 4082 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4083 &attributes)) 4084 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 4085 4086 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 4087 4088 if (!dc_stream_set_cursor_position(crtc_state->stream, 4089 &position)) 4090 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 4091 4092 update->cursor_position = &crtc_state->stream->cursor_position; 4093 } 4094 } 4095 4096 static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 4097 struct amdgpu_crtc *acrtc_attach, 4098 const struct dm_crtc_state *acrtc_state, 4099 const u64 current_ts) 4100 { 4101 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 4102 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 4103 struct amdgpu_dm_connector *aconn = 4104 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 4105 4106 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 4107 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 4108 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 4109 if (aconn->sr_skip_count > 0) 4110 aconn->sr_skip_count--; 4111 4112 /* Allow SR when skip count is 0. */ 4113 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 4114 4115 /* 4116 * If sink supports PSR SU/Panel Replay, there is no need to rely on 4117 * a vblank event disable request to enable PSR/RP. PSR SU/RP 4118 * can be enabled immediately once OS demonstrates an 4119 * adequate number of fast atomic commits to notify KMD 4120 * of update events. 4121 * See `amdgpu_dm_crtc_vblank_control_worker()`. 4122 */ 4123 if (acrtc_attach->dm_irq_params.allow_sr_entry && 4124 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 4125 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 4126 psr_event_hw_programming, false); 4127 4128 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 4129 replay_event_hw_programming, false); 4130 } 4131 } else { 4132 acrtc_attach->dm_irq_params.allow_sr_entry = false; 4133 } 4134 } 4135 4136 static void dm_arm_vblank_event(struct amdgpu_crtc *acrtc, 4137 struct dm_crtc_state *acrtc_state, 4138 bool pflip_update, 4139 bool cursor_update) 4140 { 4141 assert_spin_locked(&acrtc->base.dev->event_lock); 4142 4143 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 4144 return; 4145 4146 if (pflip_update) { 4147 drm_crtc_vblank_get(&acrtc->base); 4148 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 4149 /* Arm flip completion handling and event delivery after programming. */ 4150 prepare_flip_isr(acrtc); 4151 } else if (cursor_update) { 4152 drm_crtc_vblank_get(&acrtc->base); 4153 acrtc->event = acrtc->base.state->event; 4154 acrtc->base.state->event = NULL; 4155 } 4156 } 4157 4158 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 4159 struct drm_device *dev, 4160 struct amdgpu_display_manager *dm, 4161 struct drm_crtc *pcrtc, 4162 bool wait_for_vblank) 4163 { 4164 u32 i; 4165 u64 timestamp_ns = ktime_get_ns(); 4166 struct drm_plane *plane; 4167 struct drm_plane_state *old_plane_state, *new_plane_state; 4168 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4169 struct drm_crtc_state *new_pcrtc_state = 4170 drm_atomic_get_new_crtc_state(state, pcrtc); 4171 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4172 struct dm_crtc_state *dm_old_crtc_state = 4173 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4174 int planes_count = 0, vpos, hpos; 4175 unsigned long flags; 4176 u32 target_vblank, last_flip_vblank; 4177 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 4178 bool cursor_update = false; 4179 bool pflip_present = false; 4180 bool immediate_flip = false; 4181 bool flip_latched_during_prog = false; 4182 bool dirty_rects_changed = false; 4183 bool updated_planes_and_streams = false; 4184 struct { 4185 struct dc_surface_update surface_updates[MAX_SURFACES]; 4186 struct dc_plane_info plane_infos[MAX_SURFACES]; 4187 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 4188 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 4189 struct dc_stream_update stream_update; 4190 } *bundle; 4191 4192 bundle = kzalloc_obj(*bundle); 4193 4194 if (!bundle) { 4195 drm_err(dev, "Failed to allocate update bundle\n"); 4196 goto cleanup; 4197 } 4198 4199 /* 4200 * Disable the cursor first if we're disabling all the planes. 4201 * It'll remain on the screen after the planes are re-enabled 4202 * if we don't. 4203 * 4204 * If the cursor is transitioning from native to overlay mode, the 4205 * native cursor needs to be disabled first. 4206 */ 4207 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 4208 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4209 struct dc_cursor_position cursor_position = {0}; 4210 4211 if (!dc_stream_set_cursor_position(acrtc_state->stream, 4212 &cursor_position)) 4213 drm_err(dev, "DC failed to disable native cursor\n"); 4214 4215 bundle->stream_update.cursor_position = 4216 &acrtc_state->stream->cursor_position; 4217 } 4218 4219 if (acrtc_state->active_planes == 0 && 4220 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4221 amdgpu_dm_commit_cursors(state); 4222 4223 /* update planes when needed */ 4224 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4225 struct drm_crtc *crtc = new_plane_state->crtc; 4226 struct drm_crtc_state *new_crtc_state; 4227 struct drm_framebuffer *fb = new_plane_state->fb; 4228 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 4229 bool plane_needs_flip; 4230 struct dc_plane_state *dc_plane; 4231 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4232 4233 /* Cursor plane is handled after stream updates */ 4234 if (plane->type == DRM_PLANE_TYPE_CURSOR && 4235 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4236 if ((fb && crtc == pcrtc) || 4237 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 4238 cursor_update = true; 4239 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 4240 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 4241 } 4242 4243 continue; 4244 } 4245 4246 if (!fb || !crtc || pcrtc != crtc) 4247 continue; 4248 4249 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4250 if (!new_crtc_state->active) 4251 continue; 4252 4253 dc_plane = dm_new_plane_state->dc_state; 4254 if (!dc_plane) 4255 continue; 4256 4257 bundle->surface_updates[planes_count].surface = dc_plane; 4258 if (new_pcrtc_state->color_mgmt_changed) { 4259 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 4260 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 4261 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 4262 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 4263 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 4264 } 4265 4266 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 4267 &bundle->scaling_infos[planes_count]); 4268 4269 bundle->surface_updates[planes_count].scaling_info = 4270 &bundle->scaling_infos[planes_count]; 4271 4272 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 4273 4274 pflip_present = pflip_present || plane_needs_flip; 4275 4276 if (!plane_needs_flip) { 4277 planes_count += 1; 4278 continue; 4279 } 4280 4281 fill_dc_plane_info_and_addr( 4282 dm->adev, new_plane_state, 4283 afb->tiling_flags, 4284 &bundle->plane_infos[planes_count], 4285 &bundle->flip_addrs[planes_count].address, 4286 afb->tmz_surface); 4287 4288 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 4289 new_plane_state->plane->index, 4290 bundle->plane_infos[planes_count].dcc.enable); 4291 4292 bundle->surface_updates[planes_count].plane_info = 4293 &bundle->plane_infos[planes_count]; 4294 4295 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 4296 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 4297 fill_dc_dirty_rects(plane, old_plane_state, 4298 new_plane_state, new_crtc_state, 4299 &bundle->flip_addrs[planes_count], 4300 acrtc_state->stream->link->psr_settings.psr_version == 4301 DC_PSR_VERSION_SU_1, 4302 &dirty_rects_changed); 4303 4304 /* 4305 * If the dirty regions changed, PSR-SU need to be disabled temporarily 4306 * and enabled it again after dirty regions are stable to avoid video glitch. 4307 * PSR-SU will be enabled in 4308 * amdgpu_dm_crtc_vblank_control_worker() if user 4309 * pause the video during the PSR-SU was disabled. 4310 */ 4311 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 4312 acrtc_attach->dm_irq_params.allow_sr_entry && 4313 dirty_rects_changed) { 4314 mutex_lock(&dm->dc_lock); 4315 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 4316 timestamp_ns; 4317 dc_exit_ips_for_hw_access(dm->dc); 4318 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 4319 psr_event_hw_programming, true); 4320 mutex_unlock(&dm->dc_lock); 4321 } 4322 } 4323 4324 /* 4325 * Only allow immediate flips for fast updates that don't 4326 * change memory domain, FB pitch, DCC state, rotation or 4327 * mirroring. 4328 * 4329 * dm_crtc_helper_atomic_check() only accepts async flips with 4330 * fast updates. 4331 */ 4332 if (crtc->state->async_flip && 4333 (acrtc_state->update_type != UPDATE_TYPE_FAST || 4334 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 4335 drm_warn_once(state->dev, 4336 "[PLANE:%d:%s] async flip with non-fast update\n", 4337 plane->base.id, plane->name); 4338 4339 bundle->flip_addrs[planes_count].flip_immediate = 4340 crtc->state->async_flip && 4341 acrtc_state->update_type == UPDATE_TYPE_FAST && 4342 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 4343 4344 immediate_flip |= bundle->flip_addrs[planes_count].flip_immediate; 4345 4346 timestamp_ns = ktime_get_ns(); 4347 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 4348 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 4349 bundle->surface_updates[planes_count].surface = dc_plane; 4350 4351 if (!bundle->surface_updates[planes_count].surface) { 4352 drm_err(dev, "No surface for CRTC: id=%d\n", 4353 acrtc_attach->crtc_id); 4354 continue; 4355 } 4356 4357 if (plane == pcrtc->primary) 4358 update_freesync_state_on_stream( 4359 dm, 4360 acrtc_state, 4361 acrtc_state->stream, 4362 dc_plane, 4363 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 4364 4365 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 4366 __func__, 4367 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4368 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4369 4370 planes_count += 1; 4371 4372 } 4373 4374 if (pflip_present) { 4375 if (!vrr_active) { 4376 /* Use old throttling in non-vrr fixed refresh rate mode 4377 * to keep flip scheduling based on target vblank counts 4378 * working in a backwards compatible way, e.g., for 4379 * clients using the GLX_OML_sync_control extension or 4380 * DRI3/Present extension with defined target_msc. 4381 */ 4382 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 4383 } else { 4384 /* For variable refresh rate mode only: 4385 * Get vblank of last completed flip to avoid > 1 vrr 4386 * flips per video frame by use of throttling, but allow 4387 * flip programming anywhere in the possibly large 4388 * variable vrr vblank interval for fine-grained flip 4389 * timing control and more opportunity to avoid stutter 4390 * on late submission of flips. 4391 */ 4392 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4393 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4394 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4395 } 4396 4397 target_vblank = last_flip_vblank + wait_for_vblank; 4398 4399 /* 4400 * Wait until we're out of the vertical blank period before the one 4401 * targeted by the flip 4402 */ 4403 while ((acrtc_attach->enabled && 4404 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4405 0, &vpos, &hpos, NULL, 4406 NULL, &pcrtc->hwmode) 4407 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4408 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4409 (int)(target_vblank - 4410 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4411 usleep_range(1000, 1100); 4412 } 4413 4414 if (acrtc_state->stream) { 4415 if (acrtc_state->freesync_vrr_info_changed) 4416 bundle->stream_update.vrr_infopacket = 4417 &acrtc_state->stream->vrr_infopacket; 4418 } 4419 } 4420 4421 /* 4422 * DCE depends on a combination of GRPH_FLIP, VLINE0, and VUPDATE for 4423 * event delivery. Only GRPH_FLIP handler can send pflip events, and it 4424 * only fires if HW latched to the flip. Maintain legacy behavior by 4425 * arming event before programming. 4426 */ 4427 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) { 4428 scoped_guard(spinlock_irqsave, &pcrtc->dev->event_lock) { 4429 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4430 pflip_present, cursor_update); 4431 } 4432 } 4433 4434 /* Update the planes if changed or disable if we don't have any. */ 4435 if ((planes_count || acrtc_state->active_planes == 0) && 4436 acrtc_state->stream) { 4437 /* 4438 * If PSR or idle optimizations are enabled then flush out 4439 * any pending work before hardware programming. 4440 */ 4441 if (dm->vblank_control_workqueue) 4442 flush_workqueue(dm->vblank_control_workqueue); 4443 4444 bundle->stream_update.stream = acrtc_state->stream; 4445 if (new_pcrtc_state->mode_changed) { 4446 bundle->stream_update.src = acrtc_state->stream->src; 4447 bundle->stream_update.dst = acrtc_state->stream->dst; 4448 } 4449 4450 if (new_pcrtc_state->color_mgmt_changed) { 4451 /* 4452 * TODO: This isn't fully correct since we've actually 4453 * already modified the stream in place. 4454 */ 4455 bundle->stream_update.gamut_remap = 4456 &acrtc_state->stream->gamut_remap_matrix; 4457 bundle->stream_update.output_csc_transform = 4458 &acrtc_state->stream->csc_color_matrix; 4459 bundle->stream_update.out_transfer_func = 4460 &acrtc_state->stream->out_transfer_func; 4461 bundle->stream_update.lut3d_func = 4462 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4463 bundle->stream_update.func_shaper = 4464 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4465 } 4466 4467 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4468 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4469 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4470 4471 /* 4472 * If FreeSync state on the stream has changed then we need to 4473 * re-adjust the min/max bounds now that DC doesn't handle this 4474 * as part of commit. 4475 */ 4476 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4477 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4478 dc_stream_adjust_vmin_vmax( 4479 dm->dc, acrtc_state->stream, 4480 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4481 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4482 } 4483 mutex_lock(&dm->dc_lock); 4484 update_planes_and_stream_adapter(dm->dc, 4485 acrtc_state->update_type, 4486 planes_count, 4487 acrtc_state->stream, 4488 &bundle->stream_update, 4489 bundle->surface_updates); 4490 updated_planes_and_streams = true; 4491 4492 /** 4493 * Enable or disable the interrupts on the backend. 4494 * 4495 * Most pipes are put into power gating when unused. 4496 * 4497 * When power gating is enabled on a pipe we lose the 4498 * interrupt enablement state when power gating is disabled. 4499 * 4500 * So we need to update the IRQ control state in hardware 4501 * whenever the pipe turns on (since it could be previously 4502 * power gated) or off (since some pipes can't be power gated 4503 * on some ASICs). 4504 */ 4505 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4506 dm_update_pflip_irq_state(drm_to_adev(dev), 4507 acrtc_attach); 4508 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4509 timestamp_ns); 4510 mutex_unlock(&dm->dc_lock); 4511 } 4512 4513 /* 4514 * Update cursor state *after* programming all the planes. 4515 * This avoids redundant programming in the case where we're going 4516 * to be disabling a single plane - those pipes are being disabled. 4517 */ 4518 if (acrtc_state->active_planes && 4519 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4520 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4521 amdgpu_dm_commit_cursors(state); 4522 4523 /* 4524 * DCN specific vblank handling 4525 * ============================ 4526 * 4527 * With the event_lock held, arm the vblank event, and determine whether 4528 * deliver it immediately, or in VUPDATE_NO_LOCK IRQ (i.e. HW latch 4529 * point) handler. Do this *after* programming so that the IRQ handler 4530 * will not deliver the event before HW laches onto the programmed 4531 * values: 4532 * 4533 * Commit thread IRQ handler HW 4534 * ----------------------------------------------------------------- 4535 * arm_vblank_event() 4536 * vupdate() 4537 * vupdate_handler() 4538 * cook_timestamp() 4539 * # prev flip already latched, 4540 * # so flip_latched == true. 4541 * if event_armed && flip_latched: 4542 * send_vblank_event() 4543 * # sent before latch, **BAD!** 4544 * hw_program() 4545 * vupdate() 4546 * **latch** 4547 * 4548 * There's a consequence of arming after: it's possible for HW to latch 4549 * between start of HW programming and acrtc->event/pflip_status arming. 4550 * When this happens, the IRQ handler will send the event on the next 4551 * immediate latch point, even though HW has already latched. This is 4552 * handled by optimistically checking for HW latch after programming, 4553 * and if latched, send the event immediately: 4554 * 4555 * Commit thread IRQ handler HW 4556 * ----------------------------------------------------------------- 4557 * hw_program() 4558 * vupdate() 4559 * **latch** 4560 * vupdate_handler() 4561 * cook_timestamp() 4562 * # event_armed == false 4563 * # **no event sent!** 4564 * arm_vblank_event() 4565 * if flip_latched: 4566 * **send_vblank_event()** 4567 * disarm_vblank_event() 4568 * 4569 * The IRQ handler is expected to cook the timestamp, but we need to 4570 * cook the timestamp before optimistic sending as well. That's because 4571 * the following sequence is possible: 4572 * 4573 * Commit thread IRQ handler HW 4574 * ----------------------------------------------------------------- 4575 * hw_program() 4576 * arm_vblank_event() 4577 * vupdate() 4578 * **latch** 4579 * if flip_latched: 4580 * # Need cook before send! 4581 * **cook_timestamp()** 4582 * send_vblank_event() 4583 * disarm_vblank_event() 4584 * vupdate_handler() 4585 * cook_timestamp() 4586 * # event_armed == false 4587 * # no event sent! 4588 * 4589 * Cooking twice is OK, since DRM scanout accurate timestamps report A) 4590 * the previous vactive start if currently in vactive, or B) the next 4591 * vactive start if currently in vblank (see &get_vblank_counter). 'A)' 4592 * is what we want for the optimistic send, and for 'B)', we'll cook a 4593 * timestamp no later than the next IRQ handler run. 4594 * 4595 * The more correct fix is to wrap programming and arming with the 4596 * event_lock and thus serializing it with the IRQ handler. However, 4597 * there are various sleep-waits within 4598 * update_planes_and_stream_adapter() that makes spin locking illegal. 4599 * And on full updates, it can take 1-2 frame-times to return (see 4600 * commit_planes_for_stream). 4601 * 4602 * On DCE, GRPH_PFLIP IRQ is used and takes care of this. 4603 */ 4604 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) { 4605 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4606 4607 if (updated_planes_and_streams) { 4608 flip_latched_during_prog = 4609 !dc_get_flip_pending_on_otg(dm->dc, acrtc_attach->otg_inst); 4610 } 4611 4612 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4613 pflip_present, cursor_update); 4614 4615 /* 4616 * Deliver the event immediately on immediate flip, or on a 4617 * update that has already latched. 4618 */ 4619 if ((immediate_flip || flip_latched_during_prog) && 4620 acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED && 4621 acrtc_attach->event) { 4622 drm_crtc_accurate_vblank_count(&acrtc_attach->base); 4623 drm_crtc_send_vblank_event(&acrtc_attach->base, 4624 acrtc_attach->event); 4625 acrtc_attach->event = NULL; 4626 drm_crtc_vblank_put(&acrtc_attach->base); 4627 acrtc_attach->pflip_status = AMDGPU_FLIP_NONE; 4628 } 4629 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4630 } 4631 4632 cleanup: 4633 kfree(bundle); 4634 } 4635 4636 /* 4637 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4638 * @crtc_state: the DRM CRTC state 4639 * @stream_state: the DC stream state. 4640 * 4641 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4642 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4643 */ 4644 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4645 struct dc_stream_state *stream_state) 4646 { 4647 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4648 } 4649 4650 /** 4651 * amdgpu_dm_crtc_complete_writeback - finish a pending writeback job 4652 * @acrtc: the CRTC whose pending writeback should be completed 4653 * 4654 * Clears the pending state, signals the writeback out fence and releases the 4655 * vblank reference taken in dm_set_writeback() while the writeback was armed. 4656 * The pending flag is tested and cleared under the writeback job lock, so this 4657 * is safe to call concurrently from the completion vblank IRQ 4658 * (dm_crtc_high_irq()) and from the writeback teardown path 4659 * (dm_clear_writeback()); only the caller that observes the pending job 4660 * performs the completion. 4661 * 4662 * Return: true if a pending writeback job was completed by this call. 4663 */ 4664 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc) 4665 { 4666 unsigned long flags; 4667 bool pending; 4668 4669 if (!acrtc->wb_conn) 4670 return false; 4671 4672 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 4673 pending = acrtc->wb_pending; 4674 acrtc->wb_pending = false; 4675 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 4676 4677 if (!pending) 4678 return false; 4679 4680 drm_writeback_signal_completion(acrtc->wb_conn, 0); 4681 drm_crtc_vblank_put(&acrtc->base); 4682 4683 return true; 4684 } 4685 4686 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 4687 struct amdgpu_crtc *acrtc, 4688 struct dm_crtc_state *crtc_state) 4689 { 4690 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4691 4692 /* 4693 * If the writeback is still pending when it is torn down (its 4694 * completion vblank IRQ never fired), signal the out fence so a 4695 * waiting client does not stall and release the vblank reference 4696 * taken in dm_set_writeback(). 4697 */ 4698 amdgpu_dm_crtc_complete_writeback(acrtc); 4699 } 4700 4701 /** 4702 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4703 * @state: the drm atomic state 4704 * @dm: the display manager to update mod_power on 4705 * 4706 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4707 * in preparation for hardware programming. See also 4708 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4709 */ 4710 static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4711 struct amdgpu_display_manager *dm) 4712 { 4713 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4714 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4715 struct amdgpu_dm_connector *aconnector; 4716 struct drm_crtc *crtc; 4717 int i = 0; 4718 4719 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4720 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4721 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4722 4723 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4724 continue; 4725 4726 /* 4727 * Update mod_power on modeset event in preparation for hw 4728 * programming. Always use the old stream, since it would have 4729 * been previously added to mod_power. If old stream is null (on 4730 * crtc enable, for example), mod_power will no-op, which is the 4731 * desried behavior. 4732 */ 4733 if (old_crtc_state->active) { 4734 scoped_guard(mutex, &dm->dc_lock) { 4735 dc_exit_ips_for_hw_access(dm->dc); 4736 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4737 psr_event_hw_programming, true); 4738 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4739 replay_event_hw_programming, true); 4740 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4741 replay_event_general_ui, false); 4742 } 4743 } 4744 4745 if (new_crtc_state->active) { 4746 aconnector = (struct amdgpu_dm_connector *) 4747 dm_new_crtc_state->stream->dm_stream_context; 4748 if (old_crtc_state->active) { 4749 mod_power_replace_stream(dm->power_module, 4750 dm_old_crtc_state->stream, 4751 dm_new_crtc_state->stream, 4752 &aconnector->psr_caps); 4753 } else { 4754 mod_power_add_stream(dm->power_module, 4755 dm_new_crtc_state->stream, 4756 &aconnector->psr_caps); 4757 } 4758 } else if (old_crtc_state->active) { 4759 mod_power_remove_stream(dm->power_module, 4760 dm_old_crtc_state->stream); 4761 } 4762 } 4763 } 4764 4765 /** 4766 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4767 * @state: the drm atomic state 4768 * @dm: the display manager to update mod_power on 4769 * 4770 * Notify mod_power of mode_change. This needs to be done after dc_stream 4771 * updates have been committed, and VRR parameters have been updated. 4772 */ 4773 static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4774 struct amdgpu_display_manager *dm) 4775 { 4776 struct dm_crtc_state *dm_new_crtc_state; 4777 struct drm_crtc_state *new_crtc_state; 4778 struct amdgpu_crtc *acrtc; 4779 struct drm_crtc *crtc; 4780 int i = 0; 4781 4782 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4783 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4784 acrtc = to_amdgpu_crtc(crtc); 4785 4786 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4787 continue; 4788 4789 if (new_crtc_state->active) { 4790 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4791 &acrtc->dm_irq_params.vrr_params); 4792 mod_power_notify_mode_change(dm->power_module, 4793 dm_new_crtc_state->stream, 4794 false); 4795 4796 /* 4797 * Block PSR / Replay on the new stream until display settles post-modeset. 4798 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4799 * allow_sr_entry becomes true. 4800 */ 4801 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4802 psr_event_hw_programming, true); 4803 4804 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4805 replay_event_hw_programming | replay_event_general_ui, 4806 true); 4807 } 4808 } 4809 4810 } 4811 4812 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4813 struct dc_state *dc_state) 4814 { 4815 struct drm_device *dev = state->dev; 4816 struct amdgpu_device *adev = drm_to_adev(dev); 4817 struct amdgpu_display_manager *dm = &adev->dm; 4818 struct drm_crtc *crtc; 4819 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4820 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4821 struct drm_connector_state *old_con_state; 4822 struct drm_connector *connector; 4823 bool mode_set_reset_required = false; 4824 u32 i; 4825 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4826 bool set_backlight_level = false; 4827 4828 /* Disable writeback */ 4829 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4830 struct dm_connector_state *dm_old_con_state; 4831 struct amdgpu_crtc *acrtc; 4832 4833 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4834 continue; 4835 4836 old_crtc_state = NULL; 4837 4838 dm_old_con_state = to_dm_connector_state(old_con_state); 4839 if (!dm_old_con_state->base.crtc) 4840 continue; 4841 4842 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4843 if (acrtc) 4844 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4845 4846 if (!acrtc || !acrtc->wb_enabled) 4847 continue; 4848 4849 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4850 4851 dm_clear_writeback(dm, acrtc, dm_old_crtc_state); 4852 acrtc->wb_enabled = false; 4853 } 4854 4855 amdgpu_dm_mod_power_update_streams(state, dm); 4856 4857 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4858 new_crtc_state, i) { 4859 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4860 4861 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4862 4863 if (old_crtc_state->active && 4864 (!new_crtc_state->active || 4865 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4866 manage_dm_interrupts(adev, acrtc, NULL); 4867 dc_stream_release(dm_old_crtc_state->stream); 4868 } 4869 } 4870 4871 drm_atomic_helper_calc_timestamping_constants(state); 4872 4873 /* update changed items */ 4874 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4875 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4876 4877 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4878 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4879 4880 drm_dbg_state(state->dev, 4881 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4882 acrtc->crtc_id, 4883 new_crtc_state->enable, 4884 new_crtc_state->active, 4885 new_crtc_state->planes_changed, 4886 new_crtc_state->mode_changed, 4887 new_crtc_state->active_changed, 4888 new_crtc_state->connectors_changed); 4889 4890 /* Disable cursor if disabling crtc */ 4891 if (old_crtc_state->active && !new_crtc_state->active) { 4892 struct dc_cursor_position position; 4893 4894 memset(&position, 0, sizeof(position)); 4895 mutex_lock(&dm->dc_lock); 4896 dc_exit_ips_for_hw_access(dm->dc); 4897 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4898 mutex_unlock(&dm->dc_lock); 4899 } 4900 4901 /* Copy all transient state flags into dc state */ 4902 if (dm_new_crtc_state->stream) { 4903 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4904 dm_new_crtc_state->stream); 4905 } 4906 4907 /* handles headless hotplug case, updating new_state and 4908 * aconnector as needed 4909 */ 4910 4911 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4912 4913 drm_dbg_atomic(dev, 4914 "Atomic commit: SET crtc id %d: [%p]\n", 4915 acrtc->crtc_id, acrtc); 4916 4917 if (!dm_new_crtc_state->stream) { 4918 /* 4919 * this could happen because of issues with 4920 * userspace notifications delivery. 4921 * In this case userspace tries to set mode on 4922 * display which is disconnected in fact. 4923 * dc_sink is NULL in this case on aconnector. 4924 * We expect reset mode will come soon. 4925 * 4926 * This can also happen when unplug is done 4927 * during resume sequence ended 4928 * 4929 * In this case, we want to pretend we still 4930 * have a sink to keep the pipe running so that 4931 * hw state is consistent with the sw state 4932 */ 4933 drm_dbg_atomic(dev, 4934 "Failed to create new stream for crtc %d\n", 4935 acrtc->base.base.id); 4936 continue; 4937 } 4938 4939 if (dm_old_crtc_state->stream) 4940 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4941 4942 pm_runtime_get_noresume(dev->dev); 4943 4944 acrtc->enabled = true; 4945 acrtc->hw_mode = new_crtc_state->mode; 4946 crtc->hwmode = new_crtc_state->mode; 4947 mode_set_reset_required = true; 4948 set_backlight_level = true; 4949 } else if (modereset_required(new_crtc_state)) { 4950 drm_dbg_atomic(dev, 4951 "Atomic commit: RESET. crtc id %d:[%p]\n", 4952 acrtc->crtc_id, acrtc); 4953 /* i.e. reset mode */ 4954 if (dm_old_crtc_state->stream) 4955 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4956 4957 mode_set_reset_required = true; 4958 } 4959 } /* for_each_crtc_in_state() */ 4960 4961 /* if there mode set or reset, flush vblank work queue */ 4962 if (mode_set_reset_required) { 4963 if (dm->vblank_control_workqueue) 4964 flush_workqueue(dm->vblank_control_workqueue); 4965 } 4966 4967 dm_enable_per_frame_crtc_master_sync(dc_state); 4968 mutex_lock(&dm->dc_lock); 4969 dc_exit_ips_for_hw_access(dm->dc); 4970 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4971 4972 bool frl_stream_found = false; 4973 4974 for (i = 0; i < params.stream_count; i++) { 4975 struct dc_stream_state *stream = params.streams[i]; 4976 4977 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4978 frl_stream_found = true; 4979 break; 4980 } 4981 } 4982 if (frl_stream_found) { 4983 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 4984 &dm->hdmi_frl_status_polling_work, 4985 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 4986 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 4987 } else { 4988 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 4989 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 4990 } 4991 /* Allow idle optimization when vblank count is 0 for display off */ 4992 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 4993 dc_allow_idle_optimizations(dm->dc, true); 4994 mutex_unlock(&dm->dc_lock); 4995 4996 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4997 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4998 4999 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5000 5001 if (dm_new_crtc_state->stream != NULL) { 5002 const struct dc_stream_status *status = 5003 dc_stream_get_status(dm_new_crtc_state->stream); 5004 5005 if (!status) 5006 status = dc_state_get_stream_status(dc_state, 5007 dm_new_crtc_state->stream); 5008 if (!status) 5009 drm_err(dev, 5010 "got no status for stream %p on acrtc%p\n", 5011 dm_new_crtc_state->stream, acrtc); 5012 else 5013 acrtc->otg_inst = status->primary_otg_inst; 5014 } 5015 } 5016 5017 /* During boot up and resume the DC layer will reset the panel brightness 5018 * to fix a flicker issue. 5019 * It will cause the dm->actual_brightness is not the current panel brightness 5020 * level. (the dm->brightness is the correct panel level) 5021 * So we set the backlight level with dm->brightness value after set mode 5022 */ 5023 if (set_backlight_level) { 5024 for (i = 0; i < dm->num_of_edps; i++) { 5025 if (dm->backlight_dev[i]) 5026 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5027 } 5028 } 5029 } 5030 5031 static void dm_set_writeback(struct amdgpu_display_manager *dm, 5032 struct dm_crtc_state *crtc_state, 5033 struct drm_connector *connector, 5034 struct drm_connector_state *new_con_state) 5035 { 5036 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 5037 struct amdgpu_device *adev = dm->adev; 5038 struct amdgpu_crtc *acrtc; 5039 struct dc_writeback_info *wb_info; 5040 struct pipe_ctx *pipe = NULL; 5041 struct amdgpu_framebuffer *afb; 5042 int i = 0; 5043 5044 wb_info = kzalloc_obj(*wb_info); 5045 if (!wb_info) { 5046 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 5047 return; 5048 } 5049 5050 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 5051 if (!acrtc) { 5052 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 5053 kfree(wb_info); 5054 return; 5055 } 5056 5057 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 5058 if (!afb) { 5059 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 5060 kfree(wb_info); 5061 return; 5062 } 5063 5064 for (i = 0; i < MAX_PIPES; i++) { 5065 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 5066 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 5067 break; 5068 } 5069 } 5070 5071 /* fill in wb_info */ 5072 wb_info->wb_enabled = true; 5073 5074 wb_info->dwb_pipe_inst = 0; 5075 wb_info->dwb_params.dwbscl_black_color = 0; 5076 wb_info->dwb_params.hdr_mult = 0x1F000; 5077 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 5078 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 5079 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 5080 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 5081 5082 /* width & height from crtc */ 5083 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 5084 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 5085 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 5086 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 5087 5088 wb_info->dwb_params.cnv_params.crop_en = false; 5089 wb_info->dwb_params.stereo_params.stereo_enabled = false; 5090 5091 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 5092 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 5093 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 5094 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 5095 5096 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 5097 5098 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 5099 5100 wb_info->dwb_params.scaler_taps.h_taps = 1; 5101 wb_info->dwb_params.scaler_taps.v_taps = 1; 5102 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 5103 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 5104 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 5105 5106 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 5107 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 5108 5109 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 5110 wb_info->mcif_buf_params.luma_address[i] = afb->address; 5111 wb_info->mcif_buf_params.chroma_address[i] = 0; 5112 } 5113 5114 wb_info->mcif_buf_params.p_vmid = 1; 5115 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 5116 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 5117 wb_info->mcif_warmup_params.region_size = 5118 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 5119 } 5120 wb_info->mcif_warmup_params.p_vmid = 1; 5121 wb_info->writeback_source_plane = pipe->plane_state; 5122 5123 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 5124 5125 acrtc->wb_conn = wb_conn; 5126 drm_writeback_queue_job(wb_conn, new_con_state); 5127 5128 /* 5129 * Writeback completion is detected in the CRTC vblank IRQ 5130 * (dm_crtc_high_irq()). Take a vblank reference so the vblank interrupt 5131 * stays enabled while the writeback is pending; otherwise a 5132 * writeback-only commit right after drm_crtc_vblank_on() (e.g. 5133 * re-enabling a CRTC that was disabled) has no other vblank reference, 5134 * the IRQ never fires and the out fence times out. The matching put 5135 * happens once completion is signalled in dm_crtc_high_irq(), or when 5136 * the writeback is torn down in dm_clear_writeback(). 5137 * 5138 * Arm wb_pending only after the reference is held so the completion IRQ 5139 * cannot run its matching vblank_put before this get. 5140 */ 5141 WARN_ON(drm_crtc_vblank_get(&acrtc->base)); 5142 acrtc->wb_pending = true; 5143 } 5144 5145 static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 5146 { 5147 struct drm_connector_state *old_con_state, *new_con_state; 5148 struct drm_device *dev = state->dev; 5149 struct drm_connector *connector; 5150 struct amdgpu_device *adev = drm_to_adev(dev); 5151 int i; 5152 5153 if (!adev->dm.hdcp_workqueue) 5154 return; 5155 5156 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5157 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5158 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5159 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5160 struct dm_crtc_state *dm_new_crtc_state; 5161 struct amdgpu_dm_connector *aconnector; 5162 5163 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5164 continue; 5165 5166 aconnector = to_amdgpu_dm_connector(connector); 5167 5168 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 5169 5170 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 5171 connector->index, connector->status, connector->dpms); 5172 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 5173 old_con_state->content_protection, new_con_state->content_protection); 5174 5175 if (aconnector->dc_sink) { 5176 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 5177 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 5178 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 5179 aconnector->dc_sink->edid_caps.display_name); 5180 } 5181 } 5182 5183 new_crtc_state = NULL; 5184 old_crtc_state = NULL; 5185 5186 if (acrtc) { 5187 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5188 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5189 } 5190 5191 if (old_crtc_state) 5192 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 5193 old_crtc_state->enable, 5194 old_crtc_state->active, 5195 old_crtc_state->mode_changed, 5196 old_crtc_state->active_changed, 5197 old_crtc_state->connectors_changed); 5198 5199 if (new_crtc_state) 5200 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 5201 new_crtc_state->enable, 5202 new_crtc_state->active, 5203 new_crtc_state->mode_changed, 5204 new_crtc_state->active_changed, 5205 new_crtc_state->connectors_changed); 5206 5207 5208 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5209 5210 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 5211 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 5212 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 5213 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5214 dm_new_con_state->update_hdcp = true; 5215 continue; 5216 } 5217 5218 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 5219 old_con_state, connector, adev->dm.hdcp_workqueue)) { 5220 /* when display is unplugged from mst hub, connctor will 5221 * be destroyed within dm_dp_mst_connector_destroy. connector 5222 * hdcp perperties, like type, undesired, desired, enabled, 5223 * will be lost. So, save hdcp properties into hdcp_work within 5224 * amdgpu_dm_atomic_commit_tail. if the same display is 5225 * plugged back with same display index, its hdcp properties 5226 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 5227 */ 5228 5229 bool enable_encryption = false; 5230 5231 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 5232 enable_encryption = true; 5233 5234 if (aconnector->dc_link && aconnector->dc_sink && 5235 aconnector->dc_link->type == dc_connection_mst_branch) { 5236 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 5237 struct hdcp_workqueue *hdcp_w = 5238 &hdcp_work[aconnector->dc_link->link_index]; 5239 5240 hdcp_w->hdcp_content_type[connector->index] = 5241 new_con_state->hdcp_content_type; 5242 hdcp_w->content_protection[connector->index] = 5243 new_con_state->content_protection; 5244 } 5245 5246 if (new_crtc_state && new_crtc_state->mode_changed && 5247 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 5248 enable_encryption = true; 5249 5250 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 5251 5252 if (aconnector->dc_link) 5253 hdcp_update_display( 5254 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 5255 new_con_state->hdcp_content_type, enable_encryption); 5256 } 5257 } 5258 } 5259 5260 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 5261 { 5262 struct drm_crtc *crtc; 5263 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5264 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5265 int i, ret; 5266 5267 ret = drm_dp_mst_atomic_setup_commit(state); 5268 if (ret) 5269 return ret; 5270 5271 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5272 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5273 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5274 /* 5275 * Color management settings. We also update color properties 5276 * when a modeset is needed, to ensure it gets reprogrammed. 5277 */ 5278 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 5279 (dm_new_crtc_state->base.color_mgmt_changed || 5280 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5281 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5282 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 5283 if (ret) { 5284 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 5285 return ret; 5286 } 5287 } 5288 } 5289 5290 return 0; 5291 } 5292 5293 STATIC_IFN_KUNIT void set_multisync_trigger_params( 5294 struct dc_stream_state *stream) 5295 { 5296 struct dc_stream_state *master = NULL; 5297 5298 if (stream->triggered_crtc_reset.enabled) { 5299 master = stream->triggered_crtc_reset.event_source; 5300 stream->triggered_crtc_reset.event = 5301 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5302 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5303 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5304 } 5305 } 5306 EXPORT_IF_KUNIT(set_multisync_trigger_params); 5307 5308 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 5309 int stream_count) 5310 { 5311 int j, highest_rfr = 0, master_stream = 0; 5312 5313 for (j = 0; j < stream_count; j++) { 5314 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5315 int refresh_rate = 0; 5316 5317 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5318 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5319 if (refresh_rate > highest_rfr) { 5320 highest_rfr = refresh_rate; 5321 master_stream = j; 5322 } 5323 } 5324 } 5325 for (j = 0; j < stream_count; j++) { 5326 if (stream_set[j]) 5327 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5328 } 5329 } 5330 EXPORT_IF_KUNIT(set_master_stream); 5331 5332 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5333 { 5334 int i = 0; 5335 struct dc_stream_state *stream; 5336 5337 if (context->stream_count < 2) 5338 return; 5339 for (i = 0; i < context->stream_count ; i++) { 5340 if (!context->streams[i]) 5341 continue; 5342 /* 5343 * TODO: add a function to read AMD VSDB bits and set 5344 * crtc_sync_master.multi_sync_enabled flag 5345 * For now it's set to false 5346 */ 5347 } 5348 5349 set_master_stream(context->streams, context->stream_count); 5350 5351 for (i = 0; i < context->stream_count ; i++) { 5352 stream = context->streams[i]; 5353 5354 if (!stream) 5355 continue; 5356 5357 set_multisync_trigger_params(stream); 5358 } 5359 } 5360 5361 /** 5362 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5363 * @state: The atomic state to commit 5364 * 5365 * This will tell DC to commit the constructed DC state from atomic_check, 5366 * programming the hardware. Any failures here implies a hardware failure, since 5367 * atomic check should have filtered anything non-kosher. 5368 */ 5369 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 5370 { 5371 struct drm_device *dev = state->dev; 5372 struct amdgpu_device *adev = drm_to_adev(dev); 5373 struct amdgpu_display_manager *dm = &adev->dm; 5374 struct dm_atomic_state *dm_state; 5375 struct dc_state *dc_state = NULL; 5376 u32 i, j; 5377 struct drm_crtc *crtc; 5378 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5379 unsigned long flags; 5380 bool wait_for_vblank = true; 5381 struct drm_connector *connector; 5382 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5383 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5384 int crtc_disable_count = 0; 5385 5386 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5387 5388 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5389 drm_dp_mst_atomic_wait_for_dependencies(state); 5390 5391 dm_state = dm_atomic_get_new_state(state); 5392 if (dm_state && dm_state->context) { 5393 dc_state = dm_state->context; 5394 amdgpu_dm_commit_streams(state, dc_state); 5395 } 5396 5397 amdgpu_dm_update_hdcp(state); 5398 5399 /* Handle connector state changes */ 5400 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5401 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5402 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5403 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5404 struct dc_surface_update *dummy_updates; 5405 struct dc_stream_update stream_update; 5406 struct dc_info_packet hdr_packet; 5407 struct dc_stream_status *status = NULL; 5408 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5409 5410 memset(&stream_update, 0, sizeof(stream_update)); 5411 5412 if (acrtc) { 5413 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5414 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5415 } 5416 5417 /* Skip any modesets/resets */ 5418 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5419 continue; 5420 5421 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5422 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5423 5424 scaling_changed = is_scaling_state_different(dm_new_con_state, 5425 dm_old_con_state); 5426 5427 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5428 (dm_old_crtc_state->stream->output_color_space != 5429 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5430 output_color_space_changed = true; 5431 5432 abm_changed = dm_new_crtc_state->abm_level != 5433 dm_old_crtc_state->abm_level; 5434 5435 hdr_changed = 5436 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5437 5438 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5439 continue; 5440 5441 stream_update.stream = dm_new_crtc_state->stream; 5442 if (scaling_changed) { 5443 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5444 dm_new_con_state, dm_new_crtc_state->stream); 5445 5446 stream_update.src = dm_new_crtc_state->stream->src; 5447 stream_update.dst = dm_new_crtc_state->stream->dst; 5448 } 5449 5450 if (output_color_space_changed) { 5451 dm_new_crtc_state->stream->output_color_space 5452 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5453 5454 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5455 } 5456 5457 if (abm_changed) { 5458 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5459 5460 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5461 } 5462 5463 if (hdr_changed) { 5464 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5465 stream_update.hdr_static_metadata = &hdr_packet; 5466 } 5467 5468 status = dc_stream_get_status(dm_new_crtc_state->stream); 5469 5470 if (WARN_ON(!status)) 5471 continue; 5472 5473 WARN_ON(!status->plane_count); 5474 5475 /* 5476 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5477 * Here we create an empty update on each plane. 5478 * To fix this, DC should permit updating only stream properties. 5479 */ 5480 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5481 if (!dummy_updates) { 5482 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5483 continue; 5484 } 5485 for (j = 0; j < status->plane_count; j++) 5486 dummy_updates[j].surface = status->plane_states[j]; 5487 5488 sort(dummy_updates, status->plane_count, 5489 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5490 5491 mutex_lock(&dm->dc_lock); 5492 dc_exit_ips_for_hw_access(dm->dc); 5493 dc_update_planes_and_stream(dm->dc, 5494 dummy_updates, 5495 status->plane_count, 5496 dm_new_crtc_state->stream, 5497 &stream_update); 5498 mutex_unlock(&dm->dc_lock); 5499 kfree(dummy_updates); 5500 5501 drm_connector_update_privacy_screen(new_con_state); 5502 } 5503 5504 /** 5505 * Enable interrupts for CRTCs that are newly enabled or went through 5506 * a modeset. It was intentionally deferred until after the front end 5507 * state was modified to wait until the OTG was on and so the IRQ 5508 * handlers didn't access stale or invalid state. 5509 */ 5510 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5511 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5512 #ifdef CONFIG_DEBUG_FS 5513 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5514 #endif 5515 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5516 if (old_crtc_state->active && !new_crtc_state->active) 5517 crtc_disable_count++; 5518 5519 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5520 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5521 5522 /* For freesync config update on crtc state and params for irq */ 5523 update_stream_irq_parameters(dm, dm_new_crtc_state); 5524 5525 #ifdef CONFIG_DEBUG_FS 5526 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5527 cur_crc_src = acrtc->dm_irq_params.crc_src; 5528 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5529 #endif 5530 5531 if (new_crtc_state->active && 5532 (!old_crtc_state->active || 5533 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5534 dc_stream_retain(dm_new_crtc_state->stream); 5535 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5536 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5537 } 5538 /* Handle vrr on->off / off->on transitions */ 5539 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5540 5541 #ifdef CONFIG_DEBUG_FS 5542 if (new_crtc_state->active && 5543 (!old_crtc_state->active || 5544 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5545 /** 5546 * Frontend may have changed so reapply the CRC capture 5547 * settings for the stream. 5548 */ 5549 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5550 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5551 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5552 uint8_t cnt; 5553 5554 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5555 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5556 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5557 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5558 5559 /** 5560 * It takes 2 frames for HW to stably generate CRC when 5561 * resuming from suspend, so we set skip_frame_cnt 2. 5562 */ 5563 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5564 } 5565 } 5566 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5567 } 5568 #endif 5569 if (amdgpu_dm_crtc_configure_crc_source( 5570 crtc, dm_new_crtc_state, cur_crc_src)) 5571 drm_dbg_atomic(dev, "Failed to configure crc source"); 5572 } 5573 } 5574 #endif 5575 } 5576 5577 amdgpu_dm_mod_power_setup_streams(state, dm); 5578 5579 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5580 if (new_crtc_state->async_flip) 5581 wait_for_vblank = false; 5582 5583 /* update planes when needed per crtc*/ 5584 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5585 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5586 5587 if (dm_new_crtc_state->stream) 5588 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5589 } 5590 5591 /* Enable writeback */ 5592 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5593 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5594 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5595 5596 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5597 continue; 5598 5599 if (!new_con_state->writeback_job) 5600 continue; 5601 5602 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5603 5604 if (!new_crtc_state) 5605 continue; 5606 5607 if (acrtc->wb_enabled) 5608 continue; 5609 5610 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5611 5612 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5613 acrtc->wb_enabled = true; 5614 } 5615 5616 /* Update audio instances for each connector. */ 5617 amdgpu_dm_commit_audio(dev, state); 5618 5619 /* restore the backlight level */ 5620 for (i = 0; i < dm->num_of_edps; i++) { 5621 if (dm->backlight_dev[i] && 5622 (dm->actual_brightness[i] != dm->brightness[i])) 5623 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5624 } 5625 5626 /* 5627 * send vblank event on all events not handled in flip and 5628 * mark consumed event for drm_atomic_helper_commit_hw_done 5629 */ 5630 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5631 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5632 5633 if (new_crtc_state->event) 5634 drm_send_event_locked(dev, &new_crtc_state->event->base); 5635 5636 new_crtc_state->event = NULL; 5637 } 5638 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5639 5640 /* Signal HW programming completion */ 5641 drm_atomic_helper_commit_hw_done(state); 5642 5643 if (wait_for_vblank) 5644 drm_atomic_helper_wait_for_flip_done(dev, state); 5645 5646 drm_atomic_helper_cleanup_planes(dev, state); 5647 5648 /* Don't free the memory if we are hitting this as part of suspend. 5649 * This way we don't free any memory during suspend; see 5650 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5651 * non-suspend modeset or when the driver is torn down. 5652 */ 5653 if (!adev->in_suspend) { 5654 /* return the stolen vga memory back to VRAM */ 5655 if (!adev->mman.keep_stolen_vga_memory) 5656 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5657 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5658 } 5659 5660 /* 5661 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5662 * so we can put the GPU into runtime suspend if we're not driving any 5663 * displays anymore 5664 */ 5665 for (i = 0; i < crtc_disable_count; i++) 5666 pm_runtime_put_autosuspend(dev->dev); 5667 pm_runtime_mark_last_busy(dev->dev); 5668 5669 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5670 } 5671 5672 /* 5673 * Grabs all modesetting locks to serialize against any blocking commits, 5674 * Waits for completion of all non blocking commits. 5675 */ 5676 static int do_aquire_global_lock(struct drm_device *dev, 5677 struct drm_atomic_commit *state) 5678 { 5679 struct drm_crtc *crtc; 5680 struct drm_crtc_commit *commit; 5681 long ret; 5682 5683 /* 5684 * Adding all modeset locks to aquire_ctx will 5685 * ensure that when the framework release it the 5686 * extra locks we are locking here will get released to 5687 */ 5688 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5689 if (ret) 5690 return ret; 5691 5692 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5693 spin_lock(&crtc->commit_lock); 5694 commit = list_first_entry_or_null(&crtc->commit_list, 5695 struct drm_crtc_commit, commit_entry); 5696 if (commit) 5697 drm_crtc_commit_get(commit); 5698 spin_unlock(&crtc->commit_lock); 5699 5700 if (!commit) 5701 continue; 5702 5703 /* 5704 * Make sure all pending HW programming completed and 5705 * page flips done 5706 */ 5707 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5708 5709 if (ret > 0) 5710 ret = wait_for_completion_interruptible_timeout( 5711 &commit->flip_done, 10*HZ); 5712 5713 if (ret == 0) 5714 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5715 crtc->base.id, crtc->name); 5716 5717 drm_crtc_commit_put(commit); 5718 } 5719 5720 return ret < 0 ? ret : 0; 5721 } 5722 5723 static void get_freesync_config_for_crtc( 5724 struct dm_crtc_state *new_crtc_state, 5725 struct dm_connector_state *new_con_state) 5726 { 5727 struct mod_freesync_config config = {0}; 5728 struct amdgpu_dm_connector *aconnector; 5729 struct drm_display_mode *mode = &new_crtc_state->base.mode; 5730 int vrefresh = drm_mode_vrefresh(mode); 5731 bool fs_vid_mode = false; 5732 5733 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5734 return; 5735 5736 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 5737 5738 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 5739 vrefresh >= aconnector->min_vfreq && 5740 vrefresh <= aconnector->max_vfreq; 5741 5742 if (new_crtc_state->vrr_supported) { 5743 new_crtc_state->stream->ignore_msa_timing_param = true; 5744 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 5745 5746 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 5747 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 5748 config.vsif_supported = true; 5749 config.btr = true; 5750 5751 if (fs_vid_mode) { 5752 config.state = VRR_STATE_ACTIVE_FIXED; 5753 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 5754 goto out; 5755 } else if (new_crtc_state->base.vrr_enabled) { 5756 config.state = VRR_STATE_ACTIVE_VARIABLE; 5757 } else { 5758 config.state = VRR_STATE_INACTIVE; 5759 } 5760 } else { 5761 config.state = VRR_STATE_UNSUPPORTED; 5762 } 5763 out: 5764 new_crtc_state->freesync_config = config; 5765 } 5766 5767 static void reset_freesync_config_for_crtc( 5768 struct dm_crtc_state *new_crtc_state) 5769 { 5770 new_crtc_state->vrr_supported = false; 5771 5772 memset(&new_crtc_state->vrr_infopacket, 0, 5773 sizeof(new_crtc_state->vrr_infopacket)); 5774 } 5775 5776 STATIC_IFN_KUNIT bool 5777 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 5778 struct drm_crtc_state *new_crtc_state) 5779 { 5780 const struct drm_display_mode *old_mode, *new_mode; 5781 5782 if (!old_crtc_state || !new_crtc_state) 5783 return false; 5784 5785 old_mode = &old_crtc_state->mode; 5786 new_mode = &new_crtc_state->mode; 5787 5788 if (old_mode->clock == new_mode->clock && 5789 old_mode->hdisplay == new_mode->hdisplay && 5790 old_mode->vdisplay == new_mode->vdisplay && 5791 old_mode->htotal == new_mode->htotal && 5792 old_mode->vtotal != new_mode->vtotal && 5793 old_mode->hsync_start == new_mode->hsync_start && 5794 old_mode->vsync_start != new_mode->vsync_start && 5795 old_mode->hsync_end == new_mode->hsync_end && 5796 old_mode->vsync_end != new_mode->vsync_end && 5797 old_mode->hskew == new_mode->hskew && 5798 old_mode->vscan == new_mode->vscan && 5799 (old_mode->vsync_end - old_mode->vsync_start) == 5800 (new_mode->vsync_end - new_mode->vsync_start)) 5801 return true; 5802 5803 return false; 5804 } 5805 EXPORT_IF_KUNIT(is_timing_unchanged_for_freesync); 5806 5807 STATIC_IFN_KUNIT void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 5808 { 5809 u64 num, den, res; 5810 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 5811 5812 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 5813 5814 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 5815 den = (unsigned long long)new_crtc_state->mode.htotal * 5816 (unsigned long long)new_crtc_state->mode.vtotal; 5817 5818 res = div_u64(num, den); 5819 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 5820 } 5821 EXPORT_IF_KUNIT(set_freesync_fixed_config); 5822 5823 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5824 struct drm_atomic_commit *state, 5825 struct drm_crtc *crtc, 5826 struct drm_crtc_state *old_crtc_state, 5827 struct drm_crtc_state *new_crtc_state, 5828 bool enable, 5829 bool *lock_and_validation_needed) 5830 { 5831 struct dm_atomic_state *dm_state = NULL; 5832 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5833 struct dc_stream_state *new_stream; 5834 struct amdgpu_device *adev = dm->adev; 5835 int ret = 0; 5836 5837 /* 5838 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5839 * update changed items 5840 */ 5841 struct amdgpu_crtc *acrtc = NULL; 5842 struct drm_connector *connector = NULL; 5843 struct amdgpu_dm_connector *aconnector = NULL; 5844 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5845 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5846 5847 new_stream = NULL; 5848 5849 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5850 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5851 acrtc = to_amdgpu_crtc(crtc); 5852 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5853 if (connector) 5854 aconnector = to_amdgpu_dm_connector(connector); 5855 5856 /* TODO This hack should go away */ 5857 if (connector && enable) { 5858 /* Make sure fake sink is created in plug-in scenario */ 5859 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5860 connector); 5861 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5862 connector); 5863 5864 if (WARN_ON(!drm_new_conn_state)) { 5865 ret = -EINVAL; 5866 goto fail; 5867 } 5868 5869 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5870 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5871 5872 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5873 goto skip_modeset; 5874 5875 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5876 &new_crtc_state->mode, 5877 dm_new_conn_state, 5878 dm_old_crtc_state->stream); 5879 5880 /* 5881 * we can have no stream on ACTION_SET if a display 5882 * was disconnected during S3, in this case it is not an 5883 * error, the OS will be updated after detection, and 5884 * will do the right thing on next atomic commit 5885 */ 5886 5887 if (!new_stream) { 5888 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5889 __func__, acrtc->base.base.id); 5890 ret = -ENOMEM; 5891 goto fail; 5892 } 5893 5894 /* 5895 * TODO: Check VSDB bits to decide whether this should 5896 * be enabled or not. 5897 */ 5898 new_stream->triggered_crtc_reset.enabled = 5899 dm->force_timing_sync; 5900 5901 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5902 5903 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5904 &new_stream->hdr_static_metadata); 5905 if (ret) 5906 goto fail; 5907 5908 /* 5909 * If we already removed the old stream from the context 5910 * (and set the new stream to NULL) then we can't reuse 5911 * the old stream even if the stream and scaling are unchanged. 5912 * We'll hit the BUG_ON and black screen. 5913 * 5914 * TODO: Refactor this function to allow this check to work 5915 * in all conditions. 5916 */ 5917 if (amdgpu_freesync_vid_mode && 5918 dm_new_crtc_state->stream && 5919 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5920 goto skip_modeset; 5921 5922 if (dm_new_crtc_state->stream && 5923 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5924 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5925 new_crtc_state->mode_changed = false; 5926 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5927 new_crtc_state->mode_changed); 5928 } 5929 } 5930 5931 /* mode_changed flag may get updated above, need to check again */ 5932 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5933 goto skip_modeset; 5934 5935 drm_dbg_state(state->dev, 5936 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5937 acrtc->crtc_id, 5938 new_crtc_state->enable, 5939 new_crtc_state->active, 5940 new_crtc_state->planes_changed, 5941 new_crtc_state->mode_changed, 5942 new_crtc_state->active_changed, 5943 new_crtc_state->connectors_changed); 5944 5945 /* Remove stream for any changed/disabled CRTC */ 5946 if (!enable) { 5947 5948 if (!dm_old_crtc_state->stream) 5949 goto skip_modeset; 5950 5951 /* Unset freesync video if it was active before */ 5952 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5953 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5954 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5955 } 5956 5957 /* Now check if we should set freesync video mode */ 5958 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5959 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5960 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5961 is_timing_unchanged_for_freesync(new_crtc_state, 5962 old_crtc_state)) { 5963 new_crtc_state->mode_changed = false; 5964 drm_dbg_driver(adev_to_drm(adev), 5965 "Mode change not required for front porch change, setting mode_changed to %d", 5966 new_crtc_state->mode_changed); 5967 5968 set_freesync_fixed_config(dm_new_crtc_state); 5969 5970 goto skip_modeset; 5971 } else if (amdgpu_freesync_vid_mode && aconnector && 5972 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5973 aconnector)) { 5974 struct drm_display_mode *high_mode; 5975 5976 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5977 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 5978 set_freesync_fixed_config(dm_new_crtc_state); 5979 } 5980 5981 ret = dm_atomic_get_state(state, &dm_state); 5982 if (ret) 5983 goto fail; 5984 5985 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 5986 crtc->base.id); 5987 5988 /* i.e. reset mode */ 5989 if (dc_state_remove_stream( 5990 dm->dc, 5991 dm_state->context, 5992 dm_old_crtc_state->stream) != DC_OK) { 5993 ret = -EINVAL; 5994 goto fail; 5995 } 5996 5997 dc_stream_release(dm_old_crtc_state->stream); 5998 dm_new_crtc_state->stream = NULL; 5999 6000 reset_freesync_config_for_crtc(dm_new_crtc_state); 6001 6002 *lock_and_validation_needed = true; 6003 6004 } else {/* Add stream for any updated/enabled CRTC */ 6005 /* 6006 * Quick fix to prevent NULL pointer on new_stream when 6007 * added MST connectors not found in existing crtc_state in the chained mode 6008 * TODO: need to dig out the root cause of that 6009 */ 6010 if (!connector) 6011 goto skip_modeset; 6012 6013 if (modereset_required(new_crtc_state)) 6014 goto skip_modeset; 6015 6016 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 6017 dm_old_crtc_state->stream)) { 6018 6019 WARN_ON(dm_new_crtc_state->stream); 6020 6021 ret = dm_atomic_get_state(state, &dm_state); 6022 if (ret) 6023 goto fail; 6024 6025 dm_new_crtc_state->stream = new_stream; 6026 6027 dc_stream_retain(new_stream); 6028 6029 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 6030 crtc->base.id); 6031 6032 if (dc_state_add_stream( 6033 dm->dc, 6034 dm_state->context, 6035 dm_new_crtc_state->stream) != DC_OK) { 6036 ret = -EINVAL; 6037 goto fail; 6038 } 6039 6040 *lock_and_validation_needed = true; 6041 } 6042 } 6043 6044 skip_modeset: 6045 /* Release extra reference */ 6046 if (new_stream) 6047 dc_stream_release(new_stream); 6048 new_stream = NULL; 6049 6050 /* 6051 * We want to do dc stream updates that do not require a 6052 * full modeset below. 6053 */ 6054 if (!(enable && connector && new_crtc_state->active)) 6055 return 0; 6056 /* 6057 * Given above conditions, the dc state cannot be NULL because: 6058 * 1. We're in the process of enabling CRTCs (just been added 6059 * to the dc context, or already is on the context) 6060 * 2. Has a valid connector attached, and 6061 * 3. Is currently active and enabled. 6062 * => The dc stream state currently exists. 6063 */ 6064 BUG_ON(dm_new_crtc_state->stream == NULL); 6065 6066 /* Scaling or underscan settings */ 6067 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 6068 drm_atomic_crtc_needs_modeset(new_crtc_state)) 6069 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 6070 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 6071 6072 /* ABM settings */ 6073 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6074 6075 /* 6076 * Color management settings. We also update color properties 6077 * when a modeset is needed, to ensure it gets reprogrammed. 6078 */ 6079 if (dm_new_crtc_state->base.color_mgmt_changed || 6080 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 6081 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6082 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 6083 if (ret) 6084 goto fail; 6085 } 6086 6087 /* Update Freesync settings. */ 6088 get_freesync_config_for_crtc(dm_new_crtc_state, 6089 dm_new_conn_state); 6090 6091 return ret; 6092 6093 fail: 6094 if (new_stream) 6095 dc_stream_release(new_stream); 6096 return ret; 6097 } 6098 6099 static bool should_reset_plane(struct drm_atomic_commit *state, 6100 struct drm_plane *plane, 6101 struct drm_plane_state *old_plane_state, 6102 struct drm_plane_state *new_plane_state) 6103 { 6104 struct drm_plane *other; 6105 struct drm_plane_state *old_other_state, *new_other_state; 6106 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6107 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 6108 struct amdgpu_device *adev = drm_to_adev(plane->dev); 6109 struct drm_connector_state *new_con_state; 6110 struct drm_connector *connector; 6111 int i; 6112 6113 /* 6114 * TODO: Remove this hack for all asics once it proves that the 6115 * fast updates works fine on DCN3.2+. 6116 */ 6117 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 6118 state->allow_modeset) 6119 return true; 6120 6121 /* Check for writeback commit */ 6122 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6123 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 6124 continue; 6125 6126 if (new_con_state->writeback_job) 6127 return true; 6128 } 6129 6130 if (amdgpu_in_reset(adev) && state->allow_modeset) 6131 return true; 6132 6133 /* Exit early if we know that we're adding or removing the plane. */ 6134 if (old_plane_state->crtc != new_plane_state->crtc) 6135 return true; 6136 6137 /* old crtc == new_crtc == NULL, plane not in context. */ 6138 if (!new_plane_state->crtc) 6139 return false; 6140 6141 new_crtc_state = 6142 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 6143 old_crtc_state = 6144 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 6145 6146 if (!new_crtc_state) 6147 return true; 6148 6149 /* 6150 * A change in cursor mode means a new dc pipe needs to be acquired or 6151 * released from the state 6152 */ 6153 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 6154 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6155 if (plane->type == DRM_PLANE_TYPE_CURSOR && 6156 old_dm_crtc_state != NULL && 6157 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 6158 return true; 6159 } 6160 6161 /* CRTC Degamma changes currently require us to recreate planes. */ 6162 if (new_crtc_state->color_mgmt_changed) 6163 return true; 6164 6165 /* 6166 * On zpos change, planes need to be reordered by removing and re-adding 6167 * them one by one to the dc state, in order of descending zpos. 6168 * 6169 * TODO: We can likely skip bandwidth validation if the only thing that 6170 * changed about the plane was it'z z-ordering. 6171 */ 6172 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 6173 return true; 6174 6175 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 6176 return true; 6177 6178 /* 6179 * If there are any new primary or overlay planes being added or 6180 * removed then the z-order can potentially change. To ensure 6181 * correct z-order and pipe acquisition the current DC architecture 6182 * requires us to remove and recreate all existing planes. 6183 * 6184 * TODO: Come up with a more elegant solution for this. 6185 */ 6186 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 6187 struct amdgpu_framebuffer *old_afb, *new_afb; 6188 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 6189 6190 dm_new_other_state = to_dm_plane_state(new_other_state); 6191 dm_old_other_state = to_dm_plane_state(old_other_state); 6192 6193 if (other->type == DRM_PLANE_TYPE_CURSOR) 6194 continue; 6195 6196 if (old_other_state->crtc != new_plane_state->crtc && 6197 new_other_state->crtc != new_plane_state->crtc) 6198 continue; 6199 6200 if (old_other_state->crtc != new_other_state->crtc) 6201 return true; 6202 6203 /* Src/dst size and scaling updates. */ 6204 if (old_other_state->src_w != new_other_state->src_w || 6205 old_other_state->src_h != new_other_state->src_h || 6206 old_other_state->crtc_w != new_other_state->crtc_w || 6207 old_other_state->crtc_h != new_other_state->crtc_h) 6208 return true; 6209 6210 /* Rotation / mirroring updates. */ 6211 if (old_other_state->rotation != new_other_state->rotation) 6212 return true; 6213 6214 /* Blending updates. */ 6215 if (old_other_state->pixel_blend_mode != 6216 new_other_state->pixel_blend_mode) 6217 return true; 6218 6219 /* Alpha updates. */ 6220 if (old_other_state->alpha != new_other_state->alpha) 6221 return true; 6222 6223 /* Colorspace changes. */ 6224 if (old_other_state->color_range != new_other_state->color_range || 6225 old_other_state->color_encoding != new_other_state->color_encoding) 6226 return true; 6227 6228 /* HDR/Transfer Function changes. */ 6229 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 6230 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 6231 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 6232 dm_old_other_state->ctm != dm_new_other_state->ctm || 6233 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 6234 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 6235 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 6236 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 6237 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 6238 return true; 6239 6240 /* Framebuffer checks fall at the end. */ 6241 if (!old_other_state->fb || !new_other_state->fb) 6242 continue; 6243 6244 /* Pixel format changes can require bandwidth updates. */ 6245 if (old_other_state->fb->format != new_other_state->fb->format) 6246 return true; 6247 6248 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 6249 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 6250 6251 /* Tiling and DCC changes also require bandwidth updates. */ 6252 if (old_afb->tiling_flags != new_afb->tiling_flags || 6253 old_afb->base.modifier != new_afb->base.modifier) 6254 return true; 6255 } 6256 6257 return false; 6258 } 6259 6260 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 6261 struct drm_plane_state *new_plane_state, 6262 struct drm_framebuffer *fb) 6263 { 6264 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 6265 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 6266 unsigned int pitch; 6267 bool linear; 6268 6269 if (fb->width > new_acrtc->max_cursor_width || 6270 fb->height > new_acrtc->max_cursor_height) { 6271 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB size %dx%d\n", 6272 new_plane_state->fb->width, 6273 new_plane_state->fb->height); 6274 return -EINVAL; 6275 } 6276 if (new_plane_state->src_w != fb->width << 16 || 6277 new_plane_state->src_h != fb->height << 16) { 6278 drm_dbg_atomic(adev_to_drm(adev), "Cropping not supported for cursor plane\n"); 6279 return -EINVAL; 6280 } 6281 6282 /* Pitch in pixels */ 6283 pitch = fb->pitches[0] / fb->format->cpp[0]; 6284 6285 if (fb->width != pitch) { 6286 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB width %d doesn't match pitch %d", 6287 fb->width, pitch); 6288 return -EINVAL; 6289 } 6290 6291 switch (pitch) { 6292 case 64: 6293 case 128: 6294 case 256: 6295 /* FB pitch is supported by cursor plane */ 6296 break; 6297 default: 6298 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB pitch %d px\n", pitch); 6299 return -EINVAL; 6300 } 6301 6302 /* Core DRM takes care of checking FB modifiers, so we only need to 6303 * check tiling flags when the FB doesn't have a modifier. 6304 */ 6305 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 6306 if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 6307 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 6308 } else if (adev->family >= AMDGPU_FAMILY_AI) { 6309 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 6310 } else { 6311 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 6312 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 6313 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 6314 } 6315 if (!linear) { 6316 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB not linear"); 6317 return -EINVAL; 6318 } 6319 } 6320 6321 return 0; 6322 } 6323 6324 /* 6325 * Helper function for checking the cursor in native mode 6326 */ 6327 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 6328 struct drm_plane *plane, 6329 struct drm_plane_state *new_plane_state, 6330 bool enable) 6331 { 6332 6333 struct amdgpu_crtc *new_acrtc; 6334 int ret; 6335 6336 if (!enable || !new_plane_crtc || 6337 drm_atomic_plane_disabling(plane->state, new_plane_state)) 6338 return 0; 6339 6340 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 6341 6342 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 6343 drm_dbg_atomic(new_plane_crtc->dev, "Cropping not supported for cursor plane\n"); 6344 return -EINVAL; 6345 } 6346 6347 if (new_plane_state->fb) { 6348 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 6349 new_plane_state->fb); 6350 if (ret) 6351 return ret; 6352 } 6353 6354 return 0; 6355 } 6356 6357 static bool dm_should_update_native_cursor(struct drm_atomic_commit *state, 6358 struct drm_crtc *old_plane_crtc, 6359 struct drm_crtc *new_plane_crtc, 6360 bool enable) 6361 { 6362 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6363 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6364 6365 if (!enable) { 6366 if (old_plane_crtc == NULL) 6367 return true; 6368 6369 old_crtc_state = drm_atomic_get_old_crtc_state( 6370 state, old_plane_crtc); 6371 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6372 6373 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6374 } else { 6375 if (new_plane_crtc == NULL) 6376 return true; 6377 6378 new_crtc_state = drm_atomic_get_new_crtc_state( 6379 state, new_plane_crtc); 6380 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6381 6382 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6383 } 6384 } 6385 6386 static int dm_update_plane_state(struct dc *dc, 6387 struct drm_atomic_commit *state, 6388 struct drm_plane *plane, 6389 struct drm_plane_state *old_plane_state, 6390 struct drm_plane_state *new_plane_state, 6391 bool enable, 6392 bool *lock_and_validation_needed, 6393 bool *is_top_most_overlay) 6394 { 6395 6396 struct dm_atomic_state *dm_state = NULL; 6397 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6398 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6399 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6400 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6401 bool needs_reset, update_native_cursor; 6402 int ret = 0; 6403 6404 6405 new_plane_crtc = new_plane_state->crtc; 6406 old_plane_crtc = old_plane_state->crtc; 6407 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6408 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6409 6410 update_native_cursor = dm_should_update_native_cursor(state, 6411 old_plane_crtc, 6412 new_plane_crtc, 6413 enable); 6414 6415 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 6416 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6417 new_plane_state, enable); 6418 if (ret) 6419 return ret; 6420 6421 return 0; 6422 } 6423 6424 needs_reset = should_reset_plane(state, plane, old_plane_state, 6425 new_plane_state); 6426 6427 /* Remove any changed/removed planes */ 6428 if (!enable) { 6429 if (!needs_reset) 6430 return 0; 6431 6432 if (!old_plane_crtc) 6433 return 0; 6434 6435 old_crtc_state = drm_atomic_get_old_crtc_state( 6436 state, old_plane_crtc); 6437 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6438 6439 if (!dm_old_crtc_state->stream) 6440 return 0; 6441 6442 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 6443 plane->base.id, old_plane_crtc->base.id); 6444 6445 ret = dm_atomic_get_state(state, &dm_state); 6446 if (ret) 6447 return ret; 6448 6449 if (!dc_state_remove_plane( 6450 dc, 6451 dm_old_crtc_state->stream, 6452 dm_old_plane_state->dc_state, 6453 dm_state->context)) { 6454 6455 return -EINVAL; 6456 } 6457 6458 if (dm_old_plane_state->dc_state) 6459 dc_plane_state_release(dm_old_plane_state->dc_state); 6460 6461 dm_new_plane_state->dc_state = NULL; 6462 6463 *lock_and_validation_needed = true; 6464 6465 } else { /* Add new planes */ 6466 struct dc_plane_state *dc_new_plane_state; 6467 6468 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6469 return 0; 6470 6471 if (!new_plane_crtc) 6472 return 0; 6473 6474 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6475 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6476 6477 if (!dm_new_crtc_state->stream) 6478 return 0; 6479 6480 if (!needs_reset) 6481 return 0; 6482 6483 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 6484 if (ret) 6485 goto out; 6486 6487 WARN_ON(dm_new_plane_state->dc_state); 6488 6489 dc_new_plane_state = dc_create_plane_state(dc); 6490 if (!dc_new_plane_state) { 6491 ret = -ENOMEM; 6492 goto out; 6493 } 6494 6495 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 6496 plane->base.id, new_plane_crtc->base.id); 6497 6498 ret = fill_dc_plane_attributes( 6499 drm_to_adev(new_plane_crtc->dev), 6500 dc_new_plane_state, 6501 new_plane_state, 6502 new_crtc_state); 6503 if (ret) { 6504 dc_plane_state_release(dc_new_plane_state); 6505 goto out; 6506 } 6507 6508 ret = dm_atomic_get_state(state, &dm_state); 6509 if (ret) { 6510 dc_plane_state_release(dc_new_plane_state); 6511 goto out; 6512 } 6513 6514 /* 6515 * Any atomic check errors that occur after this will 6516 * not need a release. The plane state will be attached 6517 * to the stream, and therefore part of the atomic 6518 * state. It'll be released when the atomic state is 6519 * cleaned. 6520 */ 6521 if (!dc_state_add_plane( 6522 dc, 6523 dm_new_crtc_state->stream, 6524 dc_new_plane_state, 6525 dm_state->context)) { 6526 6527 dc_plane_state_release(dc_new_plane_state); 6528 ret = -EINVAL; 6529 goto out; 6530 } 6531 6532 dm_new_plane_state->dc_state = dc_new_plane_state; 6533 6534 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 6535 6536 /* Tell DC to do a full surface update every time there 6537 * is a plane change. Inefficient, but works for now. 6538 */ 6539 dm_new_plane_state->dc_state->update_bits.full_update = 1; 6540 6541 *lock_and_validation_needed = true; 6542 } 6543 6544 out: 6545 /* If enabling cursor overlay failed, attempt fallback to native mode */ 6546 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 6547 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6548 new_plane_state, enable); 6549 if (ret) 6550 return ret; 6551 6552 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 6553 } 6554 6555 return ret; 6556 } 6557 6558 STATIC_IFN_KUNIT void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 6559 int *src_w, int *src_h) 6560 { 6561 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 6562 case DRM_MODE_ROTATE_90: 6563 case DRM_MODE_ROTATE_270: 6564 *src_w = plane_state->src_h >> 16; 6565 *src_h = plane_state->src_w >> 16; 6566 break; 6567 case DRM_MODE_ROTATE_0: 6568 case DRM_MODE_ROTATE_180: 6569 default: 6570 *src_w = plane_state->src_w >> 16; 6571 *src_h = plane_state->src_h >> 16; 6572 break; 6573 } 6574 } 6575 EXPORT_IF_KUNIT(dm_get_oriented_plane_size); 6576 6577 STATIC_IFN_KUNIT void 6578 dm_get_plane_scale(struct drm_plane_state *plane_state, 6579 int *out_plane_scale_w, int *out_plane_scale_h) 6580 { 6581 int plane_src_w, plane_src_h; 6582 6583 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 6584 *out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0; 6585 *out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0; 6586 } 6587 EXPORT_IF_KUNIT(dm_get_plane_scale); 6588 6589 /* 6590 * The normalized_zpos value cannot be used by this iterator directly. It's only 6591 * calculated for enabled planes, potentially causing normalized_zpos collisions 6592 * between enabled/disabled planes in the atomic state. We need a unique value 6593 * so that the iterator will not generate the same object twice, or loop 6594 * indefinitely. 6595 */ 6596 static inline struct __drm_planes_state *__get_next_zpos( 6597 struct drm_atomic_commit *state, 6598 struct __drm_planes_state *prev) 6599 { 6600 unsigned int highest_zpos = 0, prev_zpos = 256; 6601 uint32_t highest_id = 0, prev_id = UINT_MAX; 6602 struct drm_plane_state *new_plane_state; 6603 struct drm_plane *plane; 6604 int i, highest_i = -1; 6605 6606 if (prev != NULL) { 6607 prev_zpos = prev->new_state->zpos; 6608 prev_id = prev->ptr->base.id; 6609 } 6610 6611 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 6612 /* Skip planes with higher zpos than the previously returned */ 6613 if (new_plane_state->zpos > prev_zpos || 6614 (new_plane_state->zpos == prev_zpos && 6615 plane->base.id >= prev_id)) 6616 continue; 6617 6618 /* Save the index of the plane with highest zpos */ 6619 if (new_plane_state->zpos > highest_zpos || 6620 (new_plane_state->zpos == highest_zpos && 6621 plane->base.id > highest_id)) { 6622 highest_zpos = new_plane_state->zpos; 6623 highest_id = plane->base.id; 6624 highest_i = i; 6625 } 6626 } 6627 6628 if (highest_i < 0) 6629 return NULL; 6630 6631 return &state->planes[highest_i]; 6632 } 6633 6634 /* 6635 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 6636 * by descending zpos, as read from the new plane state. This is the same 6637 * ordering as defined by drm_atomic_normalize_zpos(). 6638 */ 6639 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 6640 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 6641 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 6642 for_each_if(((plane) = __i->ptr, \ 6643 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 6644 (old_plane_state) = __i->old_state, \ 6645 (new_plane_state) = __i->new_state, 1)) 6646 6647 static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) 6648 { 6649 struct drm_connector *connector; 6650 struct drm_connector_state *conn_state, *old_conn_state; 6651 struct amdgpu_dm_connector *aconnector = NULL; 6652 int i; 6653 6654 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6655 if (!conn_state->crtc) 6656 conn_state = old_conn_state; 6657 6658 if (conn_state->crtc != crtc) 6659 continue; 6660 6661 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6662 continue; 6663 6664 aconnector = to_amdgpu_dm_connector(connector); 6665 if (!aconnector->mst_output_port || !aconnector->mst_root) 6666 aconnector = NULL; 6667 else 6668 break; 6669 } 6670 6671 if (!aconnector) 6672 return 0; 6673 6674 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6675 } 6676 6677 /** 6678 * DOC: Cursor Modes - Native vs Overlay 6679 * 6680 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 6681 * plane. It does not require a dedicated hw plane to enable, but it is 6682 * subjected to the same z-order and scaling as the hw plane. It also has format 6683 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 6684 * hw plane. 6685 * 6686 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 6687 * own scaling and z-pos. It also has no blending restrictions. It lends to a 6688 * cursor behavior more akin to a DRM client's expectations. However, it does 6689 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 6690 * available. 6691 */ 6692 6693 /** 6694 * dm_plane_color_pipeline_active() - Check if a plane's color pipeline active. 6695 * @state: DRM atomic state 6696 * @plane: DRM plane to check 6697 * @use_old: if true, inspect the old colorop states; otherwise the new ones 6698 * 6699 * A color pipeline may be selected (color_pipeline != NULL) but still is 6700 * inactive if every colorop in the chain is bypassed. Only return 6701 * true when at least one colorop has bypass == false, meaning the cursor 6702 * would be subjected to the transformation in native mode. 6703 * 6704 * Return: true if the pipeline modifies pixels, false otherwise. 6705 */ 6706 static bool dm_plane_color_pipeline_active(struct drm_atomic_commit *state, 6707 struct drm_plane *plane, 6708 bool use_old) 6709 { 6710 struct drm_colorop *colorop; 6711 struct drm_colorop_state *old_colorop_state, *new_colorop_state; 6712 int i; 6713 6714 for_each_oldnew_colorop_in_state(state, colorop, old_colorop_state, new_colorop_state, i) { 6715 struct drm_colorop_state *cstate = use_old ? old_colorop_state : new_colorop_state; 6716 6717 if (cstate->colorop->plane != plane) 6718 continue; 6719 if (!cstate->bypass) 6720 return true; 6721 } 6722 return false; 6723 } 6724 6725 /** 6726 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 6727 * @adev: amdgpu device 6728 * @state: DRM atomic state 6729 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 6730 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 6731 * 6732 * Get whether the cursor should be enabled in native mode, or overlay mode, on 6733 * the dm_crtc_state. 6734 * 6735 * The cursor should be enabled in overlay mode if there exists an underlying 6736 * plane - on which the cursor may be blended - that is either YUV formatted, 6737 * scaled differently from the cursor, or has a color pipeline active. 6738 * 6739 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 6740 * calling this function. 6741 * 6742 * Return: 0 on success, or an error code if getting the cursor plane state 6743 * failed. 6744 */ 6745 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 6746 struct drm_atomic_commit *state, 6747 struct dm_crtc_state *dm_crtc_state, 6748 enum amdgpu_dm_cursor_mode *cursor_mode) 6749 { 6750 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 6751 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 6752 struct drm_plane *plane; 6753 bool consider_mode_change = false; 6754 bool entire_crtc_covered = false; 6755 bool cursor_changed = false; 6756 int underlying_scale_w, underlying_scale_h; 6757 int cursor_scale_w, cursor_scale_h; 6758 int i; 6759 6760 /* Overlay cursor not supported on HW before DCN 6761 * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 6762 * as previous DCN generations, so enable native mode on DCN401/420 6763 * 6764 * Always set native cursor mode when the CRTC is disabled, 6765 * to make sure it doesn't cause atomic commits to fail when 6766 * they are trying to disable the CRTC. 6767 */ 6768 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || 6769 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 6770 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1) || 6771 !dm_crtc_state->base.enable) { 6772 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6773 return 0; 6774 } 6775 6776 /* Init cursor_mode to be the same as current */ 6777 *cursor_mode = dm_crtc_state->cursor_mode; 6778 6779 /* 6780 * Cursor mode can change if a plane's format changes, scale changes, is 6781 * enabled/disabled, z-order changes, or color management properties change. 6782 */ 6783 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 6784 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 6785 6786 /* Only care about planes on this CRTC */ 6787 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 6788 continue; 6789 6790 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6791 cursor_changed = true; 6792 6793 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 6794 drm_atomic_plane_disabling(old_plane_state, plane_state) || 6795 old_plane_state->fb->format != plane_state->fb->format) { 6796 consider_mode_change = true; 6797 break; 6798 } 6799 6800 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 6801 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 6802 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 6803 consider_mode_change = true; 6804 break; 6805 } 6806 6807 /* 6808 * A non-cursor plane moving or resizing (without a scale change) 6809 * changes how much of the CRTC it covers. This can create or 6810 * remove a hole under the cursor and thus flip the required 6811 * cursor mode (native vs overlay), so its destination rect must 6812 * be re-evaluated too. 6813 * 6814 * The cursor plane itself is deliberately excluded: the cursor 6815 * mode depends on the underlying planes' coverage, not on the 6816 * cursor's position (see the entire_crtc_covered logic below). 6817 * Triggering on cursor movement would force every legacy cursor 6818 * update off its fast path, and in a cursor-only commit - where 6819 * the underlying planes are not part of the state - the coverage 6820 * loop would see no covering plane and misevaluate the mode as 6821 * overlay, regressing flip-vs-cursor-legacy. 6822 */ 6823 if (plane->type != DRM_PLANE_TYPE_CURSOR && 6824 (old_plane_state->crtc_x != plane_state->crtc_x || 6825 old_plane_state->crtc_y != plane_state->crtc_y || 6826 old_plane_state->crtc_w != plane_state->crtc_w || 6827 old_plane_state->crtc_h != plane_state->crtc_h)) { 6828 consider_mode_change = true; 6829 break; 6830 } 6831 6832 if (dm_plane_color_pipeline_active(state, plane, true) != 6833 dm_plane_color_pipeline_active(state, plane, false)) { 6834 consider_mode_change = true; 6835 break; 6836 } 6837 } 6838 6839 if (!consider_mode_change && !crtc_state->zpos_changed) 6840 return 0; 6841 6842 /* 6843 * If no cursor change on this CRTC, and not enabled on this CRTC, then 6844 * no need to set cursor mode. This avoids needlessly locking the cursor 6845 * state. 6846 */ 6847 if (!cursor_changed && 6848 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 6849 return 0; 6850 } 6851 6852 cursor_state = drm_atomic_get_plane_state(state, 6853 crtc_state->crtc->cursor); 6854 if (IS_ERR(cursor_state)) 6855 return PTR_ERR(cursor_state); 6856 6857 /* Cursor is disabled */ 6858 if (!cursor_state->fb) 6859 return 0; 6860 6861 /* For all planes in descending z-order (all of which are below cursor 6862 * as per zpos definitions), check their scaling and format 6863 */ 6864 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 6865 6866 /* Only care about non-cursor planes on this CRTC */ 6867 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 6868 plane->type == DRM_PLANE_TYPE_CURSOR) 6869 continue; 6870 6871 /* Underlying plane is YUV format - use overlay cursor */ 6872 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 6873 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6874 return 0; 6875 } 6876 6877 /* Underlying plane has an active color pipeline - cursor would be transformed */ 6878 if (dm_plane_color_pipeline_active(state, plane, false)) { 6879 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6880 return 0; 6881 } 6882 6883 dm_get_plane_scale(plane_state, 6884 &underlying_scale_w, &underlying_scale_h); 6885 dm_get_plane_scale(cursor_state, 6886 &cursor_scale_w, &cursor_scale_h); 6887 6888 /* Underlying plane has different scale - use overlay cursor */ 6889 if (cursor_scale_w != underlying_scale_w && 6890 cursor_scale_h != underlying_scale_h) { 6891 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6892 return 0; 6893 } 6894 6895 /* If this plane covers the whole CRTC, no need to check planes underneath */ 6896 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 6897 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 6898 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 6899 entire_crtc_covered = true; 6900 break; 6901 } 6902 } 6903 6904 /* If planes do not cover the entire CRTC, use overlay mode to enable 6905 * cursor over holes 6906 */ 6907 if (entire_crtc_covered) 6908 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6909 else 6910 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6911 6912 return 0; 6913 } 6914 6915 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6916 struct drm_atomic_commit *state, 6917 struct drm_crtc_state *crtc_state) 6918 { 6919 struct drm_plane *plane; 6920 struct drm_plane_state *new_plane_state, *old_plane_state; 6921 6922 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6923 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6924 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6925 6926 if (!old_plane_state || !new_plane_state) 6927 continue; 6928 6929 if (old_plane_state->fb && new_plane_state->fb && 6930 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6931 return true; 6932 } 6933 6934 return false; 6935 } 6936 6937 /** 6938 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6939 * 6940 * @dev: The DRM device 6941 * @state: The atomic state to commit 6942 * 6943 * Validate that the given atomic state is programmable by DC into hardware. 6944 * This involves constructing a &struct dc_state reflecting the new hardware 6945 * state we wish to commit, then querying DC to see if it is programmable. It's 6946 * important not to modify the existing DC state. Otherwise, atomic_check 6947 * may unexpectedly commit hardware changes. 6948 * 6949 * When validating the DC state, it's important that the right locks are 6950 * acquired. For full updates case which removes/adds/updates streams on one 6951 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6952 * that any such full update commit will wait for completion of any outstanding 6953 * flip using DRMs synchronization events. 6954 * 6955 * Note that DM adds the affected connectors for all CRTCs in state, when that 6956 * might not seem necessary. This is because DC stream creation requires the 6957 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6958 * be possible but non-trivial - a possible TODO item. 6959 * 6960 * Return: -Error code if validation failed. 6961 */ 6962 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6963 struct drm_atomic_commit *state) 6964 { 6965 struct amdgpu_device *adev = drm_to_adev(dev); 6966 struct dm_atomic_state *dm_state = NULL; 6967 struct dc *dc = adev->dm.dc; 6968 struct drm_connector *connector; 6969 struct drm_connector_state *old_con_state, *new_con_state; 6970 struct drm_crtc *crtc; 6971 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6972 struct drm_plane *plane; 6973 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6974 enum dc_status status; 6975 int ret, i; 6976 bool lock_and_validation_needed = false; 6977 bool is_top_most_overlay = true; 6978 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6979 struct drm_dp_mst_topology_mgr *mgr; 6980 struct drm_dp_mst_topology_state *mst_state; 6981 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 6982 6983 trace_amdgpu_dm_atomic_check_begin(state); 6984 6985 ret = drm_atomic_helper_check_modeset(dev, state); 6986 if (ret) { 6987 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed: %pe\n", ERR_PTR(ret)); 6988 goto fail; 6989 } 6990 6991 /* Check connector changes */ 6992 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6993 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6994 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6995 6996 /* Skip connectors that are disabled or part of modeset already. */ 6997 if (!new_con_state->crtc) 6998 continue; 6999 7000 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 7001 if (IS_ERR(new_crtc_state)) { 7002 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed: %pe\n", new_crtc_state); 7003 ret = PTR_ERR(new_crtc_state); 7004 goto fail; 7005 } 7006 7007 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 7008 dm_old_con_state->scaling != dm_new_con_state->scaling) 7009 new_crtc_state->connectors_changed = true; 7010 } 7011 7012 if (dc_resource_is_dsc_encoding_supported(dc)) { 7013 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7014 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7015 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 7016 } 7017 7018 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7019 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 7020 ret = add_affected_mst_dsc_crtcs(state, crtc); 7021 if (ret) { 7022 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed: %pe\n", ERR_PTR(ret)); 7023 goto fail; 7024 } 7025 } 7026 } 7027 } 7028 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7029 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7030 7031 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 7032 !new_crtc_state->color_mgmt_changed && 7033 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 7034 dm_old_crtc_state->dsc_force_changed == false) 7035 continue; 7036 7037 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 7038 if (ret) { 7039 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed: %pe\n", ERR_PTR(ret)); 7040 goto fail; 7041 } 7042 7043 if (!new_crtc_state->enable) 7044 continue; 7045 7046 ret = drm_atomic_add_affected_connectors(state, crtc); 7047 if (ret) { 7048 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed: %pe\n", ERR_PTR(ret)); 7049 goto fail; 7050 } 7051 7052 ret = drm_atomic_add_affected_planes(state, crtc); 7053 if (ret) { 7054 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed: %pe\n", ERR_PTR(ret)); 7055 goto fail; 7056 } 7057 7058 if (dm_old_crtc_state->dsc_force_changed) 7059 new_crtc_state->mode_changed = true; 7060 } 7061 7062 /* 7063 * Add all primary and overlay planes on the CRTC to the state 7064 * whenever a plane is enabled to maintain correct z-ordering 7065 * and to enable fast surface updates. 7066 */ 7067 drm_for_each_crtc(crtc, dev) { 7068 bool modified = false; 7069 7070 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7071 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7072 continue; 7073 7074 if (new_plane_state->crtc == crtc || 7075 old_plane_state->crtc == crtc) { 7076 modified = true; 7077 break; 7078 } 7079 } 7080 7081 if (!modified) 7082 continue; 7083 7084 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 7085 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7086 continue; 7087 7088 new_plane_state = 7089 drm_atomic_get_plane_state(state, plane); 7090 7091 if (IS_ERR(new_plane_state)) { 7092 ret = PTR_ERR(new_plane_state); 7093 drm_dbg_atomic(dev, "new_plane_state is BAD: %pe\n", new_plane_state); 7094 goto fail; 7095 } 7096 } 7097 } 7098 7099 /* 7100 * DC consults the zpos (layer_index in DC terminology) to determine the 7101 * hw plane on which to enable the hw cursor (see 7102 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 7103 * atomic state, so call drm helper to normalize zpos. 7104 */ 7105 ret = drm_atomic_normalize_zpos(dev, state); 7106 if (ret) { 7107 drm_dbg(dev, "drm_atomic_normalize_zpos() failed: %pe\n", ERR_PTR(ret)); 7108 goto fail; 7109 } 7110 7111 /* 7112 * Determine whether cursors on each CRTC should be enabled in native or 7113 * overlay mode. 7114 */ 7115 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7116 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7117 7118 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 7119 &dm_new_crtc_state->cursor_mode); 7120 if (ret) { 7121 drm_dbg(dev, "Failed to determine cursor mode: %pe\n", ERR_PTR(ret)); 7122 goto fail; 7123 } 7124 7125 /* 7126 * If overlay cursor is needed, DC cannot go through the 7127 * native cursor update path. All enabled planes on the CRTC 7128 * need to be added for DC to not disable a plane by mistake 7129 */ 7130 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 7131 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 7132 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 7133 ret = -EINVAL; 7134 goto fail; 7135 } 7136 7137 ret = drm_atomic_add_affected_planes(state, crtc); 7138 if (ret) 7139 goto fail; 7140 } 7141 } 7142 7143 /* Remove exiting planes if they are modified */ 7144 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 7145 7146 ret = dm_update_plane_state(dc, state, plane, 7147 old_plane_state, 7148 new_plane_state, 7149 false, 7150 &lock_and_validation_needed, 7151 &is_top_most_overlay); 7152 if (ret) { 7153 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 7154 goto fail; 7155 } 7156 } 7157 7158 /* Disable all crtcs which require disable */ 7159 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7160 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7161 old_crtc_state, 7162 new_crtc_state, 7163 false, 7164 &lock_and_validation_needed); 7165 if (ret) { 7166 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 7167 goto fail; 7168 } 7169 } 7170 7171 /* Enable all crtcs which require enable */ 7172 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7173 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7174 old_crtc_state, 7175 new_crtc_state, 7176 true, 7177 &lock_and_validation_needed); 7178 if (ret) { 7179 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 7180 goto fail; 7181 } 7182 } 7183 7184 /* Add new/modified planes */ 7185 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 7186 ret = dm_update_plane_state(dc, state, plane, 7187 old_plane_state, 7188 new_plane_state, 7189 true, 7190 &lock_and_validation_needed, 7191 &is_top_most_overlay); 7192 if (ret) { 7193 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 7194 goto fail; 7195 } 7196 } 7197 7198 #if defined(CONFIG_DRM_AMD_DC_FP) 7199 if (dc_resource_is_dsc_encoding_supported(dc)) { 7200 ret = pre_validate_dsc(state, &dm_state, vars); 7201 if (ret != 0) 7202 goto fail; 7203 } 7204 #endif 7205 7206 /* Run this here since we want to validate the streams we created */ 7207 ret = drm_atomic_helper_check_planes(dev, state); 7208 if (ret) { 7209 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed: %pe\n", ERR_PTR(ret)); 7210 goto fail; 7211 } 7212 7213 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7214 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7215 if (dm_new_crtc_state->mpo_requested) 7216 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 7217 } 7218 7219 /* Check cursor restrictions */ 7220 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7221 enum amdgpu_dm_cursor_mode required_cursor_mode; 7222 int is_rotated, is_scaled; 7223 7224 /* Overlay cusor not subject to native cursor restrictions */ 7225 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7226 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 7227 continue; 7228 7229 /* Check if rotation or scaling is enabled on DCN401 */ 7230 if ((drm_plane_mask(crtc->cursor) & 7231 new_crtc_state->plane_mask) && 7232 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1) || 7233 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 7234 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { 7235 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 7236 7237 is_rotated = new_cursor_state && 7238 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 7239 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 7240 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 7241 7242 if (is_rotated || is_scaled) { 7243 drm_dbg_driver( 7244 crtc->dev, 7245 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 7246 crtc->base.id, crtc->name); 7247 ret = -EINVAL; 7248 goto fail; 7249 } 7250 } 7251 7252 /* If HW can only do native cursor, check restrictions again */ 7253 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 7254 &required_cursor_mode); 7255 if (ret) { 7256 drm_dbg_driver(crtc->dev, 7257 "[CRTC:%d:%s] Checking cursor mode failed\n", 7258 crtc->base.id, crtc->name); 7259 goto fail; 7260 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 7261 drm_dbg_driver(crtc->dev, 7262 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 7263 crtc->base.id, crtc->name); 7264 ret = -EINVAL; 7265 goto fail; 7266 } 7267 } 7268 7269 if (state->legacy_cursor_update) { 7270 /* 7271 * This is a fast cursor update coming from the plane update 7272 * helper, check if it can be done asynchronously for better 7273 * performance. 7274 */ 7275 state->async_update = 7276 !drm_atomic_helper_async_check(dev, state); 7277 7278 /* 7279 * Skip the remaining global validation if this is an async 7280 * update. Cursor updates can be done without affecting 7281 * state or bandwidth calcs and this avoids the performance 7282 * penalty of locking the private state object and 7283 * allocating a new dc_state. 7284 */ 7285 if (state->async_update) 7286 return 0; 7287 } 7288 7289 /* Check scaling and underscan changes*/ 7290 /* TODO Removed scaling changes validation due to inability to commit 7291 * new stream into context w\o causing full reset. Need to 7292 * decide how to handle. 7293 */ 7294 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7295 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7296 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7297 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7298 7299 /* Skip any modesets/resets */ 7300 if (!acrtc || drm_atomic_crtc_needs_modeset( 7301 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7302 continue; 7303 7304 /* Skip any thing not scale or underscan changes */ 7305 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7306 continue; 7307 7308 lock_and_validation_needed = true; 7309 } 7310 7311 /* set the slot info for each mst_state based on the link encoding format */ 7312 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 7313 struct amdgpu_dm_connector *aconnector; 7314 struct drm_connector *connector; 7315 struct drm_connector_list_iter iter; 7316 u8 link_coding_cap; 7317 7318 drm_connector_list_iter_begin(dev, &iter); 7319 drm_for_each_connector_iter(connector, &iter) { 7320 if (connector->index == mst_state->mgr->conn_base_id) { 7321 aconnector = to_amdgpu_dm_connector(connector); 7322 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 7323 drm_dp_mst_update_slots(mst_state, link_coding_cap); 7324 7325 break; 7326 } 7327 } 7328 drm_connector_list_iter_end(&iter); 7329 } 7330 7331 /** 7332 * Streams and planes are reset when there are changes that affect 7333 * bandwidth. Anything that affects bandwidth needs to go through 7334 * DC global validation to ensure that the configuration can be applied 7335 * to hardware. 7336 * 7337 * We have to currently stall out here in atomic_check for outstanding 7338 * commits to finish in this case because our IRQ handlers reference 7339 * DRM state directly - we can end up disabling interrupts too early 7340 * if we don't. 7341 * 7342 * TODO: Remove this stall and drop DM state private objects. 7343 */ 7344 if (lock_and_validation_needed) { 7345 ret = dm_atomic_get_state(state, &dm_state); 7346 if (ret) { 7347 drm_dbg_atomic(dev, "dm_atomic_get_state() failed: %pe\n", ERR_PTR(ret)); 7348 goto fail; 7349 } 7350 7351 ret = do_aquire_global_lock(dev, state); 7352 if (ret) { 7353 drm_dbg_atomic(dev, "do_aquire_global_lock() failed: %pe\n", ERR_PTR(ret)); 7354 goto fail; 7355 } 7356 7357 #if defined(CONFIG_DRM_AMD_DC_FP) 7358 if (dc_resource_is_dsc_encoding_supported(dc)) { 7359 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 7360 if (ret) { 7361 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed: %pe\n", ERR_PTR(ret)); 7362 ret = -EINVAL; 7363 goto fail; 7364 } 7365 } 7366 #endif 7367 7368 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 7369 if (ret) { 7370 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed: %pe\n", ERR_PTR(ret)); 7371 goto fail; 7372 } 7373 7374 /* 7375 * Perform validation of MST topology in the state: 7376 * We need to perform MST atomic check before calling 7377 * dc_validate_global_state(), or there is a chance 7378 * to get stuck in an infinite loop and hang eventually. 7379 */ 7380 ret = drm_dp_mst_atomic_check(state); 7381 if (ret) { 7382 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed: %pe\n", ERR_PTR(ret)); 7383 goto fail; 7384 } 7385 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 7386 if (status != DC_OK) { 7387 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 7388 dc_status_to_str(status), status); 7389 ret = -EINVAL; 7390 goto fail; 7391 } 7392 } else { 7393 /* 7394 * The commit is a fast update. Fast updates shouldn't change 7395 * the DC context, affect global validation, and can have their 7396 * commit work done in parallel with other commits not touching 7397 * the same resource. If we have a new DC context as part of 7398 * the DM atomic state from validation we need to free it and 7399 * retain the existing one instead. 7400 * 7401 * Furthermore, since the DM atomic state only contains the DC 7402 * context and can safely be annulled, we can free the state 7403 * and clear the associated private object now to free 7404 * some memory and avoid a possible use-after-free later. 7405 */ 7406 7407 for (i = 0; i < state->num_private_objs; i++) { 7408 struct drm_private_obj *obj = state->private_objs[i].ptr; 7409 7410 if (obj->funcs == adev->dm.atomic_obj.funcs) { 7411 int j = state->num_private_objs-1; 7412 7413 dm_atomic_destroy_state(obj, 7414 state->private_objs[i].state_to_destroy); 7415 7416 /* If i is not at the end of the array then the 7417 * last element needs to be moved to where i was 7418 * before the array can safely be truncated. 7419 */ 7420 if (i != j) 7421 state->private_objs[i] = 7422 state->private_objs[j]; 7423 7424 state->private_objs[j].ptr = NULL; 7425 state->private_objs[j].state_to_destroy = NULL; 7426 state->private_objs[j].old_state = NULL; 7427 state->private_objs[j].new_state = NULL; 7428 7429 state->num_private_objs = j; 7430 break; 7431 } 7432 } 7433 } 7434 7435 /* Store the overall update type for use later in atomic check. */ 7436 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7437 struct dm_crtc_state *dm_new_crtc_state = 7438 to_dm_crtc_state(new_crtc_state); 7439 7440 /* 7441 * Only allow async flips for fast updates that don't change 7442 * the FB pitch, the DCC state, rotation, mem_type, etc. 7443 */ 7444 if (new_crtc_state->async_flip && 7445 (lock_and_validation_needed || 7446 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 7447 drm_dbg_atomic(crtc->dev, 7448 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 7449 crtc->base.id, crtc->name); 7450 ret = -EINVAL; 7451 goto fail; 7452 } 7453 7454 dm_new_crtc_state->update_type = lock_and_validation_needed ? 7455 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 7456 } 7457 7458 /* Must be success */ 7459 WARN_ON(ret); 7460 7461 trace_amdgpu_dm_atomic_check_finish(state, ret); 7462 7463 return ret; 7464 7465 fail: 7466 if (ret == -EDEADLK) 7467 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 7468 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7469 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 7470 else 7471 drm_dbg_atomic(dev, "Atomic check failed: %pe\n", ERR_PTR(ret)); 7472 7473 trace_amdgpu_dm_atomic_check_finish(state, ret); 7474 7475 return ret; 7476 } 7477 7478 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 7479 { 7480 struct amdgpu_device *adev = drm_to_adev(dev); 7481 struct dc *dc = adev->dm.dc; 7482 int i; 7483 7484 mutex_lock(&adev->dm.dc_lock); 7485 if (dc->current_state) { 7486 for (i = 0; i < dc->current_state->stream_count; ++i) 7487 dc->current_state->streams[i] 7488 ->triggered_crtc_reset.enabled = 7489 adev->dm.force_timing_sync; 7490 7491 dm_enable_per_frame_crtc_master_sync(dc->current_state); 7492 dc_trigger_sync(dc, dc->current_state); 7493 } 7494 mutex_unlock(&adev->dm.dc_lock); 7495 } 7496 7497 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 7498 u32 value, const char *func_name) 7499 { 7500 #ifdef DM_CHECK_ADDR_0 7501 if (address == 0) { 7502 drm_err(adev_to_drm(ctx->driver_context), 7503 "invalid register write. address = 0"); 7504 return; 7505 } 7506 #endif 7507 7508 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7509 cgs_write_register(ctx->cgs_device, address, value); 7510 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 7511 } 7512 7513 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 7514 const char *func_name) 7515 { 7516 u32 value; 7517 #ifdef DM_CHECK_ADDR_0 7518 if (address == 0) { 7519 drm_err(adev_to_drm(ctx->driver_context), 7520 "invalid register read; address = 0\n"); 7521 return 0; 7522 } 7523 #endif 7524 7525 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7526 7527 value = cgs_read_register(ctx->cgs_device, address); 7528 7529 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 7530 7531 return value; 7532 } 7533 7534 void dm_acpi_process_phy_transition_interlock( 7535 const struct dc_context *ctx, 7536 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 7537 { 7538 // Not yet implemented 7539 } 7540