1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "dc/dc_state.h" 42 #include "amdgpu_dm_trace.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_dm_wb.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 #include "amdgpu_dm_replay.h" 69 #include "amdgpu_dm_backlight.h" 70 #include "amdgpu_dm_audio.h" 71 #include "amdgpu_dm_dmub.h" 72 #include "amdgpu_dm_connector.h" 73 #include "amdgpu_dm_kunit_helpers.h" 74 75 #include "ivsrcid/ivsrcid_vislands30.h" 76 77 #include <linux/backlight.h> 78 #include <linux/module.h> 79 #include <linux/moduleparam.h> 80 #include <linux/types.h> 81 #include <linux/pm_runtime.h> 82 #include <linux/pci.h> 83 #include <linux/power_supply.h> 84 #include <linux/firmware.h> 85 #include <linux/component.h> 86 #include <linux/sort.h> 87 88 #include <drm/drm_privacy_screen_consumer.h> 89 #include <drm/display/drm_dp_mst_helper.h> 90 #include <drm/display/drm_hdmi_helper.h> 91 #include <drm/drm_atomic.h> 92 #include <drm/drm_atomic_uapi.h> 93 #include <drm/drm_atomic_helper.h> 94 #include <drm/drm_blend.h> 95 #include <drm/drm_fixed.h> 96 #include <drm/drm_fourcc.h> 97 #include <drm/drm_edid.h> 98 #include <drm/drm_eld.h> 99 #include <drm/drm_mode.h> 100 #include <drm/drm_utils.h> 101 #include <drm/drm_vblank.h> 102 #include <drm/drm_colorop.h> 103 #include <drm/drm_gem_atomic_helper.h> 104 105 #include <media/cec-notifier.h> 106 #include <acpi/video.h> 107 108 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 109 110 #include "modules/inc/mod_freesync.h" 111 #include "modules/inc/mod_power.h" 112 #include "modules/power/power_helpers.h" 113 114 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 115 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 116 117 /** 118 * DOC: overview 119 * 120 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 121 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 122 * requests into DC requests, and DC responses into DRM responses. 123 * 124 * The root control structure is &struct amdgpu_display_manager. 125 */ 126 127 /* basic init/fini API */ 128 static int amdgpu_dm_init(struct amdgpu_device *adev); 129 static void amdgpu_dm_fini(struct amdgpu_device *adev); 130 static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state); 131 132 /* 133 * initializes drm_device display related structures, based on the information 134 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 135 * drm_encoder, drm_mode_config 136 * 137 * Returns 0 on success 138 */ 139 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 140 /* removes and deallocates the drm structures, created by the above function */ 141 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 142 143 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 144 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 145 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 146 147 static int amdgpu_dm_atomic_check(struct drm_device *dev, 148 struct drm_atomic_commit *state); 149 150 STATIC_IFN_KUNIT bool 151 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 152 struct drm_crtc_state *new_crtc_state); 153 154 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 155 { 156 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 157 dc_exit_ips_for_hw_access(dc); 158 } 159 160 /* 161 * dm_vblank_get_counter 162 * 163 * @brief 164 * Get counter for number of vertical blanks 165 * 166 * @param 167 * struct amdgpu_device *adev - [in] desired amdgpu device 168 * int disp_idx - [in] which CRTC to get the counter from 169 * 170 * @return 171 * Counter for vertical blanks 172 */ 173 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 174 { 175 struct amdgpu_crtc *acrtc = NULL; 176 177 if (crtc >= adev->mode_info.num_crtc) 178 return 0; 179 180 acrtc = adev->mode_info.crtcs[crtc]; 181 182 if (!acrtc->dm_irq_params.stream) { 183 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 184 crtc); 185 return 0; 186 } 187 188 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 189 } 190 191 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 192 u32 *vbl, u32 *position) 193 { 194 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 195 struct amdgpu_crtc *acrtc = NULL; 196 struct dc *dc = adev->dm.dc; 197 198 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 199 return -EINVAL; 200 201 acrtc = adev->mode_info.crtcs[crtc]; 202 203 if (!acrtc->dm_irq_params.stream) { 204 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 205 crtc); 206 return 0; 207 } 208 209 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 210 dc_allow_idle_optimizations(dc, false); 211 212 /* 213 * TODO rework base driver to use values directly. 214 * for now parse it back into reg-format 215 */ 216 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 217 &v_blank_start, 218 &v_blank_end, 219 &h_position, 220 &v_position); 221 222 *position = v_position | (h_position << 16); 223 *vbl = v_blank_start | (v_blank_end << 16); 224 225 return 0; 226 } 227 228 static bool dm_is_idle(struct amdgpu_ip_block *ip_block) 229 { 230 /* XXX todo */ 231 return true; 232 } 233 234 static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 235 { 236 /* XXX todo */ 237 return 0; 238 } 239 240 static int dm_soft_reset(struct amdgpu_ip_block *ip_block) 241 { 242 /* XXX todo */ 243 return 0; 244 } 245 246 STATIC_IFN_KUNIT bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 247 struct dm_crtc_state *new_state) 248 { 249 if (new_state->stream->adjust.timing_adjust_pending) 250 return true; 251 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 252 return true; 253 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 254 return true; 255 else 256 return false; 257 } 258 EXPORT_IF_KUNIT(is_dc_timing_adjust_needed); 259 260 /* 261 * DC will program planes with their z-order determined by their ordering 262 * in the dc_surface_updates array. This comparator is used to sort them 263 * by descending zpos. 264 */ 265 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 266 { 267 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 268 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 269 270 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 271 return sb->surface->layer_index - sa->surface->layer_index; 272 } 273 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 274 275 /** 276 * update_planes_and_stream_adapter() - Send planes to be updated in DC 277 * 278 * DC has a generic way to update planes and stream via 279 * dc_update_planes_and_stream function; however, DM might need some 280 * adjustments and preparation before calling it. This function is a wrapper 281 * for the dc_update_planes_and_stream that does any required configuration 282 * before passing control to DC. 283 * 284 * @dc: Display Core control structure 285 * @update_type: specify whether it is FULL/MEDIUM/FAST update 286 * @planes_count: planes count to update 287 * @stream: stream state 288 * @stream_update: stream update 289 * @array_of_surface_update: dc surface update pointer 290 * 291 */ 292 static inline bool update_planes_and_stream_adapter(struct dc *dc, 293 int update_type, 294 int planes_count, 295 struct dc_stream_state *stream, 296 struct dc_stream_update *stream_update, 297 struct dc_surface_update *array_of_surface_update) 298 { 299 sort(array_of_surface_update, planes_count, 300 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 301 302 /* 303 * Previous frame finished and HW is ready for optimization. 304 */ 305 dc_post_update_surfaces_to_stream(dc); 306 307 return dc_update_planes_and_stream(dc, 308 array_of_surface_update, 309 planes_count, 310 stream, 311 stream_update); 312 } 313 314 static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 315 enum amd_clockgating_state state) 316 { 317 return 0; 318 } 319 320 static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 321 enum amd_powergating_state state) 322 { 323 return 0; 324 } 325 326 /* Prototypes of private functions */ 327 static int dm_early_init(struct amdgpu_ip_block *ip_block); 328 329 /* Allocate memory for FBC compressed data */ 330 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 331 { 332 u64 pt_base; 333 u32 logical_addr_low; 334 u32 logical_addr_high; 335 u32 agp_base, agp_bot, agp_top; 336 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 337 338 memset(pa_config, 0, sizeof(*pa_config)); 339 340 agp_base = 0; 341 agp_bot = adev->gmc.agp_start >> 24; 342 agp_top = adev->gmc.agp_end >> 24; 343 344 /* AGP aperture is disabled */ 345 if (agp_bot > agp_top) { 346 logical_addr_low = adev->gmc.fb_start >> 18; 347 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 348 AMD_APU_IS_RENOIR | 349 AMD_APU_IS_GREEN_SARDINE)) 350 /* 351 * Raven2 has a HW issue that it is unable to use the vram which 352 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 353 * workaround that increase system aperture high address (add 1) 354 * to get rid of the VM fault and hardware hang. 355 */ 356 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 357 else 358 logical_addr_high = adev->gmc.fb_end >> 18; 359 } else { 360 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 361 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 362 AMD_APU_IS_RENOIR | 363 AMD_APU_IS_GREEN_SARDINE)) 364 /* 365 * Raven2 has a HW issue that it is unable to use the vram which 366 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 367 * workaround that increase system aperture high address (add 1) 368 * to get rid of the VM fault and hardware hang. 369 */ 370 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 371 else 372 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 373 } 374 375 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 376 377 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 378 AMDGPU_GPU_PAGE_SHIFT); 379 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 380 AMDGPU_GPU_PAGE_SHIFT); 381 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 382 AMDGPU_GPU_PAGE_SHIFT); 383 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 384 AMDGPU_GPU_PAGE_SHIFT); 385 page_table_base.high_part = upper_32_bits(pt_base); 386 page_table_base.low_part = lower_32_bits(pt_base); 387 388 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 389 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 390 391 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 392 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 393 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 394 395 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 396 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 397 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 398 399 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 400 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 401 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 402 403 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 404 405 } 406 407 struct amdgpu_stutter_quirk { 408 u16 chip_vendor; 409 u16 chip_device; 410 u16 subsys_vendor; 411 u16 subsys_device; 412 u8 revision; 413 }; 414 415 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 416 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 417 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 418 { 0, 0, 0, 0, 0 }, 419 }; 420 421 static bool dm_should_disable_stutter(struct pci_dev *pdev) 422 { 423 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 424 425 while (p && p->chip_device != 0) { 426 if (pdev->vendor == p->chip_vendor && 427 pdev->device == p->chip_device && 428 pdev->subsystem_vendor == p->subsys_vendor && 429 pdev->subsystem_device == p->subsys_device && 430 pdev->revision == p->revision) { 431 return true; 432 } 433 ++p; 434 } 435 return false; 436 } 437 438 439 void* 440 dm_allocate_gpu_mem( 441 struct amdgpu_device *adev, 442 enum dc_gpu_mem_alloc_type type, 443 size_t size, 444 long long *addr) 445 { 446 struct dal_allocation *da; 447 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 448 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 449 int ret; 450 451 da = kzalloc_obj(struct dal_allocation); 452 if (!da) 453 return NULL; 454 455 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 456 domain, &da->bo, 457 &da->gpu_addr, &da->cpu_ptr); 458 459 *addr = da->gpu_addr; 460 461 if (ret) { 462 kfree(da); 463 return NULL; 464 } 465 466 /* add da to list in dm */ 467 list_add(&da->list, &adev->dm.da_list); 468 469 return da->cpu_ptr; 470 } 471 472 void 473 dm_free_gpu_mem( 474 struct amdgpu_device *adev, 475 enum dc_gpu_mem_alloc_type type, 476 void *pvMem) 477 { 478 struct dal_allocation *da; 479 480 /* walk the da list in DM */ 481 list_for_each_entry(da, &adev->dm.da_list, list) { 482 if (pvMem == da->cpu_ptr) { 483 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 484 list_del(&da->list); 485 kfree(da); 486 break; 487 } 488 } 489 490 } 491 492 static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 493 { 494 struct mod_power_init_params init_data[MAX_NUM_EDP]; 495 496 if (dm->num_of_edps == 0) { 497 drm_dbg_driver( 498 dm->ddev, 499 "amdgpu: No eDP detected, skip initializing power module\n"); 500 return 0; 501 } 502 503 /* Initialize all the power module parameters */ 504 for (int i = 0; i < dm->num_of_edps; i++) { 505 init_data[i].allow_psr_smu_optimizations = 506 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 507 init_data[i].allow_psr_multi_disp_optimizations = 508 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 509 /* See dm_late_init */ 510 init_data[i].backlight_ramping_override = false; 511 init_data[i].backlight_ramping_start = 0xCCCC; 512 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 513 init_data[i].def_varibright_level = 0; 514 init_data[i].abm_config_setting = 0; 515 init_data[i].num_backlight_levels = 101; 516 init_data[i].use_nits_based_brightness = false; 517 init_data[i].panel_max_millinits = 0; 518 init_data[i].panel_min_millinits = 0; 519 init_data[i].disable_fractional_pwm = 520 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 521 init_data[i].use_custom_backlight_caps = false; 522 init_data[i].custom_backlight_caps_config_no = 0; 523 init_data[i].use_linear_backlight_curve = false; 524 init_data[i].def_varibright_enable = 0; 525 init_data[i].varibright_level = 0; 526 /* 527 * Power module uses 16-bit backlight levels (0xFFFF max) rather 528 * than 8-bit(0XFF max) 529 */ 530 init_data[i].min_backlight_pwm = 531 dm->backlight_caps[i].min_input_signal * 0x101; 532 init_data[i].max_backlight_pwm = 533 dm->backlight_caps[i].max_input_signal * 0x101; 534 init_data[i].min_abm_backlight = 535 dm->backlight_caps[i].min_input_signal * 0x101; 536 537 /* Min backlight level after ABM reduction, Don't allow below 1% 538 * 0xFFFF x 0.01 = 0x28F 539 */ 540 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 541 0x28F : init_data[i].min_abm_backlight; 542 } 543 544 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 545 if (!dm->power_module) { 546 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 547 return -ENOMEM; 548 } 549 550 mod_power_hw_init(dm->power_module); 551 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 552 553 return 0; 554 } 555 556 static int amdgpu_dm_init(struct amdgpu_device *adev) 557 { 558 struct dc_init_data init_data; 559 struct dc_callback_init init_params; 560 int r; 561 562 adev->dm.ddev = adev_to_drm(adev); 563 adev->dm.adev = adev; 564 565 /* Zero all the fields */ 566 memset(&init_data, 0, sizeof(init_data)); 567 memset(&init_params, 0, sizeof(init_params)); 568 569 mutex_init(&adev->dm.dpia_aux_lock); 570 mutex_init(&adev->dm.dc_lock); 571 mutex_init(&adev->dm.audio_lock); 572 573 spin_lock_init(&adev->dm.dmub_lock); 574 575 if (amdgpu_dm_irq_init(adev)) { 576 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 577 goto error; 578 } 579 580 /* special handling for early revisions of GC 11.5.4 */ 581 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 582 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 583 else 584 init_data.asic_id.chip_family = adev->family; 585 586 init_data.asic_id.pci_revision_id = adev->pdev->revision; 587 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 588 init_data.asic_id.chip_id = adev->pdev->device; 589 590 init_data.asic_id.vram_width = adev->gmc.vram_width; 591 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 592 init_data.asic_id.atombios_base_address = 593 adev->mode_info.atom_context->bios; 594 595 init_data.driver = adev; 596 597 /* cgs_device was created in dm_sw_init() */ 598 init_data.cgs_device = adev->dm.cgs_device; 599 600 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 601 602 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 603 case IP_VERSION(2, 1, 0): 604 switch (adev->dm.dmcub_fw_version) { 605 case 0: /* development */ 606 case 0x1: /* linux-firmware.git hash 6d9f399 */ 607 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 608 init_data.flags.disable_dmcu = false; 609 break; 610 default: 611 init_data.flags.disable_dmcu = true; 612 } 613 break; 614 case IP_VERSION(2, 0, 3): 615 init_data.flags.disable_dmcu = true; 616 break; 617 default: 618 break; 619 } 620 621 /* APU support S/G display by default except: 622 * ASICs before Carrizo, 623 * RAVEN1 (Users reported stability issue) 624 */ 625 626 if (adev->asic_type < CHIP_CARRIZO) { 627 init_data.flags.gpu_vm_support = false; 628 } else if (adev->asic_type == CHIP_RAVEN) { 629 if (adev->apu_flags & AMD_APU_IS_RAVEN) 630 init_data.flags.gpu_vm_support = false; 631 else 632 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 633 } else { 634 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 635 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 636 else 637 init_data.flags.gpu_vm_support = 638 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 639 } 640 641 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 642 643 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 644 init_data.flags.fbc_support = true; 645 646 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 647 init_data.flags.multi_mon_pp_mclk_switch = true; 648 649 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 650 init_data.flags.disable_fractional_pwm = true; 651 652 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 653 init_data.flags.edp_no_power_sequencing = true; 654 655 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 656 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 657 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 658 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 659 660 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 661 init_data.flags.enable_frl = true; 662 663 init_data.flags.seamless_boot_edp_requested = false; 664 665 if (amdgpu_device_seamless_boot_supported(adev)) { 666 init_data.flags.seamless_boot_edp_requested = true; 667 init_data.flags.allow_seamless_boot_optimization = true; 668 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 669 } 670 671 init_data.flags.enable_mipi_converter_optimization = true; 672 673 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 674 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 675 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 676 677 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 678 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 679 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 680 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 681 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 682 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 683 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 684 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 685 else 686 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 687 688 init_data.flags.disable_ips_in_vpb = 0; 689 690 /* DCN35 and above supports dynamic DTBCLK switch */ 691 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 692 init_data.flags.allow_0_dtb_clk = true; 693 694 /* Enable DWB for tested platforms only */ 695 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 696 init_data.num_virtual_links = 1; 697 698 /* DCN42 and above dpia switch to unified link training path */ 699 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 700 init_data.flags.consolidated_dpia_dp_lt = true; 701 init_data.flags.enable_dpia_pre_training = true; 702 init_data.flags.unify_link_enc_assignment = true; 703 init_data.flags.usb4_bw_alloc_support = true; 704 } 705 retrieve_dmi_info(&adev->dm); 706 if (adev->dm.edp0_on_dp1_quirk) 707 init_data.flags.support_edp0_on_dp1 = true; 708 709 if (adev->dm.bb_from_dmub) 710 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 711 else 712 init_data.bb_from_dmub = NULL; 713 714 /* Display Core create. */ 715 adev->dm.dc = dc_create(&init_data); 716 717 if (adev->dm.dc) { 718 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 719 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 720 } else { 721 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 722 goto error; 723 } 724 725 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 726 adev->dm.dc->debug.force_single_disp_pipe_split = false; 727 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 728 } 729 730 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 731 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 732 if (dm_should_disable_stutter(adev->pdev)) 733 adev->dm.dc->debug.disable_stutter = true; 734 735 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 736 adev->dm.dc->debug.disable_stutter = true; 737 738 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 739 adev->dm.dc->debug.disable_dsc = true; 740 741 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 742 adev->dm.dc->debug.disable_clock_gate = true; 743 744 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 745 adev->dm.dc->debug.force_subvp_mclk_switch = true; 746 747 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 748 adev->dm.dc->debug.force_disable_subvp = true; 749 adev->dm.dc->debug.fams2_config.bits.enable = false; 750 } 751 752 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 753 adev->dm.dc->debug.using_dml2 = true; 754 adev->dm.dc->debug.using_dml21 = true; 755 } 756 757 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 758 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 759 760 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 761 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 762 763 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 764 adev->dm.dc->debug.skip_detection_link_training = true; 765 766 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 767 768 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 769 adev->dm.dc->debug.ignore_cable_id = true; 770 771 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 772 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 773 774 r = dm_dmub_hw_init(adev); 775 if (r) { 776 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 777 goto error; 778 } 779 780 dc_hardware_init(adev->dm.dc); 781 782 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 783 if (!adev->dm.hpd_rx_offload_wq) { 784 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 785 goto error; 786 } 787 788 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 789 struct dc_phy_addr_space_config pa_config; 790 791 mmhub_read_system_context(adev, &pa_config); 792 793 // Call the DC init_memory func 794 dc_setup_system_context(adev->dm.dc, &pa_config); 795 } 796 797 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 798 if (!adev->dm.freesync_module) { 799 drm_err(adev_to_drm(adev), 800 "failed to initialize freesync_module.\n"); 801 } else 802 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 803 adev->dm.freesync_module); 804 805 amdgpu_dm_init_color_mod(); 806 807 if (adev->dm.dc->caps.max_links > 0) { 808 adev->dm.vblank_control_workqueue = 809 create_singlethread_workqueue("dm_vblank_control_workqueue"); 810 if (!adev->dm.vblank_control_workqueue) 811 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 812 } 813 814 if (adev->dm.dc->caps.ips_support && 815 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 816 adev->dm.idle_workqueue = idle_create_workqueue(adev); 817 818 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 819 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 820 821 if (!adev->dm.hdcp_workqueue) 822 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 823 else 824 drm_dbg_driver(adev_to_drm(adev), 825 "hdcp_workqueue init done %p.\n", 826 adev->dm.hdcp_workqueue); 827 828 dc_init_callbacks(adev->dm.dc, &init_params); 829 } 830 if (adev->dm.dc->caps.max_links > 0) { 831 adev->dm.hdmi_frl_status_polling_wq = 832 create_singlethread_workqueue("hdmi_frl_status_polling_workqueue"); 833 if (!adev->dm.hdmi_frl_status_polling_wq) 834 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_workqueue\n"); 835 } 836 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 837 init_completion(&adev->dm.dmub_aux_transfer_done); 838 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 839 if (!adev->dm.dmub_notify) { 840 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 841 goto error; 842 } 843 844 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 845 if (!adev->dm.delayed_hpd_wq) { 846 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 847 goto error; 848 } 849 850 amdgpu_dm_outbox_init(adev); 851 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 852 dm_dmub_aux_setconfig_callback, false)) { 853 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 854 goto error; 855 } 856 857 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 858 init_completion(&adev->dm.fused_io[i].replied); 859 860 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 861 dm_dmub_aux_fused_io_callback, false)) { 862 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 863 goto error; 864 } 865 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 866 * It is expected that DMUB will resend any pending notifications at this point. Note 867 * that hpd and hpd_irq handler registration are deferred to 868 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 869 * sequence. Connection status will be proactivly detected once in the 870 * amdgpu_dm_initialize_drm_device. 871 */ 872 dc_enable_dmub_outbox(adev->dm.dc); 873 874 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 875 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 876 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 877 } 878 879 if (amdgpu_dm_initialize_drm_device(adev)) { 880 drm_err(adev_to_drm(adev), 881 "failed to initialize sw for display support.\n"); 882 goto error; 883 } 884 885 if (amdgpu_dm_init_power_module(&adev->dm)) 886 goto error; 887 888 /* create fake encoders for MST */ 889 dm_dp_create_fake_mst_encoders(adev); 890 891 /* TODO: Add_display_info? */ 892 893 /* TODO use dynamic cursor width */ 894 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 895 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 896 897 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 898 drm_err(adev_to_drm(adev), 899 "failed to initialize vblank for display support.\n"); 900 goto error; 901 } 902 903 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 904 amdgpu_dm_crtc_secure_display_create_contexts(adev); 905 if (!adev->dm.secure_display_ctx.crtc_ctx) 906 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 907 908 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 909 adev->dm.secure_display_ctx.support_mul_roi = true; 910 911 #endif 912 913 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 914 915 return 0; 916 error: 917 amdgpu_dm_fini(adev); 918 919 return -EINVAL; 920 } 921 922 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 923 { 924 struct amdgpu_device *adev = ip_block->adev; 925 926 amdgpu_dm_audio_fini(adev); 927 928 return 0; 929 } 930 931 static void amdgpu_dm_fini(struct amdgpu_device *adev) 932 { 933 int i; 934 935 if (adev->dm.vblank_control_workqueue) { 936 destroy_workqueue(adev->dm.vblank_control_workqueue); 937 adev->dm.vblank_control_workqueue = NULL; 938 } 939 940 if (adev->dm.idle_workqueue) { 941 if (adev->dm.idle_workqueue->running) { 942 adev->dm.idle_workqueue->enable = false; 943 flush_work(&adev->dm.idle_workqueue->work); 944 } 945 946 kfree(adev->dm.idle_workqueue); 947 adev->dm.idle_workqueue = NULL; 948 } 949 950 /* 951 * Disable ISM before dc_destroy() invalidates dm->dc. 952 * 953 * Quiesce workers first without dc_lock (they take dc_lock 954 * themselves, so syncing under it would deadlock), then drive the 955 * FSM back to FULL_POWER_RUNNING under dc_lock. 956 */ 957 amdgpu_dm_ism_disable(&adev->dm); 958 scoped_guard(mutex, &adev->dm.dc_lock) 959 amdgpu_dm_ism_force_full_power(&adev->dm); 960 961 amdgpu_dm_destroy_drm_device(&adev->dm); 962 963 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 964 if (adev->dm.secure_display_ctx.crtc_ctx) { 965 for (i = 0; i < adev->mode_info.num_crtc; i++) { 966 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 967 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 968 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 969 } 970 } 971 kfree(adev->dm.secure_display_ctx.crtc_ctx); 972 adev->dm.secure_display_ctx.crtc_ctx = NULL; 973 } 974 #endif 975 if (adev->dm.hdcp_workqueue) { 976 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 977 adev->dm.hdcp_workqueue = NULL; 978 } 979 980 if (adev->dm.dc) { 981 dc_deinit_callbacks(adev->dm.dc); 982 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 983 if (dc_enable_dmub_notifications(adev->dm.dc)) { 984 kfree(adev->dm.dmub_notify); 985 adev->dm.dmub_notify = NULL; 986 destroy_workqueue(adev->dm.delayed_hpd_wq); 987 adev->dm.delayed_hpd_wq = NULL; 988 } 989 } 990 991 if (adev->dm.dmub_bo) 992 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 993 &adev->dm.dmub_bo_gpu_addr, 994 &adev->dm.dmub_bo_cpu_addr); 995 996 if (adev->dm.boot_time_crc_info.bo_ptr) 997 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 998 &adev->dm.boot_time_crc_info.gpu_addr, 999 &adev->dm.boot_time_crc_info.cpu_addr); 1000 1001 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 1002 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1003 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1004 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1005 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1006 } 1007 } 1008 1009 kfree(adev->dm.hpd_rx_offload_wq); 1010 adev->dm.hpd_rx_offload_wq = NULL; 1011 } 1012 1013 /* DC Destroy TODO: Replace destroy DAL */ 1014 if (adev->dm.dc) 1015 dc_destroy(&adev->dm.dc); 1016 /* 1017 * TODO: pageflip, vlank interrupt 1018 * 1019 * amdgpu_dm_irq_fini(adev); 1020 */ 1021 1022 if (adev->dm.cgs_device) { 1023 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1024 adev->dm.cgs_device = NULL; 1025 } 1026 if (adev->dm.freesync_module) { 1027 mod_freesync_destroy(adev->dm.freesync_module); 1028 adev->dm.freesync_module = NULL; 1029 } 1030 1031 if (adev->dm.power_module) { 1032 mod_power_destroy(adev->dm.power_module); 1033 adev->dm.power_module = NULL; 1034 } 1035 mutex_destroy(&adev->dm.audio_lock); 1036 mutex_destroy(&adev->dm.dc_lock); 1037 mutex_destroy(&adev->dm.dpia_aux_lock); 1038 } 1039 1040 static int load_dmcu_fw(struct amdgpu_device *adev) 1041 { 1042 const char *fw_name_dmcu = NULL; 1043 int r; 1044 const struct dmcu_firmware_header_v1_0 *hdr; 1045 1046 switch (adev->asic_type) { 1047 #if defined(CONFIG_DRM_AMD_DC_SI) 1048 case CHIP_TAHITI: 1049 case CHIP_PITCAIRN: 1050 case CHIP_VERDE: 1051 case CHIP_OLAND: 1052 #endif 1053 case CHIP_BONAIRE: 1054 case CHIP_HAWAII: 1055 case CHIP_KAVERI: 1056 case CHIP_KABINI: 1057 case CHIP_MULLINS: 1058 case CHIP_TONGA: 1059 case CHIP_FIJI: 1060 case CHIP_CARRIZO: 1061 case CHIP_STONEY: 1062 case CHIP_POLARIS11: 1063 case CHIP_POLARIS10: 1064 case CHIP_POLARIS12: 1065 case CHIP_VEGAM: 1066 case CHIP_VEGA10: 1067 case CHIP_VEGA12: 1068 case CHIP_VEGA20: 1069 return 0; 1070 case CHIP_NAVI12: 1071 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1072 break; 1073 case CHIP_RAVEN: 1074 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1075 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1076 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1077 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1078 else 1079 return 0; 1080 break; 1081 default: 1082 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1083 case IP_VERSION(2, 0, 2): 1084 case IP_VERSION(2, 0, 3): 1085 case IP_VERSION(2, 0, 0): 1086 case IP_VERSION(2, 1, 0): 1087 case IP_VERSION(3, 0, 0): 1088 case IP_VERSION(3, 0, 2): 1089 case IP_VERSION(3, 0, 3): 1090 case IP_VERSION(3, 0, 1): 1091 case IP_VERSION(3, 1, 2): 1092 case IP_VERSION(3, 1, 3): 1093 case IP_VERSION(3, 1, 4): 1094 case IP_VERSION(3, 1, 5): 1095 case IP_VERSION(3, 1, 6): 1096 case IP_VERSION(3, 2, 0): 1097 case IP_VERSION(3, 2, 1): 1098 case IP_VERSION(3, 5, 0): 1099 case IP_VERSION(3, 5, 1): 1100 case IP_VERSION(3, 6, 0): 1101 case IP_VERSION(4, 0, 1): 1102 case IP_VERSION(4, 2, 0): 1103 case IP_VERSION(4, 2, 1): 1104 return 0; 1105 default: 1106 break; 1107 } 1108 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1109 return -EINVAL; 1110 } 1111 1112 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1113 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1114 return 0; 1115 } 1116 1117 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1118 "%s", fw_name_dmcu); 1119 if (r == -ENODEV) { 1120 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1121 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1122 adev->dm.fw_dmcu = NULL; 1123 return 0; 1124 } 1125 if (r) { 1126 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1127 fw_name_dmcu); 1128 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1129 return r; 1130 } 1131 1132 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1133 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1134 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1135 adev->firmware.fw_size += 1136 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1137 1138 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1139 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1140 adev->firmware.fw_size += 1141 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1142 1143 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1144 1145 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1146 1147 return 0; 1148 } 1149 1150 static int dm_sw_init(struct amdgpu_ip_block *ip_block) 1151 { 1152 struct amdgpu_device *adev = ip_block->adev; 1153 int r; 1154 1155 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1156 1157 if (!adev->dm.cgs_device) { 1158 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1159 return -EINVAL; 1160 } 1161 1162 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1163 INIT_LIST_HEAD(&adev->dm.da_list); 1164 1165 r = dm_dmub_sw_init(adev); 1166 if (r) 1167 return r; 1168 1169 return load_dmcu_fw(adev); 1170 } 1171 1172 static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1173 { 1174 struct amdgpu_device *adev = ip_block->adev; 1175 struct dal_allocation *da; 1176 1177 list_for_each_entry(da, &adev->dm.da_list, list) { 1178 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1179 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1180 list_del(&da->list); 1181 kfree(da); 1182 adev->dm.bb_from_dmub = NULL; 1183 break; 1184 } 1185 } 1186 1187 1188 kfree(adev->dm.dmub_fb_info); 1189 adev->dm.dmub_fb_info = NULL; 1190 1191 if (adev->dm.dmub_srv) { 1192 dmub_srv_destroy(adev->dm.dmub_srv); 1193 kfree(adev->dm.dmub_srv); 1194 adev->dm.dmub_srv = NULL; 1195 } 1196 1197 amdgpu_ucode_release(&adev->dm.dmub_fw); 1198 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1199 1200 return 0; 1201 } 1202 1203 1204 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1205 { 1206 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1207 struct dmub_srv *dmub = NULL; 1208 union dmub_fw_boot_options option = {0}; 1209 int ret = 0; 1210 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1211 1212 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1213 !adev->dm.dc->ctx->dmub_srv) { 1214 return; 1215 } 1216 1217 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1218 bootcrc_info = &adev->dm.boot_time_crc_info; 1219 1220 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1221 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1222 return; 1223 } 1224 1225 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1226 1227 /* Return if boot time CRC is not enabled */ 1228 if (option.bits.bootcrc_en_at_S0i3 == 0) 1229 return; 1230 1231 /* Create a buffer for boot time CRC */ 1232 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1233 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1234 &bootcrc_info->bo_ptr, 1235 &bootcrc_info->gpu_addr, 1236 &bootcrc_info->cpu_addr); 1237 1238 if (ret) { 1239 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1240 } else { 1241 bootcrc_info->size = fb_size; 1242 1243 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1244 bootcrc_info->gpu_addr, bootcrc_info->size); 1245 1246 /* Send the buffer info to DMUB */ 1247 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1248 bootcrc_info->gpu_addr, bootcrc_info->size); 1249 } 1250 } 1251 1252 static int dm_late_init(struct amdgpu_ip_block *ip_block) 1253 { 1254 struct amdgpu_device *adev = ip_block->adev; 1255 1256 struct dmcu_iram_parameters params; 1257 unsigned int linear_lut[16]; 1258 int i; 1259 struct dmcu *dmcu = NULL; 1260 1261 dmcu = adev->dm.dc->res_pool->dmcu; 1262 1263 /* Init the boot time CRC (skip in resume) */ 1264 if ((adev->in_suspend == 0) && 1265 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1266 amdgpu_dm_boot_time_crc_init(adev); 1267 1268 for (i = 0; i < 16; i++) 1269 linear_lut[i] = 0xFFFF * i / 15; 1270 1271 params.set = 0; 1272 params.backlight_ramping_override = false; 1273 params.backlight_ramping_start = 0xCCCC; 1274 params.backlight_ramping_reduction = 0xCCCCCCCC; 1275 params.backlight_lut_array_size = 16; 1276 params.backlight_lut_array = linear_lut; 1277 1278 /* Min backlight level after ABM reduction, Don't allow below 1% 1279 * 0xFFFF x 0.01 = 0x28F 1280 */ 1281 params.min_abm_backlight = 0x28F; 1282 /* In the case where abm is implemented on dmcub, 1283 * dmcu object will be null. 1284 * ABM 2.4 and up are implemented on dmcub. 1285 */ 1286 if (dmcu) { 1287 if (!dmcu_load_iram(dmcu, params)) 1288 return -EINVAL; 1289 } else if (adev->dm.dc->ctx->dmub_srv) { 1290 struct dc_link *edp_links[MAX_NUM_EDP]; 1291 int edp_num; 1292 1293 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1294 for (i = 0; i < edp_num; i++) { 1295 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1296 return -EINVAL; 1297 } 1298 } 1299 1300 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1301 } 1302 1303 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1304 { 1305 u8 buf[UUID_SIZE]; 1306 guid_t guid; 1307 int ret; 1308 1309 mutex_lock(&mgr->lock); 1310 if (!mgr->mst_primary) 1311 goto out_fail; 1312 1313 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1314 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1315 goto out_fail; 1316 } 1317 1318 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1319 DP_MST_EN | 1320 DP_UP_REQ_EN | 1321 DP_UPSTREAM_IS_SRC); 1322 if (ret < 0) { 1323 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1324 goto out_fail; 1325 } 1326 1327 /* Some hubs forget their guids after they resume */ 1328 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1329 if (ret != sizeof(buf)) { 1330 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1331 goto out_fail; 1332 } 1333 1334 import_guid(&guid, buf); 1335 1336 if (guid_is_null(&guid)) { 1337 guid_gen(&guid); 1338 export_guid(buf, &guid); 1339 1340 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1341 1342 if (ret != sizeof(buf)) { 1343 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1344 goto out_fail; 1345 } 1346 } 1347 1348 guid_copy(&mgr->mst_primary->guid, &guid); 1349 1350 out_fail: 1351 mutex_unlock(&mgr->lock); 1352 } 1353 1354 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1355 { 1356 struct amdgpu_dm_connector *aconnector; 1357 struct drm_connector *connector; 1358 struct drm_connector_list_iter iter; 1359 struct drm_dp_mst_topology_mgr *mgr; 1360 1361 drm_connector_list_iter_begin(dev, &iter); 1362 drm_for_each_connector_iter(connector, &iter) { 1363 1364 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1365 continue; 1366 1367 aconnector = to_amdgpu_dm_connector(connector); 1368 if (aconnector->dc_link->type != dc_connection_mst_branch || 1369 aconnector->mst_root) 1370 continue; 1371 1372 mgr = &aconnector->mst_mgr; 1373 1374 if (suspend) { 1375 drm_dp_mst_topology_mgr_suspend(mgr); 1376 } else { 1377 /* if extended timeout is supported in hardware, 1378 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1379 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1380 */ 1381 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1382 if (!dp_is_lttpr_present(aconnector->dc_link)) 1383 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1384 1385 /* TODO: move resume_mst_branch_status() into drm mst resume again 1386 * once topology probing work is pulled out from mst resume into mst 1387 * resume 2nd step. mst resume 2nd step should be called after old 1388 * state getting restored (i.e. drm_atomic_helper_resume()). 1389 */ 1390 resume_mst_branch_status(mgr); 1391 } 1392 } 1393 drm_connector_list_iter_end(&iter); 1394 } 1395 1396 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 1397 { 1398 int ret = 0; 1399 1400 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 1401 * on window driver dc implementation. 1402 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 1403 * should be passed to smu during boot up and resume from s3. 1404 * boot up: dc calculate dcn watermark clock settings within dc_create, 1405 * dcn20_resource_construct 1406 * then call pplib functions below to pass the settings to smu: 1407 * smu_set_watermarks_for_clock_ranges 1408 * smu_set_watermarks_table 1409 * navi10_set_watermarks_table 1410 * smu_write_watermarks_table 1411 * 1412 * For Renoir, clock settings of dcn watermark are also fixed values. 1413 * dc has implemented different flow for window driver: 1414 * dc_hardware_init / dc_set_power_state 1415 * dcn10_init_hw 1416 * notify_wm_ranges 1417 * set_wm_ranges 1418 * -- Linux 1419 * smu_set_watermarks_for_clock_ranges 1420 * renoir_set_watermarks_table 1421 * smu_write_watermarks_table 1422 * 1423 * For Linux, 1424 * dc_hardware_init -> amdgpu_dm_init 1425 * dc_set_power_state --> dm_resume 1426 * 1427 * therefore, this function apply to navi10/12/14 but not Renoir 1428 * * 1429 */ 1430 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1431 case IP_VERSION(2, 0, 2): 1432 case IP_VERSION(2, 0, 0): 1433 break; 1434 default: 1435 return 0; 1436 } 1437 1438 ret = amdgpu_dpm_write_watermarks_table(adev); 1439 if (ret) { 1440 drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); 1441 return ret; 1442 } 1443 1444 return 0; 1445 } 1446 1447 static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1448 { 1449 struct amdgpu_display_manager *dm = &adev->dm; 1450 struct amdgpu_i2c_adapter *oem_i2c; 1451 struct ddc_service *oem_ddc_service; 1452 int r; 1453 1454 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1455 if (oem_ddc_service) { 1456 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1457 if (!oem_i2c) { 1458 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1459 return -ENOMEM; 1460 } 1461 1462 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1463 if (r) { 1464 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1465 kfree(oem_i2c); 1466 return r; 1467 } 1468 dm->oem_i2c = oem_i2c; 1469 } 1470 1471 return 0; 1472 } 1473 1474 /** 1475 * dm_hw_init() - Initialize DC device 1476 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1477 * 1478 * Initialize the &struct amdgpu_display_manager device. This involves calling 1479 * the initializers of each DM component, then populating the struct with them. 1480 * 1481 * Although the function implies hardware initialization, both hardware and 1482 * software are initialized here. Splitting them out to their relevant init 1483 * hooks is a future TODO item. 1484 * 1485 * Some notable things that are initialized here: 1486 * 1487 * - Display Core, both software and hardware 1488 * - DC modules that we need (freesync and color management) 1489 * - DRM software states 1490 * - Interrupt sources and handlers 1491 * - Vblank support 1492 * - Debug FS entries, if enabled 1493 */ 1494 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1495 { 1496 struct amdgpu_device *adev = ip_block->adev; 1497 int r; 1498 1499 /* Create DAL display manager */ 1500 r = amdgpu_dm_init(adev); 1501 if (r) 1502 return r; 1503 amdgpu_dm_hpd_init(adev); 1504 1505 r = dm_oem_i2c_hw_init(adev); 1506 if (r) 1507 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1508 1509 return 0; 1510 } 1511 1512 /** 1513 * dm_hw_fini() - Teardown DC device 1514 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1515 * 1516 * Teardown components within &struct amdgpu_display_manager that require 1517 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1518 * were loaded. Also flush IRQ workqueues and disable them. 1519 */ 1520 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1521 { 1522 struct amdgpu_device *adev = ip_block->adev; 1523 1524 amdgpu_dm_hpd_fini(adev); 1525 1526 amdgpu_dm_irq_fini(adev); 1527 amdgpu_dm_fini(adev); 1528 return 0; 1529 } 1530 1531 1532 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1533 struct dc_state *state, bool enable) 1534 { 1535 enum dc_irq_source irq_source; 1536 struct amdgpu_crtc *acrtc; 1537 int rc = -EBUSY; 1538 int i = 0; 1539 1540 for (i = 0; i < state->stream_count; i++) { 1541 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1542 adev, state->stream_status[i].primary_otg_inst); 1543 1544 if (acrtc && state->stream_status[i].plane_count != 0) { 1545 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1546 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1547 if (rc) 1548 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1549 enable ? "enable" : "disable"); 1550 1551 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1552 if (enable) { 1553 if (amdgpu_dm_crtc_vrr_active( 1554 to_dm_crtc_state(acrtc->base.state))) 1555 rc = amdgpu_dm_crtc_set_vupdate_irq( 1556 &acrtc->base, true); 1557 } else 1558 rc = amdgpu_dm_crtc_set_vupdate_irq( 1559 &acrtc->base, false); 1560 1561 if (rc) 1562 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1563 enable ? "en" : "dis"); 1564 } 1565 1566 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1567 /* During gpu-reset we disable and then enable vblank irq, so 1568 * don't use amdgpu_irq_get/put() to avoid refcount change. 1569 */ 1570 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 1571 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1572 } 1573 } 1574 1575 } 1576 1577 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 1578 1579 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1580 { 1581 struct dc_state *context __free(state_release) = NULL; 1582 int i; 1583 struct dc_stream_state *del_streams[MAX_PIPES]; 1584 int del_streams_count = 0; 1585 struct dc_commit_streams_params params = {}; 1586 1587 memset(del_streams, 0, sizeof(del_streams)); 1588 1589 context = dc_state_create_current_copy(dc); 1590 if (context == NULL) 1591 return DC_ERROR_UNEXPECTED; 1592 1593 /* First remove from context all streams */ 1594 for (i = 0; i < context->stream_count; i++) { 1595 struct dc_stream_state *stream = context->streams[i]; 1596 1597 del_streams[del_streams_count++] = stream; 1598 } 1599 1600 /* Remove all planes for removed streams and then remove the streams */ 1601 for (i = 0; i < del_streams_count; i++) { 1602 enum dc_status res; 1603 1604 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1605 return DC_FAIL_DETACH_SURFACES; 1606 1607 res = dc_state_remove_stream(dc, context, del_streams[i]); 1608 if (res != DC_OK) 1609 return res; 1610 } 1611 1612 params.streams = context->streams; 1613 params.stream_count = context->stream_count; 1614 1615 return dc_commit_streams(dc, ¶ms); 1616 } 1617 1618 static int dm_cache_state(struct amdgpu_device *adev) 1619 { 1620 int r; 1621 1622 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1623 if (IS_ERR(adev->dm.cached_state)) { 1624 r = PTR_ERR(adev->dm.cached_state); 1625 adev->dm.cached_state = NULL; 1626 } 1627 1628 return adev->dm.cached_state ? 0 : r; 1629 } 1630 1631 static void dm_destroy_cached_state(struct amdgpu_device *adev) 1632 { 1633 struct amdgpu_display_manager *dm = &adev->dm; 1634 struct drm_device *ddev = adev_to_drm(adev); 1635 struct dm_plane_state *dm_new_plane_state; 1636 struct drm_plane_state *new_plane_state; 1637 struct dm_crtc_state *dm_new_crtc_state; 1638 struct drm_crtc_state *new_crtc_state; 1639 struct drm_plane *plane; 1640 struct drm_crtc *crtc; 1641 int i; 1642 1643 if (!dm->cached_state) 1644 return; 1645 1646 /* Force mode set in atomic commit */ 1647 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1648 new_crtc_state->active_changed = true; 1649 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1650 reset_freesync_config_for_crtc(dm_new_crtc_state); 1651 } 1652 1653 /* 1654 * atomic_check is expected to create the dc states. We need to release 1655 * them here, since they were duplicated as part of the suspend 1656 * procedure. 1657 */ 1658 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1659 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1660 if (dm_new_crtc_state->stream) { 1661 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1662 dc_stream_release(dm_new_crtc_state->stream); 1663 dm_new_crtc_state->stream = NULL; 1664 } 1665 dm_new_crtc_state->base.color_mgmt_changed = true; 1666 } 1667 1668 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1669 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1670 if (dm_new_plane_state->dc_state) { 1671 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1672 dc_plane_state_release(dm_new_plane_state->dc_state); 1673 dm_new_plane_state->dc_state = NULL; 1674 } 1675 } 1676 1677 drm_atomic_helper_resume(ddev, dm->cached_state); 1678 1679 dm->cached_state = NULL; 1680 } 1681 1682 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1683 { 1684 struct amdgpu_device *adev = ip_block->adev; 1685 struct amdgpu_display_manager *dm = &adev->dm; 1686 1687 if (amdgpu_in_reset(adev)) { 1688 enum dc_status res; 1689 1690 /* Quiesce ISM workers before taking dc_lock (workers take 1691 * dc_lock themselves; syncing under it would deadlock). 1692 */ 1693 amdgpu_dm_ism_disable(dm); 1694 1695 mutex_lock(&dm->dc_lock); 1696 1697 amdgpu_dm_ism_force_full_power(dm); 1698 dc_allow_idle_optimizations(adev->dm.dc, false); 1699 1700 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1701 1702 if (dm->cached_dc_state) 1703 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1704 1705 res = amdgpu_dm_commit_zero_streams(dm->dc); 1706 if (res != DC_OK) { 1707 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1708 return -EINVAL; 1709 } 1710 1711 amdgpu_dm_irq_suspend(adev); 1712 1713 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1714 1715 return 0; 1716 } 1717 1718 if (!adev->dm.cached_state) { 1719 int r = dm_cache_state(adev); 1720 1721 if (r) 1722 return r; 1723 } 1724 1725 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1726 1727 s3_handle_mst(adev_to_drm(adev), true); 1728 1729 amdgpu_dm_irq_suspend(adev); 1730 1731 /* 1732 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1733 * themselves; syncing under it would deadlock). 1734 */ 1735 amdgpu_dm_ism_disable(dm); 1736 scoped_guard(mutex, &dm->dc_lock) 1737 amdgpu_dm_ism_force_full_power(dm); 1738 1739 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1740 1741 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1742 1743 if (dm->dc->caps.ips_support && adev->in_s0ix) 1744 dc_allow_idle_optimizations(dm->dc, true); 1745 1746 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1747 1748 return 0; 1749 } 1750 1751 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1752 { 1753 struct dc_sink_init_data sink_init_data = { 0 }; 1754 struct display_sink_capability sink_caps = { 0 }; 1755 enum dc_edid_status edid_status; 1756 struct dc_context *dc_ctx = link->ctx; 1757 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1758 struct dc_sink *sink = NULL; 1759 struct dc_sink *prev_sink = NULL; 1760 1761 link->type = dc_connection_none; 1762 prev_sink = link->local_sink; 1763 1764 if (prev_sink) 1765 dc_sink_release(prev_sink); 1766 1767 switch (link->connector_signal) { 1768 case SIGNAL_TYPE_HDMI_TYPE_A: { 1769 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1770 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1771 break; 1772 } 1773 1774 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1775 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1776 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1777 break; 1778 } 1779 1780 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1781 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1782 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1783 break; 1784 } 1785 1786 case SIGNAL_TYPE_LVDS: { 1787 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1788 sink_caps.signal = SIGNAL_TYPE_LVDS; 1789 break; 1790 } 1791 1792 case SIGNAL_TYPE_EDP: { 1793 sink_caps.transaction_type = 1794 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1795 sink_caps.signal = SIGNAL_TYPE_EDP; 1796 break; 1797 } 1798 1799 case SIGNAL_TYPE_DISPLAY_PORT: { 1800 sink_caps.transaction_type = 1801 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1802 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1803 break; 1804 } 1805 1806 default: 1807 drm_err(dev, "Invalid connector type! signal:%d\n", 1808 link->connector_signal); 1809 return; 1810 } 1811 1812 sink_init_data.link = link; 1813 sink_init_data.sink_signal = sink_caps.signal; 1814 1815 sink = dc_sink_create(&sink_init_data); 1816 if (!sink) { 1817 drm_err(dev, "Failed to create sink!\n"); 1818 return; 1819 } 1820 1821 /* dc_sink_create returns a new reference */ 1822 link->local_sink = sink; 1823 1824 edid_status = dm_helpers_read_local_edid( 1825 link->ctx, 1826 link, 1827 sink); 1828 1829 if (edid_status != EDID_OK) 1830 drm_err(dev, "Failed to read EDID\n"); 1831 1832 } 1833 1834 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1835 struct amdgpu_display_manager *dm) 1836 { 1837 struct { 1838 struct dc_surface_update surface_updates[MAX_SURFACES]; 1839 struct dc_plane_info plane_infos[MAX_SURFACES]; 1840 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1841 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1842 struct dc_stream_update stream_update; 1843 } *bundle __free(kfree); 1844 int k, m; 1845 1846 bundle = kzalloc_obj(*bundle); 1847 1848 if (!bundle) { 1849 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1850 return; 1851 } 1852 1853 for (k = 0; k < dc_state->stream_count; k++) { 1854 bundle->stream_update.stream = dc_state->streams[k]; 1855 1856 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1857 bundle->surface_updates[m].surface = 1858 dc_state->stream_status[k].plane_states[m]; 1859 bundle->surface_updates[m].surface->force_full_update = 1860 true; 1861 } 1862 1863 update_planes_and_stream_adapter(dm->dc, 1864 UPDATE_TYPE_FULL, 1865 dc_state->stream_status[k].plane_count, 1866 dc_state->streams[k], 1867 &bundle->stream_update, 1868 bundle->surface_updates); 1869 } 1870 } 1871 1872 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1873 struct dc_sink *sink) 1874 { 1875 struct dc_panel_patch *ppatch = NULL; 1876 1877 if (!sink) 1878 return; 1879 1880 ppatch = &sink->edid_caps.panel_patch; 1881 if (ppatch->wait_after_dpcd_poweroff_ms) { 1882 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1883 drm_dbg_driver(adev_to_drm(adev), 1884 "%s: adding a %ds delay as w/a for panel\n", 1885 __func__, 1886 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1887 } 1888 } 1889 1890 /** 1891 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1892 * @adev: amdgpu device pointer 1893 * 1894 * Iterates through all DC links and dumps information about local and remote 1895 * (MST) sinks. Should be called after connector detection is complete to see 1896 * the final state of all links. 1897 */ 1898 static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1899 { 1900 struct dc *dc = adev->dm.dc; 1901 struct drm_device *dev = adev_to_drm(adev); 1902 int li; 1903 1904 if (!dc) 1905 return; 1906 1907 for (li = 0; li < dc->link_count; li++) { 1908 struct dc_link *l = dc->links[li]; 1909 const char *name = NULL; 1910 int rs; 1911 1912 if (!l) 1913 continue; 1914 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1915 name = l->local_sink->edid_caps.display_name; 1916 else 1917 name = "n/a"; 1918 1919 drm_dbg_kms(dev, 1920 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1921 li, 1922 l->local_sink, 1923 l->type, 1924 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1925 l->sink_count, 1926 name, 1927 l->dpcd_caps.is_mst_capable, 1928 l->mst_stream_alloc_table.stream_count); 1929 1930 /* Dump remote (MST) sinks if any */ 1931 for (rs = 0; rs < l->sink_count; rs++) { 1932 struct dc_sink *rsink = l->remote_sinks[rs]; 1933 const char *rname = NULL; 1934 1935 if (!rsink) 1936 continue; 1937 if (rsink->edid_caps.display_name[0]) 1938 rname = rsink->edid_caps.display_name; 1939 else 1940 rname = "n/a"; 1941 drm_dbg_kms(dev, 1942 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1943 li, rs, 1944 rsink, 1945 rsink->sink_signal, 1946 rname); 1947 } 1948 } 1949 } 1950 1951 static int dm_resume(struct amdgpu_ip_block *ip_block) 1952 { 1953 struct amdgpu_device *adev = ip_block->adev; 1954 struct drm_device *ddev = adev_to_drm(adev); 1955 struct amdgpu_display_manager *dm = &adev->dm; 1956 struct amdgpu_dm_connector *aconnector; 1957 struct drm_connector *connector; 1958 struct drm_connector_list_iter iter; 1959 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1960 enum dc_connection_type new_connection_type = dc_connection_none; 1961 struct dc_state *dc_state; 1962 int i, r, j; 1963 struct dc_commit_streams_params commit_params = {}; 1964 1965 if (dm->dc->caps.ips_support) { 1966 if (!amdgpu_in_reset(adev)) 1967 mutex_lock(&dm->dc_lock); 1968 1969 /* Need to set POWER_STATE_D0 first or it will not execute 1970 * idle_power_optimizations command to DMUB. 1971 */ 1972 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1973 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 1974 1975 if (!amdgpu_in_reset(adev)) 1976 mutex_unlock(&dm->dc_lock); 1977 } 1978 1979 if (amdgpu_in_reset(adev)) { 1980 dc_state = dm->cached_dc_state; 1981 1982 /* 1983 * The dc->current_state is backed up into dm->cached_dc_state 1984 * before we commit 0 streams. 1985 * 1986 * DC will clear link encoder assignments on the real state 1987 * but the changes won't propagate over to the copy we made 1988 * before the 0 streams commit. 1989 * 1990 * DC expects that link encoder assignments are *not* valid 1991 * when committing a state, so as a workaround we can copy 1992 * off of the current state. 1993 * 1994 * We lose the previous assignments, but we had already 1995 * commit 0 streams anyway. 1996 */ 1997 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 1998 1999 r = dm_dmub_hw_init(adev); 2000 if (r) { 2001 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 2002 return r; 2003 } 2004 2005 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2006 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2007 2008 dc_resume(dm->dc); 2009 2010 amdgpu_dm_ism_enable(dm); 2011 amdgpu_dm_irq_resume_early(adev); 2012 2013 for (i = 0; i < dc_state->stream_count; i++) { 2014 dc_state->streams[i]->mode_changed = true; 2015 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2016 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 2017 } 2018 } 2019 2020 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2021 amdgpu_dm_outbox_init(adev); 2022 dc_enable_dmub_outbox(adev->dm.dc); 2023 } 2024 2025 commit_params.streams = dc_state->streams; 2026 commit_params.stream_count = dc_state->stream_count; 2027 dc_exit_ips_for_hw_access(dm->dc); 2028 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 2029 2030 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2031 2032 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2033 2034 dc_state_release(dm->cached_dc_state); 2035 dm->cached_dc_state = NULL; 2036 2037 amdgpu_dm_irq_resume_late(adev); 2038 2039 mutex_unlock(&dm->dc_lock); 2040 2041 /* set the backlight after a reset */ 2042 for (i = 0; i < dm->num_of_edps; i++) { 2043 if (dm->backlight_dev[i]) 2044 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 2045 } 2046 2047 return 0; 2048 } 2049 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2050 dc_state_release(dm_state->context); 2051 dm_state->context = dc_state_create(dm->dc, NULL); 2052 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2053 2054 /* Before powering on DC we need to re-initialize DMUB. */ 2055 dm_dmub_hw_resume(adev); 2056 2057 /* Re-enable outbox interrupts for DPIA. */ 2058 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2059 amdgpu_dm_outbox_init(adev); 2060 dc_enable_dmub_outbox(adev->dm.dc); 2061 } 2062 2063 /* power on hardware */ 2064 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2065 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2066 2067 /* program HPD filter */ 2068 dc_resume(dm->dc); 2069 2070 scoped_guard(mutex, &dm->dc_lock) 2071 amdgpu_dm_ism_enable(dm); 2072 2073 /* 2074 * early enable HPD Rx IRQ, should be done before set mode as short 2075 * pulse interrupts are used for MST 2076 */ 2077 amdgpu_dm_irq_resume_early(adev); 2078 2079 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 2080 2081 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2082 s3_handle_mst(ddev, false); 2083 2084 /* Do detection*/ 2085 drm_connector_list_iter_begin(ddev, &iter); 2086 drm_for_each_connector_iter(connector, &iter) { 2087 bool ret; 2088 2089 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2090 continue; 2091 2092 aconnector = to_amdgpu_dm_connector(connector); 2093 2094 if (!aconnector->dc_link) 2095 continue; 2096 2097 /* 2098 * this is the case when traversing through already created end sink 2099 * MST connectors, should be skipped 2100 */ 2101 if (aconnector->mst_root) 2102 continue; 2103 2104 /* Skip eDP detection, when there is no sink present */ 2105 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 2106 !aconnector->dc_link->edp_sink_present) 2107 continue; 2108 2109 guard(mutex)(&aconnector->hpd_lock); 2110 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2111 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2112 2113 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2114 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 2115 } else { 2116 guard(mutex)(&dm->dc_lock); 2117 dc_exit_ips_for_hw_access(dm->dc); 2118 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 2119 if (ret) { 2120 /* w/a delay for certain panels */ 2121 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2122 } 2123 } 2124 2125 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2126 aconnector->fake_enable = false; 2127 2128 if (aconnector->dc_sink) 2129 dc_sink_release(aconnector->dc_sink); 2130 aconnector->dc_sink = NULL; 2131 amdgpu_dm_update_connector_after_detect(aconnector); 2132 } 2133 drm_connector_list_iter_end(&iter); 2134 2135 dm_destroy_cached_state(adev); 2136 2137 /* Do mst topology probing after resuming cached state*/ 2138 drm_connector_list_iter_begin(ddev, &iter); 2139 drm_for_each_connector_iter(connector, &iter) { 2140 bool init = false; 2141 2142 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2143 continue; 2144 2145 aconnector = to_amdgpu_dm_connector(connector); 2146 if (aconnector->dc_link->type != dc_connection_mst_branch || 2147 aconnector->mst_root) 2148 continue; 2149 2150 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2151 init = !aconnector->mst_mgr.mst_primary; 2152 } 2153 if (init) 2154 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2155 aconnector->dc_link, false); 2156 else 2157 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2158 } 2159 drm_connector_list_iter_end(&iter); 2160 2161 /* Debug dump: list all DC links and their associated sinks after detection 2162 * is complete for all connectors. This provides a comprehensive view of the 2163 * final state without repeating the dump for each connector. 2164 */ 2165 amdgpu_dm_dump_links_and_sinks(adev); 2166 2167 amdgpu_dm_irq_resume_late(adev); 2168 2169 amdgpu_dm_smu_write_watermarks_table(adev); 2170 2171 drm_kms_helper_hotplug_event(ddev); 2172 2173 return 0; 2174 } 2175 2176 /** 2177 * DOC: DM Lifecycle 2178 * 2179 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2180 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2181 * the base driver's device list to be initialized and torn down accordingly. 2182 * 2183 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2184 */ 2185 2186 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2187 .name = "dm", 2188 .early_init = dm_early_init, 2189 .late_init = dm_late_init, 2190 .sw_init = dm_sw_init, 2191 .sw_fini = dm_sw_fini, 2192 .early_fini = amdgpu_dm_early_fini, 2193 .hw_init = dm_hw_init, 2194 .hw_fini = dm_hw_fini, 2195 .suspend = dm_suspend, 2196 .resume = dm_resume, 2197 .is_idle = dm_is_idle, 2198 .wait_for_idle = dm_wait_for_idle, 2199 .soft_reset = dm_soft_reset, 2200 .set_clockgating_state = dm_set_clockgating_state, 2201 .set_powergating_state = dm_set_powergating_state, 2202 }; 2203 2204 const struct amdgpu_ip_block_version dm_ip_block = { 2205 .type = AMD_IP_BLOCK_TYPE_DCE, 2206 .major = 1, 2207 .minor = 0, 2208 .rev = 0, 2209 .funcs = &amdgpu_dm_funcs, 2210 }; 2211 2212 2213 /** 2214 * DOC: atomic 2215 * 2216 * *WIP* 2217 */ 2218 2219 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2220 .fb_create = amdgpu_display_user_framebuffer_create, 2221 .get_format_info = amdgpu_dm_plane_get_format_info, 2222 .atomic_check = amdgpu_dm_atomic_check, 2223 .atomic_commit = drm_atomic_helper_commit, 2224 }; 2225 2226 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2227 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2228 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2229 }; 2230 2231 /* 2232 * Acquires the lock for the atomic state object and returns 2233 * the new atomic state. 2234 * 2235 * This should only be called during atomic check. 2236 */ 2237 int dm_atomic_get_state(struct drm_atomic_commit *state, 2238 struct dm_atomic_state **dm_state) 2239 { 2240 struct drm_device *dev = state->dev; 2241 struct amdgpu_device *adev = drm_to_adev(dev); 2242 struct amdgpu_display_manager *dm = &adev->dm; 2243 struct drm_private_state *priv_state; 2244 2245 if (*dm_state) 2246 return 0; 2247 2248 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2249 if (IS_ERR(priv_state)) 2250 return PTR_ERR(priv_state); 2251 2252 *dm_state = to_dm_atomic_state(priv_state); 2253 2254 return 0; 2255 } 2256 2257 static struct dm_atomic_state * 2258 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2259 { 2260 struct drm_device *dev = state->dev; 2261 struct amdgpu_device *adev = drm_to_adev(dev); 2262 struct amdgpu_display_manager *dm = &adev->dm; 2263 struct drm_private_obj *obj; 2264 struct drm_private_state *new_obj_state; 2265 int i; 2266 2267 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2268 if (obj->funcs == dm->atomic_obj.funcs) 2269 return to_dm_atomic_state(new_obj_state); 2270 } 2271 2272 return NULL; 2273 } 2274 2275 static struct drm_private_state * 2276 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2277 { 2278 struct dm_atomic_state *old_state, *new_state; 2279 2280 new_state = kzalloc_obj(*new_state); 2281 if (!new_state) 2282 return NULL; 2283 2284 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2285 2286 old_state = to_dm_atomic_state(obj->state); 2287 2288 if (old_state && old_state->context) 2289 new_state->context = dc_state_create_copy(old_state->context); 2290 2291 if (!new_state->context) { 2292 kfree(new_state); 2293 return NULL; 2294 } 2295 2296 return &new_state->base; 2297 } 2298 2299 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 2300 struct drm_private_state *state) 2301 { 2302 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2303 2304 if (dm_state && dm_state->context) 2305 dc_state_release(dm_state->context); 2306 2307 kfree(dm_state); 2308 } 2309 2310 static struct drm_private_state * 2311 dm_atomic_create_state(struct drm_private_obj *obj) 2312 { 2313 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2314 struct dm_atomic_state *dm_state; 2315 struct dc_state *context; 2316 2317 dm_state = kzalloc_obj(*dm_state); 2318 if (!dm_state) 2319 return ERR_PTR(-ENOMEM); 2320 2321 context = dc_state_create_current_copy(adev->dm.dc); 2322 if (!context) { 2323 kfree(dm_state); 2324 return ERR_PTR(-ENOMEM); 2325 } 2326 2327 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2328 dm_state->context = context; 2329 2330 return &dm_state->base; 2331 } 2332 2333 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2334 .atomic_create_state = dm_atomic_create_state, 2335 .atomic_duplicate_state = dm_atomic_duplicate_state, 2336 .atomic_destroy_state = dm_atomic_destroy_state, 2337 }; 2338 2339 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2340 { 2341 int r; 2342 2343 adev->mode_info.mode_config_initialized = true; 2344 2345 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2346 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2347 2348 adev_to_drm(adev)->mode_config.max_width = 16384; 2349 adev_to_drm(adev)->mode_config.max_height = 16384; 2350 2351 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2352 if (adev->asic_type == CHIP_HAWAII) 2353 /* disable prefer shadow for now due to hibernation issues */ 2354 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2355 else 2356 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2357 /* indicates support for immediate flip */ 2358 adev_to_drm(adev)->mode_config.async_page_flip = true; 2359 2360 drm_atomic_private_obj_init(adev_to_drm(adev), 2361 &adev->dm.atomic_obj, 2362 &dm_atomic_state_funcs); 2363 2364 r = amdgpu_display_modeset_create_props(adev); 2365 if (r) 2366 return r; 2367 2368 #ifdef AMD_PRIVATE_COLOR 2369 if (amdgpu_dm_create_color_properties(adev)) 2370 return -ENOMEM; 2371 #endif 2372 2373 r = amdgpu_dm_audio_init(adev); 2374 if (r) 2375 return r; 2376 2377 return 0; 2378 } 2379 2380 static int initialize_plane(struct amdgpu_display_manager *dm, 2381 struct amdgpu_mode_info *mode_info, int plane_id, 2382 enum drm_plane_type plane_type, 2383 const struct dc_plane_cap *plane_cap) 2384 { 2385 struct drm_plane *plane; 2386 unsigned long possible_crtcs; 2387 int ret = 0; 2388 2389 plane = kzalloc_obj(struct drm_plane); 2390 if (!plane) { 2391 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2392 return -ENOMEM; 2393 } 2394 plane->type = plane_type; 2395 2396 /* 2397 * HACK: IGT tests expect that the primary plane for a CRTC 2398 * can only have one possible CRTC. Only expose support for 2399 * any CRTC if they're not going to be used as a primary plane 2400 * for a CRTC - like overlay or underlay planes. 2401 */ 2402 possible_crtcs = 1 << plane_id; 2403 if (plane_id >= dm->dc->caps.max_streams) 2404 possible_crtcs = 0xff; 2405 2406 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2407 2408 if (ret) { 2409 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2410 kfree(plane); 2411 return ret; 2412 } 2413 2414 if (mode_info) 2415 mode_info->planes[plane_id] = plane; 2416 2417 return ret; 2418 } 2419 2420 2421 /* 2422 * In this architecture, the association 2423 * connector -> encoder -> crtc 2424 * id not really requried. The crtc and connector will hold the 2425 * display_index as an abstraction to use with DAL component 2426 * 2427 * Returns 0 on success 2428 */ 2429 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2430 { 2431 struct amdgpu_display_manager *dm = &adev->dm; 2432 s32 i; 2433 struct amdgpu_dm_connector *aconnector = NULL; 2434 struct amdgpu_encoder *aencoder = NULL; 2435 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2436 u32 link_cnt; 2437 s32 primary_planes; 2438 enum dc_connection_type new_connection_type = dc_connection_none; 2439 const struct dc_plane_cap *plane; 2440 bool psr_feature_enabled = false; 2441 bool replay_feature_enabled = false; 2442 int max_overlay = dm->dc->caps.max_slave_planes; 2443 2444 dm->display_indexes_num = dm->dc->caps.max_streams; 2445 /* Update the actual used number of crtc */ 2446 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2447 2448 amdgpu_dm_set_irq_funcs(adev); 2449 2450 link_cnt = dm->dc->caps.max_links; 2451 if (amdgpu_dm_mode_config_init(dm->adev)) { 2452 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2453 return -EINVAL; 2454 } 2455 2456 /* There is one primary plane per CRTC */ 2457 primary_planes = dm->dc->caps.max_streams; 2458 if (primary_planes > AMDGPU_MAX_PLANES) { 2459 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2460 return -EINVAL; 2461 } 2462 2463 /* 2464 * Initialize primary planes, implicit planes for legacy IOCTLS. 2465 * Order is reversed to match iteration order in atomic check. 2466 */ 2467 for (i = (primary_planes - 1); i >= 0; i--) { 2468 plane = &dm->dc->caps.planes[i]; 2469 2470 if (initialize_plane(dm, mode_info, i, 2471 DRM_PLANE_TYPE_PRIMARY, plane)) { 2472 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2473 goto fail; 2474 } 2475 } 2476 2477 /* 2478 * Initialize overlay planes, index starting after primary planes. 2479 * These planes have a higher DRM index than the primary planes since 2480 * they should be considered as having a higher z-order. 2481 * Order is reversed to match iteration order in atomic check. 2482 * 2483 * Only support DCN for now, and only expose one so we don't encourage 2484 * userspace to use up all the pipes. 2485 */ 2486 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2487 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2488 2489 /* Do not create overlay if MPO disabled */ 2490 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2491 break; 2492 2493 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2494 continue; 2495 2496 if (!plane->pixel_format_support.argb8888) 2497 continue; 2498 2499 if (max_overlay-- == 0) 2500 break; 2501 2502 if (initialize_plane(dm, NULL, primary_planes + i, 2503 DRM_PLANE_TYPE_OVERLAY, plane)) { 2504 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2505 goto fail; 2506 } 2507 } 2508 2509 for (i = 0; i < dm->dc->caps.max_streams; i++) 2510 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2511 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2512 goto fail; 2513 } 2514 2515 /* Use Outbox interrupt */ 2516 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2517 case IP_VERSION(3, 0, 0): 2518 case IP_VERSION(3, 1, 2): 2519 case IP_VERSION(3, 1, 3): 2520 case IP_VERSION(3, 1, 4): 2521 case IP_VERSION(3, 1, 5): 2522 case IP_VERSION(3, 1, 6): 2523 case IP_VERSION(3, 2, 0): 2524 case IP_VERSION(3, 2, 1): 2525 case IP_VERSION(2, 1, 0): 2526 case IP_VERSION(3, 5, 0): 2527 case IP_VERSION(3, 5, 1): 2528 case IP_VERSION(3, 6, 0): 2529 case IP_VERSION(4, 0, 1): 2530 case IP_VERSION(4, 2, 0): 2531 case IP_VERSION(4, 2, 1): 2532 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2533 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2534 goto fail; 2535 } 2536 break; 2537 default: 2538 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2539 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2540 } 2541 2542 /* Determine whether to enable PSR support by default. */ 2543 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2544 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2545 case IP_VERSION(3, 1, 2): 2546 case IP_VERSION(3, 1, 3): 2547 case IP_VERSION(3, 1, 4): 2548 case IP_VERSION(3, 1, 5): 2549 case IP_VERSION(3, 1, 6): 2550 case IP_VERSION(3, 2, 0): 2551 case IP_VERSION(3, 2, 1): 2552 case IP_VERSION(3, 5, 0): 2553 case IP_VERSION(3, 5, 1): 2554 case IP_VERSION(3, 6, 0): 2555 case IP_VERSION(4, 0, 1): 2556 case IP_VERSION(4, 2, 0): 2557 case IP_VERSION(4, 2, 1): 2558 psr_feature_enabled = true; 2559 break; 2560 default: 2561 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2562 break; 2563 } 2564 } 2565 2566 /* Determine whether to enable Replay support by default. */ 2567 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2568 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2569 case IP_VERSION(3, 1, 4): 2570 case IP_VERSION(3, 2, 0): 2571 case IP_VERSION(3, 2, 1): 2572 case IP_VERSION(3, 5, 0): 2573 case IP_VERSION(3, 5, 1): 2574 case IP_VERSION(3, 6, 0): 2575 case IP_VERSION(4, 2, 0): 2576 case IP_VERSION(4, 2, 1): 2577 replay_feature_enabled = true; 2578 break; 2579 2580 default: 2581 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2582 break; 2583 } 2584 } 2585 2586 if (link_cnt > MAX_LINKS) { 2587 drm_err(adev_to_drm(adev), 2588 "KMS: Cannot support more than %d display indexes\n", 2589 MAX_LINKS); 2590 goto fail; 2591 } 2592 2593 /* loops over all connectors on the board */ 2594 for (i = 0; i < link_cnt; i++) { 2595 struct dc_link *link = NULL; 2596 2597 link = dc_get_link_at_index(dm->dc, i); 2598 2599 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2600 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2601 2602 if (!wbcon) { 2603 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2604 continue; 2605 } 2606 2607 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2608 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2609 kfree(wbcon); 2610 continue; 2611 } 2612 2613 link->psr_settings.psr_feature_enabled = false; 2614 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2615 2616 continue; 2617 } 2618 2619 aconnector = kzalloc_obj(*aconnector); 2620 if (!aconnector) 2621 goto fail; 2622 2623 aencoder = kzalloc_obj(*aencoder); 2624 if (!aencoder) 2625 goto fail; 2626 2627 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2628 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2629 goto fail; 2630 } 2631 2632 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2633 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2634 goto fail; 2635 } 2636 2637 if (dm->hpd_rx_offload_wq) 2638 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2639 aconnector; 2640 2641 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2642 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2643 2644 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2645 amdgpu_dm_emulated_link_detect(link); 2646 amdgpu_dm_update_connector_after_detect(aconnector); 2647 } else { 2648 bool ret = false; 2649 2650 mutex_lock(&dm->dc_lock); 2651 dc_exit_ips_for_hw_access(dm->dc); 2652 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2653 mutex_unlock(&dm->dc_lock); 2654 2655 if (ret) { 2656 amdgpu_dm_update_connector_after_detect(aconnector); 2657 amdgpu_dm_setup_backlight_device(dm, aconnector); 2658 2659 /* Disable PSR if Replay can be enabled */ 2660 if (replay_feature_enabled) 2661 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2662 psr_feature_enabled = false; 2663 2664 if (psr_feature_enabled) { 2665 amdgpu_dm_set_psr_caps(link, aconnector); 2666 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2667 aconnector->base.name, 2668 link->psr_settings.psr_feature_enabled, 2669 link->psr_settings.psr_version, 2670 link->dpcd_caps.psr_info.psr_version, 2671 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2672 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2673 } 2674 } 2675 } 2676 amdgpu_set_panel_orientation(&aconnector->base); 2677 } 2678 2679 /* Debug dump: list all DC links and their associated sinks after detection 2680 * is complete for all connectors. This provides a comprehensive view of the 2681 * final state without repeating the dump for each connector. 2682 */ 2683 amdgpu_dm_dump_links_and_sinks(adev); 2684 2685 /* Software is initialized. Now we can register interrupt handlers. */ 2686 switch (adev->asic_type) { 2687 #if defined(CONFIG_DRM_AMD_DC_SI) 2688 case CHIP_TAHITI: 2689 case CHIP_PITCAIRN: 2690 case CHIP_VERDE: 2691 case CHIP_OLAND: 2692 #endif 2693 case CHIP_BONAIRE: 2694 case CHIP_HAWAII: 2695 case CHIP_KAVERI: 2696 case CHIP_KABINI: 2697 case CHIP_MULLINS: 2698 case CHIP_TONGA: 2699 case CHIP_FIJI: 2700 case CHIP_CARRIZO: 2701 case CHIP_STONEY: 2702 case CHIP_POLARIS11: 2703 case CHIP_POLARIS10: 2704 case CHIP_POLARIS12: 2705 case CHIP_VEGAM: 2706 case CHIP_VEGA10: 2707 case CHIP_VEGA12: 2708 case CHIP_VEGA20: 2709 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2710 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2711 goto fail; 2712 } 2713 break; 2714 default: 2715 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2716 case IP_VERSION(1, 0, 0): 2717 case IP_VERSION(1, 0, 1): 2718 case IP_VERSION(2, 0, 2): 2719 case IP_VERSION(2, 0, 3): 2720 case IP_VERSION(2, 0, 0): 2721 case IP_VERSION(2, 1, 0): 2722 case IP_VERSION(3, 0, 0): 2723 case IP_VERSION(3, 0, 2): 2724 case IP_VERSION(3, 0, 3): 2725 case IP_VERSION(3, 0, 1): 2726 case IP_VERSION(3, 1, 2): 2727 case IP_VERSION(3, 1, 3): 2728 case IP_VERSION(3, 1, 4): 2729 case IP_VERSION(3, 1, 5): 2730 case IP_VERSION(3, 1, 6): 2731 case IP_VERSION(3, 2, 0): 2732 case IP_VERSION(3, 2, 1): 2733 case IP_VERSION(3, 5, 0): 2734 case IP_VERSION(3, 5, 1): 2735 case IP_VERSION(3, 6, 0): 2736 case IP_VERSION(4, 0, 1): 2737 case IP_VERSION(4, 2, 0): 2738 case IP_VERSION(4, 2, 1): 2739 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2740 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2741 goto fail; 2742 } 2743 break; 2744 default: 2745 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2746 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2747 goto fail; 2748 } 2749 break; 2750 } 2751 2752 return 0; 2753 fail: 2754 kfree(aencoder); 2755 kfree(aconnector); 2756 2757 return -EINVAL; 2758 } 2759 2760 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2761 { 2762 if (dm->atomic_obj.state) 2763 drm_atomic_private_obj_fini(&dm->atomic_obj); 2764 } 2765 2766 /****************************************************************************** 2767 * amdgpu_display_funcs functions 2768 *****************************************************************************/ 2769 2770 /* 2771 * dm_bandwidth_update - program display watermarks 2772 * 2773 * @adev: amdgpu_device pointer 2774 * 2775 * Calculate and program the display watermarks and line buffer allocation. 2776 */ 2777 static void dm_bandwidth_update(struct amdgpu_device *adev) 2778 { 2779 /* TODO: implement later */ 2780 } 2781 2782 static const struct amdgpu_display_funcs dm_display_funcs = { 2783 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2784 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2785 .backlight_set_level = NULL, /* never called for DC */ 2786 .backlight_get_level = NULL, /* never called for DC */ 2787 .hpd_sense = NULL,/* called unconditionally */ 2788 .hpd_set_polarity = NULL, /* called unconditionally */ 2789 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2790 .page_flip_get_scanoutpos = 2791 dm_crtc_get_scanoutpos,/* called unconditionally */ 2792 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2793 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2794 }; 2795 2796 #if defined(CONFIG_DEBUG_KERNEL_DC) 2797 2798 static ssize_t s3_debug_store(struct device *device, 2799 struct device_attribute *attr, 2800 const char *buf, 2801 size_t count) 2802 { 2803 int ret; 2804 int s3_state; 2805 struct drm_device *drm_dev = dev_get_drvdata(device); 2806 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2807 struct amdgpu_ip_block *ip_block; 2808 2809 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2810 if (!ip_block) 2811 return -EINVAL; 2812 2813 ret = kstrtoint(buf, 0, &s3_state); 2814 2815 if (ret == 0) { 2816 if (s3_state) { 2817 dm_resume(ip_block); 2818 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2819 } else 2820 dm_suspend(ip_block); 2821 } 2822 2823 return ret == 0 ? count : 0; 2824 } 2825 2826 DEVICE_ATTR_WO(s3_debug); 2827 2828 #endif 2829 2830 static int dm_early_init(struct amdgpu_ip_block *ip_block) 2831 { 2832 struct amdgpu_device *adev = ip_block->adev; 2833 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2834 struct atom_context *ctx = mode_info->atom_context; 2835 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2836 u16 data_offset; 2837 2838 /* if there is no object header, skip DM */ 2839 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2840 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2841 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2842 return -ENOENT; 2843 } 2844 2845 switch (adev->asic_type) { 2846 #if defined(CONFIG_DRM_AMD_DC_SI) 2847 case CHIP_TAHITI: 2848 case CHIP_PITCAIRN: 2849 case CHIP_VERDE: 2850 adev->mode_info.num_crtc = 6; 2851 adev->mode_info.num_hpd = 6; 2852 adev->mode_info.num_dig = 6; 2853 break; 2854 case CHIP_OLAND: 2855 adev->mode_info.num_crtc = 2; 2856 adev->mode_info.num_hpd = 2; 2857 adev->mode_info.num_dig = 2; 2858 break; 2859 #endif 2860 case CHIP_BONAIRE: 2861 case CHIP_HAWAII: 2862 adev->mode_info.num_crtc = 6; 2863 adev->mode_info.num_hpd = 6; 2864 adev->mode_info.num_dig = 6; 2865 break; 2866 case CHIP_KAVERI: 2867 adev->mode_info.num_crtc = 4; 2868 adev->mode_info.num_hpd = 6; 2869 adev->mode_info.num_dig = 7; 2870 break; 2871 case CHIP_KABINI: 2872 case CHIP_MULLINS: 2873 adev->mode_info.num_crtc = 2; 2874 adev->mode_info.num_hpd = 6; 2875 adev->mode_info.num_dig = 6; 2876 break; 2877 case CHIP_FIJI: 2878 case CHIP_TONGA: 2879 adev->mode_info.num_crtc = 6; 2880 adev->mode_info.num_hpd = 6; 2881 adev->mode_info.num_dig = 7; 2882 break; 2883 case CHIP_CARRIZO: 2884 adev->mode_info.num_crtc = 3; 2885 adev->mode_info.num_hpd = 6; 2886 adev->mode_info.num_dig = 9; 2887 break; 2888 case CHIP_STONEY: 2889 adev->mode_info.num_crtc = 2; 2890 adev->mode_info.num_hpd = 6; 2891 adev->mode_info.num_dig = 9; 2892 break; 2893 case CHIP_POLARIS11: 2894 case CHIP_POLARIS12: 2895 adev->mode_info.num_crtc = 5; 2896 adev->mode_info.num_hpd = 5; 2897 adev->mode_info.num_dig = 5; 2898 break; 2899 case CHIP_POLARIS10: 2900 case CHIP_VEGAM: 2901 adev->mode_info.num_crtc = 6; 2902 adev->mode_info.num_hpd = 6; 2903 adev->mode_info.num_dig = 6; 2904 break; 2905 case CHIP_VEGA10: 2906 case CHIP_VEGA12: 2907 case CHIP_VEGA20: 2908 adev->mode_info.num_crtc = 6; 2909 adev->mode_info.num_hpd = 6; 2910 adev->mode_info.num_dig = 6; 2911 break; 2912 default: 2913 2914 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2915 case IP_VERSION(2, 0, 2): 2916 case IP_VERSION(3, 0, 0): 2917 adev->mode_info.num_crtc = 6; 2918 adev->mode_info.num_hpd = 6; 2919 adev->mode_info.num_dig = 6; 2920 break; 2921 case IP_VERSION(2, 0, 0): 2922 case IP_VERSION(3, 0, 2): 2923 adev->mode_info.num_crtc = 5; 2924 adev->mode_info.num_hpd = 5; 2925 adev->mode_info.num_dig = 5; 2926 break; 2927 case IP_VERSION(2, 0, 3): 2928 case IP_VERSION(3, 0, 3): 2929 adev->mode_info.num_crtc = 2; 2930 adev->mode_info.num_hpd = 2; 2931 adev->mode_info.num_dig = 2; 2932 break; 2933 case IP_VERSION(1, 0, 0): 2934 case IP_VERSION(1, 0, 1): 2935 case IP_VERSION(3, 0, 1): 2936 case IP_VERSION(2, 1, 0): 2937 case IP_VERSION(3, 1, 2): 2938 case IP_VERSION(3, 1, 3): 2939 case IP_VERSION(3, 1, 4): 2940 case IP_VERSION(3, 1, 5): 2941 case IP_VERSION(3, 1, 6): 2942 case IP_VERSION(3, 2, 0): 2943 case IP_VERSION(3, 2, 1): 2944 case IP_VERSION(3, 5, 0): 2945 case IP_VERSION(3, 5, 1): 2946 case IP_VERSION(3, 6, 0): 2947 case IP_VERSION(4, 0, 1): 2948 case IP_VERSION(4, 2, 0): 2949 case IP_VERSION(4, 2, 1): 2950 adev->mode_info.num_crtc = 4; 2951 adev->mode_info.num_hpd = 4; 2952 adev->mode_info.num_dig = 4; 2953 break; 2954 default: 2955 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2956 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2957 return -EINVAL; 2958 } 2959 break; 2960 } 2961 2962 if (adev->mode_info.funcs == NULL) 2963 adev->mode_info.funcs = &dm_display_funcs; 2964 2965 /* 2966 * Note: Do NOT change adev->reg.audio_endpt.rreg and 2967 * adev->reg.audio_endpt.wreg because they are initialised in 2968 * amdgpu_device_init() 2969 */ 2970 #if defined(CONFIG_DEBUG_KERNEL_DC) 2971 device_create_file( 2972 adev_to_drm(adev)->dev, 2973 &dev_attr_s3_debug); 2974 #endif 2975 adev->dc_enabled = true; 2976 2977 return dm_init_microcode(adev); 2978 } 2979 2980 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 2981 { 2982 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 2983 } 2984 EXPORT_IF_KUNIT(modereset_required); 2985 2986 STATIC_IFN_KUNIT int 2987 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 2988 const enum surface_pixel_format format, 2989 enum dc_color_space *color_space) 2990 { 2991 bool full_range; 2992 2993 *color_space = COLOR_SPACE_SRGB; 2994 2995 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 2996 if (plane_state->state && plane_state->state->plane_color_pipeline) 2997 return 0; 2998 2999 /* DRM color properties only affect non-RGB formats. */ 3000 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3001 return 0; 3002 3003 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 3004 3005 switch (plane_state->color_encoding) { 3006 case DRM_COLOR_YCBCR_BT601: 3007 if (full_range) 3008 *color_space = COLOR_SPACE_YCBCR601; 3009 else 3010 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 3011 break; 3012 3013 case DRM_COLOR_YCBCR_BT709: 3014 if (full_range) 3015 *color_space = COLOR_SPACE_YCBCR709; 3016 else 3017 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 3018 break; 3019 3020 case DRM_COLOR_YCBCR_BT2020: 3021 if (full_range) 3022 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 3023 else 3024 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 3025 break; 3026 3027 default: 3028 return -EINVAL; 3029 } 3030 3031 return 0; 3032 } 3033 EXPORT_IF_KUNIT(fill_plane_color_attributes); 3034 3035 static int 3036 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 3037 const struct drm_plane_state *plane_state, 3038 const u64 tiling_flags, 3039 struct dc_plane_info *plane_info, 3040 struct dc_plane_address *address, 3041 bool tmz_surface) 3042 { 3043 const struct drm_framebuffer *fb = plane_state->fb; 3044 const struct amdgpu_framebuffer *afb = 3045 to_amdgpu_framebuffer(plane_state->fb); 3046 int ret; 3047 3048 memset(plane_info, 0, sizeof(*plane_info)); 3049 3050 switch (fb->format->format) { 3051 case DRM_FORMAT_C8: 3052 plane_info->format = 3053 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3054 break; 3055 case DRM_FORMAT_RGB565: 3056 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3057 break; 3058 case DRM_FORMAT_XRGB8888: 3059 case DRM_FORMAT_ARGB8888: 3060 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3061 break; 3062 case DRM_FORMAT_XRGB2101010: 3063 case DRM_FORMAT_ARGB2101010: 3064 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3065 break; 3066 case DRM_FORMAT_XBGR2101010: 3067 case DRM_FORMAT_ABGR2101010: 3068 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3069 break; 3070 case DRM_FORMAT_XBGR8888: 3071 case DRM_FORMAT_ABGR8888: 3072 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3073 break; 3074 case DRM_FORMAT_NV21: 3075 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3076 break; 3077 case DRM_FORMAT_NV12: 3078 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3079 break; 3080 case DRM_FORMAT_P010: 3081 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 3082 break; 3083 case DRM_FORMAT_XRGB16161616F: 3084 case DRM_FORMAT_ARGB16161616F: 3085 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 3086 break; 3087 case DRM_FORMAT_XBGR16161616F: 3088 case DRM_FORMAT_ABGR16161616F: 3089 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 3090 break; 3091 case DRM_FORMAT_XRGB16161616: 3092 case DRM_FORMAT_ARGB16161616: 3093 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 3094 break; 3095 case DRM_FORMAT_XBGR16161616: 3096 case DRM_FORMAT_ABGR16161616: 3097 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 3098 break; 3099 default: 3100 drm_err(adev_to_drm(adev), 3101 "Unsupported screen format %p4cc\n", 3102 &fb->format->format); 3103 return -EINVAL; 3104 } 3105 3106 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3107 case DRM_MODE_ROTATE_0: 3108 plane_info->rotation = ROTATION_ANGLE_0; 3109 break; 3110 case DRM_MODE_ROTATE_90: 3111 plane_info->rotation = ROTATION_ANGLE_90; 3112 break; 3113 case DRM_MODE_ROTATE_180: 3114 plane_info->rotation = ROTATION_ANGLE_180; 3115 break; 3116 case DRM_MODE_ROTATE_270: 3117 plane_info->rotation = ROTATION_ANGLE_270; 3118 break; 3119 default: 3120 plane_info->rotation = ROTATION_ANGLE_0; 3121 break; 3122 } 3123 3124 3125 plane_info->visible = true; 3126 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3127 3128 plane_info->layer_index = plane_state->normalized_zpos; 3129 3130 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3131 &plane_info->color_space); 3132 if (ret) 3133 return ret; 3134 3135 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3136 plane_info->rotation, tiling_flags, 3137 &plane_info->tiling_info, 3138 &plane_info->plane_size, 3139 &plane_info->dcc, address, 3140 tmz_surface); 3141 if (ret) 3142 return ret; 3143 3144 amdgpu_dm_plane_fill_blending_from_plane_state( 3145 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3146 &plane_info->global_alpha, &plane_info->global_alpha_value); 3147 3148 return 0; 3149 } 3150 3151 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3152 struct dc_plane_state *dc_plane_state, 3153 struct drm_plane_state *plane_state, 3154 struct drm_crtc_state *crtc_state) 3155 { 3156 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3157 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3158 struct dc_scaling_info scaling_info; 3159 struct dc_plane_info plane_info; 3160 int ret; 3161 3162 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3163 if (ret) 3164 return ret; 3165 3166 dc_plane_state->src_rect = scaling_info.src_rect; 3167 dc_plane_state->dst_rect = scaling_info.dst_rect; 3168 dc_plane_state->clip_rect = scaling_info.clip_rect; 3169 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3170 3171 ret = fill_dc_plane_info_and_addr(adev, plane_state, 3172 afb->tiling_flags, 3173 &plane_info, 3174 &dc_plane_state->address, 3175 afb->tmz_surface); 3176 if (ret) 3177 return ret; 3178 3179 dc_plane_state->format = plane_info.format; 3180 dc_plane_state->color_space = plane_info.color_space; 3181 dc_plane_state->format = plane_info.format; 3182 dc_plane_state->plane_size = plane_info.plane_size; 3183 dc_plane_state->rotation = plane_info.rotation; 3184 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3185 dc_plane_state->stereo_format = plane_info.stereo_format; 3186 dc_plane_state->tiling_info = plane_info.tiling_info; 3187 dc_plane_state->visible = plane_info.visible; 3188 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3189 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3190 dc_plane_state->global_alpha = plane_info.global_alpha; 3191 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3192 dc_plane_state->dcc = plane_info.dcc; 3193 dc_plane_state->layer_index = plane_info.layer_index; 3194 dc_plane_state->flip_int_enabled = true; 3195 3196 /* 3197 * Always set input transfer function, since plane state is refreshed 3198 * every time. 3199 */ 3200 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3201 plane_state, 3202 dc_plane_state); 3203 if (ret) 3204 return ret; 3205 3206 return 0; 3207 } 3208 3209 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3210 struct rect *dirty_rect, int32_t x, 3211 s32 y, s32 width, s32 height, 3212 int *i, bool ffu) 3213 { 3214 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3215 3216 dirty_rect->x = x; 3217 dirty_rect->y = y; 3218 dirty_rect->width = width; 3219 dirty_rect->height = height; 3220 3221 if (ffu) 3222 drm_dbg(plane->dev, 3223 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3224 plane->base.id, width, height); 3225 else 3226 drm_dbg(plane->dev, 3227 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3228 plane->base.id, x, y, width, height); 3229 3230 (*i)++; 3231 } 3232 3233 /** 3234 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3235 * 3236 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3237 * remote fb 3238 * @old_plane_state: Old state of @plane 3239 * @new_plane_state: New state of @plane 3240 * @crtc_state: New state of CRTC connected to the @plane 3241 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3242 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3243 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3244 * that have changed will be updated. If PSR SU is not enabled, 3245 * or if damage clips are not available, the entire screen will be updated. 3246 * @dirty_regions_changed: dirty regions changed 3247 * 3248 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3249 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3250 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3251 * amdgpu_dm's. 3252 * 3253 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3254 * plane with regions that require flushing to the eDP remote buffer. In 3255 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3256 * implicitly provide damage clips without any client support via the plane 3257 * bounds. 3258 */ 3259 static void fill_dc_dirty_rects(struct drm_plane *plane, 3260 struct drm_plane_state *old_plane_state, 3261 struct drm_plane_state *new_plane_state, 3262 struct drm_crtc_state *crtc_state, 3263 struct dc_flip_addrs *flip_addrs, 3264 bool is_psr_su, 3265 bool *dirty_regions_changed) 3266 { 3267 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3268 struct rect *dirty_rects = flip_addrs->dirty_rects; 3269 u32 num_clips = 0; 3270 struct drm_mode_rect *clips = NULL; 3271 bool bb_changed; 3272 bool fb_changed; 3273 u32 i = 0; 3274 *dirty_regions_changed = false; 3275 3276 /* 3277 * Cursor plane has it's own dirty rect update interface. See 3278 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3279 */ 3280 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3281 return; 3282 3283 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3284 goto ffu; 3285 3286 if (!new_plane_state->ignore_damage_clips) { 3287 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3288 clips = drm_plane_get_damage_clips(new_plane_state); 3289 } 3290 3291 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3292 is_psr_su))) 3293 goto ffu; 3294 3295 if (!dm_crtc_state->mpo_requested) { 3296 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3297 goto ffu; 3298 3299 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3300 fill_dc_dirty_rect(new_plane_state->plane, 3301 &dirty_rects[flip_addrs->dirty_rect_count], 3302 clips->x1, clips->y1, 3303 clips->x2 - clips->x1, clips->y2 - clips->y1, 3304 &flip_addrs->dirty_rect_count, 3305 false); 3306 return; 3307 } 3308 3309 /* 3310 * MPO is requested. Add entire plane bounding box to dirty rects if 3311 * flipped to or damaged. 3312 * 3313 * If plane is moved or resized, also add old bounding box to dirty 3314 * rects. 3315 */ 3316 fb_changed = old_plane_state->fb->base.id != 3317 new_plane_state->fb->base.id; 3318 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3319 old_plane_state->crtc_y != new_plane_state->crtc_y || 3320 old_plane_state->crtc_w != new_plane_state->crtc_w || 3321 old_plane_state->crtc_h != new_plane_state->crtc_h); 3322 3323 drm_dbg(plane->dev, 3324 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3325 new_plane_state->plane->base.id, 3326 bb_changed, fb_changed, num_clips); 3327 3328 *dirty_regions_changed = bb_changed; 3329 3330 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3331 goto ffu; 3332 3333 if (bb_changed) { 3334 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3335 new_plane_state->crtc_x, 3336 new_plane_state->crtc_y, 3337 new_plane_state->crtc_w, 3338 new_plane_state->crtc_h, &i, false); 3339 3340 /* Add old plane bounding-box if plane is moved or resized */ 3341 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3342 old_plane_state->crtc_x, 3343 old_plane_state->crtc_y, 3344 old_plane_state->crtc_w, 3345 old_plane_state->crtc_h, &i, false); 3346 } 3347 3348 if (num_clips) { 3349 for (; i < num_clips; clips++) 3350 fill_dc_dirty_rect(new_plane_state->plane, 3351 &dirty_rects[i], clips->x1, 3352 clips->y1, clips->x2 - clips->x1, 3353 clips->y2 - clips->y1, &i, false); 3354 } else if (fb_changed && !bb_changed) { 3355 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3356 new_plane_state->crtc_x, 3357 new_plane_state->crtc_y, 3358 new_plane_state->crtc_w, 3359 new_plane_state->crtc_h, &i, false); 3360 } 3361 3362 flip_addrs->dirty_rect_count = i; 3363 return; 3364 3365 ffu: 3366 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3367 dm_crtc_state->base.mode.crtc_hdisplay, 3368 dm_crtc_state->base.mode.crtc_vdisplay, 3369 &flip_addrs->dirty_rect_count, true); 3370 } 3371 3372 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 3373 const struct drm_display_mode *mode, 3374 const struct dm_connector_state *dm_state, 3375 struct dc_stream_state *stream) 3376 { 3377 enum amdgpu_rmx_type rmx_type; 3378 3379 struct rect src = { 0 }; /* viewport in composition space*/ 3380 struct rect dst = { 0 }; /* stream addressable area */ 3381 3382 /* no mode. nothing to be done */ 3383 if (!mode) 3384 return; 3385 3386 /* Full screen scaling by default */ 3387 src.width = mode->hdisplay; 3388 src.height = mode->vdisplay; 3389 dst.width = stream->timing.h_addressable; 3390 dst.height = stream->timing.v_addressable; 3391 3392 if (dm_state) { 3393 rmx_type = dm_state->scaling; 3394 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3395 if (src.width * dst.height < 3396 src.height * dst.width) { 3397 /* height needs less upscaling/more downscaling */ 3398 dst.width = src.width * 3399 dst.height / src.height; 3400 } else { 3401 /* width needs less upscaling/more downscaling */ 3402 dst.height = src.height * 3403 dst.width / src.width; 3404 } 3405 } else if (rmx_type == RMX_CENTER) { 3406 dst = src; 3407 } 3408 3409 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3410 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3411 3412 if (dm_state->underscan_enable) { 3413 dst.x += dm_state->underscan_hborder / 2; 3414 dst.y += dm_state->underscan_vborder / 2; 3415 dst.width -= dm_state->underscan_hborder; 3416 dst.height -= dm_state->underscan_vborder; 3417 } 3418 } 3419 3420 stream->src = src; 3421 stream->dst = dst; 3422 3423 drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 3424 dst.x, dst.y, dst.width, dst.height); 3425 3426 } 3427 3428 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3429 struct dc_state *dc_state, 3430 struct dsc_mst_fairness_vars *vars) 3431 { 3432 struct dc_stream_state *stream = NULL; 3433 struct drm_connector *connector; 3434 struct drm_connector_state *new_con_state; 3435 struct amdgpu_dm_connector *aconnector; 3436 struct dm_connector_state *dm_conn_state; 3437 int i, j, ret; 3438 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3439 3440 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3441 3442 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3443 continue; 3444 3445 aconnector = to_amdgpu_dm_connector(connector); 3446 3447 if (!aconnector->mst_output_port) 3448 continue; 3449 3450 if (!new_con_state || !new_con_state->crtc) 3451 continue; 3452 3453 dm_conn_state = to_dm_connector_state(new_con_state); 3454 3455 for (j = 0; j < dc_state->stream_count; j++) { 3456 stream = dc_state->streams[j]; 3457 if (!stream) 3458 continue; 3459 3460 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3461 break; 3462 3463 stream = NULL; 3464 } 3465 3466 if (!stream) 3467 continue; 3468 3469 pbn_div = dm_mst_get_pbn_divider(stream->link); 3470 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3471 for (j = 0; j < dc_state->stream_count; j++) { 3472 if (vars[j].aconnector == aconnector) { 3473 pbn = vars[j].pbn; 3474 break; 3475 } 3476 } 3477 3478 if (j == dc_state->stream_count || pbn_div == 0) 3479 continue; 3480 3481 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3482 3483 if (stream->timing.flags.DSC != 1) { 3484 dm_conn_state->pbn = pbn; 3485 dm_conn_state->vcpi_slots = slot_num; 3486 3487 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3488 dm_conn_state->pbn, false); 3489 if (ret < 0) 3490 return ret; 3491 3492 continue; 3493 } 3494 3495 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3496 if (vcpi < 0) 3497 return vcpi; 3498 3499 dm_conn_state->pbn = pbn; 3500 dm_conn_state->vcpi_slots = vcpi; 3501 } 3502 return 0; 3503 } 3504 3505 static void manage_dm_interrupts(struct amdgpu_device *adev, 3506 struct amdgpu_crtc *acrtc, 3507 struct dm_crtc_state *acrtc_state) 3508 { /* 3509 * We cannot be sure that the frontend index maps to the same 3510 * backend index - some even map to more than one. 3511 * So we have to go through the CRTC to find the right IRQ. 3512 */ 3513 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3514 adev, 3515 acrtc->crtc_id); 3516 struct drm_device *dev = adev_to_drm(adev); 3517 3518 struct drm_vblank_crtc_config config = {0}; 3519 struct dc_crtc_timing *timing; 3520 int offdelay; 3521 3522 if (acrtc_state) { 3523 timing = &acrtc_state->stream->timing; 3524 3525 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= 3526 IP_VERSION(3, 2, 0) && 3527 !(adev->flags & AMD_IS_APU)) { 3528 /* 3529 * DGPUs NV3x and newer that support idle optimizations 3530 * experience intermittent flip-done timeouts on cursor 3531 * updates. Restore 5s offdelay behavior for now. 3532 * 3533 * Discussion on the issue: 3534 * https://lore.kernel.org/amd-gfx/20260217191632.1243826-1-sysdadmin@m1k.cloud/ 3535 */ 3536 config.offdelay_ms = 5000; 3537 config.disable_immediate = false; 3538 } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3539 IP_VERSION(3, 5, 0)) { 3540 /* 3541 * Older HW and DGPU have issues with instant off; 3542 * use a 2 frame offdelay. 3543 */ 3544 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3545 timing->v_total * 3546 timing->h_total, 3547 timing->pix_clk_100hz); 3548 3549 config.offdelay_ms = offdelay ?: 30; 3550 } else { 3551 /* offdelay_ms = 0 will never disable vblank */ 3552 config.offdelay_ms = 1; 3553 config.disable_immediate = true; 3554 } 3555 3556 drm_crtc_vblank_on_config(&acrtc->base, 3557 &config); 3558 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_get.*/ 3559 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3560 case IP_VERSION(3, 0, 0): 3561 case IP_VERSION(3, 0, 2): 3562 case IP_VERSION(3, 0, 3): 3563 case IP_VERSION(3, 2, 0): 3564 if (amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type)) 3565 drm_err(dev, "DM_IRQ: Cannot get pageflip irq!\n"); 3566 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3567 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3568 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3569 #endif 3570 } 3571 3572 } else { 3573 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3574 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3575 case IP_VERSION(3, 0, 0): 3576 case IP_VERSION(3, 0, 2): 3577 case IP_VERSION(3, 0, 3): 3578 case IP_VERSION(3, 2, 0): 3579 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3580 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3581 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3582 #endif 3583 if (amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type)) 3584 drm_err(dev, "DM_IRQ: Cannot put pageflip irq!\n"); 3585 } 3586 3587 drm_crtc_vblank_off(&acrtc->base); 3588 } 3589 } 3590 3591 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3592 struct amdgpu_crtc *acrtc) 3593 { 3594 int irq_type = 3595 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3596 3597 /** 3598 * This reads the current state for the IRQ and force reapplies 3599 * the setting to hardware. 3600 */ 3601 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3602 } 3603 3604 STATIC_IFN_KUNIT bool 3605 is_scaling_state_different(const struct dm_connector_state *dm_state, 3606 const struct dm_connector_state *old_dm_state) 3607 { 3608 if (dm_state->scaling != old_dm_state->scaling) 3609 return true; 3610 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3611 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3612 return true; 3613 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3614 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3615 return true; 3616 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3617 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3618 return true; 3619 return false; 3620 } 3621 EXPORT_IF_KUNIT(is_scaling_state_different); 3622 3623 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3624 struct drm_crtc_state *old_crtc_state, 3625 struct drm_connector_state *new_conn_state, 3626 struct drm_connector_state *old_conn_state, 3627 const struct drm_connector *connector, 3628 struct hdcp_workqueue *hdcp_w) 3629 { 3630 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3631 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3632 3633 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3634 connector->index, connector->status, connector->dpms); 3635 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3636 old_conn_state->content_protection, new_conn_state->content_protection); 3637 3638 if (old_crtc_state) 3639 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3640 old_crtc_state->enable, 3641 old_crtc_state->active, 3642 old_crtc_state->mode_changed, 3643 old_crtc_state->active_changed, 3644 old_crtc_state->connectors_changed); 3645 3646 if (new_crtc_state) 3647 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3648 new_crtc_state->enable, 3649 new_crtc_state->active, 3650 new_crtc_state->mode_changed, 3651 new_crtc_state->active_changed, 3652 new_crtc_state->connectors_changed); 3653 3654 /* hdcp content type change */ 3655 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3656 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3657 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3658 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3659 return true; 3660 } 3661 3662 /* CP is being re enabled, ignore this */ 3663 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3664 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3665 if (new_crtc_state && new_crtc_state->mode_changed) { 3666 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3667 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3668 return true; 3669 } 3670 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3671 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3672 return false; 3673 } 3674 3675 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3676 * 3677 * Handles: UNDESIRED -> ENABLED 3678 */ 3679 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3680 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3681 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3682 3683 /* Stream removed and re-enabled 3684 * 3685 * Can sometimes overlap with the HPD case, 3686 * thus set update_hdcp to false to avoid 3687 * setting HDCP multiple times. 3688 * 3689 * Handles: DESIRED -> DESIRED (Special case) 3690 */ 3691 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3692 new_conn_state->crtc && new_conn_state->crtc->enabled && 3693 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3694 dm_con_state->update_hdcp = false; 3695 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3696 __func__); 3697 return true; 3698 } 3699 3700 /* Hot-plug, headless s3, dpms 3701 * 3702 * Only start HDCP if the display is connected/enabled. 3703 * update_hdcp flag will be set to false until the next 3704 * HPD comes in. 3705 * 3706 * Handles: DESIRED -> DESIRED (Special case) 3707 */ 3708 if (dm_con_state->update_hdcp && 3709 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3710 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3711 dm_con_state->update_hdcp = false; 3712 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3713 __func__); 3714 return true; 3715 } 3716 3717 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3718 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3719 if (new_crtc_state && new_crtc_state->mode_changed) { 3720 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3721 __func__); 3722 return true; 3723 } 3724 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3725 __func__); 3726 return false; 3727 } 3728 3729 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3730 return false; 3731 } 3732 3733 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3734 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3735 __func__); 3736 return true; 3737 } 3738 3739 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3740 return false; 3741 } 3742 3743 static void remove_stream(struct amdgpu_device *adev, 3744 struct amdgpu_crtc *acrtc, 3745 struct dc_stream_state *stream) 3746 { 3747 /* this is the update mode case */ 3748 3749 acrtc->otg_inst = -1; 3750 acrtc->enabled = false; 3751 } 3752 3753 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 3754 { 3755 3756 assert_spin_locked(&acrtc->base.dev->event_lock); 3757 WARN_ON(acrtc->event); 3758 3759 acrtc->event = acrtc->base.state->event; 3760 3761 /* Set the flip status */ 3762 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3763 3764 /* Mark this event as consumed */ 3765 acrtc->base.state->event = NULL; 3766 3767 drm_dbg_state(acrtc->base.dev, 3768 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3769 acrtc->crtc_id); 3770 } 3771 3772 static void update_freesync_state_on_stream( 3773 struct amdgpu_display_manager *dm, 3774 struct dm_crtc_state *new_crtc_state, 3775 struct dc_stream_state *new_stream, 3776 struct dc_plane_state *surface, 3777 u32 flip_timestamp_in_us) 3778 { 3779 struct mod_vrr_params vrr_params; 3780 struct dc_info_packet vrr_infopacket = {0}; 3781 struct amdgpu_device *adev = dm->adev; 3782 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3783 unsigned long flags; 3784 bool pack_sdp_v1_3 = false; 3785 struct amdgpu_dm_connector *aconn; 3786 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 3787 3788 if (!new_stream) 3789 return; 3790 3791 /* 3792 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3793 * For now it's sufficient to just guard against these conditions. 3794 */ 3795 3796 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3797 return; 3798 3799 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3800 vrr_params = acrtc->dm_irq_params.vrr_params; 3801 3802 if (surface) { 3803 mod_freesync_handle_preflip( 3804 dm->freesync_module, 3805 surface, 3806 new_stream, 3807 flip_timestamp_in_us, 3808 &vrr_params); 3809 3810 if (adev->family < AMDGPU_FAMILY_AI && 3811 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 3812 mod_freesync_handle_v_update(dm->freesync_module, 3813 new_stream, &vrr_params); 3814 3815 /* Need to call this before the frame ends. */ 3816 dc_stream_adjust_vmin_vmax(dm->dc, 3817 new_crtc_state->stream, 3818 &vrr_params.adjust); 3819 } 3820 } 3821 3822 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 3823 3824 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 3825 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 3826 3827 if (aconn->vsdb_info.amd_vsdb_version == 1) 3828 packet_type = PACKET_TYPE_FS_V1; 3829 else if (aconn->vsdb_info.amd_vsdb_version == 2) 3830 packet_type = PACKET_TYPE_FS_V2; 3831 else if (aconn->vsdb_info.amd_vsdb_version == 3) 3832 packet_type = PACKET_TYPE_FS_V3; 3833 3834 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 3835 &new_stream->adaptive_sync_infopacket); 3836 } 3837 3838 mod_freesync_build_vrr_infopacket( 3839 dm->freesync_module, 3840 new_stream, 3841 &vrr_params, 3842 packet_type, 3843 TRANSFER_FUNC_UNKNOWN, 3844 &vrr_infopacket, 3845 pack_sdp_v1_3); 3846 3847 new_crtc_state->freesync_vrr_info_changed |= 3848 (memcmp(&new_crtc_state->vrr_infopacket, 3849 &vrr_infopacket, 3850 sizeof(vrr_infopacket)) != 0); 3851 3852 acrtc->dm_irq_params.vrr_params = vrr_params; 3853 new_crtc_state->vrr_infopacket = vrr_infopacket; 3854 3855 new_stream->vrr_infopacket = vrr_infopacket; 3856 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 3857 3858 if (new_crtc_state->freesync_vrr_info_changed) 3859 drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", 3860 new_crtc_state->base.crtc->base.id, 3861 (int)new_crtc_state->base.vrr_enabled, 3862 (int)vrr_params.state); 3863 3864 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3865 } 3866 3867 static void update_stream_irq_parameters( 3868 struct amdgpu_display_manager *dm, 3869 struct dm_crtc_state *new_crtc_state) 3870 { 3871 struct dc_stream_state *new_stream = new_crtc_state->stream; 3872 struct mod_vrr_params vrr_params; 3873 struct mod_freesync_config config = new_crtc_state->freesync_config; 3874 struct amdgpu_device *adev = dm->adev; 3875 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3876 unsigned long flags; 3877 3878 if (!new_stream) 3879 return; 3880 3881 /* 3882 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3883 * For now it's sufficient to just guard against these conditions. 3884 */ 3885 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3886 return; 3887 3888 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3889 vrr_params = acrtc->dm_irq_params.vrr_params; 3890 3891 if (new_crtc_state->vrr_supported && 3892 config.min_refresh_in_uhz && 3893 config.max_refresh_in_uhz) { 3894 /* 3895 * if freesync compatible mode was set, config.state will be set 3896 * in atomic check 3897 */ 3898 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 3899 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 3900 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 3901 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 3902 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 3903 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 3904 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 3905 } else { 3906 config.state = new_crtc_state->base.vrr_enabled ? 3907 VRR_STATE_ACTIVE_VARIABLE : 3908 VRR_STATE_INACTIVE; 3909 } 3910 } else { 3911 config.state = VRR_STATE_UNSUPPORTED; 3912 } 3913 3914 mod_freesync_build_vrr_params(dm->freesync_module, 3915 new_stream, 3916 &config, &vrr_params); 3917 3918 new_crtc_state->freesync_config = config; 3919 /* Copy state for access from DM IRQ handler */ 3920 acrtc->dm_irq_params.freesync_config = config; 3921 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 3922 acrtc->dm_irq_params.vrr_params = vrr_params; 3923 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3924 } 3925 3926 static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, 3927 struct dm_crtc_state *old_state, 3928 struct dm_crtc_state *new_state) 3929 { 3930 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 3931 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 3932 3933 if (!old_vrr_active && new_vrr_active) { 3934 /* Transition VRR inactive -> active: 3935 * While VRR is active, we must not disable vblank irq, as a 3936 * reenable after disable would compute bogus vblank/pflip 3937 * timestamps if it likely happened inside display front-porch. 3938 * 3939 * We also need vupdate irq for the actual core vblank handling 3940 * at end of vblank. 3941 */ 3942 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 3943 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 3944 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", 3945 __func__, new_state->base.crtc->base.id); 3946 3947 scoped_guard(mutex, &dm->dc_lock) { 3948 dc_exit_ips_for_hw_access(dm->dc); 3949 amdgpu_dm_psr_set_event(dm, new_state->stream, true, 3950 psr_event_vrr_transition, true); 3951 amdgpu_dm_replay_set_event(dm, new_state->stream, true, 3952 replay_event_vrr, true); 3953 } 3954 } else if (old_vrr_active && !new_vrr_active) { 3955 /* Transition VRR active -> inactive: 3956 * Allow vblank irq disable again for fixed refresh rate. 3957 */ 3958 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 3959 drm_crtc_vblank_put(new_state->base.crtc); 3960 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", 3961 __func__, new_state->base.crtc->base.id); 3962 3963 scoped_guard(mutex, &dm->dc_lock) { 3964 dc_exit_ips_for_hw_access(dm->dc); 3965 amdgpu_dm_psr_set_event(dm, new_state->stream, false, 3966 psr_event_vrr_transition, false); 3967 amdgpu_dm_replay_set_event(dm, new_state->stream, false, 3968 replay_event_vrr, false); 3969 } 3970 } 3971 } 3972 3973 static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 3974 { 3975 struct drm_plane *plane; 3976 struct drm_plane_state *old_plane_state; 3977 int i; 3978 3979 /* 3980 * TODO: Make this per-stream so we don't issue redundant updates for 3981 * commits with multiple streams. 3982 */ 3983 for_each_old_plane_in_state(state, plane, old_plane_state, i) 3984 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3985 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 3986 } 3987 3988 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 3989 { 3990 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 3991 3992 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 3993 } 3994 3995 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 3996 struct drm_plane_state *old_plane_state, 3997 struct dc_stream_update *update) 3998 { 3999 struct amdgpu_device *adev = drm_to_adev(plane->dev); 4000 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4001 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4002 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4003 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4004 uint64_t address = afb ? afb->address : 0; 4005 struct dc_cursor_position position = {0}; 4006 struct dc_cursor_attributes attributes; 4007 int ret; 4008 4009 if (!plane->state->fb && !old_plane_state->fb) 4010 return; 4011 4012 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 4013 amdgpu_crtc->crtc_id, plane->state->crtc_w, 4014 plane->state->crtc_h); 4015 4016 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 4017 if (ret) 4018 return; 4019 4020 if (!position.enable) { 4021 /* turn off cursor */ 4022 if (crtc_state && crtc_state->stream) { 4023 dc_stream_set_cursor_position(crtc_state->stream, 4024 &position); 4025 update->cursor_position = &crtc_state->stream->cursor_position; 4026 } 4027 return; 4028 } 4029 4030 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4031 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4032 4033 memset(&attributes, 0, sizeof(attributes)); 4034 attributes.address.high_part = upper_32_bits(address); 4035 attributes.address.low_part = lower_32_bits(address); 4036 attributes.width = plane->state->crtc_w; 4037 attributes.height = plane->state->crtc_h; 4038 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4039 attributes.rotation_angle = 0; 4040 attributes.attribute_flags.value = 0; 4041 4042 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 4043 * legacy gamma setup. 4044 */ 4045 if (crtc_state->cm_is_degamma_srgb && 4046 adev->dm.dc->caps.color.dpp.gamma_corr) 4047 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 4048 4049 if (afb) 4050 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 4051 4052 if (crtc_state->stream) { 4053 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4054 &attributes)) 4055 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 4056 4057 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 4058 4059 if (!dc_stream_set_cursor_position(crtc_state->stream, 4060 &position)) 4061 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 4062 4063 update->cursor_position = &crtc_state->stream->cursor_position; 4064 } 4065 } 4066 4067 static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 4068 struct amdgpu_crtc *acrtc_attach, 4069 const struct dm_crtc_state *acrtc_state, 4070 const u64 current_ts) 4071 { 4072 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 4073 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 4074 struct amdgpu_dm_connector *aconn = 4075 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 4076 4077 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 4078 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 4079 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 4080 if (aconn->sr_skip_count > 0) 4081 aconn->sr_skip_count--; 4082 4083 /* Allow SR when skip count is 0. */ 4084 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 4085 4086 /* 4087 * If sink supports PSR SU/Panel Replay, there is no need to rely on 4088 * a vblank event disable request to enable PSR/RP. PSR SU/RP 4089 * can be enabled immediately once OS demonstrates an 4090 * adequate number of fast atomic commits to notify KMD 4091 * of update events. 4092 * See `amdgpu_dm_crtc_vblank_control_worker()`. 4093 */ 4094 if (acrtc_attach->dm_irq_params.allow_sr_entry && 4095 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 4096 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 4097 psr_event_hw_programming, false); 4098 4099 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 4100 replay_event_hw_programming, false); 4101 } 4102 } else { 4103 acrtc_attach->dm_irq_params.allow_sr_entry = false; 4104 } 4105 } 4106 4107 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 4108 struct drm_device *dev, 4109 struct amdgpu_display_manager *dm, 4110 struct drm_crtc *pcrtc, 4111 bool wait_for_vblank) 4112 { 4113 u32 i; 4114 u64 timestamp_ns = ktime_get_ns(); 4115 struct drm_plane *plane; 4116 struct drm_plane_state *old_plane_state, *new_plane_state; 4117 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4118 struct drm_crtc_state *new_pcrtc_state = 4119 drm_atomic_get_new_crtc_state(state, pcrtc); 4120 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4121 struct dm_crtc_state *dm_old_crtc_state = 4122 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4123 int planes_count = 0, vpos, hpos; 4124 unsigned long flags; 4125 u32 target_vblank, last_flip_vblank; 4126 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 4127 bool cursor_update = false; 4128 bool pflip_present = false; 4129 bool dirty_rects_changed = false; 4130 bool updated_planes_and_streams = false; 4131 struct { 4132 struct dc_surface_update surface_updates[MAX_SURFACES]; 4133 struct dc_plane_info plane_infos[MAX_SURFACES]; 4134 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 4135 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 4136 struct dc_stream_update stream_update; 4137 } *bundle; 4138 4139 bundle = kzalloc_obj(*bundle); 4140 4141 if (!bundle) { 4142 drm_err(dev, "Failed to allocate update bundle\n"); 4143 goto cleanup; 4144 } 4145 4146 /* 4147 * Disable the cursor first if we're disabling all the planes. 4148 * It'll remain on the screen after the planes are re-enabled 4149 * if we don't. 4150 * 4151 * If the cursor is transitioning from native to overlay mode, the 4152 * native cursor needs to be disabled first. 4153 */ 4154 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 4155 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4156 struct dc_cursor_position cursor_position = {0}; 4157 4158 if (!dc_stream_set_cursor_position(acrtc_state->stream, 4159 &cursor_position)) 4160 drm_err(dev, "DC failed to disable native cursor\n"); 4161 4162 bundle->stream_update.cursor_position = 4163 &acrtc_state->stream->cursor_position; 4164 } 4165 4166 if (acrtc_state->active_planes == 0 && 4167 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4168 amdgpu_dm_commit_cursors(state); 4169 4170 /* update planes when needed */ 4171 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4172 struct drm_crtc *crtc = new_plane_state->crtc; 4173 struct drm_crtc_state *new_crtc_state; 4174 struct drm_framebuffer *fb = new_plane_state->fb; 4175 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 4176 bool plane_needs_flip; 4177 struct dc_plane_state *dc_plane; 4178 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4179 4180 /* Cursor plane is handled after stream updates */ 4181 if (plane->type == DRM_PLANE_TYPE_CURSOR && 4182 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4183 if ((fb && crtc == pcrtc) || 4184 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 4185 cursor_update = true; 4186 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 4187 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 4188 } 4189 4190 continue; 4191 } 4192 4193 if (!fb || !crtc || pcrtc != crtc) 4194 continue; 4195 4196 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4197 if (!new_crtc_state->active) 4198 continue; 4199 4200 dc_plane = dm_new_plane_state->dc_state; 4201 if (!dc_plane) 4202 continue; 4203 4204 bundle->surface_updates[planes_count].surface = dc_plane; 4205 if (new_pcrtc_state->color_mgmt_changed) { 4206 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 4207 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 4208 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 4209 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 4210 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 4211 } 4212 4213 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 4214 &bundle->scaling_infos[planes_count]); 4215 4216 bundle->surface_updates[planes_count].scaling_info = 4217 &bundle->scaling_infos[planes_count]; 4218 4219 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 4220 4221 pflip_present = pflip_present || plane_needs_flip; 4222 4223 if (!plane_needs_flip) { 4224 planes_count += 1; 4225 continue; 4226 } 4227 4228 fill_dc_plane_info_and_addr( 4229 dm->adev, new_plane_state, 4230 afb->tiling_flags, 4231 &bundle->plane_infos[planes_count], 4232 &bundle->flip_addrs[planes_count].address, 4233 afb->tmz_surface); 4234 4235 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 4236 new_plane_state->plane->index, 4237 bundle->plane_infos[planes_count].dcc.enable); 4238 4239 bundle->surface_updates[planes_count].plane_info = 4240 &bundle->plane_infos[planes_count]; 4241 4242 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 4243 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 4244 fill_dc_dirty_rects(plane, old_plane_state, 4245 new_plane_state, new_crtc_state, 4246 &bundle->flip_addrs[planes_count], 4247 acrtc_state->stream->link->psr_settings.psr_version == 4248 DC_PSR_VERSION_SU_1, 4249 &dirty_rects_changed); 4250 4251 /* 4252 * If the dirty regions changed, PSR-SU need to be disabled temporarily 4253 * and enabled it again after dirty regions are stable to avoid video glitch. 4254 * PSR-SU will be enabled in 4255 * amdgpu_dm_crtc_vblank_control_worker() if user 4256 * pause the video during the PSR-SU was disabled. 4257 */ 4258 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 4259 acrtc_attach->dm_irq_params.allow_sr_entry && 4260 dirty_rects_changed) { 4261 mutex_lock(&dm->dc_lock); 4262 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 4263 timestamp_ns; 4264 dc_exit_ips_for_hw_access(dm->dc); 4265 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 4266 psr_event_hw_programming, true); 4267 mutex_unlock(&dm->dc_lock); 4268 } 4269 } 4270 4271 /* 4272 * Only allow immediate flips for fast updates that don't 4273 * change memory domain, FB pitch, DCC state, rotation or 4274 * mirroring. 4275 * 4276 * dm_crtc_helper_atomic_check() only accepts async flips with 4277 * fast updates. 4278 */ 4279 if (crtc->state->async_flip && 4280 (acrtc_state->update_type != UPDATE_TYPE_FAST || 4281 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 4282 drm_warn_once(state->dev, 4283 "[PLANE:%d:%s] async flip with non-fast update\n", 4284 plane->base.id, plane->name); 4285 4286 bundle->flip_addrs[planes_count].flip_immediate = 4287 crtc->state->async_flip && 4288 acrtc_state->update_type == UPDATE_TYPE_FAST && 4289 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 4290 4291 timestamp_ns = ktime_get_ns(); 4292 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 4293 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 4294 bundle->surface_updates[planes_count].surface = dc_plane; 4295 4296 if (!bundle->surface_updates[planes_count].surface) { 4297 drm_err(dev, "No surface for CRTC: id=%d\n", 4298 acrtc_attach->crtc_id); 4299 continue; 4300 } 4301 4302 if (plane == pcrtc->primary) 4303 update_freesync_state_on_stream( 4304 dm, 4305 acrtc_state, 4306 acrtc_state->stream, 4307 dc_plane, 4308 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 4309 4310 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 4311 __func__, 4312 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4313 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4314 4315 planes_count += 1; 4316 4317 } 4318 4319 if (pflip_present) { 4320 if (!vrr_active) { 4321 /* Use old throttling in non-vrr fixed refresh rate mode 4322 * to keep flip scheduling based on target vblank counts 4323 * working in a backwards compatible way, e.g., for 4324 * clients using the GLX_OML_sync_control extension or 4325 * DRI3/Present extension with defined target_msc. 4326 */ 4327 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 4328 } else { 4329 /* For variable refresh rate mode only: 4330 * Get vblank of last completed flip to avoid > 1 vrr 4331 * flips per video frame by use of throttling, but allow 4332 * flip programming anywhere in the possibly large 4333 * variable vrr vblank interval for fine-grained flip 4334 * timing control and more opportunity to avoid stutter 4335 * on late submission of flips. 4336 */ 4337 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4338 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4339 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4340 } 4341 4342 target_vblank = last_flip_vblank + wait_for_vblank; 4343 4344 /* 4345 * Wait until we're out of the vertical blank period before the one 4346 * targeted by the flip 4347 */ 4348 while ((acrtc_attach->enabled && 4349 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4350 0, &vpos, &hpos, NULL, 4351 NULL, &pcrtc->hwmode) 4352 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4353 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4354 (int)(target_vblank - 4355 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4356 usleep_range(1000, 1100); 4357 } 4358 4359 /** 4360 * Prepare the flip event for the pageflip interrupt to handle. 4361 * 4362 * This only works in the case where we've already turned on the 4363 * appropriate hardware blocks (eg. HUBP) so in the transition case 4364 * from 0 -> n planes we have to skip a hardware generated event 4365 * and rely on sending it from software. 4366 */ 4367 if (acrtc_attach->base.state->event && 4368 acrtc_state->active_planes > 0) { 4369 drm_crtc_vblank_get(pcrtc); 4370 4371 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4372 4373 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 4374 prepare_flip_isr(acrtc_attach); 4375 4376 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4377 } 4378 4379 if (acrtc_state->stream) { 4380 if (acrtc_state->freesync_vrr_info_changed) 4381 bundle->stream_update.vrr_infopacket = 4382 &acrtc_state->stream->vrr_infopacket; 4383 } 4384 } else if (cursor_update && acrtc_state->active_planes > 0) { 4385 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4386 if (acrtc_attach->base.state->event) { 4387 drm_crtc_vblank_get(pcrtc); 4388 acrtc_attach->event = acrtc_attach->base.state->event; 4389 acrtc_attach->base.state->event = NULL; 4390 } 4391 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4392 } 4393 4394 /* Update the planes if changed or disable if we don't have any. */ 4395 if ((planes_count || acrtc_state->active_planes == 0) && 4396 acrtc_state->stream) { 4397 /* 4398 * If PSR or idle optimizations are enabled then flush out 4399 * any pending work before hardware programming. 4400 */ 4401 if (dm->vblank_control_workqueue) 4402 flush_workqueue(dm->vblank_control_workqueue); 4403 4404 bundle->stream_update.stream = acrtc_state->stream; 4405 if (new_pcrtc_state->mode_changed) { 4406 bundle->stream_update.src = acrtc_state->stream->src; 4407 bundle->stream_update.dst = acrtc_state->stream->dst; 4408 } 4409 4410 if (new_pcrtc_state->color_mgmt_changed) { 4411 /* 4412 * TODO: This isn't fully correct since we've actually 4413 * already modified the stream in place. 4414 */ 4415 bundle->stream_update.gamut_remap = 4416 &acrtc_state->stream->gamut_remap_matrix; 4417 bundle->stream_update.output_csc_transform = 4418 &acrtc_state->stream->csc_color_matrix; 4419 bundle->stream_update.out_transfer_func = 4420 &acrtc_state->stream->out_transfer_func; 4421 bundle->stream_update.lut3d_func = 4422 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4423 bundle->stream_update.func_shaper = 4424 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4425 } 4426 4427 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4428 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4429 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4430 4431 /* 4432 * If FreeSync state on the stream has changed then we need to 4433 * re-adjust the min/max bounds now that DC doesn't handle this 4434 * as part of commit. 4435 */ 4436 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4437 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4438 dc_stream_adjust_vmin_vmax( 4439 dm->dc, acrtc_state->stream, 4440 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4441 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4442 } 4443 mutex_lock(&dm->dc_lock); 4444 update_planes_and_stream_adapter(dm->dc, 4445 acrtc_state->update_type, 4446 planes_count, 4447 acrtc_state->stream, 4448 &bundle->stream_update, 4449 bundle->surface_updates); 4450 updated_planes_and_streams = true; 4451 4452 /** 4453 * Enable or disable the interrupts on the backend. 4454 * 4455 * Most pipes are put into power gating when unused. 4456 * 4457 * When power gating is enabled on a pipe we lose the 4458 * interrupt enablement state when power gating is disabled. 4459 * 4460 * So we need to update the IRQ control state in hardware 4461 * whenever the pipe turns on (since it could be previously 4462 * power gated) or off (since some pipes can't be power gated 4463 * on some ASICs). 4464 */ 4465 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4466 dm_update_pflip_irq_state(drm_to_adev(dev), 4467 acrtc_attach); 4468 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4469 timestamp_ns); 4470 mutex_unlock(&dm->dc_lock); 4471 } 4472 4473 /* 4474 * Update cursor state *after* programming all the planes. 4475 * This avoids redundant programming in the case where we're going 4476 * to be disabling a single plane - those pipes are being disabled. 4477 */ 4478 if (acrtc_state->active_planes && 4479 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4480 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4481 amdgpu_dm_commit_cursors(state); 4482 4483 cleanup: 4484 kfree(bundle); 4485 } 4486 4487 /* 4488 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4489 * @crtc_state: the DRM CRTC state 4490 * @stream_state: the DC stream state. 4491 * 4492 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4493 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4494 */ 4495 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4496 struct dc_stream_state *stream_state) 4497 { 4498 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4499 } 4500 4501 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 4502 struct dm_crtc_state *crtc_state) 4503 { 4504 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4505 } 4506 4507 /** 4508 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4509 * @state: the drm atomic state 4510 * @dm: the display manager to update mod_power on 4511 * 4512 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4513 * in preparation for hardware programming. See also 4514 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4515 */ 4516 static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4517 struct amdgpu_display_manager *dm) 4518 { 4519 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4520 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4521 struct amdgpu_dm_connector *aconnector; 4522 struct drm_crtc *crtc; 4523 int i = 0; 4524 4525 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4526 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4527 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4528 4529 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4530 continue; 4531 4532 /* 4533 * Update mod_power on modeset event in preparation for hw 4534 * programming. Always use the old stream, since it would have 4535 * been previously added to mod_power. If old stream is null (on 4536 * crtc enable, for example), mod_power will no-op, which is the 4537 * desried behavior. 4538 */ 4539 if (old_crtc_state->active) { 4540 scoped_guard(mutex, &dm->dc_lock) { 4541 dc_exit_ips_for_hw_access(dm->dc); 4542 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4543 psr_event_hw_programming, true); 4544 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4545 replay_event_hw_programming, true); 4546 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4547 replay_event_general_ui, false); 4548 } 4549 } 4550 4551 if (new_crtc_state->active) { 4552 aconnector = (struct amdgpu_dm_connector *) 4553 dm_new_crtc_state->stream->dm_stream_context; 4554 if (old_crtc_state->active) { 4555 mod_power_replace_stream(dm->power_module, 4556 dm_old_crtc_state->stream, 4557 dm_new_crtc_state->stream, 4558 &aconnector->psr_caps); 4559 } else { 4560 mod_power_add_stream(dm->power_module, 4561 dm_new_crtc_state->stream, 4562 &aconnector->psr_caps); 4563 } 4564 } else if (old_crtc_state->active) { 4565 mod_power_remove_stream(dm->power_module, 4566 dm_old_crtc_state->stream); 4567 } 4568 } 4569 } 4570 4571 /** 4572 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4573 * @state: the drm atomic state 4574 * @dm: the display manager to update mod_power on 4575 * 4576 * Notify mod_power of mode_change. This needs to be done after dc_stream 4577 * updates have been committed, and VRR parameters have been updated. 4578 */ 4579 static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4580 struct amdgpu_display_manager *dm) 4581 { 4582 struct dm_crtc_state *dm_new_crtc_state; 4583 struct drm_crtc_state *new_crtc_state; 4584 struct amdgpu_crtc *acrtc; 4585 struct drm_crtc *crtc; 4586 int i = 0; 4587 4588 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4589 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4590 acrtc = to_amdgpu_crtc(crtc); 4591 4592 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4593 continue; 4594 4595 if (new_crtc_state->active) { 4596 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4597 &acrtc->dm_irq_params.vrr_params); 4598 mod_power_notify_mode_change(dm->power_module, 4599 dm_new_crtc_state->stream, 4600 false); 4601 4602 /* 4603 * Block PSR / Replay on the new stream until display settles post-modeset. 4604 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4605 * allow_sr_entry becomes true. 4606 */ 4607 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4608 psr_event_hw_programming, true); 4609 4610 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4611 replay_event_hw_programming | replay_event_general_ui, 4612 true); 4613 } 4614 } 4615 4616 } 4617 4618 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4619 struct dc_state *dc_state) 4620 { 4621 struct drm_device *dev = state->dev; 4622 struct amdgpu_device *adev = drm_to_adev(dev); 4623 struct amdgpu_display_manager *dm = &adev->dm; 4624 struct drm_crtc *crtc; 4625 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4626 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4627 struct drm_connector_state *old_con_state; 4628 struct drm_connector *connector; 4629 bool mode_set_reset_required = false; 4630 u32 i; 4631 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4632 bool set_backlight_level = false; 4633 4634 /* Disable writeback */ 4635 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4636 struct dm_connector_state *dm_old_con_state; 4637 struct amdgpu_crtc *acrtc; 4638 4639 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4640 continue; 4641 4642 old_crtc_state = NULL; 4643 4644 dm_old_con_state = to_dm_connector_state(old_con_state); 4645 if (!dm_old_con_state->base.crtc) 4646 continue; 4647 4648 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4649 if (acrtc) 4650 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4651 4652 if (!acrtc || !acrtc->wb_enabled) 4653 continue; 4654 4655 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4656 4657 dm_clear_writeback(dm, dm_old_crtc_state); 4658 acrtc->wb_enabled = false; 4659 } 4660 4661 amdgpu_dm_mod_power_update_streams(state, dm); 4662 4663 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4664 new_crtc_state, i) { 4665 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4666 4667 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4668 4669 if (old_crtc_state->active && 4670 (!new_crtc_state->active || 4671 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4672 manage_dm_interrupts(adev, acrtc, NULL); 4673 dc_stream_release(dm_old_crtc_state->stream); 4674 } 4675 } 4676 4677 drm_atomic_helper_calc_timestamping_constants(state); 4678 4679 /* update changed items */ 4680 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4681 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4682 4683 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4684 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4685 4686 drm_dbg_state(state->dev, 4687 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4688 acrtc->crtc_id, 4689 new_crtc_state->enable, 4690 new_crtc_state->active, 4691 new_crtc_state->planes_changed, 4692 new_crtc_state->mode_changed, 4693 new_crtc_state->active_changed, 4694 new_crtc_state->connectors_changed); 4695 4696 /* Disable cursor if disabling crtc */ 4697 if (old_crtc_state->active && !new_crtc_state->active) { 4698 struct dc_cursor_position position; 4699 4700 memset(&position, 0, sizeof(position)); 4701 mutex_lock(&dm->dc_lock); 4702 dc_exit_ips_for_hw_access(dm->dc); 4703 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4704 mutex_unlock(&dm->dc_lock); 4705 } 4706 4707 /* Copy all transient state flags into dc state */ 4708 if (dm_new_crtc_state->stream) { 4709 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4710 dm_new_crtc_state->stream); 4711 } 4712 4713 /* handles headless hotplug case, updating new_state and 4714 * aconnector as needed 4715 */ 4716 4717 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4718 4719 drm_dbg_atomic(dev, 4720 "Atomic commit: SET crtc id %d: [%p]\n", 4721 acrtc->crtc_id, acrtc); 4722 4723 if (!dm_new_crtc_state->stream) { 4724 /* 4725 * this could happen because of issues with 4726 * userspace notifications delivery. 4727 * In this case userspace tries to set mode on 4728 * display which is disconnected in fact. 4729 * dc_sink is NULL in this case on aconnector. 4730 * We expect reset mode will come soon. 4731 * 4732 * This can also happen when unplug is done 4733 * during resume sequence ended 4734 * 4735 * In this case, we want to pretend we still 4736 * have a sink to keep the pipe running so that 4737 * hw state is consistent with the sw state 4738 */ 4739 drm_dbg_atomic(dev, 4740 "Failed to create new stream for crtc %d\n", 4741 acrtc->base.base.id); 4742 continue; 4743 } 4744 4745 if (dm_old_crtc_state->stream) 4746 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4747 4748 pm_runtime_get_noresume(dev->dev); 4749 4750 acrtc->enabled = true; 4751 acrtc->hw_mode = new_crtc_state->mode; 4752 crtc->hwmode = new_crtc_state->mode; 4753 mode_set_reset_required = true; 4754 set_backlight_level = true; 4755 } else if (modereset_required(new_crtc_state)) { 4756 drm_dbg_atomic(dev, 4757 "Atomic commit: RESET. crtc id %d:[%p]\n", 4758 acrtc->crtc_id, acrtc); 4759 /* i.e. reset mode */ 4760 if (dm_old_crtc_state->stream) 4761 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4762 4763 mode_set_reset_required = true; 4764 } 4765 } /* for_each_crtc_in_state() */ 4766 4767 /* if there mode set or reset, flush vblank work queue */ 4768 if (mode_set_reset_required) { 4769 if (dm->vblank_control_workqueue) 4770 flush_workqueue(dm->vblank_control_workqueue); 4771 } 4772 4773 dm_enable_per_frame_crtc_master_sync(dc_state); 4774 mutex_lock(&dm->dc_lock); 4775 dc_exit_ips_for_hw_access(dm->dc); 4776 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4777 4778 bool frl_stream_found = false; 4779 4780 for (i = 0; i < params.stream_count; i++) { 4781 struct dc_stream_state *stream = params.streams[i]; 4782 4783 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4784 frl_stream_found = true; 4785 break; 4786 } 4787 } 4788 if (frl_stream_found) { 4789 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 4790 &dm->hdmi_frl_status_polling_work, 4791 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 4792 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 4793 } else { 4794 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 4795 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 4796 } 4797 /* Allow idle optimization when vblank count is 0 for display off */ 4798 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 4799 dc_allow_idle_optimizations(dm->dc, true); 4800 mutex_unlock(&dm->dc_lock); 4801 4802 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4803 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4804 4805 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4806 4807 if (dm_new_crtc_state->stream != NULL) { 4808 const struct dc_stream_status *status = 4809 dc_stream_get_status(dm_new_crtc_state->stream); 4810 4811 if (!status) 4812 status = dc_state_get_stream_status(dc_state, 4813 dm_new_crtc_state->stream); 4814 if (!status) 4815 drm_err(dev, 4816 "got no status for stream %p on acrtc%p\n", 4817 dm_new_crtc_state->stream, acrtc); 4818 else 4819 acrtc->otg_inst = status->primary_otg_inst; 4820 } 4821 } 4822 4823 /* During boot up and resume the DC layer will reset the panel brightness 4824 * to fix a flicker issue. 4825 * It will cause the dm->actual_brightness is not the current panel brightness 4826 * level. (the dm->brightness is the correct panel level) 4827 * So we set the backlight level with dm->brightness value after set mode 4828 */ 4829 if (set_backlight_level) { 4830 for (i = 0; i < dm->num_of_edps; i++) { 4831 if (dm->backlight_dev[i]) 4832 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 4833 } 4834 } 4835 } 4836 4837 static void dm_set_writeback(struct amdgpu_display_manager *dm, 4838 struct dm_crtc_state *crtc_state, 4839 struct drm_connector *connector, 4840 struct drm_connector_state *new_con_state) 4841 { 4842 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 4843 struct amdgpu_device *adev = dm->adev; 4844 struct amdgpu_crtc *acrtc; 4845 struct dc_writeback_info *wb_info; 4846 struct pipe_ctx *pipe = NULL; 4847 struct amdgpu_framebuffer *afb; 4848 int i = 0; 4849 4850 wb_info = kzalloc_obj(*wb_info); 4851 if (!wb_info) { 4852 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 4853 return; 4854 } 4855 4856 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 4857 if (!acrtc) { 4858 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 4859 kfree(wb_info); 4860 return; 4861 } 4862 4863 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 4864 if (!afb) { 4865 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 4866 kfree(wb_info); 4867 return; 4868 } 4869 4870 for (i = 0; i < MAX_PIPES; i++) { 4871 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 4872 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 4873 break; 4874 } 4875 } 4876 4877 /* fill in wb_info */ 4878 wb_info->wb_enabled = true; 4879 4880 wb_info->dwb_pipe_inst = 0; 4881 wb_info->dwb_params.dwbscl_black_color = 0; 4882 wb_info->dwb_params.hdr_mult = 0x1F000; 4883 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 4884 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 4885 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 4886 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 4887 4888 /* width & height from crtc */ 4889 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 4890 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 4891 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 4892 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 4893 4894 wb_info->dwb_params.cnv_params.crop_en = false; 4895 wb_info->dwb_params.stereo_params.stereo_enabled = false; 4896 4897 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 4898 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 4899 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 4900 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 4901 4902 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 4903 4904 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 4905 4906 wb_info->dwb_params.scaler_taps.h_taps = 1; 4907 wb_info->dwb_params.scaler_taps.v_taps = 1; 4908 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 4909 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 4910 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 4911 4912 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 4913 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 4914 4915 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 4916 wb_info->mcif_buf_params.luma_address[i] = afb->address; 4917 wb_info->mcif_buf_params.chroma_address[i] = 0; 4918 } 4919 4920 wb_info->mcif_buf_params.p_vmid = 1; 4921 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 4922 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 4923 wb_info->mcif_warmup_params.region_size = 4924 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 4925 } 4926 wb_info->mcif_warmup_params.p_vmid = 1; 4927 wb_info->writeback_source_plane = pipe->plane_state; 4928 4929 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 4930 4931 acrtc->wb_pending = true; 4932 acrtc->wb_conn = wb_conn; 4933 drm_writeback_queue_job(wb_conn, new_con_state); 4934 } 4935 4936 static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 4937 { 4938 struct drm_connector_state *old_con_state, *new_con_state; 4939 struct drm_device *dev = state->dev; 4940 struct drm_connector *connector; 4941 struct amdgpu_device *adev = drm_to_adev(dev); 4942 int i; 4943 4944 if (!adev->dm.hdcp_workqueue) 4945 return; 4946 4947 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4948 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4949 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4950 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4951 struct dm_crtc_state *dm_new_crtc_state; 4952 struct amdgpu_dm_connector *aconnector; 4953 4954 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 4955 continue; 4956 4957 aconnector = to_amdgpu_dm_connector(connector); 4958 4959 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 4960 4961 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 4962 connector->index, connector->status, connector->dpms); 4963 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 4964 old_con_state->content_protection, new_con_state->content_protection); 4965 4966 if (aconnector->dc_sink) { 4967 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 4968 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 4969 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 4970 aconnector->dc_sink->edid_caps.display_name); 4971 } 4972 } 4973 4974 new_crtc_state = NULL; 4975 old_crtc_state = NULL; 4976 4977 if (acrtc) { 4978 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4979 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4980 } 4981 4982 if (old_crtc_state) 4983 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4984 old_crtc_state->enable, 4985 old_crtc_state->active, 4986 old_crtc_state->mode_changed, 4987 old_crtc_state->active_changed, 4988 old_crtc_state->connectors_changed); 4989 4990 if (new_crtc_state) 4991 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4992 new_crtc_state->enable, 4993 new_crtc_state->active, 4994 new_crtc_state->mode_changed, 4995 new_crtc_state->active_changed, 4996 new_crtc_state->connectors_changed); 4997 4998 4999 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5000 5001 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 5002 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 5003 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 5004 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5005 dm_new_con_state->update_hdcp = true; 5006 continue; 5007 } 5008 5009 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 5010 old_con_state, connector, adev->dm.hdcp_workqueue)) { 5011 /* when display is unplugged from mst hub, connctor will 5012 * be destroyed within dm_dp_mst_connector_destroy. connector 5013 * hdcp perperties, like type, undesired, desired, enabled, 5014 * will be lost. So, save hdcp properties into hdcp_work within 5015 * amdgpu_dm_atomic_commit_tail. if the same display is 5016 * plugged back with same display index, its hdcp properties 5017 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 5018 */ 5019 5020 bool enable_encryption = false; 5021 5022 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 5023 enable_encryption = true; 5024 5025 if (aconnector->dc_link && aconnector->dc_sink && 5026 aconnector->dc_link->type == dc_connection_mst_branch) { 5027 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 5028 struct hdcp_workqueue *hdcp_w = 5029 &hdcp_work[aconnector->dc_link->link_index]; 5030 5031 hdcp_w->hdcp_content_type[connector->index] = 5032 new_con_state->hdcp_content_type; 5033 hdcp_w->content_protection[connector->index] = 5034 new_con_state->content_protection; 5035 } 5036 5037 if (new_crtc_state && new_crtc_state->mode_changed && 5038 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 5039 enable_encryption = true; 5040 5041 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 5042 5043 if (aconnector->dc_link) 5044 hdcp_update_display( 5045 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 5046 new_con_state->hdcp_content_type, enable_encryption); 5047 } 5048 } 5049 } 5050 5051 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 5052 { 5053 struct drm_crtc *crtc; 5054 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5055 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5056 int i, ret; 5057 5058 ret = drm_dp_mst_atomic_setup_commit(state); 5059 if (ret) 5060 return ret; 5061 5062 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5063 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5064 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5065 /* 5066 * Color management settings. We also update color properties 5067 * when a modeset is needed, to ensure it gets reprogrammed. 5068 */ 5069 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 5070 (dm_new_crtc_state->base.color_mgmt_changed || 5071 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5072 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5073 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 5074 if (ret) { 5075 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 5076 return ret; 5077 } 5078 } 5079 } 5080 5081 return 0; 5082 } 5083 5084 STATIC_IFN_KUNIT void set_multisync_trigger_params( 5085 struct dc_stream_state *stream) 5086 { 5087 struct dc_stream_state *master = NULL; 5088 5089 if (stream->triggered_crtc_reset.enabled) { 5090 master = stream->triggered_crtc_reset.event_source; 5091 stream->triggered_crtc_reset.event = 5092 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5093 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5094 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5095 } 5096 } 5097 EXPORT_IF_KUNIT(set_multisync_trigger_params); 5098 5099 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 5100 int stream_count) 5101 { 5102 int j, highest_rfr = 0, master_stream = 0; 5103 5104 for (j = 0; j < stream_count; j++) { 5105 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5106 int refresh_rate = 0; 5107 5108 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5109 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5110 if (refresh_rate > highest_rfr) { 5111 highest_rfr = refresh_rate; 5112 master_stream = j; 5113 } 5114 } 5115 } 5116 for (j = 0; j < stream_count; j++) { 5117 if (stream_set[j]) 5118 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5119 } 5120 } 5121 EXPORT_IF_KUNIT(set_master_stream); 5122 5123 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5124 { 5125 int i = 0; 5126 struct dc_stream_state *stream; 5127 5128 if (context->stream_count < 2) 5129 return; 5130 for (i = 0; i < context->stream_count ; i++) { 5131 if (!context->streams[i]) 5132 continue; 5133 /* 5134 * TODO: add a function to read AMD VSDB bits and set 5135 * crtc_sync_master.multi_sync_enabled flag 5136 * For now it's set to false 5137 */ 5138 } 5139 5140 set_master_stream(context->streams, context->stream_count); 5141 5142 for (i = 0; i < context->stream_count ; i++) { 5143 stream = context->streams[i]; 5144 5145 if (!stream) 5146 continue; 5147 5148 set_multisync_trigger_params(stream); 5149 } 5150 } 5151 5152 /** 5153 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5154 * @state: The atomic state to commit 5155 * 5156 * This will tell DC to commit the constructed DC state from atomic_check, 5157 * programming the hardware. Any failures here implies a hardware failure, since 5158 * atomic check should have filtered anything non-kosher. 5159 */ 5160 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 5161 { 5162 struct drm_device *dev = state->dev; 5163 struct amdgpu_device *adev = drm_to_adev(dev); 5164 struct amdgpu_display_manager *dm = &adev->dm; 5165 struct dm_atomic_state *dm_state; 5166 struct dc_state *dc_state = NULL; 5167 u32 i, j; 5168 struct drm_crtc *crtc; 5169 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5170 unsigned long flags; 5171 bool wait_for_vblank = true; 5172 struct drm_connector *connector; 5173 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5174 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5175 int crtc_disable_count = 0; 5176 5177 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5178 5179 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5180 drm_dp_mst_atomic_wait_for_dependencies(state); 5181 5182 dm_state = dm_atomic_get_new_state(state); 5183 if (dm_state && dm_state->context) { 5184 dc_state = dm_state->context; 5185 amdgpu_dm_commit_streams(state, dc_state); 5186 } 5187 5188 amdgpu_dm_update_hdcp(state); 5189 5190 /* Handle connector state changes */ 5191 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5192 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5193 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5194 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5195 struct dc_surface_update *dummy_updates; 5196 struct dc_stream_update stream_update; 5197 struct dc_info_packet hdr_packet; 5198 struct dc_stream_status *status = NULL; 5199 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5200 5201 memset(&stream_update, 0, sizeof(stream_update)); 5202 5203 if (acrtc) { 5204 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5205 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5206 } 5207 5208 /* Skip any modesets/resets */ 5209 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5210 continue; 5211 5212 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5213 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5214 5215 scaling_changed = is_scaling_state_different(dm_new_con_state, 5216 dm_old_con_state); 5217 5218 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5219 (dm_old_crtc_state->stream->output_color_space != 5220 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5221 output_color_space_changed = true; 5222 5223 abm_changed = dm_new_crtc_state->abm_level != 5224 dm_old_crtc_state->abm_level; 5225 5226 hdr_changed = 5227 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5228 5229 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5230 continue; 5231 5232 stream_update.stream = dm_new_crtc_state->stream; 5233 if (scaling_changed) { 5234 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5235 dm_new_con_state, dm_new_crtc_state->stream); 5236 5237 stream_update.src = dm_new_crtc_state->stream->src; 5238 stream_update.dst = dm_new_crtc_state->stream->dst; 5239 } 5240 5241 if (output_color_space_changed) { 5242 dm_new_crtc_state->stream->output_color_space 5243 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5244 5245 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5246 } 5247 5248 if (abm_changed) { 5249 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5250 5251 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5252 } 5253 5254 if (hdr_changed) { 5255 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5256 stream_update.hdr_static_metadata = &hdr_packet; 5257 } 5258 5259 status = dc_stream_get_status(dm_new_crtc_state->stream); 5260 5261 if (WARN_ON(!status)) 5262 continue; 5263 5264 WARN_ON(!status->plane_count); 5265 5266 /* 5267 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5268 * Here we create an empty update on each plane. 5269 * To fix this, DC should permit updating only stream properties. 5270 */ 5271 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5272 if (!dummy_updates) { 5273 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5274 continue; 5275 } 5276 for (j = 0; j < status->plane_count; j++) 5277 dummy_updates[j].surface = status->plane_states[j]; 5278 5279 sort(dummy_updates, status->plane_count, 5280 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5281 5282 mutex_lock(&dm->dc_lock); 5283 dc_exit_ips_for_hw_access(dm->dc); 5284 dc_update_planes_and_stream(dm->dc, 5285 dummy_updates, 5286 status->plane_count, 5287 dm_new_crtc_state->stream, 5288 &stream_update); 5289 mutex_unlock(&dm->dc_lock); 5290 kfree(dummy_updates); 5291 5292 drm_connector_update_privacy_screen(new_con_state); 5293 } 5294 5295 /** 5296 * Enable interrupts for CRTCs that are newly enabled or went through 5297 * a modeset. It was intentionally deferred until after the front end 5298 * state was modified to wait until the OTG was on and so the IRQ 5299 * handlers didn't access stale or invalid state. 5300 */ 5301 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5302 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5303 #ifdef CONFIG_DEBUG_FS 5304 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5305 #endif 5306 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5307 if (old_crtc_state->active && !new_crtc_state->active) 5308 crtc_disable_count++; 5309 5310 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5311 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5312 5313 /* For freesync config update on crtc state and params for irq */ 5314 update_stream_irq_parameters(dm, dm_new_crtc_state); 5315 5316 #ifdef CONFIG_DEBUG_FS 5317 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5318 cur_crc_src = acrtc->dm_irq_params.crc_src; 5319 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5320 #endif 5321 5322 if (new_crtc_state->active && 5323 (!old_crtc_state->active || 5324 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5325 dc_stream_retain(dm_new_crtc_state->stream); 5326 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5327 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5328 } 5329 /* Handle vrr on->off / off->on transitions */ 5330 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5331 5332 #ifdef CONFIG_DEBUG_FS 5333 if (new_crtc_state->active && 5334 (!old_crtc_state->active || 5335 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5336 /** 5337 * Frontend may have changed so reapply the CRC capture 5338 * settings for the stream. 5339 */ 5340 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5341 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5342 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5343 uint8_t cnt; 5344 5345 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5346 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5347 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5348 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5349 5350 /** 5351 * It takes 2 frames for HW to stably generate CRC when 5352 * resuming from suspend, so we set skip_frame_cnt 2. 5353 */ 5354 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5355 } 5356 } 5357 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5358 } 5359 #endif 5360 if (amdgpu_dm_crtc_configure_crc_source( 5361 crtc, dm_new_crtc_state, cur_crc_src)) 5362 drm_dbg_atomic(dev, "Failed to configure crc source"); 5363 } 5364 } 5365 #endif 5366 } 5367 5368 amdgpu_dm_mod_power_setup_streams(state, dm); 5369 5370 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5371 if (new_crtc_state->async_flip) 5372 wait_for_vblank = false; 5373 5374 /* update planes when needed per crtc*/ 5375 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5376 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5377 5378 if (dm_new_crtc_state->stream) 5379 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5380 } 5381 5382 /* Enable writeback */ 5383 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5384 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5385 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5386 5387 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5388 continue; 5389 5390 if (!new_con_state->writeback_job) 5391 continue; 5392 5393 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5394 5395 if (!new_crtc_state) 5396 continue; 5397 5398 if (acrtc->wb_enabled) 5399 continue; 5400 5401 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5402 5403 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5404 acrtc->wb_enabled = true; 5405 } 5406 5407 /* Update audio instances for each connector. */ 5408 amdgpu_dm_commit_audio(dev, state); 5409 5410 /* restore the backlight level */ 5411 for (i = 0; i < dm->num_of_edps; i++) { 5412 if (dm->backlight_dev[i] && 5413 (dm->actual_brightness[i] != dm->brightness[i])) 5414 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5415 } 5416 5417 /* 5418 * send vblank event on all events not handled in flip and 5419 * mark consumed event for drm_atomic_helper_commit_hw_done 5420 */ 5421 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5422 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5423 5424 if (new_crtc_state->event) 5425 drm_send_event_locked(dev, &new_crtc_state->event->base); 5426 5427 new_crtc_state->event = NULL; 5428 } 5429 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5430 5431 /* Signal HW programming completion */ 5432 drm_atomic_helper_commit_hw_done(state); 5433 5434 if (wait_for_vblank) 5435 drm_atomic_helper_wait_for_flip_done(dev, state); 5436 5437 drm_atomic_helper_cleanup_planes(dev, state); 5438 5439 /* Don't free the memory if we are hitting this as part of suspend. 5440 * This way we don't free any memory during suspend; see 5441 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5442 * non-suspend modeset or when the driver is torn down. 5443 */ 5444 if (!adev->in_suspend) { 5445 /* return the stolen vga memory back to VRAM */ 5446 if (!adev->mman.keep_stolen_vga_memory) 5447 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5448 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5449 } 5450 5451 /* 5452 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5453 * so we can put the GPU into runtime suspend if we're not driving any 5454 * displays anymore 5455 */ 5456 for (i = 0; i < crtc_disable_count; i++) 5457 pm_runtime_put_autosuspend(dev->dev); 5458 pm_runtime_mark_last_busy(dev->dev); 5459 5460 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5461 } 5462 5463 /* 5464 * Grabs all modesetting locks to serialize against any blocking commits, 5465 * Waits for completion of all non blocking commits. 5466 */ 5467 static int do_aquire_global_lock(struct drm_device *dev, 5468 struct drm_atomic_commit *state) 5469 { 5470 struct drm_crtc *crtc; 5471 struct drm_crtc_commit *commit; 5472 long ret; 5473 5474 /* 5475 * Adding all modeset locks to aquire_ctx will 5476 * ensure that when the framework release it the 5477 * extra locks we are locking here will get released to 5478 */ 5479 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5480 if (ret) 5481 return ret; 5482 5483 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5484 spin_lock(&crtc->commit_lock); 5485 commit = list_first_entry_or_null(&crtc->commit_list, 5486 struct drm_crtc_commit, commit_entry); 5487 if (commit) 5488 drm_crtc_commit_get(commit); 5489 spin_unlock(&crtc->commit_lock); 5490 5491 if (!commit) 5492 continue; 5493 5494 /* 5495 * Make sure all pending HW programming completed and 5496 * page flips done 5497 */ 5498 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5499 5500 if (ret > 0) 5501 ret = wait_for_completion_interruptible_timeout( 5502 &commit->flip_done, 10*HZ); 5503 5504 if (ret == 0) 5505 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5506 crtc->base.id, crtc->name); 5507 5508 drm_crtc_commit_put(commit); 5509 } 5510 5511 return ret < 0 ? ret : 0; 5512 } 5513 5514 static void get_freesync_config_for_crtc( 5515 struct dm_crtc_state *new_crtc_state, 5516 struct dm_connector_state *new_con_state) 5517 { 5518 struct mod_freesync_config config = {0}; 5519 struct amdgpu_dm_connector *aconnector; 5520 struct drm_display_mode *mode = &new_crtc_state->base.mode; 5521 int vrefresh = drm_mode_vrefresh(mode); 5522 bool fs_vid_mode = false; 5523 5524 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5525 return; 5526 5527 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 5528 5529 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 5530 vrefresh >= aconnector->min_vfreq && 5531 vrefresh <= aconnector->max_vfreq; 5532 5533 if (new_crtc_state->vrr_supported) { 5534 new_crtc_state->stream->ignore_msa_timing_param = true; 5535 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 5536 5537 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 5538 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 5539 config.vsif_supported = true; 5540 config.btr = true; 5541 5542 if (fs_vid_mode) { 5543 config.state = VRR_STATE_ACTIVE_FIXED; 5544 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 5545 goto out; 5546 } else if (new_crtc_state->base.vrr_enabled) { 5547 config.state = VRR_STATE_ACTIVE_VARIABLE; 5548 } else { 5549 config.state = VRR_STATE_INACTIVE; 5550 } 5551 } else { 5552 config.state = VRR_STATE_UNSUPPORTED; 5553 } 5554 out: 5555 new_crtc_state->freesync_config = config; 5556 } 5557 5558 static void reset_freesync_config_for_crtc( 5559 struct dm_crtc_state *new_crtc_state) 5560 { 5561 new_crtc_state->vrr_supported = false; 5562 5563 memset(&new_crtc_state->vrr_infopacket, 0, 5564 sizeof(new_crtc_state->vrr_infopacket)); 5565 } 5566 5567 STATIC_IFN_KUNIT bool 5568 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 5569 struct drm_crtc_state *new_crtc_state) 5570 { 5571 const struct drm_display_mode *old_mode, *new_mode; 5572 5573 if (!old_crtc_state || !new_crtc_state) 5574 return false; 5575 5576 old_mode = &old_crtc_state->mode; 5577 new_mode = &new_crtc_state->mode; 5578 5579 if (old_mode->clock == new_mode->clock && 5580 old_mode->hdisplay == new_mode->hdisplay && 5581 old_mode->vdisplay == new_mode->vdisplay && 5582 old_mode->htotal == new_mode->htotal && 5583 old_mode->vtotal != new_mode->vtotal && 5584 old_mode->hsync_start == new_mode->hsync_start && 5585 old_mode->vsync_start != new_mode->vsync_start && 5586 old_mode->hsync_end == new_mode->hsync_end && 5587 old_mode->vsync_end != new_mode->vsync_end && 5588 old_mode->hskew == new_mode->hskew && 5589 old_mode->vscan == new_mode->vscan && 5590 (old_mode->vsync_end - old_mode->vsync_start) == 5591 (new_mode->vsync_end - new_mode->vsync_start)) 5592 return true; 5593 5594 return false; 5595 } 5596 EXPORT_IF_KUNIT(is_timing_unchanged_for_freesync); 5597 5598 STATIC_IFN_KUNIT void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 5599 { 5600 u64 num, den, res; 5601 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 5602 5603 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 5604 5605 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 5606 den = (unsigned long long)new_crtc_state->mode.htotal * 5607 (unsigned long long)new_crtc_state->mode.vtotal; 5608 5609 res = div_u64(num, den); 5610 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 5611 } 5612 EXPORT_IF_KUNIT(set_freesync_fixed_config); 5613 5614 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5615 struct drm_atomic_commit *state, 5616 struct drm_crtc *crtc, 5617 struct drm_crtc_state *old_crtc_state, 5618 struct drm_crtc_state *new_crtc_state, 5619 bool enable, 5620 bool *lock_and_validation_needed) 5621 { 5622 struct dm_atomic_state *dm_state = NULL; 5623 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5624 struct dc_stream_state *new_stream; 5625 struct amdgpu_device *adev = dm->adev; 5626 int ret = 0; 5627 5628 /* 5629 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5630 * update changed items 5631 */ 5632 struct amdgpu_crtc *acrtc = NULL; 5633 struct drm_connector *connector = NULL; 5634 struct amdgpu_dm_connector *aconnector = NULL; 5635 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5636 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5637 5638 new_stream = NULL; 5639 5640 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5641 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5642 acrtc = to_amdgpu_crtc(crtc); 5643 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5644 if (connector) 5645 aconnector = to_amdgpu_dm_connector(connector); 5646 5647 /* TODO This hack should go away */ 5648 if (connector && enable) { 5649 /* Make sure fake sink is created in plug-in scenario */ 5650 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5651 connector); 5652 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5653 connector); 5654 5655 if (WARN_ON(!drm_new_conn_state)) { 5656 ret = -EINVAL; 5657 goto fail; 5658 } 5659 5660 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5661 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5662 5663 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5664 goto skip_modeset; 5665 5666 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5667 &new_crtc_state->mode, 5668 dm_new_conn_state, 5669 dm_old_crtc_state->stream); 5670 5671 /* 5672 * we can have no stream on ACTION_SET if a display 5673 * was disconnected during S3, in this case it is not an 5674 * error, the OS will be updated after detection, and 5675 * will do the right thing on next atomic commit 5676 */ 5677 5678 if (!new_stream) { 5679 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5680 __func__, acrtc->base.base.id); 5681 ret = -ENOMEM; 5682 goto fail; 5683 } 5684 5685 /* 5686 * TODO: Check VSDB bits to decide whether this should 5687 * be enabled or not. 5688 */ 5689 new_stream->triggered_crtc_reset.enabled = 5690 dm->force_timing_sync; 5691 5692 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5693 5694 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5695 &new_stream->hdr_static_metadata); 5696 if (ret) 5697 goto fail; 5698 5699 /* 5700 * If we already removed the old stream from the context 5701 * (and set the new stream to NULL) then we can't reuse 5702 * the old stream even if the stream and scaling are unchanged. 5703 * We'll hit the BUG_ON and black screen. 5704 * 5705 * TODO: Refactor this function to allow this check to work 5706 * in all conditions. 5707 */ 5708 if (amdgpu_freesync_vid_mode && 5709 dm_new_crtc_state->stream && 5710 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5711 goto skip_modeset; 5712 5713 if (dm_new_crtc_state->stream && 5714 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5715 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5716 new_crtc_state->mode_changed = false; 5717 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5718 new_crtc_state->mode_changed); 5719 } 5720 } 5721 5722 /* mode_changed flag may get updated above, need to check again */ 5723 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5724 goto skip_modeset; 5725 5726 drm_dbg_state(state->dev, 5727 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5728 acrtc->crtc_id, 5729 new_crtc_state->enable, 5730 new_crtc_state->active, 5731 new_crtc_state->planes_changed, 5732 new_crtc_state->mode_changed, 5733 new_crtc_state->active_changed, 5734 new_crtc_state->connectors_changed); 5735 5736 /* Remove stream for any changed/disabled CRTC */ 5737 if (!enable) { 5738 5739 if (!dm_old_crtc_state->stream) 5740 goto skip_modeset; 5741 5742 /* Unset freesync video if it was active before */ 5743 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5744 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5745 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5746 } 5747 5748 /* Now check if we should set freesync video mode */ 5749 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5750 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5751 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5752 is_timing_unchanged_for_freesync(new_crtc_state, 5753 old_crtc_state)) { 5754 new_crtc_state->mode_changed = false; 5755 drm_dbg_driver(adev_to_drm(adev), 5756 "Mode change not required for front porch change, setting mode_changed to %d", 5757 new_crtc_state->mode_changed); 5758 5759 set_freesync_fixed_config(dm_new_crtc_state); 5760 5761 goto skip_modeset; 5762 } else if (amdgpu_freesync_vid_mode && aconnector && 5763 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5764 aconnector)) { 5765 struct drm_display_mode *high_mode; 5766 5767 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5768 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 5769 set_freesync_fixed_config(dm_new_crtc_state); 5770 } 5771 5772 ret = dm_atomic_get_state(state, &dm_state); 5773 if (ret) 5774 goto fail; 5775 5776 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 5777 crtc->base.id); 5778 5779 /* i.e. reset mode */ 5780 if (dc_state_remove_stream( 5781 dm->dc, 5782 dm_state->context, 5783 dm_old_crtc_state->stream) != DC_OK) { 5784 ret = -EINVAL; 5785 goto fail; 5786 } 5787 5788 dc_stream_release(dm_old_crtc_state->stream); 5789 dm_new_crtc_state->stream = NULL; 5790 5791 reset_freesync_config_for_crtc(dm_new_crtc_state); 5792 5793 *lock_and_validation_needed = true; 5794 5795 } else {/* Add stream for any updated/enabled CRTC */ 5796 /* 5797 * Quick fix to prevent NULL pointer on new_stream when 5798 * added MST connectors not found in existing crtc_state in the chained mode 5799 * TODO: need to dig out the root cause of that 5800 */ 5801 if (!connector) 5802 goto skip_modeset; 5803 5804 if (modereset_required(new_crtc_state)) 5805 goto skip_modeset; 5806 5807 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 5808 dm_old_crtc_state->stream)) { 5809 5810 WARN_ON(dm_new_crtc_state->stream); 5811 5812 ret = dm_atomic_get_state(state, &dm_state); 5813 if (ret) 5814 goto fail; 5815 5816 dm_new_crtc_state->stream = new_stream; 5817 5818 dc_stream_retain(new_stream); 5819 5820 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 5821 crtc->base.id); 5822 5823 if (dc_state_add_stream( 5824 dm->dc, 5825 dm_state->context, 5826 dm_new_crtc_state->stream) != DC_OK) { 5827 ret = -EINVAL; 5828 goto fail; 5829 } 5830 5831 *lock_and_validation_needed = true; 5832 } 5833 } 5834 5835 skip_modeset: 5836 /* Release extra reference */ 5837 if (new_stream) 5838 dc_stream_release(new_stream); 5839 5840 /* 5841 * We want to do dc stream updates that do not require a 5842 * full modeset below. 5843 */ 5844 if (!(enable && connector && new_crtc_state->active)) 5845 return 0; 5846 /* 5847 * Given above conditions, the dc state cannot be NULL because: 5848 * 1. We're in the process of enabling CRTCs (just been added 5849 * to the dc context, or already is on the context) 5850 * 2. Has a valid connector attached, and 5851 * 3. Is currently active and enabled. 5852 * => The dc stream state currently exists. 5853 */ 5854 BUG_ON(dm_new_crtc_state->stream == NULL); 5855 5856 /* Scaling or underscan settings */ 5857 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 5858 drm_atomic_crtc_needs_modeset(new_crtc_state)) 5859 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 5860 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5861 5862 /* ABM settings */ 5863 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5864 5865 /* 5866 * Color management settings. We also update color properties 5867 * when a modeset is needed, to ensure it gets reprogrammed. 5868 */ 5869 if (dm_new_crtc_state->base.color_mgmt_changed || 5870 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5871 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5872 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 5873 if (ret) 5874 goto fail; 5875 } 5876 5877 /* Update Freesync settings. */ 5878 get_freesync_config_for_crtc(dm_new_crtc_state, 5879 dm_new_conn_state); 5880 5881 return ret; 5882 5883 fail: 5884 if (new_stream) 5885 dc_stream_release(new_stream); 5886 return ret; 5887 } 5888 5889 static bool should_reset_plane(struct drm_atomic_commit *state, 5890 struct drm_plane *plane, 5891 struct drm_plane_state *old_plane_state, 5892 struct drm_plane_state *new_plane_state) 5893 { 5894 struct drm_plane *other; 5895 struct drm_plane_state *old_other_state, *new_other_state; 5896 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5897 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 5898 struct amdgpu_device *adev = drm_to_adev(plane->dev); 5899 struct drm_connector_state *new_con_state; 5900 struct drm_connector *connector; 5901 int i; 5902 5903 /* 5904 * TODO: Remove this hack for all asics once it proves that the 5905 * fast updates works fine on DCN3.2+. 5906 */ 5907 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 5908 state->allow_modeset) 5909 return true; 5910 5911 /* Check for writeback commit */ 5912 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5913 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5914 continue; 5915 5916 if (new_con_state->writeback_job) 5917 return true; 5918 } 5919 5920 if (amdgpu_in_reset(adev) && state->allow_modeset) 5921 return true; 5922 5923 /* Exit early if we know that we're adding or removing the plane. */ 5924 if (old_plane_state->crtc != new_plane_state->crtc) 5925 return true; 5926 5927 /* old crtc == new_crtc == NULL, plane not in context. */ 5928 if (!new_plane_state->crtc) 5929 return false; 5930 5931 new_crtc_state = 5932 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 5933 old_crtc_state = 5934 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 5935 5936 if (!new_crtc_state) 5937 return true; 5938 5939 /* 5940 * A change in cursor mode means a new dc pipe needs to be acquired or 5941 * released from the state 5942 */ 5943 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5944 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5945 if (plane->type == DRM_PLANE_TYPE_CURSOR && 5946 old_dm_crtc_state != NULL && 5947 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 5948 return true; 5949 } 5950 5951 /* CRTC Degamma changes currently require us to recreate planes. */ 5952 if (new_crtc_state->color_mgmt_changed) 5953 return true; 5954 5955 /* 5956 * On zpos change, planes need to be reordered by removing and re-adding 5957 * them one by one to the dc state, in order of descending zpos. 5958 * 5959 * TODO: We can likely skip bandwidth validation if the only thing that 5960 * changed about the plane was it'z z-ordering. 5961 */ 5962 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 5963 return true; 5964 5965 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 5966 return true; 5967 5968 /* 5969 * If there are any new primary or overlay planes being added or 5970 * removed then the z-order can potentially change. To ensure 5971 * correct z-order and pipe acquisition the current DC architecture 5972 * requires us to remove and recreate all existing planes. 5973 * 5974 * TODO: Come up with a more elegant solution for this. 5975 */ 5976 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 5977 struct amdgpu_framebuffer *old_afb, *new_afb; 5978 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 5979 5980 dm_new_other_state = to_dm_plane_state(new_other_state); 5981 dm_old_other_state = to_dm_plane_state(old_other_state); 5982 5983 if (other->type == DRM_PLANE_TYPE_CURSOR) 5984 continue; 5985 5986 if (old_other_state->crtc != new_plane_state->crtc && 5987 new_other_state->crtc != new_plane_state->crtc) 5988 continue; 5989 5990 if (old_other_state->crtc != new_other_state->crtc) 5991 return true; 5992 5993 /* Src/dst size and scaling updates. */ 5994 if (old_other_state->src_w != new_other_state->src_w || 5995 old_other_state->src_h != new_other_state->src_h || 5996 old_other_state->crtc_w != new_other_state->crtc_w || 5997 old_other_state->crtc_h != new_other_state->crtc_h) 5998 return true; 5999 6000 /* Rotation / mirroring updates. */ 6001 if (old_other_state->rotation != new_other_state->rotation) 6002 return true; 6003 6004 /* Blending updates. */ 6005 if (old_other_state->pixel_blend_mode != 6006 new_other_state->pixel_blend_mode) 6007 return true; 6008 6009 /* Alpha updates. */ 6010 if (old_other_state->alpha != new_other_state->alpha) 6011 return true; 6012 6013 /* Colorspace changes. */ 6014 if (old_other_state->color_range != new_other_state->color_range || 6015 old_other_state->color_encoding != new_other_state->color_encoding) 6016 return true; 6017 6018 /* HDR/Transfer Function changes. */ 6019 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 6020 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 6021 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 6022 dm_old_other_state->ctm != dm_new_other_state->ctm || 6023 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 6024 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 6025 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 6026 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 6027 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 6028 return true; 6029 6030 /* Framebuffer checks fall at the end. */ 6031 if (!old_other_state->fb || !new_other_state->fb) 6032 continue; 6033 6034 /* Pixel format changes can require bandwidth updates. */ 6035 if (old_other_state->fb->format != new_other_state->fb->format) 6036 return true; 6037 6038 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 6039 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 6040 6041 /* Tiling and DCC changes also require bandwidth updates. */ 6042 if (old_afb->tiling_flags != new_afb->tiling_flags || 6043 old_afb->base.modifier != new_afb->base.modifier) 6044 return true; 6045 } 6046 6047 return false; 6048 } 6049 6050 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 6051 struct drm_plane_state *new_plane_state, 6052 struct drm_framebuffer *fb) 6053 { 6054 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 6055 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 6056 unsigned int pitch; 6057 bool linear; 6058 6059 if (fb->width > new_acrtc->max_cursor_width || 6060 fb->height > new_acrtc->max_cursor_height) { 6061 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB size %dx%d\n", 6062 new_plane_state->fb->width, 6063 new_plane_state->fb->height); 6064 return -EINVAL; 6065 } 6066 if (new_plane_state->src_w != fb->width << 16 || 6067 new_plane_state->src_h != fb->height << 16) { 6068 drm_dbg_atomic(adev_to_drm(adev), "Cropping not supported for cursor plane\n"); 6069 return -EINVAL; 6070 } 6071 6072 /* Pitch in pixels */ 6073 pitch = fb->pitches[0] / fb->format->cpp[0]; 6074 6075 if (fb->width != pitch) { 6076 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB width %d doesn't match pitch %d", 6077 fb->width, pitch); 6078 return -EINVAL; 6079 } 6080 6081 switch (pitch) { 6082 case 64: 6083 case 128: 6084 case 256: 6085 /* FB pitch is supported by cursor plane */ 6086 break; 6087 default: 6088 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB pitch %d px\n", pitch); 6089 return -EINVAL; 6090 } 6091 6092 /* Core DRM takes care of checking FB modifiers, so we only need to 6093 * check tiling flags when the FB doesn't have a modifier. 6094 */ 6095 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 6096 if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 6097 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 6098 } else if (adev->family >= AMDGPU_FAMILY_AI) { 6099 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 6100 } else { 6101 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 6102 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 6103 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 6104 } 6105 if (!linear) { 6106 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB not linear"); 6107 return -EINVAL; 6108 } 6109 } 6110 6111 return 0; 6112 } 6113 6114 /* 6115 * Helper function for checking the cursor in native mode 6116 */ 6117 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 6118 struct drm_plane *plane, 6119 struct drm_plane_state *new_plane_state, 6120 bool enable) 6121 { 6122 6123 struct amdgpu_crtc *new_acrtc; 6124 int ret; 6125 6126 if (!enable || !new_plane_crtc || 6127 drm_atomic_plane_disabling(plane->state, new_plane_state)) 6128 return 0; 6129 6130 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 6131 6132 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 6133 drm_dbg_atomic(new_plane_crtc->dev, "Cropping not supported for cursor plane\n"); 6134 return -EINVAL; 6135 } 6136 6137 if (new_plane_state->fb) { 6138 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 6139 new_plane_state->fb); 6140 if (ret) 6141 return ret; 6142 } 6143 6144 return 0; 6145 } 6146 6147 static bool dm_should_update_native_cursor(struct drm_atomic_commit *state, 6148 struct drm_crtc *old_plane_crtc, 6149 struct drm_crtc *new_plane_crtc, 6150 bool enable) 6151 { 6152 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6153 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6154 6155 if (!enable) { 6156 if (old_plane_crtc == NULL) 6157 return true; 6158 6159 old_crtc_state = drm_atomic_get_old_crtc_state( 6160 state, old_plane_crtc); 6161 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6162 6163 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6164 } else { 6165 if (new_plane_crtc == NULL) 6166 return true; 6167 6168 new_crtc_state = drm_atomic_get_new_crtc_state( 6169 state, new_plane_crtc); 6170 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6171 6172 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6173 } 6174 } 6175 6176 static int dm_update_plane_state(struct dc *dc, 6177 struct drm_atomic_commit *state, 6178 struct drm_plane *plane, 6179 struct drm_plane_state *old_plane_state, 6180 struct drm_plane_state *new_plane_state, 6181 bool enable, 6182 bool *lock_and_validation_needed, 6183 bool *is_top_most_overlay) 6184 { 6185 6186 struct dm_atomic_state *dm_state = NULL; 6187 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6188 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6189 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6190 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6191 bool needs_reset, update_native_cursor; 6192 int ret = 0; 6193 6194 6195 new_plane_crtc = new_plane_state->crtc; 6196 old_plane_crtc = old_plane_state->crtc; 6197 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6198 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6199 6200 update_native_cursor = dm_should_update_native_cursor(state, 6201 old_plane_crtc, 6202 new_plane_crtc, 6203 enable); 6204 6205 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 6206 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6207 new_plane_state, enable); 6208 if (ret) 6209 return ret; 6210 6211 return 0; 6212 } 6213 6214 needs_reset = should_reset_plane(state, plane, old_plane_state, 6215 new_plane_state); 6216 6217 /* Remove any changed/removed planes */ 6218 if (!enable) { 6219 if (!needs_reset) 6220 return 0; 6221 6222 if (!old_plane_crtc) 6223 return 0; 6224 6225 old_crtc_state = drm_atomic_get_old_crtc_state( 6226 state, old_plane_crtc); 6227 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6228 6229 if (!dm_old_crtc_state->stream) 6230 return 0; 6231 6232 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 6233 plane->base.id, old_plane_crtc->base.id); 6234 6235 ret = dm_atomic_get_state(state, &dm_state); 6236 if (ret) 6237 return ret; 6238 6239 if (!dc_state_remove_plane( 6240 dc, 6241 dm_old_crtc_state->stream, 6242 dm_old_plane_state->dc_state, 6243 dm_state->context)) { 6244 6245 return -EINVAL; 6246 } 6247 6248 if (dm_old_plane_state->dc_state) 6249 dc_plane_state_release(dm_old_plane_state->dc_state); 6250 6251 dm_new_plane_state->dc_state = NULL; 6252 6253 *lock_and_validation_needed = true; 6254 6255 } else { /* Add new planes */ 6256 struct dc_plane_state *dc_new_plane_state; 6257 6258 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6259 return 0; 6260 6261 if (!new_plane_crtc) 6262 return 0; 6263 6264 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6265 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6266 6267 if (!dm_new_crtc_state->stream) 6268 return 0; 6269 6270 if (!needs_reset) 6271 return 0; 6272 6273 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 6274 if (ret) 6275 goto out; 6276 6277 WARN_ON(dm_new_plane_state->dc_state); 6278 6279 dc_new_plane_state = dc_create_plane_state(dc); 6280 if (!dc_new_plane_state) { 6281 ret = -ENOMEM; 6282 goto out; 6283 } 6284 6285 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 6286 plane->base.id, new_plane_crtc->base.id); 6287 6288 ret = fill_dc_plane_attributes( 6289 drm_to_adev(new_plane_crtc->dev), 6290 dc_new_plane_state, 6291 new_plane_state, 6292 new_crtc_state); 6293 if (ret) { 6294 dc_plane_state_release(dc_new_plane_state); 6295 goto out; 6296 } 6297 6298 ret = dm_atomic_get_state(state, &dm_state); 6299 if (ret) { 6300 dc_plane_state_release(dc_new_plane_state); 6301 goto out; 6302 } 6303 6304 /* 6305 * Any atomic check errors that occur after this will 6306 * not need a release. The plane state will be attached 6307 * to the stream, and therefore part of the atomic 6308 * state. It'll be released when the atomic state is 6309 * cleaned. 6310 */ 6311 if (!dc_state_add_plane( 6312 dc, 6313 dm_new_crtc_state->stream, 6314 dc_new_plane_state, 6315 dm_state->context)) { 6316 6317 dc_plane_state_release(dc_new_plane_state); 6318 ret = -EINVAL; 6319 goto out; 6320 } 6321 6322 dm_new_plane_state->dc_state = dc_new_plane_state; 6323 6324 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 6325 6326 /* Tell DC to do a full surface update every time there 6327 * is a plane change. Inefficient, but works for now. 6328 */ 6329 dm_new_plane_state->dc_state->update_bits.full_update = 1; 6330 6331 *lock_and_validation_needed = true; 6332 } 6333 6334 out: 6335 /* If enabling cursor overlay failed, attempt fallback to native mode */ 6336 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 6337 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6338 new_plane_state, enable); 6339 if (ret) 6340 return ret; 6341 6342 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 6343 } 6344 6345 return ret; 6346 } 6347 6348 STATIC_IFN_KUNIT void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 6349 int *src_w, int *src_h) 6350 { 6351 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 6352 case DRM_MODE_ROTATE_90: 6353 case DRM_MODE_ROTATE_270: 6354 *src_w = plane_state->src_h >> 16; 6355 *src_h = plane_state->src_w >> 16; 6356 break; 6357 case DRM_MODE_ROTATE_0: 6358 case DRM_MODE_ROTATE_180: 6359 default: 6360 *src_w = plane_state->src_w >> 16; 6361 *src_h = plane_state->src_h >> 16; 6362 break; 6363 } 6364 } 6365 EXPORT_IF_KUNIT(dm_get_oriented_plane_size); 6366 6367 STATIC_IFN_KUNIT void 6368 dm_get_plane_scale(struct drm_plane_state *plane_state, 6369 int *out_plane_scale_w, int *out_plane_scale_h) 6370 { 6371 int plane_src_w, plane_src_h; 6372 6373 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 6374 *out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0; 6375 *out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0; 6376 } 6377 EXPORT_IF_KUNIT(dm_get_plane_scale); 6378 6379 /* 6380 * The normalized_zpos value cannot be used by this iterator directly. It's only 6381 * calculated for enabled planes, potentially causing normalized_zpos collisions 6382 * between enabled/disabled planes in the atomic state. We need a unique value 6383 * so that the iterator will not generate the same object twice, or loop 6384 * indefinitely. 6385 */ 6386 static inline struct __drm_planes_state *__get_next_zpos( 6387 struct drm_atomic_commit *state, 6388 struct __drm_planes_state *prev) 6389 { 6390 unsigned int highest_zpos = 0, prev_zpos = 256; 6391 uint32_t highest_id = 0, prev_id = UINT_MAX; 6392 struct drm_plane_state *new_plane_state; 6393 struct drm_plane *plane; 6394 int i, highest_i = -1; 6395 6396 if (prev != NULL) { 6397 prev_zpos = prev->new_state->zpos; 6398 prev_id = prev->ptr->base.id; 6399 } 6400 6401 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 6402 /* Skip planes with higher zpos than the previously returned */ 6403 if (new_plane_state->zpos > prev_zpos || 6404 (new_plane_state->zpos == prev_zpos && 6405 plane->base.id >= prev_id)) 6406 continue; 6407 6408 /* Save the index of the plane with highest zpos */ 6409 if (new_plane_state->zpos > highest_zpos || 6410 (new_plane_state->zpos == highest_zpos && 6411 plane->base.id > highest_id)) { 6412 highest_zpos = new_plane_state->zpos; 6413 highest_id = plane->base.id; 6414 highest_i = i; 6415 } 6416 } 6417 6418 if (highest_i < 0) 6419 return NULL; 6420 6421 return &state->planes[highest_i]; 6422 } 6423 6424 /* 6425 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 6426 * by descending zpos, as read from the new plane state. This is the same 6427 * ordering as defined by drm_atomic_normalize_zpos(). 6428 */ 6429 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 6430 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 6431 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 6432 for_each_if(((plane) = __i->ptr, \ 6433 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 6434 (old_plane_state) = __i->old_state, \ 6435 (new_plane_state) = __i->new_state, 1)) 6436 6437 static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) 6438 { 6439 struct drm_connector *connector; 6440 struct drm_connector_state *conn_state, *old_conn_state; 6441 struct amdgpu_dm_connector *aconnector = NULL; 6442 int i; 6443 6444 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6445 if (!conn_state->crtc) 6446 conn_state = old_conn_state; 6447 6448 if (conn_state->crtc != crtc) 6449 continue; 6450 6451 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6452 continue; 6453 6454 aconnector = to_amdgpu_dm_connector(connector); 6455 if (!aconnector->mst_output_port || !aconnector->mst_root) 6456 aconnector = NULL; 6457 else 6458 break; 6459 } 6460 6461 if (!aconnector) 6462 return 0; 6463 6464 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6465 } 6466 6467 /** 6468 * DOC: Cursor Modes - Native vs Overlay 6469 * 6470 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 6471 * plane. It does not require a dedicated hw plane to enable, but it is 6472 * subjected to the same z-order and scaling as the hw plane. It also has format 6473 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 6474 * hw plane. 6475 * 6476 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 6477 * own scaling and z-pos. It also has no blending restrictions. It lends to a 6478 * cursor behavior more akin to a DRM client's expectations. However, it does 6479 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 6480 * available. 6481 */ 6482 6483 /** 6484 * dm_plane_color_pipeline_active() - Check if a plane's color pipeline active. 6485 * @state: DRM atomic state 6486 * @plane: DRM plane to check 6487 * @use_old: if true, inspect the old colorop states; otherwise the new ones 6488 * 6489 * A color pipeline may be selected (color_pipeline != NULL) but still is 6490 * inactive if every colorop in the chain is bypassed. Only return 6491 * true when at least one colorop has bypass == false, meaning the cursor 6492 * would be subjected to the transformation in native mode. 6493 * 6494 * Return: true if the pipeline modifies pixels, false otherwise. 6495 */ 6496 static bool dm_plane_color_pipeline_active(struct drm_atomic_commit *state, 6497 struct drm_plane *plane, 6498 bool use_old) 6499 { 6500 struct drm_colorop *colorop; 6501 struct drm_colorop_state *old_colorop_state, *new_colorop_state; 6502 int i; 6503 6504 for_each_oldnew_colorop_in_state(state, colorop, old_colorop_state, new_colorop_state, i) { 6505 struct drm_colorop_state *cstate = use_old ? old_colorop_state : new_colorop_state; 6506 6507 if (cstate->colorop->plane != plane) 6508 continue; 6509 if (!cstate->bypass) 6510 return true; 6511 } 6512 return false; 6513 } 6514 6515 /** 6516 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 6517 * @adev: amdgpu device 6518 * @state: DRM atomic state 6519 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 6520 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 6521 * 6522 * Get whether the cursor should be enabled in native mode, or overlay mode, on 6523 * the dm_crtc_state. 6524 * 6525 * The cursor should be enabled in overlay mode if there exists an underlying 6526 * plane - on which the cursor may be blended - that is either YUV formatted, 6527 * scaled differently from the cursor, or has a color pipeline active. 6528 * 6529 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 6530 * calling this function. 6531 * 6532 * Return: 0 on success, or an error code if getting the cursor plane state 6533 * failed. 6534 */ 6535 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 6536 struct drm_atomic_commit *state, 6537 struct dm_crtc_state *dm_crtc_state, 6538 enum amdgpu_dm_cursor_mode *cursor_mode) 6539 { 6540 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 6541 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 6542 struct drm_plane *plane; 6543 bool consider_mode_change = false; 6544 bool entire_crtc_covered = false; 6545 bool cursor_changed = false; 6546 int underlying_scale_w, underlying_scale_h; 6547 int cursor_scale_w, cursor_scale_h; 6548 int i; 6549 6550 /* Overlay cursor not supported on HW before DCN 6551 * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 6552 * as previous DCN generations, so enable native mode on DCN401/420 6553 */ 6554 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || 6555 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 6556 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1)) { 6557 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6558 return 0; 6559 } 6560 6561 /* Init cursor_mode to be the same as current */ 6562 *cursor_mode = dm_crtc_state->cursor_mode; 6563 6564 /* 6565 * Cursor mode can change if a plane's format changes, scale changes, is 6566 * enabled/disabled, z-order changes, or color management properties change. 6567 */ 6568 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 6569 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 6570 6571 /* Only care about planes on this CRTC */ 6572 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 6573 continue; 6574 6575 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6576 cursor_changed = true; 6577 6578 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 6579 drm_atomic_plane_disabling(old_plane_state, plane_state) || 6580 old_plane_state->fb->format != plane_state->fb->format) { 6581 consider_mode_change = true; 6582 break; 6583 } 6584 6585 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 6586 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 6587 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 6588 consider_mode_change = true; 6589 break; 6590 } 6591 6592 if (dm_plane_color_pipeline_active(state, plane, true) != 6593 dm_plane_color_pipeline_active(state, plane, false)) { 6594 consider_mode_change = true; 6595 break; 6596 } 6597 } 6598 6599 if (!consider_mode_change && !crtc_state->zpos_changed) 6600 return 0; 6601 6602 /* 6603 * If no cursor change on this CRTC, and not enabled on this CRTC, then 6604 * no need to set cursor mode. This avoids needlessly locking the cursor 6605 * state. 6606 */ 6607 if (!cursor_changed && 6608 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 6609 return 0; 6610 } 6611 6612 cursor_state = drm_atomic_get_plane_state(state, 6613 crtc_state->crtc->cursor); 6614 if (IS_ERR(cursor_state)) 6615 return PTR_ERR(cursor_state); 6616 6617 /* Cursor is disabled */ 6618 if (!cursor_state->fb) 6619 return 0; 6620 6621 /* For all planes in descending z-order (all of which are below cursor 6622 * as per zpos definitions), check their scaling and format 6623 */ 6624 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 6625 6626 /* Only care about non-cursor planes on this CRTC */ 6627 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 6628 plane->type == DRM_PLANE_TYPE_CURSOR) 6629 continue; 6630 6631 /* Underlying plane is YUV format - use overlay cursor */ 6632 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 6633 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6634 return 0; 6635 } 6636 6637 /* Underlying plane has an active color pipeline - cursor would be transformed */ 6638 if (dm_plane_color_pipeline_active(state, plane, false)) { 6639 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6640 return 0; 6641 } 6642 6643 dm_get_plane_scale(plane_state, 6644 &underlying_scale_w, &underlying_scale_h); 6645 dm_get_plane_scale(cursor_state, 6646 &cursor_scale_w, &cursor_scale_h); 6647 6648 /* Underlying plane has different scale - use overlay cursor */ 6649 if (cursor_scale_w != underlying_scale_w && 6650 cursor_scale_h != underlying_scale_h) { 6651 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6652 return 0; 6653 } 6654 6655 /* If this plane covers the whole CRTC, no need to check planes underneath */ 6656 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 6657 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 6658 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 6659 entire_crtc_covered = true; 6660 break; 6661 } 6662 } 6663 6664 /* If planes do not cover the entire CRTC, use overlay mode to enable 6665 * cursor over holes 6666 */ 6667 if (entire_crtc_covered) 6668 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6669 else 6670 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6671 6672 return 0; 6673 } 6674 6675 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6676 struct drm_atomic_commit *state, 6677 struct drm_crtc_state *crtc_state) 6678 { 6679 struct drm_plane *plane; 6680 struct drm_plane_state *new_plane_state, *old_plane_state; 6681 6682 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6683 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6684 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6685 6686 if (!old_plane_state || !new_plane_state) 6687 continue; 6688 6689 if (old_plane_state->fb && new_plane_state->fb && 6690 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6691 return true; 6692 } 6693 6694 return false; 6695 } 6696 6697 /** 6698 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6699 * 6700 * @dev: The DRM device 6701 * @state: The atomic state to commit 6702 * 6703 * Validate that the given atomic state is programmable by DC into hardware. 6704 * This involves constructing a &struct dc_state reflecting the new hardware 6705 * state we wish to commit, then querying DC to see if it is programmable. It's 6706 * important not to modify the existing DC state. Otherwise, atomic_check 6707 * may unexpectedly commit hardware changes. 6708 * 6709 * When validating the DC state, it's important that the right locks are 6710 * acquired. For full updates case which removes/adds/updates streams on one 6711 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6712 * that any such full update commit will wait for completion of any outstanding 6713 * flip using DRMs synchronization events. 6714 * 6715 * Note that DM adds the affected connectors for all CRTCs in state, when that 6716 * might not seem necessary. This is because DC stream creation requires the 6717 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6718 * be possible but non-trivial - a possible TODO item. 6719 * 6720 * Return: -Error code if validation failed. 6721 */ 6722 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6723 struct drm_atomic_commit *state) 6724 { 6725 struct amdgpu_device *adev = drm_to_adev(dev); 6726 struct dm_atomic_state *dm_state = NULL; 6727 struct dc *dc = adev->dm.dc; 6728 struct drm_connector *connector; 6729 struct drm_connector_state *old_con_state, *new_con_state; 6730 struct drm_crtc *crtc; 6731 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6732 struct drm_plane *plane; 6733 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6734 enum dc_status status; 6735 int ret, i; 6736 bool lock_and_validation_needed = false; 6737 bool is_top_most_overlay = true; 6738 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6739 struct drm_dp_mst_topology_mgr *mgr; 6740 struct drm_dp_mst_topology_state *mst_state; 6741 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 6742 6743 trace_amdgpu_dm_atomic_check_begin(state); 6744 6745 ret = drm_atomic_helper_check_modeset(dev, state); 6746 if (ret) { 6747 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n"); 6748 goto fail; 6749 } 6750 6751 /* Check connector changes */ 6752 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6753 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6754 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6755 6756 /* Skip connectors that are disabled or part of modeset already. */ 6757 if (!new_con_state->crtc) 6758 continue; 6759 6760 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 6761 if (IS_ERR(new_crtc_state)) { 6762 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n"); 6763 ret = PTR_ERR(new_crtc_state); 6764 goto fail; 6765 } 6766 6767 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 6768 dm_old_con_state->scaling != dm_new_con_state->scaling) 6769 new_crtc_state->connectors_changed = true; 6770 } 6771 6772 if (dc_resource_is_dsc_encoding_supported(dc)) { 6773 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6774 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6775 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 6776 } 6777 6778 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6779 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6780 ret = add_affected_mst_dsc_crtcs(state, crtc); 6781 if (ret) { 6782 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n"); 6783 goto fail; 6784 } 6785 } 6786 } 6787 } 6788 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6789 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6790 6791 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6792 !new_crtc_state->color_mgmt_changed && 6793 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 6794 dm_old_crtc_state->dsc_force_changed == false) 6795 continue; 6796 6797 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 6798 if (ret) { 6799 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n"); 6800 goto fail; 6801 } 6802 6803 if (!new_crtc_state->enable) 6804 continue; 6805 6806 ret = drm_atomic_add_affected_connectors(state, crtc); 6807 if (ret) { 6808 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n"); 6809 goto fail; 6810 } 6811 6812 ret = drm_atomic_add_affected_planes(state, crtc); 6813 if (ret) { 6814 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n"); 6815 goto fail; 6816 } 6817 6818 if (dm_old_crtc_state->dsc_force_changed) 6819 new_crtc_state->mode_changed = true; 6820 } 6821 6822 /* 6823 * Add all primary and overlay planes on the CRTC to the state 6824 * whenever a plane is enabled to maintain correct z-ordering 6825 * and to enable fast surface updates. 6826 */ 6827 drm_for_each_crtc(crtc, dev) { 6828 bool modified = false; 6829 6830 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6831 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6832 continue; 6833 6834 if (new_plane_state->crtc == crtc || 6835 old_plane_state->crtc == crtc) { 6836 modified = true; 6837 break; 6838 } 6839 } 6840 6841 if (!modified) 6842 continue; 6843 6844 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6845 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6846 continue; 6847 6848 new_plane_state = 6849 drm_atomic_get_plane_state(state, plane); 6850 6851 if (IS_ERR(new_plane_state)) { 6852 ret = PTR_ERR(new_plane_state); 6853 drm_dbg_atomic(dev, "new_plane_state is BAD\n"); 6854 goto fail; 6855 } 6856 } 6857 } 6858 6859 /* 6860 * DC consults the zpos (layer_index in DC terminology) to determine the 6861 * hw plane on which to enable the hw cursor (see 6862 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 6863 * atomic state, so call drm helper to normalize zpos. 6864 */ 6865 ret = drm_atomic_normalize_zpos(dev, state); 6866 if (ret) { 6867 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 6868 goto fail; 6869 } 6870 6871 /* 6872 * Determine whether cursors on each CRTC should be enabled in native or 6873 * overlay mode. 6874 */ 6875 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6876 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6877 6878 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6879 &dm_new_crtc_state->cursor_mode); 6880 if (ret) { 6881 drm_dbg(dev, "Failed to determine cursor mode\n"); 6882 goto fail; 6883 } 6884 6885 /* 6886 * If overlay cursor is needed, DC cannot go through the 6887 * native cursor update path. All enabled planes on the CRTC 6888 * need to be added for DC to not disable a plane by mistake 6889 */ 6890 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6891 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 6892 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 6893 ret = -EINVAL; 6894 goto fail; 6895 } 6896 6897 ret = drm_atomic_add_affected_planes(state, crtc); 6898 if (ret) 6899 goto fail; 6900 } 6901 } 6902 6903 /* Remove exiting planes if they are modified */ 6904 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6905 6906 ret = dm_update_plane_state(dc, state, plane, 6907 old_plane_state, 6908 new_plane_state, 6909 false, 6910 &lock_and_validation_needed, 6911 &is_top_most_overlay); 6912 if (ret) { 6913 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 6914 goto fail; 6915 } 6916 } 6917 6918 /* Disable all crtcs which require disable */ 6919 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6920 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6921 old_crtc_state, 6922 new_crtc_state, 6923 false, 6924 &lock_and_validation_needed); 6925 if (ret) { 6926 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n"); 6927 goto fail; 6928 } 6929 } 6930 6931 /* Enable all crtcs which require enable */ 6932 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6933 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6934 old_crtc_state, 6935 new_crtc_state, 6936 true, 6937 &lock_and_validation_needed); 6938 if (ret) { 6939 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n"); 6940 goto fail; 6941 } 6942 } 6943 6944 /* Add new/modified planes */ 6945 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6946 ret = dm_update_plane_state(dc, state, plane, 6947 old_plane_state, 6948 new_plane_state, 6949 true, 6950 &lock_and_validation_needed, 6951 &is_top_most_overlay); 6952 if (ret) { 6953 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 6954 goto fail; 6955 } 6956 } 6957 6958 #if defined(CONFIG_DRM_AMD_DC_FP) 6959 if (dc_resource_is_dsc_encoding_supported(dc)) { 6960 ret = pre_validate_dsc(state, &dm_state, vars); 6961 if (ret != 0) 6962 goto fail; 6963 } 6964 #endif 6965 6966 /* Run this here since we want to validate the streams we created */ 6967 ret = drm_atomic_helper_check_planes(dev, state); 6968 if (ret) { 6969 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n"); 6970 goto fail; 6971 } 6972 6973 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6974 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6975 if (dm_new_crtc_state->mpo_requested) 6976 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 6977 } 6978 6979 /* Check cursor restrictions */ 6980 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6981 enum amdgpu_dm_cursor_mode required_cursor_mode; 6982 int is_rotated, is_scaled; 6983 6984 /* Overlay cusor not subject to native cursor restrictions */ 6985 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6986 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 6987 continue; 6988 6989 /* Check if rotation or scaling is enabled on DCN401 */ 6990 if ((drm_plane_mask(crtc->cursor) & 6991 new_crtc_state->plane_mask) && 6992 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1) || 6993 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 6994 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { 6995 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 6996 6997 is_rotated = new_cursor_state && 6998 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 6999 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 7000 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 7001 7002 if (is_rotated || is_scaled) { 7003 drm_dbg_driver( 7004 crtc->dev, 7005 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 7006 crtc->base.id, crtc->name); 7007 ret = -EINVAL; 7008 goto fail; 7009 } 7010 } 7011 7012 /* If HW can only do native cursor, check restrictions again */ 7013 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 7014 &required_cursor_mode); 7015 if (ret) { 7016 drm_dbg_driver(crtc->dev, 7017 "[CRTC:%d:%s] Checking cursor mode failed\n", 7018 crtc->base.id, crtc->name); 7019 goto fail; 7020 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 7021 drm_dbg_driver(crtc->dev, 7022 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 7023 crtc->base.id, crtc->name); 7024 ret = -EINVAL; 7025 goto fail; 7026 } 7027 } 7028 7029 if (state->legacy_cursor_update) { 7030 /* 7031 * This is a fast cursor update coming from the plane update 7032 * helper, check if it can be done asynchronously for better 7033 * performance. 7034 */ 7035 state->async_update = 7036 !drm_atomic_helper_async_check(dev, state); 7037 7038 /* 7039 * Skip the remaining global validation if this is an async 7040 * update. Cursor updates can be done without affecting 7041 * state or bandwidth calcs and this avoids the performance 7042 * penalty of locking the private state object and 7043 * allocating a new dc_state. 7044 */ 7045 if (state->async_update) 7046 return 0; 7047 } 7048 7049 /* Check scaling and underscan changes*/ 7050 /* TODO Removed scaling changes validation due to inability to commit 7051 * new stream into context w\o causing full reset. Need to 7052 * decide how to handle. 7053 */ 7054 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7055 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7056 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7057 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7058 7059 /* Skip any modesets/resets */ 7060 if (!acrtc || drm_atomic_crtc_needs_modeset( 7061 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7062 continue; 7063 7064 /* Skip any thing not scale or underscan changes */ 7065 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7066 continue; 7067 7068 lock_and_validation_needed = true; 7069 } 7070 7071 /* set the slot info for each mst_state based on the link encoding format */ 7072 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 7073 struct amdgpu_dm_connector *aconnector; 7074 struct drm_connector *connector; 7075 struct drm_connector_list_iter iter; 7076 u8 link_coding_cap; 7077 7078 drm_connector_list_iter_begin(dev, &iter); 7079 drm_for_each_connector_iter(connector, &iter) { 7080 if (connector->index == mst_state->mgr->conn_base_id) { 7081 aconnector = to_amdgpu_dm_connector(connector); 7082 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 7083 drm_dp_mst_update_slots(mst_state, link_coding_cap); 7084 7085 break; 7086 } 7087 } 7088 drm_connector_list_iter_end(&iter); 7089 } 7090 7091 /** 7092 * Streams and planes are reset when there are changes that affect 7093 * bandwidth. Anything that affects bandwidth needs to go through 7094 * DC global validation to ensure that the configuration can be applied 7095 * to hardware. 7096 * 7097 * We have to currently stall out here in atomic_check for outstanding 7098 * commits to finish in this case because our IRQ handlers reference 7099 * DRM state directly - we can end up disabling interrupts too early 7100 * if we don't. 7101 * 7102 * TODO: Remove this stall and drop DM state private objects. 7103 */ 7104 if (lock_and_validation_needed) { 7105 ret = dm_atomic_get_state(state, &dm_state); 7106 if (ret) { 7107 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); 7108 goto fail; 7109 } 7110 7111 ret = do_aquire_global_lock(dev, state); 7112 if (ret) { 7113 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n"); 7114 goto fail; 7115 } 7116 7117 #if defined(CONFIG_DRM_AMD_DC_FP) 7118 if (dc_resource_is_dsc_encoding_supported(dc)) { 7119 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 7120 if (ret) { 7121 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n"); 7122 ret = -EINVAL; 7123 goto fail; 7124 } 7125 } 7126 #endif 7127 7128 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 7129 if (ret) { 7130 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); 7131 goto fail; 7132 } 7133 7134 /* 7135 * Perform validation of MST topology in the state: 7136 * We need to perform MST atomic check before calling 7137 * dc_validate_global_state(), or there is a chance 7138 * to get stuck in an infinite loop and hang eventually. 7139 */ 7140 ret = drm_dp_mst_atomic_check(state); 7141 if (ret) { 7142 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); 7143 goto fail; 7144 } 7145 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 7146 if (status != DC_OK) { 7147 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 7148 dc_status_to_str(status), status); 7149 ret = -EINVAL; 7150 goto fail; 7151 } 7152 } else { 7153 /* 7154 * The commit is a fast update. Fast updates shouldn't change 7155 * the DC context, affect global validation, and can have their 7156 * commit work done in parallel with other commits not touching 7157 * the same resource. If we have a new DC context as part of 7158 * the DM atomic state from validation we need to free it and 7159 * retain the existing one instead. 7160 * 7161 * Furthermore, since the DM atomic state only contains the DC 7162 * context and can safely be annulled, we can free the state 7163 * and clear the associated private object now to free 7164 * some memory and avoid a possible use-after-free later. 7165 */ 7166 7167 for (i = 0; i < state->num_private_objs; i++) { 7168 struct drm_private_obj *obj = state->private_objs[i].ptr; 7169 7170 if (obj->funcs == adev->dm.atomic_obj.funcs) { 7171 int j = state->num_private_objs-1; 7172 7173 dm_atomic_destroy_state(obj, 7174 state->private_objs[i].state_to_destroy); 7175 7176 /* If i is not at the end of the array then the 7177 * last element needs to be moved to where i was 7178 * before the array can safely be truncated. 7179 */ 7180 if (i != j) 7181 state->private_objs[i] = 7182 state->private_objs[j]; 7183 7184 state->private_objs[j].ptr = NULL; 7185 state->private_objs[j].state_to_destroy = NULL; 7186 state->private_objs[j].old_state = NULL; 7187 state->private_objs[j].new_state = NULL; 7188 7189 state->num_private_objs = j; 7190 break; 7191 } 7192 } 7193 } 7194 7195 /* Store the overall update type for use later in atomic check. */ 7196 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7197 struct dm_crtc_state *dm_new_crtc_state = 7198 to_dm_crtc_state(new_crtc_state); 7199 7200 /* 7201 * Only allow async flips for fast updates that don't change 7202 * the FB pitch, the DCC state, rotation, mem_type, etc. 7203 */ 7204 if (new_crtc_state->async_flip && 7205 (lock_and_validation_needed || 7206 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 7207 drm_dbg_atomic(crtc->dev, 7208 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 7209 crtc->base.id, crtc->name); 7210 ret = -EINVAL; 7211 goto fail; 7212 } 7213 7214 dm_new_crtc_state->update_type = lock_and_validation_needed ? 7215 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 7216 } 7217 7218 /* Must be success */ 7219 WARN_ON(ret); 7220 7221 trace_amdgpu_dm_atomic_check_finish(state, ret); 7222 7223 return ret; 7224 7225 fail: 7226 if (ret == -EDEADLK) 7227 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 7228 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7229 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 7230 else 7231 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret); 7232 7233 trace_amdgpu_dm_atomic_check_finish(state, ret); 7234 7235 return ret; 7236 } 7237 7238 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 7239 { 7240 struct amdgpu_device *adev = drm_to_adev(dev); 7241 struct dc *dc = adev->dm.dc; 7242 int i; 7243 7244 mutex_lock(&adev->dm.dc_lock); 7245 if (dc->current_state) { 7246 for (i = 0; i < dc->current_state->stream_count; ++i) 7247 dc->current_state->streams[i] 7248 ->triggered_crtc_reset.enabled = 7249 adev->dm.force_timing_sync; 7250 7251 dm_enable_per_frame_crtc_master_sync(dc->current_state); 7252 dc_trigger_sync(dc, dc->current_state); 7253 } 7254 mutex_unlock(&adev->dm.dc_lock); 7255 } 7256 7257 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 7258 u32 value, const char *func_name) 7259 { 7260 #ifdef DM_CHECK_ADDR_0 7261 if (address == 0) { 7262 drm_err(adev_to_drm(ctx->driver_context), 7263 "invalid register write. address = 0"); 7264 return; 7265 } 7266 #endif 7267 7268 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7269 cgs_write_register(ctx->cgs_device, address, value); 7270 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 7271 } 7272 7273 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 7274 const char *func_name) 7275 { 7276 u32 value; 7277 #ifdef DM_CHECK_ADDR_0 7278 if (address == 0) { 7279 drm_err(adev_to_drm(ctx->driver_context), 7280 "invalid register read; address = 0\n"); 7281 return 0; 7282 } 7283 #endif 7284 7285 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7286 7287 value = cgs_read_register(ctx->cgs_device, address); 7288 7289 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 7290 7291 return value; 7292 } 7293 7294 void dm_acpi_process_phy_transition_interlock( 7295 const struct dc_context *ctx, 7296 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 7297 { 7298 // Not yet implemented 7299 } 7300