1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "dc/dc_state.h" 42 #include "amdgpu_dm_trace.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_dm_wb.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 #include "amdgpu_dm_replay.h" 69 #include "amdgpu_dm_backlight.h" 70 #include "amdgpu_dm_audio.h" 71 #include "amdgpu_dm_dmub.h" 72 #include "amdgpu_dm_connector.h" 73 #include "amdgpu_dm_pp_smu.h" 74 #include "amdgpu_dm_freesync.h" 75 #include "amdgpu_dm_cursor.h" 76 77 #include "ivsrcid/ivsrcid_vislands30.h" 78 79 #include <linux/backlight.h> 80 #include <linux/module.h> 81 #include <linux/moduleparam.h> 82 #include <linux/types.h> 83 #include <linux/pm_runtime.h> 84 #include <linux/pci.h> 85 #include <linux/power_supply.h> 86 #include <linux/firmware.h> 87 #include <linux/component.h> 88 #include <linux/sort.h> 89 90 #include <drm/drm_privacy_screen_consumer.h> 91 #include <drm/display/drm_dp_mst_helper.h> 92 #include <drm/display/drm_hdmi_helper.h> 93 #include <drm/drm_atomic.h> 94 #include <drm/drm_atomic_uapi.h> 95 #include <drm/drm_atomic_helper.h> 96 #include <drm/drm_blend.h> 97 #include <drm/drm_fixed.h> 98 #include <drm/drm_fourcc.h> 99 #include <drm/drm_edid.h> 100 #include <drm/drm_eld.h> 101 #include <drm/drm_mode.h> 102 #include <drm/drm_utils.h> 103 #include <drm/drm_vblank.h> 104 #include <drm/drm_colorop.h> 105 #include <drm/drm_gem_atomic_helper.h> 106 107 #include <media/cec-notifier.h> 108 #include <acpi/video.h> 109 110 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 111 112 #include "modules/inc/mod_freesync.h" 113 #include "modules/inc/mod_power.h" 114 #include "modules/power/power_helpers.h" 115 116 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 117 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 118 119 /** 120 * DOC: overview 121 * 122 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 123 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 124 * requests into DC requests, and DC responses into DRM responses. 125 * 126 * The root control structure is &struct amdgpu_display_manager. 127 */ 128 129 /* basic init/fini API */ 130 static int amdgpu_dm_init(struct amdgpu_device *adev); 131 static void amdgpu_dm_fini(struct amdgpu_device *adev); 132 133 /* 134 * initializes drm_device display related structures, based on the information 135 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 136 * drm_encoder, drm_mode_config 137 * 138 * Returns 0 on success 139 */ 140 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 141 /* removes and deallocates the drm structures, created by the above function */ 142 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 143 144 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 145 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 146 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 147 148 static int amdgpu_dm_atomic_check(struct drm_device *dev, 149 struct drm_atomic_commit *state); 150 151 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 152 { 153 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 154 dc_exit_ips_for_hw_access(dc); 155 } 156 157 /* 158 * dm_vblank_get_counter 159 * 160 * @brief 161 * Get counter for number of vertical blanks 162 * 163 * @param 164 * struct amdgpu_device *adev - [in] desired amdgpu device 165 * int disp_idx - [in] which CRTC to get the counter from 166 * 167 * @return 168 * Counter for vertical blanks 169 */ 170 STATIC_IFN_KUNIT u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 171 { 172 struct amdgpu_crtc *acrtc = NULL; 173 174 if (crtc >= adev->mode_info.num_crtc) 175 return 0; 176 177 acrtc = adev->mode_info.crtcs[crtc]; 178 179 if (!acrtc->dm_irq_params.stream) { 180 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 181 crtc); 182 return 0; 183 } 184 185 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 186 } 187 EXPORT_IF_KUNIT(dm_vblank_get_counter); 188 189 STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 190 u32 *vbl, u32 *position) 191 { 192 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 193 struct amdgpu_crtc *acrtc = NULL; 194 struct dc *dc = adev->dm.dc; 195 196 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 197 return -EINVAL; 198 199 acrtc = adev->mode_info.crtcs[crtc]; 200 201 if (!acrtc->dm_irq_params.stream) { 202 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 203 crtc); 204 return 0; 205 } 206 207 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 208 dc_allow_idle_optimizations(dc, false); 209 210 /* 211 * TODO rework base driver to use values directly. 212 * for now parse it back into reg-format 213 */ 214 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 215 &v_blank_start, 216 &v_blank_end, 217 &h_position, 218 &v_position); 219 220 *position = v_position | (h_position << 16); 221 *vbl = v_blank_start | (v_blank_end << 16); 222 223 return 0; 224 } 225 EXPORT_IF_KUNIT(dm_crtc_get_scanoutpos); 226 227 STATIC_IFN_KUNIT bool dm_is_idle(struct amdgpu_ip_block *ip_block) 228 { 229 /* XXX todo */ 230 return true; 231 } 232 EXPORT_IF_KUNIT(dm_is_idle); 233 234 STATIC_IFN_KUNIT int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 235 { 236 /* XXX todo */ 237 return 0; 238 } 239 EXPORT_IF_KUNIT(dm_wait_for_idle); 240 241 STATIC_IFN_KUNIT int dm_soft_reset(struct amdgpu_ip_block *ip_block) 242 { 243 /* XXX todo */ 244 return 0; 245 } 246 EXPORT_IF_KUNIT(dm_soft_reset); 247 248 /* 249 * DC will program planes with their z-order determined by their ordering 250 * in the dc_surface_updates array. This comparator is used to sort them 251 * by descending zpos. 252 */ 253 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 254 { 255 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 256 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 257 258 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 259 return sb->surface->layer_index - sa->surface->layer_index; 260 } 261 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 262 263 /** 264 * update_planes_and_stream_adapter() - Send planes to be updated in DC 265 * 266 * DC has a generic way to update planes and stream via 267 * dc_update_planes_and_stream function; however, DM might need some 268 * adjustments and preparation before calling it. This function is a wrapper 269 * for the dc_update_planes_and_stream that does any required configuration 270 * before passing control to DC. 271 * 272 * @dc: Display Core control structure 273 * @update_type: specify whether it is FULL/MEDIUM/FAST update 274 * @planes_count: planes count to update 275 * @stream: stream state 276 * @stream_update: stream update 277 * @array_of_surface_update: dc surface update pointer 278 * 279 */ 280 static inline bool update_planes_and_stream_adapter(struct dc *dc, 281 int update_type, 282 int planes_count, 283 struct dc_stream_state *stream, 284 struct dc_stream_update *stream_update, 285 struct dc_surface_update *array_of_surface_update) 286 { 287 sort(array_of_surface_update, planes_count, 288 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 289 290 /* 291 * Previous frame finished and HW is ready for optimization. 292 */ 293 dc_post_update_surfaces_to_stream(dc); 294 295 return dc_update_planes_and_stream(dc, 296 array_of_surface_update, 297 planes_count, 298 stream, 299 stream_update); 300 } 301 302 STATIC_IFN_KUNIT int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 303 enum amd_clockgating_state state) 304 { 305 return 0; 306 } 307 EXPORT_IF_KUNIT(dm_set_clockgating_state); 308 309 STATIC_IFN_KUNIT int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 310 enum amd_powergating_state state) 311 { 312 return 0; 313 } 314 EXPORT_IF_KUNIT(dm_set_powergating_state); 315 316 /* Prototypes of private functions */ 317 static int dm_early_init(struct amdgpu_ip_block *ip_block); 318 319 /* Allocate memory for FBC compressed data */ 320 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 321 { 322 u64 pt_base; 323 u32 logical_addr_low; 324 u32 logical_addr_high; 325 u32 agp_base, agp_bot, agp_top; 326 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 327 328 memset(pa_config, 0, sizeof(*pa_config)); 329 330 agp_base = 0; 331 agp_bot = adev->gmc.agp_start >> 24; 332 agp_top = adev->gmc.agp_end >> 24; 333 334 /* AGP aperture is disabled */ 335 if (agp_bot > agp_top) { 336 logical_addr_low = adev->gmc.fb_start >> 18; 337 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 338 AMD_APU_IS_RENOIR | 339 AMD_APU_IS_GREEN_SARDINE)) 340 /* 341 * Raven2 has a HW issue that it is unable to use the vram which 342 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 343 * workaround that increase system aperture high address (add 1) 344 * to get rid of the VM fault and hardware hang. 345 */ 346 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 347 else 348 logical_addr_high = adev->gmc.fb_end >> 18; 349 } else { 350 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 351 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 352 AMD_APU_IS_RENOIR | 353 AMD_APU_IS_GREEN_SARDINE)) 354 /* 355 * Raven2 has a HW issue that it is unable to use the vram which 356 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 357 * workaround that increase system aperture high address (add 1) 358 * to get rid of the VM fault and hardware hang. 359 */ 360 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 361 else 362 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 363 } 364 365 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 366 367 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 368 AMDGPU_GPU_PAGE_SHIFT); 369 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 370 AMDGPU_GPU_PAGE_SHIFT); 371 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 372 AMDGPU_GPU_PAGE_SHIFT); 373 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 374 AMDGPU_GPU_PAGE_SHIFT); 375 page_table_base.high_part = upper_32_bits(pt_base); 376 page_table_base.low_part = lower_32_bits(pt_base); 377 378 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 379 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 380 381 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 382 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 383 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 384 385 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 386 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 387 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 388 389 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 390 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 391 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 392 393 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 394 395 } 396 397 static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 398 { 399 struct mod_power_init_params init_data[MAX_NUM_EDP]; 400 401 if (dm->num_of_edps == 0) { 402 drm_dbg_driver( 403 dm->ddev, 404 "amdgpu: No eDP detected, skip initializing power module\n"); 405 return 0; 406 } 407 408 /* Initialize all the power module parameters */ 409 for (int i = 0; i < dm->num_of_edps; i++) { 410 init_data[i].allow_psr_smu_optimizations = 411 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 412 init_data[i].allow_psr_multi_disp_optimizations = 413 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 414 /* See dm_late_init */ 415 init_data[i].backlight_ramping_override = false; 416 init_data[i].backlight_ramping_start = 0xCCCC; 417 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 418 init_data[i].def_varibright_level = 0; 419 init_data[i].abm_config_setting = 0; 420 init_data[i].num_backlight_levels = 101; 421 init_data[i].use_nits_based_brightness = false; 422 init_data[i].panel_max_millinits = 0; 423 init_data[i].panel_min_millinits = 0; 424 init_data[i].disable_fractional_pwm = 425 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 426 init_data[i].use_custom_backlight_caps = false; 427 init_data[i].custom_backlight_caps_config_no = 0; 428 init_data[i].use_linear_backlight_curve = false; 429 init_data[i].def_varibright_enable = 0; 430 init_data[i].varibright_level = 0; 431 /* 432 * Power module uses 16-bit backlight levels (0xFFFF max) rather 433 * than 8-bit(0XFF max) 434 */ 435 init_data[i].min_backlight_pwm = 436 dm->backlight_caps[i].min_input_signal * 0x101; 437 init_data[i].max_backlight_pwm = 438 dm->backlight_caps[i].max_input_signal * 0x101; 439 init_data[i].min_abm_backlight = 440 dm->backlight_caps[i].min_input_signal * 0x101; 441 442 /* Min backlight level after ABM reduction, Don't allow below 1% 443 * 0xFFFF x 0.01 = 0x28F 444 */ 445 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 446 0x28F : init_data[i].min_abm_backlight; 447 } 448 449 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 450 if (!dm->power_module) { 451 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 452 return -ENOMEM; 453 } 454 455 mod_power_hw_init(dm->power_module); 456 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 457 458 return 0; 459 } 460 461 static int amdgpu_dm_init(struct amdgpu_device *adev) 462 { 463 struct dc_init_data init_data; 464 struct dc_callback_init init_params; 465 int r; 466 467 adev->dm.ddev = adev_to_drm(adev); 468 adev->dm.adev = adev; 469 470 /* Zero all the fields */ 471 memset(&init_data, 0, sizeof(init_data)); 472 memset(&init_params, 0, sizeof(init_params)); 473 474 mutex_init(&adev->dm.dpia_aux_lock); 475 mutex_init(&adev->dm.dc_lock); 476 mutex_init(&adev->dm.audio_lock); 477 478 spin_lock_init(&adev->dm.dmub_lock); 479 480 if (amdgpu_dm_irq_init(adev)) { 481 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 482 goto error; 483 } 484 485 /* special handling for early revisions of GC 11.5.4 */ 486 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 487 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 488 else 489 init_data.asic_id.chip_family = adev->family; 490 491 init_data.asic_id.pci_revision_id = adev->pdev->revision; 492 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 493 init_data.asic_id.chip_id = adev->pdev->device; 494 495 init_data.asic_id.vram_width = adev->gmc.vram_width; 496 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 497 init_data.asic_id.atombios_base_address = 498 adev->mode_info.atom_context->bios; 499 500 init_data.driver = adev; 501 502 /* cgs_device was created in dm_sw_init() */ 503 init_data.cgs_device = adev->dm.cgs_device; 504 505 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 506 507 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 508 case IP_VERSION(2, 1, 0): 509 switch (adev->dm.dmcub_fw_version) { 510 case 0: /* development */ 511 case 0x1: /* linux-firmware.git hash 6d9f399 */ 512 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 513 init_data.flags.disable_dmcu = false; 514 break; 515 default: 516 init_data.flags.disable_dmcu = true; 517 } 518 break; 519 case IP_VERSION(2, 0, 3): 520 init_data.flags.disable_dmcu = true; 521 break; 522 default: 523 break; 524 } 525 526 /* APU support S/G display by default except: 527 * ASICs before Carrizo, 528 * RAVEN1 (Users reported stability issue) 529 */ 530 531 if (adev->asic_type < CHIP_CARRIZO) { 532 init_data.flags.gpu_vm_support = false; 533 } else if (adev->asic_type == CHIP_RAVEN) { 534 if (adev->apu_flags & AMD_APU_IS_RAVEN) 535 init_data.flags.gpu_vm_support = false; 536 else 537 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 538 } else { 539 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 540 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 541 else 542 init_data.flags.gpu_vm_support = 543 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 544 } 545 546 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 547 548 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 549 init_data.flags.fbc_support = true; 550 551 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 552 init_data.flags.multi_mon_pp_mclk_switch = true; 553 554 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 555 init_data.flags.disable_fractional_pwm = true; 556 557 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 558 init_data.flags.edp_no_power_sequencing = true; 559 560 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 561 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 562 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 563 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 564 565 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 566 init_data.flags.enable_frl = true; 567 568 init_data.flags.seamless_boot_edp_requested = false; 569 570 if (amdgpu_device_seamless_boot_supported(adev)) { 571 init_data.flags.seamless_boot_edp_requested = true; 572 init_data.flags.allow_seamless_boot_optimization = true; 573 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 574 } 575 576 init_data.flags.enable_mipi_converter_optimization = true; 577 578 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 579 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 580 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 581 582 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 583 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 584 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 585 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 586 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 587 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 588 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 589 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 590 else 591 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 592 593 init_data.flags.disable_ips_in_vpb = 0; 594 595 /* DCN35 and above supports dynamic DTBCLK switch */ 596 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 597 init_data.flags.allow_0_dtb_clk = true; 598 599 /* Enable DWB for tested platforms only */ 600 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 601 init_data.num_virtual_links = 1; 602 603 /* DCN42 and above dpia switch to unified link training path */ 604 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 605 init_data.flags.consolidated_dpia_dp_lt = true; 606 init_data.flags.enable_dpia_pre_training = true; 607 init_data.flags.unify_link_enc_assignment = true; 608 init_data.flags.usb4_bw_alloc_support = true; 609 } 610 retrieve_dmi_info(&adev->dm); 611 if (adev->dm.edp0_on_dp1_quirk) 612 init_data.flags.support_edp0_on_dp1 = true; 613 614 if (adev->dm.bb_from_dmub) 615 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 616 else 617 init_data.bb_from_dmub = NULL; 618 619 /* Display Core create. */ 620 adev->dm.dc = dc_create(&init_data); 621 622 if (adev->dm.dc) { 623 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 624 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 625 } else { 626 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 627 goto error; 628 } 629 630 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 631 adev->dm.dc->debug.force_single_disp_pipe_split = false; 632 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 633 } 634 635 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 636 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 637 if (dm_should_disable_stutter(adev->pdev)) 638 adev->dm.dc->debug.disable_stutter = true; 639 640 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 641 adev->dm.dc->debug.disable_stutter = true; 642 643 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 644 adev->dm.dc->debug.disable_dsc = true; 645 646 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 647 adev->dm.dc->debug.disable_clock_gate = true; 648 649 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 650 adev->dm.dc->debug.force_subvp_mclk_switch = true; 651 652 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 653 adev->dm.dc->debug.force_disable_subvp = true; 654 adev->dm.dc->debug.fams2_config.bits.enable = false; 655 } 656 657 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 658 adev->dm.dc->debug.using_dml2 = true; 659 adev->dm.dc->debug.using_dml21 = true; 660 } 661 662 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 663 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 664 665 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 666 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 667 668 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 669 adev->dm.dc->debug.skip_detection_link_training = true; 670 671 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 672 673 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 674 adev->dm.dc->debug.ignore_cable_id = true; 675 676 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 677 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 678 679 r = dm_dmub_hw_init(adev); 680 if (r) { 681 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 682 goto error; 683 } 684 685 dc_hardware_init(adev->dm.dc); 686 687 /* GOP/vBIOS may leave an OPTC enabled for a display present at power-on 688 * but no longer driven (e.g. an external DP unplugged at boot). Such a 689 * dangling pipe keeps DCN out of idle and blocks s0i3. Power it down 690 * here when nothing needs to be preserved. 691 */ 692 if (adev->flags & AMD_IS_APU) 693 dc_disable_dangling_timing_generators(adev->dm.dc); 694 695 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 696 if (!adev->dm.hpd_rx_offload_wq) { 697 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 698 goto error; 699 } 700 701 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 702 struct dc_phy_addr_space_config pa_config; 703 704 mmhub_read_system_context(adev, &pa_config); 705 706 // Call the DC init_memory func 707 dc_setup_system_context(adev->dm.dc, &pa_config); 708 } 709 710 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 711 if (!adev->dm.freesync_module) { 712 drm_err(adev_to_drm(adev), 713 "failed to initialize freesync_module.\n"); 714 } else 715 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 716 adev->dm.freesync_module); 717 718 amdgpu_dm_init_color_mod(); 719 720 if (adev->dm.dc->caps.max_links > 0) { 721 adev->dm.vblank_control_workqueue = 722 create_singlethread_workqueue("dm_vblank_control_workqueue"); 723 if (!adev->dm.vblank_control_workqueue) 724 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 725 } 726 727 if (adev->dm.dc->caps.ips_support && 728 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 729 adev->dm.idle_workqueue = idle_create_workqueue(adev); 730 731 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 732 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 733 734 if (!adev->dm.hdcp_workqueue) 735 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 736 else 737 drm_dbg_driver(adev_to_drm(adev), 738 "hdcp_workqueue init done %p.\n", 739 adev->dm.hdcp_workqueue); 740 741 dc_init_callbacks(adev->dm.dc, &init_params); 742 } 743 if (adev->dm.dc->caps.max_links > 0) { 744 adev->dm.hdmi_frl_status_polling_wq = 745 create_singlethread_workqueue("hdmi_frl_status_polling_workqueue"); 746 if (!adev->dm.hdmi_frl_status_polling_wq) 747 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_workqueue\n"); 748 } 749 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 750 init_completion(&adev->dm.dmub_aux_transfer_done); 751 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 752 if (!adev->dm.dmub_notify) { 753 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 754 goto error; 755 } 756 757 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 758 if (!adev->dm.delayed_hpd_wq) { 759 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 760 goto error; 761 } 762 763 amdgpu_dm_outbox_init(adev); 764 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 765 dm_dmub_aux_setconfig_callback, false)) { 766 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 767 goto error; 768 } 769 770 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 771 init_completion(&adev->dm.fused_io[i].replied); 772 773 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 774 dm_dmub_aux_fused_io_callback, false)) { 775 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 776 goto error; 777 } 778 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 779 * It is expected that DMUB will resend any pending notifications at this point. Note 780 * that hpd and hpd_irq handler registration are deferred to 781 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 782 * sequence. Connection status will be proactivly detected once in the 783 * amdgpu_dm_initialize_drm_device. 784 */ 785 dc_enable_dmub_outbox(adev->dm.dc); 786 787 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 788 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 789 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 790 } 791 792 if (amdgpu_dm_initialize_drm_device(adev)) { 793 drm_err(adev_to_drm(adev), 794 "failed to initialize sw for display support.\n"); 795 goto error; 796 } 797 798 if (amdgpu_dm_init_power_module(&adev->dm)) 799 goto error; 800 801 /* create fake encoders for MST */ 802 dm_dp_create_fake_mst_encoders(adev); 803 804 /* TODO: Add_display_info? */ 805 806 /* TODO use dynamic cursor width */ 807 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 808 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 809 810 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 811 drm_err(adev_to_drm(adev), 812 "failed to initialize vblank for display support.\n"); 813 goto error; 814 } 815 816 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 817 amdgpu_dm_crtc_secure_display_create_contexts(adev); 818 if (!adev->dm.secure_display_ctx.crtc_ctx) 819 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 820 821 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 822 adev->dm.secure_display_ctx.support_mul_roi = true; 823 824 #endif 825 826 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 827 828 return 0; 829 error: 830 amdgpu_dm_fini(adev); 831 832 return -EINVAL; 833 } 834 835 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 836 { 837 struct amdgpu_device *adev = ip_block->adev; 838 839 amdgpu_dm_audio_fini(adev); 840 841 return 0; 842 } 843 844 static void amdgpu_dm_fini(struct amdgpu_device *adev) 845 { 846 int i; 847 848 if (adev->dm.vblank_control_workqueue) { 849 destroy_workqueue(adev->dm.vblank_control_workqueue); 850 adev->dm.vblank_control_workqueue = NULL; 851 } 852 853 if (adev->dm.idle_workqueue) { 854 if (adev->dm.idle_workqueue->running) { 855 adev->dm.idle_workqueue->enable = false; 856 flush_work(&adev->dm.idle_workqueue->work); 857 } 858 859 kfree(adev->dm.idle_workqueue); 860 adev->dm.idle_workqueue = NULL; 861 } 862 863 /* 864 * Disable ISM before dc_destroy() invalidates dm->dc. 865 * 866 * Quiesce workers first without dc_lock (they take dc_lock 867 * themselves, so syncing under it would deadlock), then drive the 868 * FSM back to FULL_POWER_RUNNING under dc_lock. 869 */ 870 amdgpu_dm_ism_disable(&adev->dm); 871 scoped_guard(mutex, &adev->dm.dc_lock) 872 amdgpu_dm_ism_force_full_power(&adev->dm); 873 874 amdgpu_dm_destroy_drm_device(&adev->dm); 875 876 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 877 if (adev->dm.secure_display_ctx.crtc_ctx) { 878 for (i = 0; i < adev->mode_info.num_crtc; i++) { 879 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 880 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 881 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 882 } 883 } 884 kfree(adev->dm.secure_display_ctx.crtc_ctx); 885 adev->dm.secure_display_ctx.crtc_ctx = NULL; 886 } 887 #endif 888 if (adev->dm.hdcp_workqueue) { 889 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 890 adev->dm.hdcp_workqueue = NULL; 891 } 892 893 if (adev->dm.dc) { 894 dc_deinit_callbacks(adev->dm.dc); 895 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 896 if (dc_enable_dmub_notifications(adev->dm.dc)) { 897 kfree(adev->dm.dmub_notify); 898 adev->dm.dmub_notify = NULL; 899 destroy_workqueue(adev->dm.delayed_hpd_wq); 900 adev->dm.delayed_hpd_wq = NULL; 901 } 902 } 903 904 if (adev->dm.dmub_bo) 905 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 906 &adev->dm.dmub_bo_gpu_addr, 907 &adev->dm.dmub_bo_cpu_addr); 908 909 if (adev->dm.boot_time_crc_info.bo_ptr) 910 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 911 &adev->dm.boot_time_crc_info.gpu_addr, 912 &adev->dm.boot_time_crc_info.cpu_addr); 913 914 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 915 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 916 if (adev->dm.hpd_rx_offload_wq[i].wq) { 917 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 918 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 919 } 920 } 921 922 kfree(adev->dm.hpd_rx_offload_wq); 923 adev->dm.hpd_rx_offload_wq = NULL; 924 } 925 926 amdgpu_dm_irq_fini(adev); 927 928 /* DC Destroy TODO: Replace destroy DAL */ 929 if (adev->dm.dc) 930 dc_destroy(&adev->dm.dc); 931 932 if (adev->dm.cgs_device) { 933 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 934 adev->dm.cgs_device = NULL; 935 } 936 if (adev->dm.freesync_module) { 937 mod_freesync_destroy(adev->dm.freesync_module); 938 adev->dm.freesync_module = NULL; 939 } 940 941 if (adev->dm.power_module) { 942 mod_power_destroy(adev->dm.power_module); 943 adev->dm.power_module = NULL; 944 } 945 mutex_destroy(&adev->dm.audio_lock); 946 mutex_destroy(&adev->dm.dc_lock); 947 mutex_destroy(&adev->dm.dpia_aux_lock); 948 } 949 950 static int load_dmcu_fw(struct amdgpu_device *adev) 951 { 952 const char *fw_name_dmcu = NULL; 953 int r; 954 const struct dmcu_firmware_header_v1_0 *hdr; 955 956 switch (adev->asic_type) { 957 #if defined(CONFIG_DRM_AMD_DC_SI) 958 case CHIP_TAHITI: 959 case CHIP_PITCAIRN: 960 case CHIP_VERDE: 961 case CHIP_OLAND: 962 #endif 963 case CHIP_BONAIRE: 964 case CHIP_HAWAII: 965 case CHIP_KAVERI: 966 case CHIP_KABINI: 967 case CHIP_MULLINS: 968 case CHIP_TONGA: 969 case CHIP_FIJI: 970 case CHIP_CARRIZO: 971 case CHIP_STONEY: 972 case CHIP_POLARIS11: 973 case CHIP_POLARIS10: 974 case CHIP_POLARIS12: 975 case CHIP_VEGAM: 976 case CHIP_VEGA10: 977 case CHIP_VEGA12: 978 case CHIP_VEGA20: 979 return 0; 980 case CHIP_NAVI12: 981 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 982 break; 983 case CHIP_RAVEN: 984 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 985 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 986 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 987 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 988 else 989 return 0; 990 break; 991 default: 992 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 993 case IP_VERSION(2, 0, 2): 994 case IP_VERSION(2, 0, 3): 995 case IP_VERSION(2, 0, 0): 996 case IP_VERSION(2, 1, 0): 997 case IP_VERSION(3, 0, 0): 998 case IP_VERSION(3, 0, 2): 999 case IP_VERSION(3, 0, 3): 1000 case IP_VERSION(3, 0, 1): 1001 case IP_VERSION(3, 1, 2): 1002 case IP_VERSION(3, 1, 3): 1003 case IP_VERSION(3, 1, 4): 1004 case IP_VERSION(3, 1, 5): 1005 case IP_VERSION(3, 1, 6): 1006 case IP_VERSION(3, 2, 0): 1007 case IP_VERSION(3, 2, 1): 1008 case IP_VERSION(3, 5, 0): 1009 case IP_VERSION(3, 5, 1): 1010 case IP_VERSION(3, 6, 0): 1011 case IP_VERSION(4, 0, 1): 1012 case IP_VERSION(4, 2, 0): 1013 case IP_VERSION(4, 2, 1): 1014 case IP_VERSION(6, 0, 0): 1015 return 0; 1016 default: 1017 break; 1018 } 1019 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1020 return -EINVAL; 1021 } 1022 1023 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1024 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1025 return 0; 1026 } 1027 1028 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1029 "%s", fw_name_dmcu); 1030 if (r == -ENODEV) { 1031 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1032 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1033 adev->dm.fw_dmcu = NULL; 1034 return 0; 1035 } 1036 if (r) { 1037 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1038 fw_name_dmcu); 1039 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1040 return r; 1041 } 1042 1043 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1044 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1045 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1046 adev->firmware.fw_size += 1047 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1048 1049 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1050 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1051 adev->firmware.fw_size += 1052 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1053 1054 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1055 1056 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1057 1058 return 0; 1059 } 1060 1061 static int dm_sw_init(struct amdgpu_ip_block *ip_block) 1062 { 1063 struct amdgpu_device *adev = ip_block->adev; 1064 int r; 1065 1066 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1067 1068 if (!adev->dm.cgs_device) { 1069 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1070 return -EINVAL; 1071 } 1072 1073 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1074 INIT_LIST_HEAD(&adev->dm.da_list); 1075 1076 r = dm_dmub_sw_init(adev); 1077 if (r) 1078 return r; 1079 1080 return load_dmcu_fw(adev); 1081 } 1082 1083 static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1084 { 1085 struct amdgpu_device *adev = ip_block->adev; 1086 struct dal_allocation *da; 1087 1088 list_for_each_entry(da, &adev->dm.da_list, list) { 1089 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1090 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1091 list_del(&da->list); 1092 kfree(da); 1093 adev->dm.bb_from_dmub = NULL; 1094 break; 1095 } 1096 } 1097 1098 1099 kfree(adev->dm.dmub_fb_info); 1100 adev->dm.dmub_fb_info = NULL; 1101 1102 if (adev->dm.dmub_srv) { 1103 dmub_srv_destroy(adev->dm.dmub_srv); 1104 kfree(adev->dm.dmub_srv); 1105 adev->dm.dmub_srv = NULL; 1106 } 1107 1108 amdgpu_ucode_release(&adev->dm.dmub_fw); 1109 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1110 1111 return 0; 1112 } 1113 1114 1115 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1116 { 1117 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1118 struct dmub_srv *dmub = NULL; 1119 union dmub_fw_boot_options option = {0}; 1120 int ret = 0; 1121 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1122 1123 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1124 !adev->dm.dc->ctx->dmub_srv) { 1125 return; 1126 } 1127 1128 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1129 bootcrc_info = &adev->dm.boot_time_crc_info; 1130 1131 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1132 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1133 return; 1134 } 1135 1136 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1137 1138 /* Return if boot time CRC is not enabled */ 1139 if (option.bits.bootcrc_en_at_S0i3 == 0) 1140 return; 1141 1142 /* Create a buffer for boot time CRC */ 1143 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1144 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1145 &bootcrc_info->bo_ptr, 1146 &bootcrc_info->gpu_addr, 1147 &bootcrc_info->cpu_addr); 1148 1149 if (ret) { 1150 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1151 } else { 1152 bootcrc_info->size = fb_size; 1153 1154 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1155 bootcrc_info->gpu_addr, bootcrc_info->size); 1156 1157 /* Send the buffer info to DMUB */ 1158 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1159 bootcrc_info->gpu_addr, bootcrc_info->size); 1160 } 1161 } 1162 1163 static int dm_late_init(struct amdgpu_ip_block *ip_block) 1164 { 1165 struct amdgpu_device *adev = ip_block->adev; 1166 1167 struct dmcu_iram_parameters params; 1168 unsigned int linear_lut[16]; 1169 int i; 1170 struct dmcu *dmcu = NULL; 1171 1172 dmcu = adev->dm.dc->res_pool->dmcu; 1173 1174 /* Init the boot time CRC (skip in resume) */ 1175 if ((adev->in_suspend == 0) && 1176 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1177 amdgpu_dm_boot_time_crc_init(adev); 1178 1179 for (i = 0; i < 16; i++) 1180 linear_lut[i] = 0xFFFF * i / 15; 1181 1182 params.set = 0; 1183 params.backlight_ramping_override = false; 1184 params.backlight_ramping_start = 0xCCCC; 1185 params.backlight_ramping_reduction = 0xCCCCCCCC; 1186 params.backlight_lut_array_size = 16; 1187 params.backlight_lut_array = linear_lut; 1188 1189 /* Min backlight level after ABM reduction, Don't allow below 1% 1190 * 0xFFFF x 0.01 = 0x28F 1191 */ 1192 params.min_abm_backlight = 0x28F; 1193 /* In the case where abm is implemented on dmcub, 1194 * dmcu object will be null. 1195 * ABM 2.4 and up are implemented on dmcub. 1196 */ 1197 if (dmcu) { 1198 if (!dmcu_load_iram(dmcu, params)) 1199 return -EINVAL; 1200 } else if (adev->dm.dc->ctx->dmub_srv) { 1201 struct dc_link *edp_links[MAX_NUM_EDP]; 1202 int edp_num; 1203 1204 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1205 for (i = 0; i < edp_num; i++) { 1206 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1207 return -EINVAL; 1208 } 1209 } 1210 1211 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1212 } 1213 1214 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1215 { 1216 u8 buf[UUID_SIZE]; 1217 guid_t guid; 1218 int ret; 1219 1220 mutex_lock(&mgr->lock); 1221 if (!mgr->mst_primary) 1222 goto out_fail; 1223 1224 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1225 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1226 goto out_fail; 1227 } 1228 1229 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1230 DP_MST_EN | 1231 DP_UP_REQ_EN | 1232 DP_UPSTREAM_IS_SRC); 1233 if (ret < 0) { 1234 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1235 goto out_fail; 1236 } 1237 1238 /* Some hubs forget their guids after they resume */ 1239 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1240 if (ret != sizeof(buf)) { 1241 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1242 goto out_fail; 1243 } 1244 1245 import_guid(&guid, buf); 1246 1247 if (guid_is_null(&guid)) { 1248 guid_gen(&guid); 1249 export_guid(buf, &guid); 1250 1251 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1252 1253 if (ret != sizeof(buf)) { 1254 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1255 goto out_fail; 1256 } 1257 } 1258 1259 guid_copy(&mgr->mst_primary->guid, &guid); 1260 1261 out_fail: 1262 mutex_unlock(&mgr->lock); 1263 } 1264 1265 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1266 { 1267 struct amdgpu_dm_connector *aconnector; 1268 struct drm_connector *connector; 1269 struct drm_connector_list_iter iter; 1270 struct drm_dp_mst_topology_mgr *mgr; 1271 1272 drm_connector_list_iter_begin(dev, &iter); 1273 drm_for_each_connector_iter(connector, &iter) { 1274 1275 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1276 continue; 1277 1278 aconnector = to_amdgpu_dm_connector(connector); 1279 if (aconnector->dc_link->type != dc_connection_mst_branch || 1280 aconnector->mst_root) 1281 continue; 1282 1283 mgr = &aconnector->mst_mgr; 1284 1285 if (suspend) { 1286 drm_dp_mst_topology_mgr_suspend(mgr); 1287 } else { 1288 /* if extended timeout is supported in hardware, 1289 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1290 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1291 */ 1292 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1293 if (!dp_is_lttpr_present(aconnector->dc_link)) 1294 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1295 1296 /* TODO: move resume_mst_branch_status() into drm mst resume again 1297 * once topology probing work is pulled out from mst resume into mst 1298 * resume 2nd step. mst resume 2nd step should be called after old 1299 * state getting restored (i.e. drm_atomic_helper_resume()). 1300 */ 1301 resume_mst_branch_status(mgr); 1302 } 1303 } 1304 drm_connector_list_iter_end(&iter); 1305 } 1306 1307 static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1308 { 1309 struct amdgpu_display_manager *dm = &adev->dm; 1310 struct amdgpu_i2c_adapter *oem_i2c; 1311 struct ddc_service *oem_ddc_service; 1312 int r; 1313 1314 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1315 if (oem_ddc_service) { 1316 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1317 if (!oem_i2c) { 1318 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1319 return -ENOMEM; 1320 } 1321 1322 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1323 if (r) { 1324 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1325 kfree(oem_i2c); 1326 return r; 1327 } 1328 dm->oem_i2c = oem_i2c; 1329 } 1330 1331 return 0; 1332 } 1333 1334 /** 1335 * dm_hw_init() - Initialize DC device 1336 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1337 * 1338 * Initialize the &struct amdgpu_display_manager device. This involves calling 1339 * the initializers of each DM component, then populating the struct with them. 1340 * 1341 * Although the function implies hardware initialization, both hardware and 1342 * software are initialized here. Splitting them out to their relevant init 1343 * hooks is a future TODO item. 1344 * 1345 * Some notable things that are initialized here: 1346 * 1347 * - Display Core, both software and hardware 1348 * - DC modules that we need (freesync and color management) 1349 * - DRM software states 1350 * - Interrupt sources and handlers 1351 * - Vblank support 1352 * - Debug FS entries, if enabled 1353 */ 1354 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1355 { 1356 struct amdgpu_device *adev = ip_block->adev; 1357 int r; 1358 1359 adev->dm.i2c_devres_group = devres_open_group(adev->dev, NULL, GFP_KERNEL); 1360 if (!adev->dm.i2c_devres_group) 1361 return -ENOMEM; 1362 1363 /* Create DAL display manager */ 1364 r = amdgpu_dm_init(adev); 1365 if (r) 1366 goto err_release_i2c; 1367 amdgpu_dm_hpd_init(adev); 1368 1369 r = dm_oem_i2c_hw_init(adev); 1370 if (r) 1371 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1372 1373 devres_close_group(adev->dev, adev->dm.i2c_devres_group); 1374 return 0; 1375 1376 err_release_i2c: 1377 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1378 return r; 1379 } 1380 1381 /** 1382 * dm_hw_fini() - Teardown DC device 1383 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1384 * 1385 * Teardown components within &struct amdgpu_display_manager that require 1386 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1387 * were loaded. Also flush IRQ workqueues and disable them. 1388 */ 1389 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1390 { 1391 struct amdgpu_device *adev = ip_block->adev; 1392 1393 if (adev->dm.i2c_devres_group) 1394 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1395 1396 amdgpu_dm_hpd_fini(adev); 1397 1398 amdgpu_dm_fini(adev); 1399 return 0; 1400 } 1401 1402 1403 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1404 struct dc_state *state, bool enable) 1405 { 1406 enum dc_irq_source irq_source; 1407 struct amdgpu_crtc *acrtc; 1408 int rc = -EBUSY; 1409 int i = 0; 1410 1411 for (i = 0; i < state->stream_count; i++) { 1412 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1413 adev, state->stream_status[i].primary_otg_inst); 1414 1415 if (acrtc && state->stream_status[i].plane_count != 0 && 1416 amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 1417 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1418 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1419 if (rc) 1420 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1421 enable ? "enable" : "disable"); 1422 1423 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1424 if (enable) { 1425 if (amdgpu_dm_crtc_vrr_active( 1426 to_dm_crtc_state(acrtc->base.state))) 1427 rc = amdgpu_dm_crtc_set_vupdate_irq( 1428 &acrtc->base, true); 1429 } else 1430 rc = amdgpu_dm_crtc_set_vupdate_irq( 1431 &acrtc->base, false); 1432 1433 if (rc) 1434 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1435 enable ? "en" : "dis"); 1436 } 1437 1438 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1439 /* During gpu-reset we disable and then enable vblank irq, so 1440 * don't use amdgpu_irq_get/put() to avoid refcount change. 1441 */ 1442 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 1443 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1444 1445 } else if (acrtc && state->stream_status[i].plane_count != 0) { 1446 /* DCN only needs to toggle VUPDATE_NO_LOCK */ 1447 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, enable); 1448 if (rc) 1449 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1450 enable ? "en" : "dis"); 1451 } 1452 } 1453 1454 } 1455 1456 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 1457 1458 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1459 { 1460 struct dc_state *context __free(state_release) = NULL; 1461 int i; 1462 struct dc_stream_state *del_streams[MAX_PIPES]; 1463 int del_streams_count = 0; 1464 struct dc_commit_streams_params params = {}; 1465 1466 memset(del_streams, 0, sizeof(del_streams)); 1467 1468 context = dc_state_create_current_copy(dc); 1469 if (context == NULL) 1470 return DC_ERROR_UNEXPECTED; 1471 1472 /* First remove from context all streams */ 1473 for (i = 0; i < context->stream_count; i++) { 1474 struct dc_stream_state *stream = context->streams[i]; 1475 1476 del_streams[del_streams_count++] = stream; 1477 } 1478 1479 /* Remove all planes for removed streams and then remove the streams */ 1480 for (i = 0; i < del_streams_count; i++) { 1481 enum dc_status res; 1482 1483 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1484 return DC_FAIL_DETACH_SURFACES; 1485 1486 res = dc_state_remove_stream(dc, context, del_streams[i]); 1487 if (res != DC_OK) 1488 return res; 1489 } 1490 1491 params.streams = context->streams; 1492 params.stream_count = context->stream_count; 1493 1494 return dc_commit_streams(dc, ¶ms); 1495 } 1496 1497 static int dm_cache_state(struct amdgpu_device *adev) 1498 { 1499 int r; 1500 1501 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1502 if (IS_ERR(adev->dm.cached_state)) { 1503 r = PTR_ERR(adev->dm.cached_state); 1504 adev->dm.cached_state = NULL; 1505 } 1506 1507 return adev->dm.cached_state ? 0 : r; 1508 } 1509 1510 static void dm_destroy_cached_state(struct amdgpu_device *adev) 1511 { 1512 struct amdgpu_display_manager *dm = &adev->dm; 1513 struct drm_device *ddev = adev_to_drm(adev); 1514 struct dm_plane_state *dm_new_plane_state; 1515 struct drm_plane_state *new_plane_state; 1516 struct dm_crtc_state *dm_new_crtc_state; 1517 struct drm_crtc_state *new_crtc_state; 1518 struct drm_plane *plane; 1519 struct drm_crtc *crtc; 1520 int i; 1521 1522 if (!dm->cached_state) 1523 return; 1524 1525 /* Force mode set in atomic commit */ 1526 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1527 new_crtc_state->active_changed = true; 1528 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1529 amdgpu_dm_reset_freesync_config_for_crtc(dm_new_crtc_state); 1530 } 1531 1532 /* 1533 * atomic_check is expected to create the dc states. We need to release 1534 * them here, since they were duplicated as part of the suspend 1535 * procedure. 1536 */ 1537 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1538 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1539 if (dm_new_crtc_state->stream) { 1540 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1541 dc_stream_release(dm_new_crtc_state->stream); 1542 dm_new_crtc_state->stream = NULL; 1543 } 1544 dm_new_crtc_state->base.color_mgmt_changed = true; 1545 } 1546 1547 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1548 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1549 if (dm_new_plane_state->dc_state) { 1550 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1551 dc_plane_state_release(dm_new_plane_state->dc_state); 1552 dm_new_plane_state->dc_state = NULL; 1553 } 1554 } 1555 1556 drm_atomic_helper_resume(ddev, dm->cached_state); 1557 1558 dm->cached_state = NULL; 1559 } 1560 1561 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1562 { 1563 struct amdgpu_device *adev = ip_block->adev; 1564 struct amdgpu_display_manager *dm = &adev->dm; 1565 1566 if (amdgpu_in_reset(adev)) { 1567 enum dc_status res; 1568 1569 /* Quiesce ISM workers before taking dc_lock (workers take 1570 * dc_lock themselves; syncing under it would deadlock). 1571 */ 1572 amdgpu_dm_ism_disable(dm); 1573 1574 mutex_lock(&dm->dc_lock); 1575 1576 amdgpu_dm_ism_force_full_power(dm); 1577 dc_allow_idle_optimizations(adev->dm.dc, false); 1578 1579 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1580 1581 if (dm->cached_dc_state) 1582 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1583 1584 res = amdgpu_dm_commit_zero_streams(dm->dc); 1585 if (res != DC_OK) { 1586 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1587 return -EINVAL; 1588 } 1589 1590 amdgpu_dm_irq_suspend(adev); 1591 1592 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1593 1594 return 0; 1595 } 1596 1597 if (!adev->dm.cached_state) { 1598 int r = dm_cache_state(adev); 1599 1600 if (r) 1601 return r; 1602 } 1603 1604 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1605 1606 s3_handle_mst(adev_to_drm(adev), true); 1607 1608 amdgpu_dm_irq_suspend(adev); 1609 1610 /* 1611 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1612 * themselves; syncing under it would deadlock). 1613 */ 1614 amdgpu_dm_ism_disable(dm); 1615 scoped_guard(mutex, &dm->dc_lock) 1616 amdgpu_dm_ism_force_full_power(dm); 1617 1618 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1619 1620 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1621 1622 if (dm->dc->caps.ips_support && adev->in_s0ix) 1623 dc_allow_idle_optimizations(dm->dc, true); 1624 1625 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1626 1627 return 0; 1628 } 1629 1630 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1631 { 1632 struct dc_sink_init_data sink_init_data = { 0 }; 1633 struct display_sink_capability sink_caps = { 0 }; 1634 enum dc_edid_status edid_status; 1635 struct dc_context *dc_ctx = link->ctx; 1636 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1637 struct dc_sink *sink = NULL; 1638 struct dc_sink *prev_sink = NULL; 1639 1640 link->type = dc_connection_none; 1641 prev_sink = link->local_sink; 1642 1643 if (prev_sink) 1644 dc_sink_release(prev_sink); 1645 1646 switch (link->connector_signal) { 1647 case SIGNAL_TYPE_HDMI_TYPE_A: { 1648 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1649 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1650 break; 1651 } 1652 1653 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1654 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1655 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1656 break; 1657 } 1658 1659 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1660 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1661 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1662 break; 1663 } 1664 1665 case SIGNAL_TYPE_LVDS: { 1666 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1667 sink_caps.signal = SIGNAL_TYPE_LVDS; 1668 break; 1669 } 1670 1671 case SIGNAL_TYPE_EDP: { 1672 sink_caps.transaction_type = 1673 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1674 sink_caps.signal = SIGNAL_TYPE_EDP; 1675 break; 1676 } 1677 1678 case SIGNAL_TYPE_DISPLAY_PORT: { 1679 sink_caps.transaction_type = 1680 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1681 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1682 break; 1683 } 1684 1685 default: 1686 drm_err(dev, "Invalid connector type! signal:%d\n", 1687 link->connector_signal); 1688 return; 1689 } 1690 1691 sink_init_data.link = link; 1692 sink_init_data.sink_signal = sink_caps.signal; 1693 1694 sink = dc_sink_create(&sink_init_data); 1695 if (!sink) { 1696 drm_err(dev, "Failed to create sink!\n"); 1697 return; 1698 } 1699 1700 /* dc_sink_create returns a new reference */ 1701 link->local_sink = sink; 1702 1703 edid_status = dm_helpers_read_local_edid( 1704 link->ctx, 1705 link, 1706 sink); 1707 1708 if (edid_status != EDID_OK) 1709 drm_err(dev, "Failed to read EDID\n"); 1710 1711 } 1712 1713 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1714 struct amdgpu_display_manager *dm) 1715 { 1716 struct { 1717 struct dc_surface_update surface_updates[MAX_SURFACES]; 1718 struct dc_plane_info plane_infos[MAX_SURFACES]; 1719 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1720 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1721 struct dc_stream_update stream_update; 1722 } *bundle __free(kfree); 1723 int k, m; 1724 1725 bundle = kzalloc_obj(*bundle); 1726 1727 if (!bundle) { 1728 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1729 return; 1730 } 1731 1732 for (k = 0; k < dc_state->stream_count; k++) { 1733 bundle->stream_update.stream = dc_state->streams[k]; 1734 1735 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1736 bundle->surface_updates[m].surface = 1737 dc_state->stream_status[k].plane_states[m]; 1738 bundle->surface_updates[m].surface->force_full_update = 1739 true; 1740 } 1741 1742 update_planes_and_stream_adapter(dm->dc, 1743 UPDATE_TYPE_FULL, 1744 dc_state->stream_status[k].plane_count, 1745 dc_state->streams[k], 1746 &bundle->stream_update, 1747 bundle->surface_updates); 1748 } 1749 } 1750 1751 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1752 struct dc_sink *sink) 1753 { 1754 struct dc_panel_patch *ppatch = NULL; 1755 1756 if (!sink) 1757 return; 1758 1759 ppatch = &sink->edid_caps.panel_patch; 1760 if (ppatch->wait_after_dpcd_poweroff_ms) { 1761 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1762 drm_dbg_driver(adev_to_drm(adev), 1763 "%s: adding a %ds delay as w/a for panel\n", 1764 __func__, 1765 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1766 } 1767 } 1768 EXPORT_IF_KUNIT(amdgpu_dm_apply_delay_after_dpcd_poweroff); 1769 1770 /** 1771 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1772 * @adev: amdgpu device pointer 1773 * 1774 * Iterates through all DC links and dumps information about local and remote 1775 * (MST) sinks. Should be called after connector detection is complete to see 1776 * the final state of all links. 1777 */ 1778 static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1779 { 1780 struct dc *dc = adev->dm.dc; 1781 struct drm_device *dev = adev_to_drm(adev); 1782 int li; 1783 1784 if (!dc) 1785 return; 1786 1787 for (li = 0; li < dc->link_count; li++) { 1788 struct dc_link *l = dc->links[li]; 1789 const char *name = NULL; 1790 int rs; 1791 1792 if (!l) 1793 continue; 1794 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1795 name = l->local_sink->edid_caps.display_name; 1796 else 1797 name = "n/a"; 1798 1799 drm_dbg_kms(dev, 1800 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1801 li, 1802 l->local_sink, 1803 l->type, 1804 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1805 l->sink_count, 1806 name, 1807 l->dpcd_caps.is_mst_capable, 1808 l->mst_stream_alloc_table.stream_count); 1809 1810 /* Dump remote (MST) sinks if any */ 1811 for (rs = 0; rs < l->sink_count; rs++) { 1812 struct dc_sink *rsink = l->remote_sinks[rs]; 1813 const char *rname = NULL; 1814 1815 if (!rsink) 1816 continue; 1817 if (rsink->edid_caps.display_name[0]) 1818 rname = rsink->edid_caps.display_name; 1819 else 1820 rname = "n/a"; 1821 drm_dbg_kms(dev, 1822 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1823 li, rs, 1824 rsink, 1825 rsink->sink_signal, 1826 rname); 1827 } 1828 } 1829 } 1830 1831 static int dm_resume(struct amdgpu_ip_block *ip_block) 1832 { 1833 struct amdgpu_device *adev = ip_block->adev; 1834 struct drm_device *ddev = adev_to_drm(adev); 1835 struct amdgpu_display_manager *dm = &adev->dm; 1836 struct amdgpu_dm_connector *aconnector; 1837 struct drm_connector *connector; 1838 struct drm_connector_list_iter iter; 1839 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1840 enum dc_connection_type new_connection_type = dc_connection_none; 1841 struct dc_state *dc_state; 1842 int i, r, j; 1843 struct dc_commit_streams_params commit_params = {}; 1844 1845 if (dm->dc->caps.ips_support) { 1846 if (!amdgpu_in_reset(adev)) 1847 mutex_lock(&dm->dc_lock); 1848 1849 /* Need to set POWER_STATE_D0 first or it will not execute 1850 * idle_power_optimizations command to DMUB. 1851 */ 1852 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1853 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 1854 1855 if (!amdgpu_in_reset(adev)) 1856 mutex_unlock(&dm->dc_lock); 1857 } 1858 1859 if (amdgpu_in_reset(adev)) { 1860 dc_state = dm->cached_dc_state; 1861 1862 /* 1863 * The dc->current_state is backed up into dm->cached_dc_state 1864 * before we commit 0 streams. 1865 * 1866 * DC will clear link encoder assignments on the real state 1867 * but the changes won't propagate over to the copy we made 1868 * before the 0 streams commit. 1869 * 1870 * DC expects that link encoder assignments are *not* valid 1871 * when committing a state, so as a workaround we can copy 1872 * off of the current state. 1873 * 1874 * We lose the previous assignments, but we had already 1875 * commit 0 streams anyway. 1876 */ 1877 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 1878 1879 r = dm_dmub_hw_init(adev); 1880 if (r) { 1881 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 1882 return r; 1883 } 1884 1885 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1886 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1887 1888 dc_resume(dm->dc); 1889 1890 amdgpu_dm_ism_enable(dm); 1891 amdgpu_dm_irq_resume_early(adev); 1892 1893 for (i = 0; i < dc_state->stream_count; i++) { 1894 dc_state->streams[i]->mode_changed = true; 1895 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 1896 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 1897 } 1898 } 1899 1900 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1901 amdgpu_dm_outbox_init(adev); 1902 dc_enable_dmub_outbox(adev->dm.dc); 1903 } 1904 1905 commit_params.streams = dc_state->streams; 1906 commit_params.stream_count = dc_state->stream_count; 1907 dc_exit_ips_for_hw_access(dm->dc); 1908 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 1909 1910 dm_gpureset_commit_state(dm->cached_dc_state, dm); 1911 1912 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 1913 1914 dc_state_release(dm->cached_dc_state); 1915 dm->cached_dc_state = NULL; 1916 1917 amdgpu_dm_irq_resume_late(adev); 1918 1919 mutex_unlock(&dm->dc_lock); 1920 1921 /* set the backlight after a reset */ 1922 for (i = 0; i < dm->num_of_edps; i++) { 1923 if (dm->backlight_dev[i]) 1924 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 1925 } 1926 1927 return 0; 1928 } 1929 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 1930 dc_state_release(dm_state->context); 1931 dm_state->context = dc_state_create(dm->dc, NULL); 1932 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 1933 1934 /* Before powering on DC we need to re-initialize DMUB. */ 1935 dm_dmub_hw_resume(adev); 1936 1937 /* Re-enable outbox interrupts for DPIA. */ 1938 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1939 amdgpu_dm_outbox_init(adev); 1940 dc_enable_dmub_outbox(adev->dm.dc); 1941 } 1942 1943 /* power on hardware */ 1944 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1945 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 1946 1947 /* program HPD filter */ 1948 dc_resume(dm->dc); 1949 1950 scoped_guard(mutex, &dm->dc_lock) 1951 amdgpu_dm_ism_enable(dm); 1952 1953 /* 1954 * early enable HPD Rx IRQ, should be done before set mode as short 1955 * pulse interrupts are used for MST 1956 */ 1957 amdgpu_dm_irq_resume_early(adev); 1958 1959 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 1960 1961 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 1962 s3_handle_mst(ddev, false); 1963 1964 /* Do detection*/ 1965 drm_connector_list_iter_begin(ddev, &iter); 1966 drm_for_each_connector_iter(connector, &iter) { 1967 bool ret; 1968 1969 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1970 continue; 1971 1972 aconnector = to_amdgpu_dm_connector(connector); 1973 1974 if (!aconnector->dc_link) 1975 continue; 1976 1977 /* 1978 * this is the case when traversing through already created end sink 1979 * MST connectors, should be skipped 1980 */ 1981 if (aconnector->mst_root) 1982 continue; 1983 1984 /* Skip eDP detection, when there is no sink present */ 1985 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 1986 !aconnector->dc_link->edp_sink_present) 1987 continue; 1988 1989 guard(mutex)(&aconnector->hpd_lock); 1990 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 1991 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 1992 1993 if (aconnector->base.force && new_connection_type == dc_connection_none) { 1994 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 1995 } else { 1996 guard(mutex)(&dm->dc_lock); 1997 dc_exit_ips_for_hw_access(dm->dc); 1998 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 1999 if (ret) { 2000 /* w/a delay for certain panels */ 2001 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2002 } 2003 } 2004 2005 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2006 aconnector->fake_enable = false; 2007 2008 if (aconnector->dc_sink) 2009 dc_sink_release(aconnector->dc_sink); 2010 aconnector->dc_sink = NULL; 2011 amdgpu_dm_update_connector_after_detect(aconnector); 2012 } 2013 drm_connector_list_iter_end(&iter); 2014 2015 dm_destroy_cached_state(adev); 2016 2017 /* Do mst topology probing after resuming cached state*/ 2018 drm_connector_list_iter_begin(ddev, &iter); 2019 drm_for_each_connector_iter(connector, &iter) { 2020 bool init = false; 2021 2022 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2023 continue; 2024 2025 aconnector = to_amdgpu_dm_connector(connector); 2026 if (aconnector->dc_link->type != dc_connection_mst_branch || 2027 aconnector->mst_root) 2028 continue; 2029 2030 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2031 init = !aconnector->mst_mgr.mst_primary; 2032 } 2033 if (init) 2034 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2035 aconnector->dc_link, false); 2036 else 2037 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2038 } 2039 drm_connector_list_iter_end(&iter); 2040 2041 /* Debug dump: list all DC links and their associated sinks after detection 2042 * is complete for all connectors. This provides a comprehensive view of the 2043 * final state without repeating the dump for each connector. 2044 */ 2045 amdgpu_dm_dump_links_and_sinks(adev); 2046 2047 amdgpu_dm_irq_resume_late(adev); 2048 2049 amdgpu_dm_smu_write_watermarks_table(adev); 2050 2051 drm_kms_helper_hotplug_event(ddev); 2052 2053 return 0; 2054 } 2055 2056 /** 2057 * DOC: DM Lifecycle 2058 * 2059 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2060 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2061 * the base driver's device list to be initialized and torn down accordingly. 2062 * 2063 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2064 */ 2065 2066 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2067 .name = "dm", 2068 .early_init = dm_early_init, 2069 .late_init = dm_late_init, 2070 .sw_init = dm_sw_init, 2071 .sw_fini = dm_sw_fini, 2072 .early_fini = amdgpu_dm_early_fini, 2073 .hw_init = dm_hw_init, 2074 .hw_fini = dm_hw_fini, 2075 .suspend = dm_suspend, 2076 .resume = dm_resume, 2077 .is_idle = dm_is_idle, 2078 .wait_for_idle = dm_wait_for_idle, 2079 .soft_reset = dm_soft_reset, 2080 .set_clockgating_state = dm_set_clockgating_state, 2081 .set_powergating_state = dm_set_powergating_state, 2082 }; 2083 2084 const struct amdgpu_ip_block_version dm_ip_block = { 2085 .type = AMD_IP_BLOCK_TYPE_DCE, 2086 .major = 1, 2087 .minor = 0, 2088 .rev = 0, 2089 .funcs = &amdgpu_dm_funcs, 2090 }; 2091 2092 2093 /** 2094 * DOC: atomic 2095 * 2096 * *WIP* 2097 */ 2098 2099 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2100 .fb_create = amdgpu_display_user_framebuffer_create, 2101 .get_format_info = amdgpu_dm_plane_get_format_info, 2102 .atomic_check = amdgpu_dm_atomic_check, 2103 .atomic_commit = drm_atomic_helper_commit, 2104 }; 2105 2106 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2107 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2108 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2109 }; 2110 2111 /* 2112 * Acquires the lock for the atomic state object and returns 2113 * the new atomic state. 2114 * 2115 * This should only be called during atomic check. 2116 */ 2117 int dm_atomic_get_state(struct drm_atomic_commit *state, 2118 struct dm_atomic_state **dm_state) 2119 { 2120 struct drm_device *dev = state->dev; 2121 struct amdgpu_device *adev = drm_to_adev(dev); 2122 struct amdgpu_display_manager *dm = &adev->dm; 2123 struct drm_private_state *priv_state; 2124 2125 if (*dm_state) 2126 return 0; 2127 2128 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2129 if (IS_ERR(priv_state)) 2130 return PTR_ERR(priv_state); 2131 2132 *dm_state = to_dm_atomic_state(priv_state); 2133 2134 return 0; 2135 } 2136 2137 STATIC_IFN_KUNIT struct dm_atomic_state * 2138 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2139 { 2140 struct drm_device *dev = state->dev; 2141 struct amdgpu_device *adev = drm_to_adev(dev); 2142 struct amdgpu_display_manager *dm = &adev->dm; 2143 struct drm_private_obj *obj; 2144 struct drm_private_state *new_obj_state; 2145 int i; 2146 2147 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2148 if (obj->funcs == dm->atomic_obj.funcs) 2149 return to_dm_atomic_state(new_obj_state); 2150 } 2151 2152 return NULL; 2153 } 2154 EXPORT_IF_KUNIT(dm_atomic_get_new_state); 2155 2156 static struct drm_private_state * 2157 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2158 { 2159 struct dm_atomic_state *old_state, *new_state; 2160 2161 new_state = kzalloc_obj(*new_state); 2162 if (!new_state) 2163 return NULL; 2164 2165 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2166 2167 old_state = to_dm_atomic_state(obj->state); 2168 2169 if (old_state && old_state->context) 2170 new_state->context = dc_state_create_copy(old_state->context); 2171 2172 if (!new_state->context) { 2173 kfree(new_state); 2174 return NULL; 2175 } 2176 2177 return &new_state->base; 2178 } 2179 2180 STATIC_IFN_KUNIT void dm_atomic_destroy_state(struct drm_private_obj *obj, 2181 struct drm_private_state *state) 2182 { 2183 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2184 2185 if (dm_state && dm_state->context) 2186 dc_state_release(dm_state->context); 2187 2188 kfree(dm_state); 2189 } 2190 EXPORT_IF_KUNIT(dm_atomic_destroy_state); 2191 2192 static struct drm_private_state * 2193 dm_atomic_create_state(struct drm_private_obj *obj) 2194 { 2195 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2196 struct dm_atomic_state *dm_state; 2197 struct dc_state *context; 2198 2199 dm_state = kzalloc_obj(*dm_state); 2200 if (!dm_state) 2201 return ERR_PTR(-ENOMEM); 2202 2203 context = dc_state_create_current_copy(adev->dm.dc); 2204 if (!context) { 2205 kfree(dm_state); 2206 return ERR_PTR(-ENOMEM); 2207 } 2208 2209 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2210 dm_state->context = context; 2211 2212 return &dm_state->base; 2213 } 2214 2215 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2216 .atomic_create_state = dm_atomic_create_state, 2217 .atomic_duplicate_state = dm_atomic_duplicate_state, 2218 .atomic_destroy_state = dm_atomic_destroy_state, 2219 }; 2220 2221 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2222 { 2223 int r; 2224 2225 adev->mode_info.mode_config_initialized = true; 2226 2227 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2228 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2229 2230 adev_to_drm(adev)->mode_config.max_width = 16384; 2231 adev_to_drm(adev)->mode_config.max_height = 16384; 2232 2233 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2234 if (adev->asic_type == CHIP_HAWAII) 2235 /* disable prefer shadow for now due to hibernation issues */ 2236 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2237 else 2238 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2239 /* indicates support for immediate flip */ 2240 adev_to_drm(adev)->mode_config.async_page_flip = true; 2241 2242 drm_atomic_private_obj_init(adev_to_drm(adev), 2243 &adev->dm.atomic_obj, 2244 &dm_atomic_state_funcs); 2245 2246 r = amdgpu_display_modeset_create_props(adev); 2247 if (r) 2248 return r; 2249 2250 #ifdef AMD_PRIVATE_COLOR 2251 if (amdgpu_dm_create_color_properties(adev)) 2252 return -ENOMEM; 2253 #endif 2254 2255 r = amdgpu_dm_audio_init(adev); 2256 if (r) 2257 return r; 2258 2259 return 0; 2260 } 2261 2262 static int initialize_plane(struct amdgpu_display_manager *dm, 2263 struct amdgpu_mode_info *mode_info, int plane_id, 2264 enum drm_plane_type plane_type, 2265 const struct dc_plane_cap *plane_cap) 2266 { 2267 struct drm_plane *plane; 2268 unsigned long possible_crtcs; 2269 int ret = 0; 2270 2271 plane = kzalloc_obj(struct drm_plane); 2272 if (!plane) { 2273 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2274 return -ENOMEM; 2275 } 2276 plane->type = plane_type; 2277 2278 /* 2279 * HACK: IGT tests expect that the primary plane for a CRTC 2280 * can only have one possible CRTC. Only expose support for 2281 * any CRTC if they're not going to be used as a primary plane 2282 * for a CRTC - like overlay or underlay planes. 2283 */ 2284 possible_crtcs = 1 << plane_id; 2285 if (plane_id >= dm->dc->caps.max_streams) 2286 possible_crtcs = 0xff; 2287 2288 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2289 2290 if (ret) { 2291 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2292 kfree(plane); 2293 return ret; 2294 } 2295 2296 if (mode_info) 2297 mode_info->planes[plane_id] = plane; 2298 2299 return ret; 2300 } 2301 2302 2303 /* 2304 * In this architecture, the association 2305 * connector -> encoder -> crtc 2306 * id not really requried. The crtc and connector will hold the 2307 * display_index as an abstraction to use with DAL component 2308 * 2309 * Returns 0 on success 2310 */ 2311 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2312 { 2313 struct amdgpu_display_manager *dm = &adev->dm; 2314 s32 i; 2315 struct amdgpu_dm_connector *aconnector = NULL; 2316 struct amdgpu_encoder *aencoder = NULL; 2317 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2318 u32 link_cnt; 2319 s32 primary_planes; 2320 enum dc_connection_type new_connection_type = dc_connection_none; 2321 const struct dc_plane_cap *plane; 2322 bool psr_feature_enabled = false; 2323 bool replay_feature_enabled = false; 2324 int max_overlay = dm->dc->caps.max_slave_planes; 2325 2326 dm->display_indexes_num = dm->dc->caps.max_streams; 2327 /* Update the actual used number of crtc */ 2328 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2329 2330 amdgpu_dm_set_irq_funcs(adev); 2331 2332 link_cnt = dm->dc->caps.max_links; 2333 if (amdgpu_dm_mode_config_init(dm->adev)) { 2334 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2335 return -EINVAL; 2336 } 2337 2338 /* There is one primary plane per CRTC */ 2339 primary_planes = dm->dc->caps.max_streams; 2340 if (primary_planes > AMDGPU_MAX_PLANES) { 2341 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2342 return -EINVAL; 2343 } 2344 2345 /* 2346 * Initialize primary planes, implicit planes for legacy IOCTLS. 2347 * Order is reversed to match iteration order in atomic check. 2348 */ 2349 for (i = (primary_planes - 1); i >= 0; i--) { 2350 plane = &dm->dc->caps.planes[i]; 2351 2352 if (initialize_plane(dm, mode_info, i, 2353 DRM_PLANE_TYPE_PRIMARY, plane)) { 2354 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2355 goto fail; 2356 } 2357 } 2358 2359 /* 2360 * Initialize overlay planes, index starting after primary planes. 2361 * These planes have a higher DRM index than the primary planes since 2362 * they should be considered as having a higher z-order. 2363 * Order is reversed to match iteration order in atomic check. 2364 * 2365 * Only support DCN for now, and only expose one so we don't encourage 2366 * userspace to use up all the pipes. 2367 */ 2368 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2369 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2370 2371 /* Do not create overlay if MPO disabled */ 2372 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2373 break; 2374 2375 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2376 continue; 2377 2378 if (!plane->pixel_format_support.argb8888) 2379 continue; 2380 2381 if (max_overlay-- == 0) 2382 break; 2383 2384 if (initialize_plane(dm, NULL, primary_planes + i, 2385 DRM_PLANE_TYPE_OVERLAY, plane)) { 2386 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2387 goto fail; 2388 } 2389 } 2390 2391 for (i = 0; i < dm->dc->caps.max_streams; i++) 2392 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2393 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2394 goto fail; 2395 } 2396 2397 /* Use Outbox interrupt */ 2398 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2399 case IP_VERSION(3, 0, 0): 2400 case IP_VERSION(3, 1, 2): 2401 case IP_VERSION(3, 1, 3): 2402 case IP_VERSION(3, 1, 4): 2403 case IP_VERSION(3, 1, 5): 2404 case IP_VERSION(3, 1, 6): 2405 case IP_VERSION(3, 2, 0): 2406 case IP_VERSION(3, 2, 1): 2407 case IP_VERSION(2, 1, 0): 2408 case IP_VERSION(3, 5, 0): 2409 case IP_VERSION(3, 5, 1): 2410 case IP_VERSION(3, 6, 0): 2411 case IP_VERSION(4, 0, 1): 2412 case IP_VERSION(4, 2, 0): 2413 case IP_VERSION(4, 2, 1): 2414 case IP_VERSION(6, 0, 0): 2415 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2416 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2417 goto fail; 2418 } 2419 break; 2420 default: 2421 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2422 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2423 } 2424 2425 /* Determine whether to enable PSR support by default. */ 2426 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2427 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2428 case IP_VERSION(3, 1, 2): 2429 case IP_VERSION(3, 1, 3): 2430 case IP_VERSION(3, 1, 4): 2431 case IP_VERSION(3, 1, 5): 2432 case IP_VERSION(3, 1, 6): 2433 case IP_VERSION(3, 2, 0): 2434 case IP_VERSION(3, 2, 1): 2435 case IP_VERSION(3, 5, 0): 2436 case IP_VERSION(3, 5, 1): 2437 case IP_VERSION(3, 6, 0): 2438 case IP_VERSION(4, 0, 1): 2439 case IP_VERSION(4, 2, 0): 2440 case IP_VERSION(4, 2, 1): 2441 case IP_VERSION(6, 0, 0): 2442 psr_feature_enabled = true; 2443 break; 2444 default: 2445 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2446 break; 2447 } 2448 } 2449 2450 /* Determine whether to enable Replay support by default. */ 2451 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2452 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2453 case IP_VERSION(3, 1, 4): 2454 case IP_VERSION(3, 2, 0): 2455 case IP_VERSION(3, 2, 1): 2456 case IP_VERSION(3, 5, 0): 2457 case IP_VERSION(3, 5, 1): 2458 case IP_VERSION(3, 6, 0): 2459 case IP_VERSION(4, 2, 0): 2460 case IP_VERSION(4, 2, 1): 2461 case IP_VERSION(6, 0, 0): 2462 replay_feature_enabled = true; 2463 break; 2464 2465 default: 2466 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2467 break; 2468 } 2469 } 2470 2471 if (link_cnt > MAX_LINKS) { 2472 drm_err(adev_to_drm(adev), 2473 "KMS: Cannot support more than %d display indexes\n", 2474 MAX_LINKS); 2475 goto fail; 2476 } 2477 2478 /* loops over all connectors on the board */ 2479 for (i = 0; i < link_cnt; i++) { 2480 struct dc_link *link = NULL; 2481 2482 link = dc_get_link_at_index(dm->dc, i); 2483 2484 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2485 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2486 2487 if (!wbcon) { 2488 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2489 continue; 2490 } 2491 2492 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2493 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2494 kfree(wbcon); 2495 continue; 2496 } 2497 2498 link->psr_settings.psr_feature_enabled = false; 2499 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2500 2501 continue; 2502 } 2503 2504 aconnector = kzalloc_obj(*aconnector); 2505 if (!aconnector) 2506 goto fail; 2507 2508 aencoder = kzalloc_obj(*aencoder); 2509 if (!aencoder) 2510 goto fail; 2511 2512 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2513 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2514 goto fail; 2515 } 2516 2517 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2518 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2519 goto fail; 2520 } 2521 2522 if (dm->hpd_rx_offload_wq) 2523 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2524 aconnector; 2525 2526 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2527 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2528 2529 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2530 amdgpu_dm_emulated_link_detect(link); 2531 amdgpu_dm_update_connector_after_detect(aconnector); 2532 } else { 2533 bool ret = false; 2534 2535 mutex_lock(&dm->dc_lock); 2536 dc_exit_ips_for_hw_access(dm->dc); 2537 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2538 mutex_unlock(&dm->dc_lock); 2539 2540 if (ret) { 2541 amdgpu_dm_update_connector_after_detect(aconnector); 2542 amdgpu_dm_setup_backlight_device(dm, aconnector); 2543 2544 /* Disable PSR if Replay can be enabled */ 2545 if (replay_feature_enabled) 2546 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2547 psr_feature_enabled = false; 2548 2549 if (psr_feature_enabled) { 2550 amdgpu_dm_set_psr_caps(link, aconnector); 2551 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2552 aconnector->base.name, 2553 link->psr_settings.psr_feature_enabled, 2554 link->psr_settings.psr_version, 2555 link->dpcd_caps.psr_info.psr_version, 2556 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2557 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2558 } 2559 } 2560 } 2561 amdgpu_set_panel_orientation(&aconnector->base); 2562 } 2563 2564 /* Debug dump: list all DC links and their associated sinks after detection 2565 * is complete for all connectors. This provides a comprehensive view of the 2566 * final state without repeating the dump for each connector. 2567 */ 2568 amdgpu_dm_dump_links_and_sinks(adev); 2569 2570 /* Software is initialized. Now we can register interrupt handlers. */ 2571 switch (adev->asic_type) { 2572 #if defined(CONFIG_DRM_AMD_DC_SI) 2573 case CHIP_TAHITI: 2574 case CHIP_PITCAIRN: 2575 case CHIP_VERDE: 2576 case CHIP_OLAND: 2577 #endif 2578 case CHIP_BONAIRE: 2579 case CHIP_HAWAII: 2580 case CHIP_KAVERI: 2581 case CHIP_KABINI: 2582 case CHIP_MULLINS: 2583 case CHIP_TONGA: 2584 case CHIP_FIJI: 2585 case CHIP_CARRIZO: 2586 case CHIP_STONEY: 2587 case CHIP_POLARIS11: 2588 case CHIP_POLARIS10: 2589 case CHIP_POLARIS12: 2590 case CHIP_VEGAM: 2591 case CHIP_VEGA10: 2592 case CHIP_VEGA12: 2593 case CHIP_VEGA20: 2594 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2595 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2596 goto fail; 2597 } 2598 break; 2599 default: 2600 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2601 case IP_VERSION(1, 0, 0): 2602 case IP_VERSION(1, 0, 1): 2603 case IP_VERSION(2, 0, 2): 2604 case IP_VERSION(2, 0, 3): 2605 case IP_VERSION(2, 0, 0): 2606 case IP_VERSION(2, 1, 0): 2607 case IP_VERSION(3, 0, 0): 2608 case IP_VERSION(3, 0, 2): 2609 case IP_VERSION(3, 0, 3): 2610 case IP_VERSION(3, 0, 1): 2611 case IP_VERSION(3, 1, 2): 2612 case IP_VERSION(3, 1, 3): 2613 case IP_VERSION(3, 1, 4): 2614 case IP_VERSION(3, 1, 5): 2615 case IP_VERSION(3, 1, 6): 2616 case IP_VERSION(3, 2, 0): 2617 case IP_VERSION(3, 2, 1): 2618 case IP_VERSION(3, 5, 0): 2619 case IP_VERSION(3, 5, 1): 2620 case IP_VERSION(3, 6, 0): 2621 case IP_VERSION(4, 0, 1): 2622 case IP_VERSION(4, 2, 0): 2623 case IP_VERSION(4, 2, 1): 2624 case IP_VERSION(6, 0, 0): 2625 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2626 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2627 goto fail; 2628 } 2629 break; 2630 default: 2631 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2632 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2633 goto fail; 2634 } 2635 break; 2636 } 2637 2638 return 0; 2639 fail: 2640 kfree(aencoder); 2641 kfree(aconnector); 2642 2643 return -EINVAL; 2644 } 2645 2646 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2647 { 2648 if (dm->atomic_obj.state) 2649 drm_atomic_private_obj_fini(&dm->atomic_obj); 2650 } 2651 2652 /****************************************************************************** 2653 * amdgpu_display_funcs functions 2654 *****************************************************************************/ 2655 2656 /* 2657 * dm_bandwidth_update - program display watermarks 2658 * 2659 * @adev: amdgpu_device pointer 2660 * 2661 * Calculate and program the display watermarks and line buffer allocation. 2662 */ 2663 STATIC_IFN_KUNIT void dm_bandwidth_update(struct amdgpu_device *adev) 2664 { 2665 /* TODO: implement later */ 2666 } 2667 EXPORT_IF_KUNIT(dm_bandwidth_update); 2668 2669 static const struct amdgpu_display_funcs dm_display_funcs = { 2670 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2671 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2672 .backlight_set_level = NULL, /* never called for DC */ 2673 .backlight_get_level = NULL, /* never called for DC */ 2674 .hpd_sense = NULL,/* called unconditionally */ 2675 .hpd_set_polarity = NULL, /* called unconditionally */ 2676 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2677 .page_flip_get_scanoutpos = 2678 dm_crtc_get_scanoutpos,/* called unconditionally */ 2679 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2680 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2681 }; 2682 2683 #if defined(CONFIG_DEBUG_KERNEL_DC) 2684 2685 static ssize_t s3_debug_store(struct device *device, 2686 struct device_attribute *attr, 2687 const char *buf, 2688 size_t count) 2689 { 2690 int ret; 2691 int s3_state; 2692 struct drm_device *drm_dev = dev_get_drvdata(device); 2693 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2694 struct amdgpu_ip_block *ip_block; 2695 2696 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2697 if (!ip_block) 2698 return -EINVAL; 2699 2700 ret = kstrtoint(buf, 0, &s3_state); 2701 2702 if (ret == 0) { 2703 if (s3_state) { 2704 dm_resume(ip_block); 2705 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2706 } else 2707 dm_suspend(ip_block); 2708 } 2709 2710 return ret == 0 ? count : 0; 2711 } 2712 2713 DEVICE_ATTR_WO(s3_debug); 2714 2715 #endif 2716 2717 static int dm_early_init(struct amdgpu_ip_block *ip_block) 2718 { 2719 struct amdgpu_device *adev = ip_block->adev; 2720 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2721 struct atom_context *ctx = mode_info->atom_context; 2722 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2723 u16 data_offset; 2724 2725 /* if there is no object header, skip DM */ 2726 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2727 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2728 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2729 return -ENOENT; 2730 } 2731 2732 switch (adev->asic_type) { 2733 #if defined(CONFIG_DRM_AMD_DC_SI) 2734 case CHIP_TAHITI: 2735 case CHIP_PITCAIRN: 2736 case CHIP_VERDE: 2737 adev->mode_info.num_crtc = 6; 2738 adev->mode_info.num_hpd = 6; 2739 adev->mode_info.num_dig = 6; 2740 break; 2741 case CHIP_OLAND: 2742 adev->mode_info.num_crtc = 2; 2743 adev->mode_info.num_hpd = 2; 2744 adev->mode_info.num_dig = 2; 2745 break; 2746 #endif 2747 case CHIP_BONAIRE: 2748 case CHIP_HAWAII: 2749 adev->mode_info.num_crtc = 6; 2750 adev->mode_info.num_hpd = 6; 2751 adev->mode_info.num_dig = 6; 2752 break; 2753 case CHIP_KAVERI: 2754 adev->mode_info.num_crtc = 4; 2755 adev->mode_info.num_hpd = 6; 2756 adev->mode_info.num_dig = 7; 2757 break; 2758 case CHIP_KABINI: 2759 case CHIP_MULLINS: 2760 adev->mode_info.num_crtc = 2; 2761 adev->mode_info.num_hpd = 6; 2762 adev->mode_info.num_dig = 6; 2763 break; 2764 case CHIP_FIJI: 2765 case CHIP_TONGA: 2766 adev->mode_info.num_crtc = 6; 2767 adev->mode_info.num_hpd = 6; 2768 adev->mode_info.num_dig = 7; 2769 break; 2770 case CHIP_CARRIZO: 2771 adev->mode_info.num_crtc = 3; 2772 adev->mode_info.num_hpd = 6; 2773 adev->mode_info.num_dig = 9; 2774 break; 2775 case CHIP_STONEY: 2776 adev->mode_info.num_crtc = 2; 2777 adev->mode_info.num_hpd = 6; 2778 adev->mode_info.num_dig = 9; 2779 break; 2780 case CHIP_POLARIS11: 2781 case CHIP_POLARIS12: 2782 adev->mode_info.num_crtc = 5; 2783 adev->mode_info.num_hpd = 5; 2784 adev->mode_info.num_dig = 5; 2785 break; 2786 case CHIP_POLARIS10: 2787 case CHIP_VEGAM: 2788 adev->mode_info.num_crtc = 6; 2789 adev->mode_info.num_hpd = 6; 2790 adev->mode_info.num_dig = 6; 2791 break; 2792 case CHIP_VEGA10: 2793 case CHIP_VEGA12: 2794 case CHIP_VEGA20: 2795 adev->mode_info.num_crtc = 6; 2796 adev->mode_info.num_hpd = 6; 2797 adev->mode_info.num_dig = 6; 2798 break; 2799 default: 2800 2801 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2802 case IP_VERSION(2, 0, 2): 2803 case IP_VERSION(3, 0, 0): 2804 adev->mode_info.num_crtc = 6; 2805 adev->mode_info.num_hpd = 6; 2806 adev->mode_info.num_dig = 6; 2807 break; 2808 case IP_VERSION(2, 0, 0): 2809 case IP_VERSION(3, 0, 2): 2810 adev->mode_info.num_crtc = 5; 2811 adev->mode_info.num_hpd = 5; 2812 adev->mode_info.num_dig = 5; 2813 break; 2814 case IP_VERSION(2, 0, 3): 2815 case IP_VERSION(3, 0, 3): 2816 adev->mode_info.num_crtc = 2; 2817 adev->mode_info.num_hpd = 2; 2818 adev->mode_info.num_dig = 2; 2819 break; 2820 case IP_VERSION(1, 0, 0): 2821 case IP_VERSION(1, 0, 1): 2822 case IP_VERSION(3, 0, 1): 2823 case IP_VERSION(2, 1, 0): 2824 case IP_VERSION(3, 1, 2): 2825 case IP_VERSION(3, 1, 3): 2826 case IP_VERSION(3, 1, 4): 2827 case IP_VERSION(3, 1, 5): 2828 case IP_VERSION(3, 1, 6): 2829 case IP_VERSION(3, 2, 0): 2830 case IP_VERSION(3, 2, 1): 2831 case IP_VERSION(3, 5, 0): 2832 case IP_VERSION(3, 5, 1): 2833 case IP_VERSION(3, 6, 0): 2834 case IP_VERSION(4, 0, 1): 2835 case IP_VERSION(4, 2, 0): 2836 case IP_VERSION(4, 2, 1): 2837 case IP_VERSION(6, 0, 0): 2838 adev->mode_info.num_crtc = 4; 2839 adev->mode_info.num_hpd = 4; 2840 adev->mode_info.num_dig = 4; 2841 break; 2842 default: 2843 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2844 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2845 return -EINVAL; 2846 } 2847 break; 2848 } 2849 2850 if (adev->mode_info.funcs == NULL) 2851 adev->mode_info.funcs = &dm_display_funcs; 2852 2853 /* 2854 * Note: Do NOT change adev->reg.audio_endpt.rreg and 2855 * adev->reg.audio_endpt.wreg because they are initialised in 2856 * amdgpu_device_init() 2857 */ 2858 #if defined(CONFIG_DEBUG_KERNEL_DC) 2859 device_create_file( 2860 adev_to_drm(adev)->dev, 2861 &dev_attr_s3_debug); 2862 #endif 2863 adev->dc_enabled = true; 2864 2865 return dm_init_microcode(adev); 2866 } 2867 2868 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 2869 { 2870 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 2871 } 2872 EXPORT_IF_KUNIT(modereset_required); 2873 2874 STATIC_IFN_KUNIT int 2875 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 2876 const enum surface_pixel_format format, 2877 enum dc_color_space *color_space) 2878 { 2879 bool full_range; 2880 2881 *color_space = COLOR_SPACE_SRGB; 2882 2883 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 2884 if (plane_state->state && plane_state->state->plane_color_pipeline) 2885 return 0; 2886 2887 /* DRM color properties only affect non-RGB formats. */ 2888 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 2889 return 0; 2890 2891 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 2892 2893 switch (plane_state->color_encoding) { 2894 case DRM_COLOR_YCBCR_BT601: 2895 if (full_range) 2896 *color_space = COLOR_SPACE_YCBCR601; 2897 else 2898 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 2899 break; 2900 2901 case DRM_COLOR_YCBCR_BT709: 2902 if (full_range) 2903 *color_space = COLOR_SPACE_YCBCR709; 2904 else 2905 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 2906 break; 2907 2908 case DRM_COLOR_YCBCR_BT2020: 2909 if (full_range) 2910 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 2911 else 2912 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 2913 break; 2914 2915 default: 2916 return -EINVAL; 2917 } 2918 2919 return 0; 2920 } 2921 EXPORT_IF_KUNIT(fill_plane_color_attributes); 2922 2923 static int 2924 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 2925 const struct drm_plane_state *plane_state, 2926 struct dc_plane_info *plane_info, 2927 struct dc_plane_address *address, 2928 bool tmz_surface) 2929 { 2930 const struct drm_framebuffer *fb = plane_state->fb; 2931 const struct amdgpu_framebuffer *afb = 2932 to_amdgpu_framebuffer(plane_state->fb); 2933 int ret; 2934 2935 memset(plane_info, 0, sizeof(*plane_info)); 2936 2937 switch (fb->format->format) { 2938 case DRM_FORMAT_C8: 2939 plane_info->format = 2940 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 2941 break; 2942 case DRM_FORMAT_RGB565: 2943 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 2944 break; 2945 case DRM_FORMAT_XRGB8888: 2946 case DRM_FORMAT_ARGB8888: 2947 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 2948 break; 2949 case DRM_FORMAT_XRGB2101010: 2950 case DRM_FORMAT_ARGB2101010: 2951 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 2952 break; 2953 case DRM_FORMAT_XBGR2101010: 2954 case DRM_FORMAT_ABGR2101010: 2955 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 2956 break; 2957 case DRM_FORMAT_XBGR8888: 2958 case DRM_FORMAT_ABGR8888: 2959 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 2960 break; 2961 case DRM_FORMAT_NV21: 2962 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 2963 break; 2964 case DRM_FORMAT_NV12: 2965 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 2966 break; 2967 case DRM_FORMAT_P010: 2968 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 2969 break; 2970 case DRM_FORMAT_XRGB16161616F: 2971 case DRM_FORMAT_ARGB16161616F: 2972 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 2973 break; 2974 case DRM_FORMAT_XBGR16161616F: 2975 case DRM_FORMAT_ABGR16161616F: 2976 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 2977 break; 2978 case DRM_FORMAT_XRGB16161616: 2979 case DRM_FORMAT_ARGB16161616: 2980 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 2981 break; 2982 case DRM_FORMAT_XBGR16161616: 2983 case DRM_FORMAT_ABGR16161616: 2984 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 2985 break; 2986 default: 2987 drm_err(adev_to_drm(adev), 2988 "Unsupported screen format %p4cc\n", 2989 &fb->format->format); 2990 return -EINVAL; 2991 } 2992 2993 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 2994 case DRM_MODE_ROTATE_0: 2995 plane_info->rotation = ROTATION_ANGLE_0; 2996 break; 2997 case DRM_MODE_ROTATE_90: 2998 plane_info->rotation = ROTATION_ANGLE_90; 2999 break; 3000 case DRM_MODE_ROTATE_180: 3001 plane_info->rotation = ROTATION_ANGLE_180; 3002 break; 3003 case DRM_MODE_ROTATE_270: 3004 plane_info->rotation = ROTATION_ANGLE_270; 3005 break; 3006 default: 3007 plane_info->rotation = ROTATION_ANGLE_0; 3008 break; 3009 } 3010 3011 3012 plane_info->visible = true; 3013 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3014 3015 plane_info->layer_index = plane_state->normalized_zpos; 3016 3017 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3018 &plane_info->color_space); 3019 if (ret) 3020 return ret; 3021 3022 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3023 plane_info->rotation, 3024 &plane_info->tiling_info, 3025 &plane_info->plane_size, 3026 &plane_info->dcc, address, 3027 tmz_surface); 3028 if (ret) 3029 return ret; 3030 3031 amdgpu_dm_plane_fill_blending_from_plane_state( 3032 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3033 &plane_info->global_alpha, &plane_info->global_alpha_value); 3034 3035 return 0; 3036 } 3037 3038 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3039 struct dc_plane_state *dc_plane_state, 3040 struct drm_plane_state *plane_state, 3041 struct drm_crtc_state *crtc_state) 3042 { 3043 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3044 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3045 struct dc_scaling_info scaling_info; 3046 struct dc_plane_info plane_info; 3047 int ret; 3048 3049 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3050 if (ret) 3051 return ret; 3052 3053 dc_plane_state->src_rect = scaling_info.src_rect; 3054 dc_plane_state->dst_rect = scaling_info.dst_rect; 3055 dc_plane_state->clip_rect = scaling_info.clip_rect; 3056 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3057 3058 ret = fill_dc_plane_info_and_addr(adev, plane_state, 3059 &plane_info, 3060 &dc_plane_state->address, 3061 afb->tmz_surface); 3062 if (ret) 3063 return ret; 3064 3065 dc_plane_state->format = plane_info.format; 3066 dc_plane_state->color_space = plane_info.color_space; 3067 dc_plane_state->format = plane_info.format; 3068 dc_plane_state->plane_size = plane_info.plane_size; 3069 dc_plane_state->rotation = plane_info.rotation; 3070 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3071 dc_plane_state->stereo_format = plane_info.stereo_format; 3072 dc_plane_state->tiling_info = plane_info.tiling_info; 3073 dc_plane_state->visible = plane_info.visible; 3074 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3075 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3076 dc_plane_state->global_alpha = plane_info.global_alpha; 3077 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3078 dc_plane_state->dcc = plane_info.dcc; 3079 dc_plane_state->layer_index = plane_info.layer_index; 3080 dc_plane_state->flip_int_enabled = true; 3081 3082 /* 3083 * Always set input transfer function, since plane state is refreshed 3084 * every time. 3085 */ 3086 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3087 plane_state, 3088 dc_plane_state); 3089 if (ret) 3090 return ret; 3091 3092 return 0; 3093 } 3094 3095 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3096 struct rect *dirty_rect, int32_t x, 3097 s32 y, s32 width, s32 height, 3098 int *i, bool ffu) 3099 { 3100 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3101 3102 dirty_rect->x = x; 3103 dirty_rect->y = y; 3104 dirty_rect->width = width; 3105 dirty_rect->height = height; 3106 3107 if (ffu) 3108 drm_dbg(plane->dev, 3109 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3110 plane->base.id, width, height); 3111 else 3112 drm_dbg(plane->dev, 3113 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3114 plane->base.id, x, y, width, height); 3115 3116 (*i)++; 3117 } 3118 3119 /** 3120 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3121 * 3122 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3123 * remote fb 3124 * @old_plane_state: Old state of @plane 3125 * @new_plane_state: New state of @plane 3126 * @crtc_state: New state of CRTC connected to the @plane 3127 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3128 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3129 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3130 * that have changed will be updated. If PSR SU is not enabled, 3131 * or if damage clips are not available, the entire screen will be updated. 3132 * @dirty_regions_changed: dirty regions changed 3133 * 3134 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3135 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3136 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3137 * amdgpu_dm's. 3138 * 3139 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3140 * plane with regions that require flushing to the eDP remote buffer. In 3141 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3142 * implicitly provide damage clips without any client support via the plane 3143 * bounds. 3144 */ 3145 static void fill_dc_dirty_rects(struct drm_plane *plane, 3146 struct drm_plane_state *old_plane_state, 3147 struct drm_plane_state *new_plane_state, 3148 struct drm_crtc_state *crtc_state, 3149 struct dc_flip_addrs *flip_addrs, 3150 bool is_psr_su, 3151 bool *dirty_regions_changed) 3152 { 3153 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3154 struct rect *dirty_rects = flip_addrs->dirty_rects; 3155 u32 num_clips = 0; 3156 struct drm_mode_rect *clips = NULL; 3157 bool bb_changed; 3158 bool fb_changed; 3159 u32 i = 0; 3160 *dirty_regions_changed = false; 3161 3162 /* 3163 * Cursor plane has it's own dirty rect update interface. See 3164 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3165 */ 3166 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3167 return; 3168 3169 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3170 goto ffu; 3171 3172 if (!new_plane_state->ignore_damage_clips) { 3173 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3174 clips = drm_plane_get_damage_clips(new_plane_state); 3175 } 3176 3177 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3178 is_psr_su))) 3179 goto ffu; 3180 3181 if (!dm_crtc_state->mpo_requested) { 3182 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3183 goto ffu; 3184 3185 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3186 fill_dc_dirty_rect(new_plane_state->plane, 3187 &dirty_rects[flip_addrs->dirty_rect_count], 3188 clips->x1, clips->y1, 3189 clips->x2 - clips->x1, clips->y2 - clips->y1, 3190 &flip_addrs->dirty_rect_count, 3191 false); 3192 return; 3193 } 3194 3195 /* 3196 * MPO is requested. Add entire plane bounding box to dirty rects if 3197 * flipped to or damaged. 3198 * 3199 * If plane is moved or resized, also add old bounding box to dirty 3200 * rects. 3201 */ 3202 fb_changed = old_plane_state->fb->base.id != 3203 new_plane_state->fb->base.id; 3204 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3205 old_plane_state->crtc_y != new_plane_state->crtc_y || 3206 old_plane_state->crtc_w != new_plane_state->crtc_w || 3207 old_plane_state->crtc_h != new_plane_state->crtc_h); 3208 3209 drm_dbg(plane->dev, 3210 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3211 new_plane_state->plane->base.id, 3212 bb_changed, fb_changed, num_clips); 3213 3214 *dirty_regions_changed = bb_changed; 3215 3216 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3217 goto ffu; 3218 3219 if (bb_changed) { 3220 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3221 new_plane_state->crtc_x, 3222 new_plane_state->crtc_y, 3223 new_plane_state->crtc_w, 3224 new_plane_state->crtc_h, &i, false); 3225 3226 /* Add old plane bounding-box if plane is moved or resized */ 3227 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3228 old_plane_state->crtc_x, 3229 old_plane_state->crtc_y, 3230 old_plane_state->crtc_w, 3231 old_plane_state->crtc_h, &i, false); 3232 } 3233 3234 if (num_clips) { 3235 for (; i < num_clips; clips++) 3236 fill_dc_dirty_rect(new_plane_state->plane, 3237 &dirty_rects[i], clips->x1, 3238 clips->y1, clips->x2 - clips->x1, 3239 clips->y2 - clips->y1, &i, false); 3240 } else if (fb_changed && !bb_changed) { 3241 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3242 new_plane_state->crtc_x, 3243 new_plane_state->crtc_y, 3244 new_plane_state->crtc_w, 3245 new_plane_state->crtc_h, &i, false); 3246 } 3247 3248 flip_addrs->dirty_rect_count = i; 3249 return; 3250 3251 ffu: 3252 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3253 dm_crtc_state->base.mode.crtc_hdisplay, 3254 dm_crtc_state->base.mode.crtc_vdisplay, 3255 &flip_addrs->dirty_rect_count, true); 3256 } 3257 3258 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3259 struct dc_state *dc_state, 3260 struct dsc_mst_fairness_vars *vars) 3261 { 3262 struct dc_stream_state *stream = NULL; 3263 struct drm_connector *connector; 3264 struct drm_connector_state *new_con_state; 3265 struct amdgpu_dm_connector *aconnector; 3266 struct dm_connector_state *dm_conn_state; 3267 int i, j, ret; 3268 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3269 3270 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3271 3272 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3273 continue; 3274 3275 aconnector = to_amdgpu_dm_connector(connector); 3276 3277 if (!aconnector->mst_output_port) 3278 continue; 3279 3280 if (!new_con_state || !new_con_state->crtc) 3281 continue; 3282 3283 dm_conn_state = to_dm_connector_state(new_con_state); 3284 3285 for (j = 0; j < dc_state->stream_count; j++) { 3286 stream = dc_state->streams[j]; 3287 if (!stream) 3288 continue; 3289 3290 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3291 break; 3292 3293 stream = NULL; 3294 } 3295 3296 if (!stream) 3297 continue; 3298 3299 pbn_div = dm_mst_get_pbn_divider(stream->link); 3300 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3301 for (j = 0; j < dc_state->stream_count; j++) { 3302 if (vars[j].aconnector == aconnector) { 3303 pbn = vars[j].pbn; 3304 break; 3305 } 3306 } 3307 3308 if (j == dc_state->stream_count || pbn_div == 0) 3309 continue; 3310 3311 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3312 3313 if (stream->timing.flags.DSC != 1) { 3314 dm_conn_state->pbn = pbn; 3315 dm_conn_state->vcpi_slots = slot_num; 3316 3317 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3318 dm_conn_state->pbn, false); 3319 if (ret < 0) 3320 return ret; 3321 3322 continue; 3323 } 3324 3325 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3326 if (vcpi < 0) 3327 return vcpi; 3328 3329 dm_conn_state->pbn = pbn; 3330 dm_conn_state->vcpi_slots = vcpi; 3331 } 3332 return 0; 3333 } 3334 3335 static void manage_dm_interrupts(struct amdgpu_device *adev, 3336 struct amdgpu_crtc *acrtc, 3337 struct dm_crtc_state *acrtc_state) 3338 { /* 3339 * We cannot be sure that the frontend index maps to the same 3340 * backend index - some even map to more than one. 3341 * So we have to go through the CRTC to find the right IRQ. 3342 */ 3343 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3344 adev, 3345 acrtc->crtc_id); 3346 struct drm_device *dev = adev_to_drm(adev); 3347 3348 struct drm_vblank_crtc_config config = {0}; 3349 struct dc_crtc_timing *timing; 3350 int offdelay; 3351 3352 if (acrtc_state) { 3353 timing = &acrtc_state->stream->timing; 3354 3355 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3356 IP_VERSION(3, 5, 0) || 3357 !(adev->flags & AMD_IS_APU)) { 3358 /* 3359 * Older HW and DGPU have issues with instant off; 3360 * use a 2 frame offdelay. 3361 */ 3362 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3363 timing->v_total * 3364 timing->h_total, 3365 timing->pix_clk_100hz); 3366 3367 config.offdelay_ms = offdelay ?: 30; 3368 } else { 3369 /* offdelay_ms = 0 will never disable vblank */ 3370 config.offdelay_ms = 1; 3371 config.disable_immediate = true; 3372 } 3373 3374 drm_crtc_vblank_on_config(&acrtc->base, 3375 &config); 3376 /* 3377 * Since pflip_high_irq is no longer registered for DCN, grab an 3378 * extra reference to vupdate irq instead to workaround this 3379 * issue: 3380 * https://gitlab.freedesktop.org/drm/amd/-/work_items/3936 3381 * 3382 * The callbacks to drm_vblank_on/off should really take care of 3383 * this though. 3384 */ 3385 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3386 case IP_VERSION(3, 0, 0): 3387 case IP_VERSION(3, 0, 2): 3388 case IP_VERSION(3, 0, 3): 3389 case IP_VERSION(3, 2, 0): 3390 if (amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type)) 3391 drm_err(dev, "DM_IRQ: Cannot get vupdate irq!\n"); 3392 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3393 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3394 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3395 #endif 3396 } 3397 3398 } else { 3399 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3400 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3401 case IP_VERSION(3, 0, 0): 3402 case IP_VERSION(3, 0, 2): 3403 case IP_VERSION(3, 0, 3): 3404 case IP_VERSION(3, 2, 0): 3405 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3406 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3407 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3408 #endif 3409 if (amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type)) 3410 drm_err(dev, "DM_IRQ: Cannot put vupdate irq!\n"); 3411 } 3412 3413 drm_crtc_vblank_off(&acrtc->base); 3414 } 3415 } 3416 3417 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3418 struct amdgpu_crtc *acrtc) 3419 { 3420 int irq_type = 3421 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3422 3423 /* GRPH_PFLIP is not used on DCN; nothing to reapply. */ 3424 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) 3425 return; 3426 3427 /** 3428 * This reads the current state for the IRQ and force reapplies 3429 * the setting to hardware. 3430 */ 3431 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3432 } 3433 3434 STATIC_IFN_KUNIT bool 3435 is_scaling_state_different(const struct dm_connector_state *dm_state, 3436 const struct dm_connector_state *old_dm_state) 3437 { 3438 if (dm_state->scaling != old_dm_state->scaling) 3439 return true; 3440 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3441 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3442 return true; 3443 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3444 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3445 return true; 3446 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3447 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3448 return true; 3449 return false; 3450 } 3451 EXPORT_IF_KUNIT(is_scaling_state_different); 3452 3453 STATIC_IFN_KUNIT bool 3454 is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3455 struct drm_crtc_state *old_crtc_state, 3456 struct drm_connector_state *new_conn_state, 3457 struct drm_connector_state *old_conn_state, 3458 const struct drm_connector *connector, 3459 struct hdcp_workqueue *hdcp_w) 3460 { 3461 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3462 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3463 3464 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3465 connector->index, connector->status, connector->dpms); 3466 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3467 old_conn_state->content_protection, new_conn_state->content_protection); 3468 3469 if (old_crtc_state) 3470 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3471 old_crtc_state->enable, 3472 old_crtc_state->active, 3473 old_crtc_state->mode_changed, 3474 old_crtc_state->active_changed, 3475 old_crtc_state->connectors_changed); 3476 3477 if (new_crtc_state) 3478 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3479 new_crtc_state->enable, 3480 new_crtc_state->active, 3481 new_crtc_state->mode_changed, 3482 new_crtc_state->active_changed, 3483 new_crtc_state->connectors_changed); 3484 3485 /* hdcp content type change */ 3486 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3487 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3488 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3489 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3490 return true; 3491 } 3492 3493 /* CP is being re enabled, ignore this */ 3494 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3495 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3496 if (new_crtc_state && new_crtc_state->mode_changed) { 3497 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3498 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3499 return true; 3500 } 3501 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3502 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3503 return false; 3504 } 3505 3506 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3507 * 3508 * Handles: UNDESIRED -> ENABLED 3509 */ 3510 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3511 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3512 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3513 3514 /* Stream removed and re-enabled 3515 * 3516 * Can sometimes overlap with the HPD case, 3517 * thus set update_hdcp to false to avoid 3518 * setting HDCP multiple times. 3519 * 3520 * Handles: DESIRED -> DESIRED (Special case) 3521 */ 3522 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3523 new_conn_state->crtc && new_conn_state->crtc->enabled && 3524 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3525 dm_con_state->update_hdcp = false; 3526 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3527 __func__); 3528 return true; 3529 } 3530 3531 /* Hot-plug, headless s3, dpms 3532 * 3533 * Only start HDCP if the display is connected/enabled. 3534 * update_hdcp flag will be set to false until the next 3535 * HPD comes in. 3536 * 3537 * Handles: DESIRED -> DESIRED (Special case) 3538 */ 3539 if (dm_con_state->update_hdcp && 3540 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3541 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3542 dm_con_state->update_hdcp = false; 3543 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3544 __func__); 3545 return true; 3546 } 3547 3548 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3549 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3550 if (new_crtc_state && new_crtc_state->mode_changed) { 3551 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3552 __func__); 3553 return true; 3554 } 3555 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3556 __func__); 3557 return false; 3558 } 3559 3560 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3561 return false; 3562 } 3563 3564 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3565 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3566 __func__); 3567 return true; 3568 } 3569 3570 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3571 return false; 3572 } 3573 EXPORT_IF_KUNIT(is_content_protection_different); 3574 3575 static void remove_stream(struct amdgpu_device *adev, 3576 struct amdgpu_crtc *acrtc, 3577 struct dc_stream_state *stream) 3578 { 3579 /* this is the update mode case */ 3580 3581 acrtc->otg_inst = -1; 3582 acrtc->enabled = false; 3583 } 3584 3585 static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 3586 { 3587 struct drm_plane *plane; 3588 struct drm_plane_state *old_plane_state; 3589 int i; 3590 3591 /* 3592 * TODO: Make this per-stream so we don't issue redundant updates for 3593 * commits with multiple streams. 3594 */ 3595 for_each_old_plane_in_state(state, plane, old_plane_state, i) 3596 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3597 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 3598 } 3599 3600 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 3601 { 3602 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 3603 3604 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 3605 } 3606 3607 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 3608 struct drm_plane_state *old_plane_state, 3609 struct dc_stream_update *update) 3610 { 3611 struct amdgpu_device *adev = drm_to_adev(plane->dev); 3612 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 3613 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 3614 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 3615 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 3616 uint64_t address = afb ? afb->address : 0; 3617 struct dc_cursor_position position = {0}; 3618 struct dc_cursor_attributes attributes; 3619 int ret; 3620 3621 if (!plane->state->fb && !old_plane_state->fb) 3622 return; 3623 3624 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 3625 amdgpu_crtc->crtc_id, plane->state->crtc_w, 3626 plane->state->crtc_h); 3627 3628 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 3629 if (ret) 3630 return; 3631 3632 if (!position.enable) { 3633 /* turn off cursor */ 3634 if (crtc_state && crtc_state->stream) { 3635 dc_stream_set_cursor_position(crtc_state->stream, 3636 &position); 3637 update->cursor_position = &crtc_state->stream->cursor_position; 3638 } 3639 return; 3640 } 3641 3642 amdgpu_crtc->cursor_width = plane->state->crtc_w; 3643 amdgpu_crtc->cursor_height = plane->state->crtc_h; 3644 3645 memset(&attributes, 0, sizeof(attributes)); 3646 attributes.address.high_part = upper_32_bits(address); 3647 attributes.address.low_part = lower_32_bits(address); 3648 attributes.width = plane->state->crtc_w; 3649 attributes.height = plane->state->crtc_h; 3650 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 3651 attributes.rotation_angle = 0; 3652 attributes.attribute_flags.value = 0; 3653 3654 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 3655 * legacy gamma setup. 3656 */ 3657 if (crtc_state->cm_is_degamma_srgb && 3658 adev->dm.dc->caps.color.dpp.gamma_corr) 3659 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 3660 3661 if (afb) 3662 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 3663 3664 if (crtc_state->stream) { 3665 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 3666 &attributes)) 3667 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 3668 3669 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 3670 3671 if (!dc_stream_set_cursor_position(crtc_state->stream, 3672 &position)) 3673 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 3674 3675 update->cursor_position = &crtc_state->stream->cursor_position; 3676 } 3677 } 3678 3679 static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 3680 struct amdgpu_crtc *acrtc_attach, 3681 const struct dm_crtc_state *acrtc_state, 3682 const u64 current_ts) 3683 { 3684 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 3685 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 3686 struct amdgpu_dm_connector *aconn = 3687 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 3688 3689 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 3690 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 3691 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 3692 if (aconn->sr_skip_count > 0) 3693 aconn->sr_skip_count--; 3694 3695 /* Allow SR when skip count is 0. */ 3696 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 3697 3698 /* 3699 * If sink supports PSR SU/Panel Replay, there is no need to rely on 3700 * a vblank event disable request to enable PSR/RP. PSR SU/RP 3701 * can be enabled immediately once OS demonstrates an 3702 * adequate number of fast atomic commits to notify KMD 3703 * of update events. 3704 * See `amdgpu_dm_crtc_vblank_control_worker()`. 3705 */ 3706 if (acrtc_attach->dm_irq_params.allow_sr_entry && 3707 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 3708 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 3709 psr_event_hw_programming, false); 3710 3711 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 3712 replay_event_hw_programming, false); 3713 } 3714 } else { 3715 acrtc_attach->dm_irq_params.allow_sr_entry = false; 3716 } 3717 } 3718 3719 static void dm_arm_vblank_event(struct amdgpu_crtc *acrtc, 3720 struct dm_crtc_state *acrtc_state, 3721 bool pflip_update, 3722 bool cursor_update) 3723 { 3724 assert_spin_locked(&acrtc->base.dev->event_lock); 3725 3726 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 3727 return; 3728 3729 if (pflip_update) { 3730 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 3731 WARN_ON(acrtc->event); 3732 3733 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3734 acrtc->event = acrtc->base.state->event; 3735 acrtc->base.state->event = NULL; 3736 3737 drm_dbg_state(acrtc->base.dev, 3738 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3739 acrtc->crtc_id); 3740 } else if (cursor_update) { 3741 acrtc->event = acrtc->base.state->event; 3742 acrtc->base.state->event = NULL; 3743 } 3744 } 3745 3746 /** 3747 * dm_arm_vblank_event_pre_programming - Prepare for programming 3748 * @acrtc: The amdgpu CRTC to prepare 3749 * @acrtc_state: The new CRTC state 3750 * @pflip_update: Whether a page flip is being programmed 3751 * @cursor_update: Whether a cursor update is being programmed 3752 * 3753 * Grab a reference on the vblank counter if a page flip or cursor update is to 3754 * be programmed. Do this before programming so the HW is not in any 3755 * idle-optimized state (such as PSR). 3756 */ 3757 static void dm_arm_vblank_event_pre_programming(struct amdgpu_crtc *acrtc, 3758 struct dm_crtc_state *acrtc_state, 3759 bool pflip_update, 3760 bool cursor_update) 3761 { 3762 assert_spin_locked(&acrtc->base.dev->event_lock); 3763 3764 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 3765 return; 3766 3767 if (pflip_update || cursor_update) 3768 drm_crtc_vblank_get(&acrtc->base); 3769 } 3770 3771 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 3772 struct drm_device *dev, 3773 struct amdgpu_display_manager *dm, 3774 struct drm_crtc *pcrtc, 3775 bool wait_for_vblank) 3776 { 3777 u32 i; 3778 u64 timestamp_ns = ktime_get_ns(); 3779 struct drm_plane *plane; 3780 struct drm_plane_state *old_plane_state, *new_plane_state; 3781 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 3782 struct drm_crtc_state *new_pcrtc_state = 3783 drm_atomic_get_new_crtc_state(state, pcrtc); 3784 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 3785 struct dm_crtc_state *dm_old_crtc_state = 3786 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 3787 int planes_count = 0, vpos, hpos; 3788 unsigned long flags; 3789 u32 target_vblank, last_flip_vblank; 3790 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 3791 bool cursor_update = false; 3792 bool pflip_present = false; 3793 bool immediate_flip = false; 3794 bool flip_latched_during_prog = false; 3795 bool dirty_rects_changed = false; 3796 bool updated_planes_and_streams = false; 3797 struct { 3798 struct dc_surface_update surface_updates[MAX_SURFACES]; 3799 struct dc_plane_info plane_infos[MAX_SURFACES]; 3800 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 3801 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 3802 struct dc_stream_update stream_update; 3803 } *bundle; 3804 3805 bundle = kzalloc_obj(*bundle); 3806 3807 if (!bundle) { 3808 drm_err(dev, "Failed to allocate update bundle\n"); 3809 goto cleanup; 3810 } 3811 3812 /* 3813 * Disable the cursor first if we're disabling all the planes. 3814 * It'll remain on the screen after the planes are re-enabled 3815 * if we don't. 3816 * 3817 * If the cursor is transitioning from native to overlay mode, the 3818 * native cursor needs to be disabled first. 3819 */ 3820 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 3821 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 3822 struct dc_cursor_position cursor_position = {0}; 3823 3824 if (!dc_stream_set_cursor_position(acrtc_state->stream, 3825 &cursor_position)) 3826 drm_err(dev, "DC failed to disable native cursor\n"); 3827 3828 bundle->stream_update.cursor_position = 3829 &acrtc_state->stream->cursor_position; 3830 } 3831 3832 if (acrtc_state->active_planes == 0 && 3833 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 3834 amdgpu_dm_commit_cursors(state); 3835 3836 /* update planes when needed */ 3837 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 3838 struct drm_crtc *crtc = new_plane_state->crtc; 3839 struct drm_crtc_state *new_crtc_state; 3840 struct drm_framebuffer *fb = new_plane_state->fb; 3841 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 3842 bool plane_needs_flip; 3843 struct dc_plane_state *dc_plane; 3844 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 3845 3846 /* Cursor plane is handled after stream updates */ 3847 if (plane->type == DRM_PLANE_TYPE_CURSOR && 3848 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 3849 if ((fb && crtc == pcrtc) || 3850 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 3851 cursor_update = true; 3852 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 3853 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 3854 } 3855 3856 continue; 3857 } 3858 3859 if (!fb || !crtc || pcrtc != crtc) 3860 continue; 3861 3862 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 3863 if (!new_crtc_state->active) 3864 continue; 3865 3866 dc_plane = dm_new_plane_state->dc_state; 3867 if (!dc_plane) 3868 continue; 3869 3870 bundle->surface_updates[planes_count].surface = dc_plane; 3871 if (new_pcrtc_state->color_mgmt_changed) { 3872 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 3873 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 3874 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 3875 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 3876 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 3877 } 3878 3879 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 3880 &bundle->scaling_infos[planes_count]); 3881 3882 bundle->surface_updates[planes_count].scaling_info = 3883 &bundle->scaling_infos[planes_count]; 3884 3885 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 3886 3887 pflip_present = pflip_present || plane_needs_flip; 3888 3889 if (!plane_needs_flip) { 3890 planes_count += 1; 3891 continue; 3892 } 3893 3894 fill_dc_plane_info_and_addr( 3895 dm->adev, new_plane_state, 3896 &bundle->plane_infos[planes_count], 3897 &bundle->flip_addrs[planes_count].address, 3898 afb->tmz_surface); 3899 3900 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 3901 new_plane_state->plane->index, 3902 bundle->plane_infos[planes_count].dcc.enable); 3903 3904 bundle->surface_updates[planes_count].plane_info = 3905 &bundle->plane_infos[planes_count]; 3906 3907 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 3908 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 3909 fill_dc_dirty_rects(plane, old_plane_state, 3910 new_plane_state, new_crtc_state, 3911 &bundle->flip_addrs[planes_count], 3912 acrtc_state->stream->link->psr_settings.psr_version == 3913 DC_PSR_VERSION_SU_1, 3914 &dirty_rects_changed); 3915 3916 /* 3917 * If the dirty regions changed, PSR-SU need to be disabled temporarily 3918 * and enabled it again after dirty regions are stable to avoid video glitch. 3919 * PSR-SU will be enabled in 3920 * amdgpu_dm_crtc_vblank_control_worker() if user 3921 * pause the video during the PSR-SU was disabled. 3922 */ 3923 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 3924 acrtc_attach->dm_irq_params.allow_sr_entry && 3925 dirty_rects_changed) { 3926 mutex_lock(&dm->dc_lock); 3927 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 3928 timestamp_ns; 3929 dc_exit_ips_for_hw_access(dm->dc); 3930 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 3931 psr_event_hw_programming, true); 3932 mutex_unlock(&dm->dc_lock); 3933 } 3934 } 3935 3936 /* 3937 * Only allow immediate flips for fast updates that don't 3938 * change memory domain, FB pitch, DCC state, rotation or 3939 * mirroring. 3940 * 3941 * dm_crtc_helper_atomic_check() only accepts async flips with 3942 * fast updates. 3943 */ 3944 if (crtc->state->async_flip && 3945 (acrtc_state->update_type != UPDATE_TYPE_FAST || 3946 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 3947 drm_warn_once(state->dev, 3948 "[PLANE:%d:%s] async flip with non-fast update\n", 3949 plane->base.id, plane->name); 3950 3951 bundle->flip_addrs[planes_count].flip_immediate = 3952 crtc->state->async_flip && 3953 acrtc_state->update_type == UPDATE_TYPE_FAST && 3954 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 3955 3956 immediate_flip |= bundle->flip_addrs[planes_count].flip_immediate; 3957 3958 timestamp_ns = ktime_get_ns(); 3959 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 3960 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 3961 bundle->surface_updates[planes_count].surface = dc_plane; 3962 3963 if (!bundle->surface_updates[planes_count].surface) { 3964 drm_err(dev, "No surface for CRTC: id=%d\n", 3965 acrtc_attach->crtc_id); 3966 continue; 3967 } 3968 3969 if (plane == pcrtc->primary) 3970 amdgpu_dm_update_freesync_state_on_stream( 3971 dm, 3972 acrtc_state, 3973 acrtc_state->stream, 3974 dc_plane, 3975 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 3976 3977 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 3978 __func__, 3979 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 3980 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 3981 3982 planes_count += 1; 3983 3984 } 3985 3986 if (pflip_present) { 3987 if (!vrr_active) { 3988 /* Use old throttling in non-vrr fixed refresh rate mode 3989 * to keep flip scheduling based on target vblank counts 3990 * working in a backwards compatible way, e.g., for 3991 * clients using the GLX_OML_sync_control extension or 3992 * DRI3/Present extension with defined target_msc. 3993 */ 3994 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 3995 } else { 3996 /* For variable refresh rate mode only: 3997 * Get vblank of last completed flip to avoid > 1 vrr 3998 * flips per video frame by use of throttling, but allow 3999 * flip programming anywhere in the possibly large 4000 * variable vrr vblank interval for fine-grained flip 4001 * timing control and more opportunity to avoid stutter 4002 * on late submission of flips. 4003 */ 4004 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4005 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4006 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4007 } 4008 4009 target_vblank = last_flip_vblank + wait_for_vblank; 4010 4011 /* 4012 * Wait until we're out of the vertical blank period before the one 4013 * targeted by the flip 4014 */ 4015 while ((acrtc_attach->enabled && 4016 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4017 0, &vpos, &hpos, NULL, 4018 NULL, &pcrtc->hwmode) 4019 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4020 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4021 (int)(target_vblank - 4022 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4023 usleep_range(1000, 1100); 4024 } 4025 4026 if (acrtc_state->stream) { 4027 if (acrtc_state->freesync_vrr_info_changed) 4028 bundle->stream_update.vrr_infopacket = 4029 &acrtc_state->stream->vrr_infopacket; 4030 } 4031 } 4032 4033 scoped_guard(spinlock_irqsave, &pcrtc->dev->event_lock) { 4034 dm_arm_vblank_event_pre_programming(acrtc_attach, acrtc_state, 4035 pflip_present, 4036 cursor_update); 4037 /* 4038 * DCE depends on a combination of GRPH_FLIP, VLINE0, and 4039 * VUPDATE for event delivery. Only GRPH_FLIP handler can send 4040 * pflip events, and it only fires if HW latched to the flip. 4041 * Maintain legacy behavior by arming event before programming. 4042 */ 4043 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) { 4044 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4045 pflip_present, cursor_update); 4046 } 4047 } 4048 4049 /* Update the planes if changed or disable if we don't have any. */ 4050 if ((planes_count || acrtc_state->active_planes == 0) && 4051 acrtc_state->stream) { 4052 /* 4053 * If PSR or idle optimizations are enabled then flush out 4054 * any pending work before hardware programming. 4055 */ 4056 if (dm->vblank_control_workqueue) 4057 flush_workqueue(dm->vblank_control_workqueue); 4058 4059 bundle->stream_update.stream = acrtc_state->stream; 4060 if (new_pcrtc_state->mode_changed) { 4061 bundle->stream_update.src = acrtc_state->stream->src; 4062 bundle->stream_update.dst = acrtc_state->stream->dst; 4063 } 4064 4065 if (new_pcrtc_state->color_mgmt_changed) { 4066 /* 4067 * TODO: This isn't fully correct since we've actually 4068 * already modified the stream in place. 4069 */ 4070 bundle->stream_update.gamut_remap = 4071 &acrtc_state->stream->gamut_remap_matrix; 4072 bundle->stream_update.output_csc_transform = 4073 &acrtc_state->stream->csc_color_matrix; 4074 bundle->stream_update.out_transfer_func = 4075 &acrtc_state->stream->out_transfer_func; 4076 bundle->stream_update.lut3d_func = 4077 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4078 bundle->stream_update.func_shaper = 4079 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4080 } 4081 4082 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4083 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4084 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4085 4086 /* 4087 * If FreeSync state on the stream has changed then we need to 4088 * re-adjust the min/max bounds now that DC doesn't handle this 4089 * as part of commit. 4090 */ 4091 if (amdgpu_dm_is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4092 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4093 dc_stream_adjust_vmin_vmax( 4094 dm->dc, acrtc_state->stream, 4095 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4096 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4097 } 4098 mutex_lock(&dm->dc_lock); 4099 update_planes_and_stream_adapter(dm->dc, 4100 acrtc_state->update_type, 4101 planes_count, 4102 acrtc_state->stream, 4103 &bundle->stream_update, 4104 bundle->surface_updates); 4105 updated_planes_and_streams = true; 4106 4107 /** 4108 * Enable or disable the interrupts on the backend. 4109 * 4110 * Most pipes are put into power gating when unused. 4111 * 4112 * When power gating is enabled on a pipe we lose the 4113 * interrupt enablement state when power gating is disabled. 4114 * 4115 * So we need to update the IRQ control state in hardware 4116 * whenever the pipe turns on (since it could be previously 4117 * power gated) or off (since some pipes can't be power gated 4118 * on some ASICs). 4119 */ 4120 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4121 dm_update_pflip_irq_state(drm_to_adev(dev), 4122 acrtc_attach); 4123 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4124 timestamp_ns); 4125 mutex_unlock(&dm->dc_lock); 4126 } 4127 4128 /* 4129 * Update cursor state *after* programming all the planes. 4130 * This avoids redundant programming in the case where we're going 4131 * to be disabling a single plane - those pipes are being disabled. 4132 */ 4133 if (acrtc_state->active_planes && 4134 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4135 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4136 amdgpu_dm_commit_cursors(state); 4137 4138 /* 4139 * DCN specific vblank handling 4140 * ============================ 4141 * 4142 * With the event_lock held, arm the vblank event, and determine whether 4143 * deliver it immediately, or in VUPDATE_NO_LOCK IRQ (i.e. HW latch 4144 * point) handler. Do this *after* programming so that the IRQ handler 4145 * will not deliver the event before HW laches onto the programmed 4146 * values: 4147 * 4148 * Commit thread IRQ handler HW 4149 * ----------------------------------------------------------------- 4150 * arm_vblank_event() 4151 * vupdate() 4152 * vupdate_handler() 4153 * cook_timestamp() 4154 * # prev flip already latched, 4155 * # so flip_latched == true. 4156 * if event_armed && flip_latched: 4157 * send_vblank_event() 4158 * # sent before latch, **BAD!** 4159 * hw_program() 4160 * vupdate() 4161 * **latch** 4162 * 4163 * There's a consequence of arming after: it's possible for HW to latch 4164 * between start of HW programming and acrtc->event/pflip_status arming. 4165 * When this happens, the IRQ handler will send the event on the next 4166 * immediate latch point, even though HW has already latched. This is 4167 * handled by optimistically checking for HW latch after programming, 4168 * and if latched, send the event immediately: 4169 * 4170 * Commit thread IRQ handler HW 4171 * ----------------------------------------------------------------- 4172 * hw_program() 4173 * vupdate() 4174 * **latch** 4175 * vupdate_handler() 4176 * cook_timestamp() 4177 * # event_armed == false 4178 * # **no event sent!** 4179 * arm_vblank_event() 4180 * if flip_latched: 4181 * **send_vblank_event()** 4182 * disarm_vblank_event() 4183 * 4184 * The IRQ handler is expected to cook the timestamp, but we need to 4185 * cook the timestamp before optimistic sending as well. That's because 4186 * the following sequence is possible: 4187 * 4188 * Commit thread IRQ handler HW 4189 * ----------------------------------------------------------------- 4190 * hw_program() 4191 * arm_vblank_event() 4192 * vupdate() 4193 * **latch** 4194 * if flip_latched: 4195 * # Need cook before send! 4196 * **cook_timestamp()** 4197 * send_vblank_event() 4198 * disarm_vblank_event() 4199 * vupdate_handler() 4200 * cook_timestamp() 4201 * # event_armed == false 4202 * # no event sent! 4203 * 4204 * Cooking twice is OK, since DRM scanout accurate timestamps report A) 4205 * the previous vactive start if currently in vactive, or B) the next 4206 * vactive start if currently in vblank (see &get_vblank_counter). 'A)' 4207 * is what we want for the optimistic send, and for 'B)', we'll cook a 4208 * timestamp no later than the next IRQ handler run. 4209 * 4210 * The more correct fix is to wrap programming and arming with the 4211 * event_lock and thus serializing it with the IRQ handler. However, 4212 * there are various sleep-waits within 4213 * update_planes_and_stream_adapter() that makes spin locking illegal. 4214 * And on full updates, it can take 1-2 frame-times to return (see 4215 * commit_planes_for_stream). 4216 * 4217 * On DCE, GRPH_PFLIP IRQ is used and takes care of this. 4218 */ 4219 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) { 4220 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4221 4222 if (updated_planes_and_streams) { 4223 flip_latched_during_prog = 4224 !dc_get_flip_pending_on_otg(dm->dc, acrtc_attach->otg_inst); 4225 } 4226 4227 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4228 pflip_present, cursor_update); 4229 4230 /* 4231 * Deliver the event immediately on immediate flip, or on a 4232 * update that has already latched. 4233 */ 4234 if ((immediate_flip || flip_latched_during_prog) && 4235 acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED && 4236 acrtc_attach->event) { 4237 drm_crtc_accurate_vblank_count(&acrtc_attach->base); 4238 drm_crtc_send_vblank_event(&acrtc_attach->base, 4239 acrtc_attach->event); 4240 acrtc_attach->event = NULL; 4241 drm_crtc_vblank_put(&acrtc_attach->base); 4242 acrtc_attach->pflip_status = AMDGPU_FLIP_NONE; 4243 } 4244 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4245 } 4246 4247 cleanup: 4248 kfree(bundle); 4249 } 4250 4251 /* 4252 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4253 * @crtc_state: the DRM CRTC state 4254 * @stream_state: the DC stream state. 4255 * 4256 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4257 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4258 */ 4259 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4260 struct dc_stream_state *stream_state) 4261 { 4262 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4263 } 4264 4265 /** 4266 * amdgpu_dm_crtc_complete_writeback - finish a pending writeback job 4267 * @acrtc: the CRTC whose pending writeback should be completed 4268 * 4269 * Clears the pending state, signals the writeback out fence and releases the 4270 * vblank reference taken in dm_set_writeback() while the writeback was armed. 4271 * The pending flag is tested and cleared under the writeback job lock, so this 4272 * is safe to call concurrently from the completion vblank IRQ 4273 * (dm_crtc_high_irq()) and from the writeback teardown path 4274 * (dm_clear_writeback()); only the caller that observes the pending job 4275 * performs the completion. 4276 * 4277 * Return: true if a pending writeback job was completed by this call. 4278 */ 4279 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc) 4280 { 4281 unsigned long flags; 4282 bool pending; 4283 4284 if (!acrtc->wb_conn) 4285 return false; 4286 4287 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 4288 pending = acrtc->wb_pending; 4289 acrtc->wb_pending = false; 4290 acrtc->wb_frame_done = false; 4291 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 4292 4293 if (!pending) 4294 return false; 4295 4296 drm_writeback_signal_completion(acrtc->wb_conn, 0); 4297 drm_crtc_vblank_put(&acrtc->base); 4298 4299 return true; 4300 } 4301 EXPORT_IF_KUNIT(amdgpu_dm_crtc_complete_writeback); 4302 4303 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 4304 struct amdgpu_crtc *acrtc, 4305 struct dm_crtc_state *crtc_state) 4306 { 4307 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4308 4309 /* 4310 * If the writeback is still pending when it is torn down (its 4311 * completion vblank IRQ never fired), signal the out fence so a 4312 * waiting client does not stall and release the vblank reference 4313 * taken in dm_set_writeback(). 4314 */ 4315 amdgpu_dm_crtc_complete_writeback(acrtc); 4316 } 4317 4318 /** 4319 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4320 * @state: the drm atomic state 4321 * @dm: the display manager to update mod_power on 4322 * 4323 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4324 * in preparation for hardware programming. See also 4325 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4326 */ 4327 static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4328 struct amdgpu_display_manager *dm) 4329 { 4330 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4331 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4332 struct amdgpu_dm_connector *aconnector; 4333 struct drm_crtc *crtc; 4334 int i = 0; 4335 4336 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4337 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4338 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4339 4340 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4341 continue; 4342 4343 /* 4344 * Update mod_power on modeset event in preparation for hw 4345 * programming. Always use the old stream, since it would have 4346 * been previously added to mod_power. If old stream is null (on 4347 * crtc enable, for example), mod_power will no-op, which is the 4348 * desried behavior. 4349 */ 4350 if (old_crtc_state->active) { 4351 scoped_guard(mutex, &dm->dc_lock) { 4352 dc_exit_ips_for_hw_access(dm->dc); 4353 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4354 psr_event_hw_programming, true); 4355 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4356 replay_event_hw_programming, true); 4357 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4358 replay_event_general_ui, false); 4359 } 4360 } 4361 4362 if (new_crtc_state->active) { 4363 aconnector = (struct amdgpu_dm_connector *) 4364 dm_new_crtc_state->stream->dm_stream_context; 4365 if (old_crtc_state->active) { 4366 mod_power_replace_stream(dm->power_module, 4367 dm_old_crtc_state->stream, 4368 dm_new_crtc_state->stream, 4369 &aconnector->psr_caps); 4370 } else { 4371 mod_power_add_stream(dm->power_module, 4372 dm_new_crtc_state->stream, 4373 &aconnector->psr_caps); 4374 } 4375 } else if (old_crtc_state->active) { 4376 mod_power_remove_stream(dm->power_module, 4377 dm_old_crtc_state->stream); 4378 } 4379 } 4380 } 4381 4382 /** 4383 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4384 * @state: the drm atomic state 4385 * @dm: the display manager to update mod_power on 4386 * 4387 * Notify mod_power of mode_change. This needs to be done after dc_stream 4388 * updates have been committed, and VRR parameters have been updated. 4389 */ 4390 static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4391 struct amdgpu_display_manager *dm) 4392 { 4393 struct dm_crtc_state *dm_new_crtc_state; 4394 struct drm_crtc_state *new_crtc_state; 4395 struct amdgpu_crtc *acrtc; 4396 struct drm_crtc *crtc; 4397 int i = 0; 4398 4399 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4400 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4401 acrtc = to_amdgpu_crtc(crtc); 4402 4403 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4404 continue; 4405 4406 if (new_crtc_state->active) { 4407 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4408 &acrtc->dm_irq_params.vrr_params); 4409 mod_power_notify_mode_change(dm->power_module, 4410 dm_new_crtc_state->stream, 4411 false); 4412 4413 /* 4414 * Block PSR / Replay on the new stream until display settles post-modeset. 4415 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4416 * allow_sr_entry becomes true. 4417 */ 4418 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4419 psr_event_hw_programming, true); 4420 4421 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4422 replay_event_hw_programming | replay_event_general_ui, 4423 true); 4424 } 4425 } 4426 4427 } 4428 4429 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4430 struct dc_state *dc_state) 4431 { 4432 struct drm_device *dev = state->dev; 4433 struct amdgpu_device *adev = drm_to_adev(dev); 4434 struct amdgpu_display_manager *dm = &adev->dm; 4435 struct drm_crtc *crtc; 4436 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4437 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4438 struct drm_connector_state *old_con_state; 4439 struct drm_connector *connector; 4440 bool mode_set_reset_required = false; 4441 u32 i; 4442 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4443 bool set_backlight_level = false; 4444 4445 /* Disable writeback */ 4446 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4447 struct dm_connector_state *dm_old_con_state; 4448 struct amdgpu_crtc *acrtc; 4449 4450 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4451 continue; 4452 4453 old_crtc_state = NULL; 4454 4455 dm_old_con_state = to_dm_connector_state(old_con_state); 4456 if (!dm_old_con_state->base.crtc) 4457 continue; 4458 4459 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4460 if (acrtc) 4461 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4462 4463 if (!acrtc || !acrtc->wb_enabled) 4464 continue; 4465 4466 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4467 4468 dm_clear_writeback(dm, acrtc, dm_old_crtc_state); 4469 acrtc->wb_enabled = false; 4470 } 4471 4472 amdgpu_dm_mod_power_update_streams(state, dm); 4473 4474 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4475 new_crtc_state, i) { 4476 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4477 4478 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4479 4480 if (old_crtc_state->active && 4481 (!new_crtc_state->active || 4482 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4483 manage_dm_interrupts(adev, acrtc, NULL); 4484 dc_stream_release(dm_old_crtc_state->stream); 4485 } 4486 } 4487 4488 drm_atomic_helper_calc_timestamping_constants(state); 4489 4490 /* update changed items */ 4491 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4492 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4493 4494 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4495 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4496 4497 drm_dbg_state(state->dev, 4498 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4499 acrtc->crtc_id, 4500 new_crtc_state->enable, 4501 new_crtc_state->active, 4502 new_crtc_state->planes_changed, 4503 new_crtc_state->mode_changed, 4504 new_crtc_state->active_changed, 4505 new_crtc_state->connectors_changed); 4506 4507 /* Disable cursor if disabling crtc */ 4508 if (old_crtc_state->active && !new_crtc_state->active) { 4509 struct dc_cursor_position position; 4510 4511 memset(&position, 0, sizeof(position)); 4512 mutex_lock(&dm->dc_lock); 4513 dc_exit_ips_for_hw_access(dm->dc); 4514 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4515 mutex_unlock(&dm->dc_lock); 4516 } 4517 4518 /* Copy all transient state flags into dc state */ 4519 if (dm_new_crtc_state->stream) { 4520 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4521 dm_new_crtc_state->stream); 4522 } 4523 4524 /* handles headless hotplug case, updating new_state and 4525 * aconnector as needed 4526 */ 4527 4528 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4529 4530 drm_dbg_atomic(dev, 4531 "Atomic commit: SET crtc id %d: [%p]\n", 4532 acrtc->crtc_id, acrtc); 4533 4534 if (!dm_new_crtc_state->stream) { 4535 /* 4536 * this could happen because of issues with 4537 * userspace notifications delivery. 4538 * In this case userspace tries to set mode on 4539 * display which is disconnected in fact. 4540 * dc_sink is NULL in this case on aconnector. 4541 * We expect reset mode will come soon. 4542 * 4543 * This can also happen when unplug is done 4544 * during resume sequence ended 4545 * 4546 * In this case, we want to pretend we still 4547 * have a sink to keep the pipe running so that 4548 * hw state is consistent with the sw state 4549 */ 4550 drm_dbg_atomic(dev, 4551 "Failed to create new stream for crtc %d\n", 4552 acrtc->base.base.id); 4553 continue; 4554 } 4555 4556 if (dm_old_crtc_state->stream) 4557 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4558 4559 pm_runtime_get_noresume(dev->dev); 4560 4561 acrtc->enabled = true; 4562 acrtc->hw_mode = new_crtc_state->mode; 4563 crtc->hwmode = new_crtc_state->mode; 4564 mode_set_reset_required = true; 4565 set_backlight_level = true; 4566 } else if (modereset_required(new_crtc_state)) { 4567 drm_dbg_atomic(dev, 4568 "Atomic commit: RESET. crtc id %d:[%p]\n", 4569 acrtc->crtc_id, acrtc); 4570 /* i.e. reset mode */ 4571 if (dm_old_crtc_state->stream) 4572 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4573 4574 mode_set_reset_required = true; 4575 } 4576 } /* for_each_crtc_in_state() */ 4577 4578 /* if there mode set or reset, flush vblank work queue */ 4579 if (mode_set_reset_required) { 4580 if (dm->vblank_control_workqueue) 4581 flush_workqueue(dm->vblank_control_workqueue); 4582 } 4583 4584 dm_enable_per_frame_crtc_master_sync(dc_state); 4585 mutex_lock(&dm->dc_lock); 4586 dc_exit_ips_for_hw_access(dm->dc); 4587 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4588 4589 bool frl_stream_found = false; 4590 4591 for (i = 0; i < params.stream_count; i++) { 4592 struct dc_stream_state *stream = params.streams[i]; 4593 4594 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4595 frl_stream_found = true; 4596 break; 4597 } 4598 } 4599 if (frl_stream_found) { 4600 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 4601 &dm->hdmi_frl_status_polling_work, 4602 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 4603 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 4604 } else { 4605 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 4606 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 4607 } 4608 /* Allow idle optimization when vblank count is 0 for display off */ 4609 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 4610 dc_allow_idle_optimizations(dm->dc, true); 4611 mutex_unlock(&dm->dc_lock); 4612 4613 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4614 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4615 4616 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4617 4618 if (dm_new_crtc_state->stream != NULL) { 4619 const struct dc_stream_status *status = 4620 dc_stream_get_status(dm_new_crtc_state->stream); 4621 4622 if (!status) 4623 status = dc_state_get_stream_status(dc_state, 4624 dm_new_crtc_state->stream); 4625 if (!status) 4626 drm_err(dev, 4627 "got no status for stream %p on acrtc%p\n", 4628 dm_new_crtc_state->stream, acrtc); 4629 else 4630 acrtc->otg_inst = status->primary_otg_inst; 4631 } 4632 } 4633 4634 /* During boot up and resume the DC layer will reset the panel brightness 4635 * to fix a flicker issue. 4636 * It will cause the dm->actual_brightness is not the current panel brightness 4637 * level. (the dm->brightness is the correct panel level) 4638 * So we set the backlight level with dm->brightness value after set mode 4639 */ 4640 if (set_backlight_level) { 4641 for (i = 0; i < dm->num_of_edps; i++) { 4642 if (dm->backlight_dev[i]) 4643 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 4644 } 4645 } 4646 } 4647 4648 static void dm_set_writeback(struct amdgpu_display_manager *dm, 4649 struct dm_crtc_state *crtc_state, 4650 struct drm_connector *connector, 4651 struct drm_connector_state *new_con_state) 4652 { 4653 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 4654 struct amdgpu_device *adev = dm->adev; 4655 struct amdgpu_crtc *acrtc; 4656 struct dc_writeback_info *wb_info; 4657 struct pipe_ctx *pipe = NULL; 4658 struct amdgpu_framebuffer *afb; 4659 int i = 0; 4660 4661 wb_info = kzalloc_obj(*wb_info); 4662 if (!wb_info) { 4663 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 4664 goto cleanup; 4665 } 4666 4667 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 4668 if (!acrtc) { 4669 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 4670 goto cleanup; 4671 } 4672 4673 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 4674 if (!afb) { 4675 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 4676 goto cleanup; 4677 } 4678 4679 for (i = 0; i < MAX_PIPES; i++) { 4680 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 4681 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 4682 break; 4683 } 4684 } 4685 4686 if (!pipe) { 4687 drm_err(adev_to_drm(adev), "No pipe found for stream\n"); 4688 goto cleanup; 4689 } 4690 4691 /* fill in wb_info */ 4692 wb_info->wb_enabled = true; 4693 4694 wb_info->dwb_pipe_inst = 0; 4695 wb_info->dwb_params.dwbscl_black_color = 0; 4696 wb_info->dwb_params.hdr_mult = 0x1F000; 4697 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 4698 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 4699 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 4700 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 4701 4702 /* width & height from crtc */ 4703 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 4704 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 4705 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 4706 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 4707 4708 wb_info->dwb_params.cnv_params.crop_en = false; 4709 wb_info->dwb_params.stereo_params.stereo_enabled = false; 4710 4711 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 4712 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 4713 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 4714 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 4715 4716 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 4717 4718 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 4719 4720 wb_info->dwb_params.scaler_taps.h_taps = 1; 4721 wb_info->dwb_params.scaler_taps.v_taps = 1; 4722 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 4723 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 4724 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 4725 4726 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 4727 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 4728 4729 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 4730 wb_info->mcif_buf_params.luma_address[i] = afb->address; 4731 wb_info->mcif_buf_params.chroma_address[i] = 0; 4732 } 4733 4734 wb_info->mcif_buf_params.p_vmid = 1; 4735 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 4736 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 4737 wb_info->mcif_warmup_params.region_size = 4738 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 4739 } 4740 wb_info->mcif_warmup_params.p_vmid = 1; 4741 wb_info->writeback_source_plane = pipe->plane_state; 4742 4743 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 4744 4745 acrtc->wb_conn = wb_conn; 4746 drm_writeback_queue_job(wb_conn, new_con_state); 4747 4748 /* 4749 * Writeback completion is detected in the CRTC vblank IRQ 4750 * (dm_crtc_high_irq()). Take a vblank reference so the vblank interrupt 4751 * stays enabled while the writeback is pending; otherwise a 4752 * writeback-only commit right after drm_crtc_vblank_on() (e.g. 4753 * re-enabling a CRTC that was disabled) has no other vblank reference, 4754 * the IRQ never fires and the out fence times out. The matching put 4755 * happens once completion is signalled in dm_crtc_high_irq(), or when 4756 * the writeback is torn down in dm_clear_writeback(). 4757 * 4758 * Arm wb_pending only after the reference is held so the completion IRQ 4759 * cannot run its matching vblank_put before this get. 4760 */ 4761 WARN_ON(drm_crtc_vblank_get(&acrtc->base)); 4762 acrtc->wb_frame_done = false; 4763 acrtc->wb_pending = true; 4764 4765 cleanup: 4766 kfree(wb_info); 4767 } 4768 4769 static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 4770 { 4771 struct drm_connector_state *old_con_state, *new_con_state; 4772 struct drm_device *dev = state->dev; 4773 struct drm_connector *connector; 4774 struct amdgpu_device *adev = drm_to_adev(dev); 4775 int i; 4776 4777 if (!adev->dm.hdcp_workqueue) 4778 return; 4779 4780 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 4781 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 4782 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 4783 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4784 struct dm_crtc_state *dm_new_crtc_state; 4785 struct amdgpu_dm_connector *aconnector; 4786 4787 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 4788 continue; 4789 4790 aconnector = to_amdgpu_dm_connector(connector); 4791 4792 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 4793 4794 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 4795 connector->index, connector->status, connector->dpms); 4796 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 4797 old_con_state->content_protection, new_con_state->content_protection); 4798 4799 if (aconnector->dc_sink) { 4800 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 4801 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 4802 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 4803 aconnector->dc_sink->edid_caps.display_name); 4804 } 4805 } 4806 4807 new_crtc_state = NULL; 4808 old_crtc_state = NULL; 4809 4810 if (acrtc) { 4811 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 4812 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4813 } 4814 4815 if (old_crtc_state) 4816 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4817 old_crtc_state->enable, 4818 old_crtc_state->active, 4819 old_crtc_state->mode_changed, 4820 old_crtc_state->active_changed, 4821 old_crtc_state->connectors_changed); 4822 4823 if (new_crtc_state) 4824 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 4825 new_crtc_state->enable, 4826 new_crtc_state->active, 4827 new_crtc_state->mode_changed, 4828 new_crtc_state->active_changed, 4829 new_crtc_state->connectors_changed); 4830 4831 4832 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4833 4834 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 4835 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 4836 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 4837 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 4838 dm_new_con_state->update_hdcp = true; 4839 continue; 4840 } 4841 4842 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 4843 old_con_state, connector, adev->dm.hdcp_workqueue)) { 4844 /* when display is unplugged from mst hub, connctor will 4845 * be destroyed within dm_dp_mst_connector_destroy. connector 4846 * hdcp perperties, like type, undesired, desired, enabled, 4847 * will be lost. So, save hdcp properties into hdcp_work within 4848 * amdgpu_dm_atomic_commit_tail. if the same display is 4849 * plugged back with same display index, its hdcp properties 4850 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 4851 */ 4852 4853 bool enable_encryption = false; 4854 4855 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 4856 enable_encryption = true; 4857 4858 if (aconnector->dc_link && aconnector->dc_sink && 4859 aconnector->dc_link->type == dc_connection_mst_branch) { 4860 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 4861 struct hdcp_workqueue *hdcp_w = 4862 &hdcp_work[aconnector->dc_link->link_index]; 4863 4864 hdcp_w->hdcp_content_type[connector->index] = 4865 new_con_state->hdcp_content_type; 4866 hdcp_w->content_protection[connector->index] = 4867 new_con_state->content_protection; 4868 } 4869 4870 if (new_crtc_state && new_crtc_state->mode_changed && 4871 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 4872 enable_encryption = true; 4873 4874 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 4875 4876 if (aconnector->dc_link) 4877 hdcp_update_display( 4878 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 4879 new_con_state->hdcp_content_type, enable_encryption); 4880 } 4881 } 4882 } 4883 4884 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 4885 { 4886 struct drm_crtc *crtc; 4887 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4888 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4889 int i, ret; 4890 4891 ret = drm_dp_mst_atomic_setup_commit(state); 4892 if (ret) 4893 return ret; 4894 4895 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4896 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4897 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4898 /* 4899 * Color management settings. We also update color properties 4900 * when a modeset is needed, to ensure it gets reprogrammed. 4901 */ 4902 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 4903 (dm_new_crtc_state->base.color_mgmt_changed || 4904 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 4905 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4906 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 4907 if (ret) { 4908 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 4909 return ret; 4910 } 4911 } 4912 } 4913 4914 return 0; 4915 } 4916 4917 STATIC_IFN_KUNIT void set_multisync_trigger_params( 4918 struct dc_stream_state *stream) 4919 { 4920 struct dc_stream_state *master = NULL; 4921 4922 if (stream->triggered_crtc_reset.enabled) { 4923 master = stream->triggered_crtc_reset.event_source; 4924 stream->triggered_crtc_reset.event = 4925 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 4926 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 4927 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 4928 } 4929 } 4930 EXPORT_IF_KUNIT(set_multisync_trigger_params); 4931 4932 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 4933 int stream_count) 4934 { 4935 int j, highest_rfr = 0, master_stream = 0; 4936 4937 for (j = 0; j < stream_count; j++) { 4938 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 4939 int refresh_rate = 0; 4940 4941 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 4942 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 4943 if (refresh_rate > highest_rfr) { 4944 highest_rfr = refresh_rate; 4945 master_stream = j; 4946 } 4947 } 4948 } 4949 for (j = 0; j < stream_count; j++) { 4950 if (stream_set[j]) 4951 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 4952 } 4953 } 4954 EXPORT_IF_KUNIT(set_master_stream); 4955 4956 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 4957 { 4958 int i = 0; 4959 struct dc_stream_state *stream; 4960 4961 if (context->stream_count < 2) 4962 return; 4963 for (i = 0; i < context->stream_count ; i++) { 4964 if (!context->streams[i]) 4965 continue; 4966 /* 4967 * TODO: add a function to read AMD VSDB bits and set 4968 * crtc_sync_master.multi_sync_enabled flag 4969 * For now it's set to false 4970 */ 4971 } 4972 4973 set_master_stream(context->streams, context->stream_count); 4974 4975 for (i = 0; i < context->stream_count ; i++) { 4976 stream = context->streams[i]; 4977 4978 if (!stream) 4979 continue; 4980 4981 set_multisync_trigger_params(stream); 4982 } 4983 } 4984 EXPORT_IF_KUNIT(dm_enable_per_frame_crtc_master_sync); 4985 4986 /** 4987 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 4988 * @state: The atomic state to commit 4989 * 4990 * This will tell DC to commit the constructed DC state from atomic_check, 4991 * programming the hardware. Any failures here implies a hardware failure, since 4992 * atomic check should have filtered anything non-kosher. 4993 */ 4994 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 4995 { 4996 struct drm_device *dev = state->dev; 4997 struct amdgpu_device *adev = drm_to_adev(dev); 4998 struct amdgpu_display_manager *dm = &adev->dm; 4999 struct dm_atomic_state *dm_state; 5000 struct dc_state *dc_state = NULL; 5001 u32 i, j; 5002 struct drm_crtc *crtc; 5003 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5004 unsigned long flags; 5005 bool wait_for_vblank = true; 5006 struct drm_connector *connector; 5007 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5008 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5009 int crtc_disable_count = 0; 5010 5011 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5012 5013 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5014 drm_dp_mst_atomic_wait_for_dependencies(state); 5015 5016 dm_state = dm_atomic_get_new_state(state); 5017 if (dm_state && dm_state->context) { 5018 dc_state = dm_state->context; 5019 amdgpu_dm_commit_streams(state, dc_state); 5020 } 5021 5022 amdgpu_dm_update_hdcp(state); 5023 5024 /* Handle connector state changes */ 5025 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5026 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5027 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5028 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5029 struct dc_surface_update *dummy_updates; 5030 struct dc_stream_update stream_update; 5031 struct dc_info_packet hdr_packet; 5032 struct dc_stream_status *status = NULL; 5033 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5034 5035 memset(&stream_update, 0, sizeof(stream_update)); 5036 5037 if (acrtc) { 5038 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5039 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5040 } 5041 5042 /* Skip any modesets/resets */ 5043 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5044 continue; 5045 5046 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5047 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5048 5049 scaling_changed = is_scaling_state_different(dm_new_con_state, 5050 dm_old_con_state); 5051 5052 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5053 (dm_old_crtc_state->stream->output_color_space != 5054 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5055 output_color_space_changed = true; 5056 5057 abm_changed = dm_new_crtc_state->abm_level != 5058 dm_old_crtc_state->abm_level; 5059 5060 hdr_changed = 5061 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5062 5063 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5064 continue; 5065 5066 stream_update.stream = dm_new_crtc_state->stream; 5067 if (scaling_changed) { 5068 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5069 dm_new_con_state, dm_new_crtc_state->stream); 5070 5071 stream_update.src = dm_new_crtc_state->stream->src; 5072 stream_update.dst = dm_new_crtc_state->stream->dst; 5073 } 5074 5075 if (output_color_space_changed) { 5076 dm_new_crtc_state->stream->output_color_space 5077 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5078 5079 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5080 } 5081 5082 if (abm_changed) { 5083 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5084 5085 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5086 } 5087 5088 if (hdr_changed) { 5089 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5090 stream_update.hdr_static_metadata = &hdr_packet; 5091 } 5092 5093 status = dc_stream_get_status(dm_new_crtc_state->stream); 5094 5095 if (WARN_ON(!status)) 5096 continue; 5097 5098 WARN_ON(!status->plane_count); 5099 5100 /* 5101 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5102 * Here we create an empty update on each plane. 5103 * To fix this, DC should permit updating only stream properties. 5104 */ 5105 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5106 if (!dummy_updates) { 5107 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5108 continue; 5109 } 5110 for (j = 0; j < status->plane_count; j++) 5111 dummy_updates[j].surface = status->plane_states[j]; 5112 5113 sort(dummy_updates, status->plane_count, 5114 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5115 5116 mutex_lock(&dm->dc_lock); 5117 dc_exit_ips_for_hw_access(dm->dc); 5118 dc_update_planes_and_stream(dm->dc, 5119 dummy_updates, 5120 status->plane_count, 5121 dm_new_crtc_state->stream, 5122 &stream_update); 5123 mutex_unlock(&dm->dc_lock); 5124 kfree(dummy_updates); 5125 5126 drm_connector_update_privacy_screen(new_con_state); 5127 } 5128 5129 /** 5130 * Enable interrupts for CRTCs that are newly enabled or went through 5131 * a modeset. It was intentionally deferred until after the front end 5132 * state was modified to wait until the OTG was on and so the IRQ 5133 * handlers didn't access stale or invalid state. 5134 */ 5135 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5136 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5137 #ifdef CONFIG_DEBUG_FS 5138 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5139 #endif 5140 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5141 if (old_crtc_state->active && !new_crtc_state->active) 5142 crtc_disable_count++; 5143 5144 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5145 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5146 5147 /* For freesync config update on crtc state and params for irq */ 5148 amdgpu_dm_update_stream_irq_parameters(dm, dm_new_crtc_state); 5149 5150 #ifdef CONFIG_DEBUG_FS 5151 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5152 cur_crc_src = acrtc->dm_irq_params.crc_src; 5153 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5154 #endif 5155 5156 if (new_crtc_state->active && 5157 (!old_crtc_state->active || 5158 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5159 dc_stream_retain(dm_new_crtc_state->stream); 5160 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5161 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5162 } 5163 /* Handle vrr on->off / off->on transitions */ 5164 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5165 5166 #ifdef CONFIG_DEBUG_FS 5167 if (new_crtc_state->active && 5168 (!old_crtc_state->active || 5169 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5170 /** 5171 * Frontend may have changed so reapply the CRC capture 5172 * settings for the stream. 5173 */ 5174 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5175 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5176 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5177 uint8_t cnt; 5178 5179 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5180 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5181 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5182 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5183 5184 /** 5185 * It takes 2 frames for HW to stably generate CRC when 5186 * resuming from suspend, so we set skip_frame_cnt 2. 5187 */ 5188 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5189 } 5190 } 5191 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5192 } 5193 #endif 5194 if (amdgpu_dm_crtc_configure_crc_source( 5195 crtc, dm_new_crtc_state, cur_crc_src)) 5196 drm_dbg_atomic(dev, "Failed to configure crc source"); 5197 } 5198 } 5199 #endif 5200 } 5201 5202 amdgpu_dm_mod_power_setup_streams(state, dm); 5203 5204 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5205 if (new_crtc_state->async_flip) 5206 wait_for_vblank = false; 5207 5208 /* update planes when needed per crtc*/ 5209 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5210 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5211 5212 if (dm_new_crtc_state->stream) 5213 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5214 } 5215 5216 /* Enable writeback */ 5217 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5218 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5219 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5220 5221 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5222 continue; 5223 5224 if (!new_con_state->writeback_job) 5225 continue; 5226 5227 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5228 5229 if (!new_crtc_state) 5230 continue; 5231 5232 if (acrtc->wb_enabled) 5233 continue; 5234 5235 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5236 5237 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5238 acrtc->wb_enabled = true; 5239 } 5240 5241 /* Update audio instances for each connector. */ 5242 amdgpu_dm_commit_audio(dev, state); 5243 5244 /* restore the backlight level */ 5245 for (i = 0; i < dm->num_of_edps; i++) { 5246 if (dm->backlight_dev[i] && 5247 (dm->actual_brightness[i] != dm->brightness[i])) 5248 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5249 } 5250 5251 /* 5252 * send vblank event on all events not handled in flip and 5253 * mark consumed event for drm_atomic_helper_commit_hw_done 5254 */ 5255 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5256 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5257 5258 if (new_crtc_state->event) 5259 drm_send_event_locked(dev, &new_crtc_state->event->base); 5260 5261 new_crtc_state->event = NULL; 5262 } 5263 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5264 5265 /* Signal HW programming completion */ 5266 drm_atomic_helper_commit_hw_done(state); 5267 5268 if (wait_for_vblank) 5269 drm_atomic_helper_wait_for_flip_done(dev, state); 5270 5271 drm_atomic_helper_cleanup_planes(dev, state); 5272 5273 /* Don't free the memory if we are hitting this as part of suspend. 5274 * This way we don't free any memory during suspend; see 5275 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5276 * non-suspend modeset or when the driver is torn down. 5277 */ 5278 if (!adev->in_suspend) { 5279 /* return the stolen vga memory back to VRAM */ 5280 if (!adev->mman.keep_stolen_vga_memory) 5281 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5282 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5283 } 5284 5285 /* 5286 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5287 * so we can put the GPU into runtime suspend if we're not driving any 5288 * displays anymore 5289 */ 5290 for (i = 0; i < crtc_disable_count; i++) 5291 pm_runtime_put_autosuspend(dev->dev); 5292 pm_runtime_mark_last_busy(dev->dev); 5293 5294 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5295 } 5296 5297 /* 5298 * Grabs all modesetting locks to serialize against any blocking commits, 5299 * Waits for completion of all non blocking commits. 5300 */ 5301 static int do_aquire_global_lock(struct drm_device *dev, 5302 struct drm_atomic_commit *state) 5303 { 5304 struct drm_crtc *crtc; 5305 struct drm_crtc_commit *commit; 5306 long ret; 5307 5308 /* 5309 * Adding all modeset locks to aquire_ctx will 5310 * ensure that when the framework release it the 5311 * extra locks we are locking here will get released to 5312 */ 5313 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5314 if (ret) 5315 return ret; 5316 5317 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5318 spin_lock(&crtc->commit_lock); 5319 commit = list_first_entry_or_null(&crtc->commit_list, 5320 struct drm_crtc_commit, commit_entry); 5321 if (commit) 5322 drm_crtc_commit_get(commit); 5323 spin_unlock(&crtc->commit_lock); 5324 5325 if (!commit) 5326 continue; 5327 5328 /* 5329 * Make sure all pending HW programming completed and 5330 * page flips done 5331 */ 5332 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5333 5334 if (ret > 0) 5335 ret = wait_for_completion_interruptible_timeout( 5336 &commit->flip_done, 10*HZ); 5337 5338 if (ret == 0) 5339 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5340 crtc->base.id, crtc->name); 5341 5342 drm_crtc_commit_put(commit); 5343 } 5344 5345 return ret < 0 ? ret : 0; 5346 } 5347 5348 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5349 struct drm_atomic_commit *state, 5350 struct drm_crtc *crtc, 5351 struct drm_crtc_state *old_crtc_state, 5352 struct drm_crtc_state *new_crtc_state, 5353 bool enable, 5354 bool *lock_and_validation_needed) 5355 { 5356 struct dm_atomic_state *dm_state = NULL; 5357 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5358 struct dc_stream_state *new_stream; 5359 struct amdgpu_device *adev = dm->adev; 5360 int ret = 0; 5361 5362 /* 5363 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5364 * update changed items 5365 */ 5366 struct amdgpu_crtc *acrtc = NULL; 5367 struct drm_connector *connector = NULL; 5368 struct amdgpu_dm_connector *aconnector = NULL; 5369 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5370 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5371 5372 new_stream = NULL; 5373 5374 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5375 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5376 acrtc = to_amdgpu_crtc(crtc); 5377 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5378 if (connector) 5379 aconnector = to_amdgpu_dm_connector(connector); 5380 5381 /* TODO This hack should go away */ 5382 if (connector && enable) { 5383 /* Make sure fake sink is created in plug-in scenario */ 5384 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5385 connector); 5386 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5387 connector); 5388 5389 if (WARN_ON(!drm_new_conn_state)) { 5390 ret = -EINVAL; 5391 goto fail; 5392 } 5393 5394 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5395 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5396 5397 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5398 goto skip_modeset; 5399 5400 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5401 &new_crtc_state->mode, 5402 dm_new_conn_state, 5403 dm_old_crtc_state->stream); 5404 5405 /* 5406 * we can have no stream on ACTION_SET if a display 5407 * was disconnected during S3, in this case it is not an 5408 * error, the OS will be updated after detection, and 5409 * will do the right thing on next atomic commit 5410 */ 5411 5412 if (!new_stream) { 5413 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5414 __func__, acrtc->base.base.id); 5415 ret = -ENOMEM; 5416 goto fail; 5417 } 5418 5419 /* 5420 * TODO: Check VSDB bits to decide whether this should 5421 * be enabled or not. 5422 */ 5423 new_stream->triggered_crtc_reset.enabled = 5424 dm->force_timing_sync; 5425 5426 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5427 5428 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5429 &new_stream->hdr_static_metadata); 5430 if (ret) 5431 goto fail; 5432 5433 /* 5434 * If we already removed the old stream from the context 5435 * (and set the new stream to NULL) then we can't reuse 5436 * the old stream even if the stream and scaling are unchanged. 5437 * We'll hit the BUG_ON and black screen. 5438 * 5439 * TODO: Refactor this function to allow this check to work 5440 * in all conditions. 5441 */ 5442 if (amdgpu_freesync_vid_mode && 5443 dm_new_crtc_state->stream && 5444 amdgpu_dm_is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5445 goto skip_modeset; 5446 5447 if (dm_new_crtc_state->stream && 5448 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5449 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5450 new_crtc_state->mode_changed = false; 5451 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5452 new_crtc_state->mode_changed); 5453 } 5454 } 5455 5456 /* mode_changed flag may get updated above, need to check again */ 5457 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5458 goto skip_modeset; 5459 5460 drm_dbg_state(state->dev, 5461 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5462 acrtc->crtc_id, 5463 new_crtc_state->enable, 5464 new_crtc_state->active, 5465 new_crtc_state->planes_changed, 5466 new_crtc_state->mode_changed, 5467 new_crtc_state->active_changed, 5468 new_crtc_state->connectors_changed); 5469 5470 /* Remove stream for any changed/disabled CRTC */ 5471 if (!enable) { 5472 5473 if (!dm_old_crtc_state->stream) 5474 goto skip_modeset; 5475 5476 /* Unset freesync video if it was active before */ 5477 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5478 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5479 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5480 } 5481 5482 /* Now check if we should set freesync video mode */ 5483 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5484 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5485 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5486 amdgpu_dm_is_timing_unchanged_for_freesync(new_crtc_state, 5487 old_crtc_state)) { 5488 new_crtc_state->mode_changed = false; 5489 drm_dbg_driver(adev_to_drm(adev), 5490 "Mode change not required for front porch change, setting mode_changed to %d", 5491 new_crtc_state->mode_changed); 5492 5493 amdgpu_dm_set_freesync_fixed_config(dm_new_crtc_state); 5494 5495 goto skip_modeset; 5496 } else if (amdgpu_freesync_vid_mode && aconnector && 5497 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5498 aconnector)) { 5499 struct drm_display_mode *high_mode; 5500 5501 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5502 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 5503 amdgpu_dm_set_freesync_fixed_config(dm_new_crtc_state); 5504 } 5505 5506 ret = dm_atomic_get_state(state, &dm_state); 5507 if (ret) 5508 goto fail; 5509 5510 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 5511 crtc->base.id); 5512 5513 /* i.e. reset mode */ 5514 if (dc_state_remove_stream( 5515 dm->dc, 5516 dm_state->context, 5517 dm_old_crtc_state->stream) != DC_OK) { 5518 ret = -EINVAL; 5519 goto fail; 5520 } 5521 5522 dc_stream_release(dm_old_crtc_state->stream); 5523 dm_new_crtc_state->stream = NULL; 5524 5525 amdgpu_dm_reset_freesync_config_for_crtc(dm_new_crtc_state); 5526 5527 *lock_and_validation_needed = true; 5528 5529 } else {/* Add stream for any updated/enabled CRTC */ 5530 /* 5531 * Quick fix to prevent NULL pointer on new_stream when 5532 * added MST connectors not found in existing crtc_state in the chained mode 5533 * TODO: need to dig out the root cause of that 5534 */ 5535 if (!connector) 5536 goto skip_modeset; 5537 5538 if (modereset_required(new_crtc_state)) 5539 goto skip_modeset; 5540 5541 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 5542 dm_old_crtc_state->stream)) { 5543 5544 WARN_ON(dm_new_crtc_state->stream); 5545 5546 ret = dm_atomic_get_state(state, &dm_state); 5547 if (ret) 5548 goto fail; 5549 5550 dm_new_crtc_state->stream = new_stream; 5551 5552 dc_stream_retain(new_stream); 5553 5554 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 5555 crtc->base.id); 5556 5557 if (dc_state_add_stream( 5558 dm->dc, 5559 dm_state->context, 5560 dm_new_crtc_state->stream) != DC_OK) { 5561 ret = -EINVAL; 5562 goto fail; 5563 } 5564 5565 *lock_and_validation_needed = true; 5566 } 5567 } 5568 5569 skip_modeset: 5570 /* Release extra reference */ 5571 if (new_stream) 5572 dc_stream_release(new_stream); 5573 new_stream = NULL; 5574 5575 /* 5576 * We want to do dc stream updates that do not require a 5577 * full modeset below. 5578 */ 5579 if (!(enable && connector && new_crtc_state->active)) 5580 return 0; 5581 /* 5582 * Given above conditions, the dc state cannot be NULL because: 5583 * 1. We're in the process of enabling CRTCs (just been added 5584 * to the dc context, or already is on the context) 5585 * 2. Has a valid connector attached, and 5586 * 3. Is currently active and enabled. 5587 * => The dc stream state currently exists. 5588 */ 5589 BUG_ON(dm_new_crtc_state->stream == NULL); 5590 5591 /* Scaling or underscan settings */ 5592 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 5593 drm_atomic_crtc_needs_modeset(new_crtc_state)) 5594 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 5595 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5596 5597 /* ABM settings */ 5598 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5599 5600 /* 5601 * Color management settings. We also update color properties 5602 * when a modeset is needed, to ensure it gets reprogrammed. 5603 */ 5604 if (dm_new_crtc_state->base.color_mgmt_changed || 5605 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5606 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5607 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 5608 if (ret) 5609 goto fail; 5610 } 5611 5612 /* Update Freesync settings. */ 5613 amdgpu_dm_get_freesync_config_for_crtc(dm_new_crtc_state, 5614 dm_new_conn_state); 5615 5616 return ret; 5617 5618 fail: 5619 if (new_stream) 5620 dc_stream_release(new_stream); 5621 return ret; 5622 } 5623 5624 static bool should_reset_plane(struct drm_atomic_commit *state, 5625 struct drm_plane *plane, 5626 struct drm_plane_state *old_plane_state, 5627 struct drm_plane_state *new_plane_state) 5628 { 5629 struct drm_plane *other; 5630 struct drm_plane_state *old_other_state, *new_other_state; 5631 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5632 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 5633 struct amdgpu_device *adev = drm_to_adev(plane->dev); 5634 struct drm_connector_state *new_con_state; 5635 struct drm_connector *connector; 5636 int i; 5637 5638 /* 5639 * TODO: Remove this hack for all asics once it proves that the 5640 * fast updates works fine on DCN3.2+. 5641 */ 5642 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 5643 state->allow_modeset) 5644 return true; 5645 5646 /* Check for writeback commit */ 5647 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5648 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5649 continue; 5650 5651 if (new_con_state->writeback_job) 5652 return true; 5653 } 5654 5655 if (amdgpu_in_reset(adev) && state->allow_modeset) 5656 return true; 5657 5658 /* Exit early if we know that we're adding or removing the plane. */ 5659 if (old_plane_state->crtc != new_plane_state->crtc) 5660 return true; 5661 5662 /* old crtc == new_crtc == NULL, plane not in context. */ 5663 if (!new_plane_state->crtc) 5664 return false; 5665 5666 new_crtc_state = 5667 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 5668 old_crtc_state = 5669 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 5670 5671 if (!new_crtc_state) 5672 return true; 5673 5674 /* 5675 * A change in cursor mode means a new dc pipe needs to be acquired or 5676 * released from the state 5677 */ 5678 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 5679 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 5680 if (plane->type == DRM_PLANE_TYPE_CURSOR && 5681 old_dm_crtc_state != NULL && 5682 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 5683 return true; 5684 } 5685 5686 /* CRTC Degamma changes currently require us to recreate planes. */ 5687 if (new_crtc_state->color_mgmt_changed) 5688 return true; 5689 5690 /* 5691 * On zpos change, planes need to be reordered by removing and re-adding 5692 * them one by one to the dc state, in order of descending zpos. 5693 * 5694 * TODO: We can likely skip bandwidth validation if the only thing that 5695 * changed about the plane was it'z z-ordering. 5696 */ 5697 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 5698 return true; 5699 5700 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 5701 return true; 5702 5703 /* 5704 * If there are any new primary or overlay planes being added or 5705 * removed then the z-order can potentially change. To ensure 5706 * correct z-order and pipe acquisition the current DC architecture 5707 * requires us to remove and recreate all existing planes. 5708 * 5709 * TODO: Come up with a more elegant solution for this. 5710 */ 5711 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 5712 struct amdgpu_framebuffer *old_afb, *new_afb; 5713 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 5714 5715 dm_new_other_state = to_dm_plane_state(new_other_state); 5716 dm_old_other_state = to_dm_plane_state(old_other_state); 5717 5718 if (other->type == DRM_PLANE_TYPE_CURSOR) 5719 continue; 5720 5721 if (old_other_state->crtc != new_plane_state->crtc && 5722 new_other_state->crtc != new_plane_state->crtc) 5723 continue; 5724 5725 if (old_other_state->crtc != new_other_state->crtc) 5726 return true; 5727 5728 /* Src/dst size and scaling updates. */ 5729 if (old_other_state->src_w != new_other_state->src_w || 5730 old_other_state->src_h != new_other_state->src_h || 5731 old_other_state->crtc_w != new_other_state->crtc_w || 5732 old_other_state->crtc_h != new_other_state->crtc_h) 5733 return true; 5734 5735 /* Rotation / mirroring updates. */ 5736 if (old_other_state->rotation != new_other_state->rotation) 5737 return true; 5738 5739 /* Blending updates. */ 5740 if (old_other_state->pixel_blend_mode != 5741 new_other_state->pixel_blend_mode) 5742 return true; 5743 5744 /* Alpha updates. */ 5745 if (old_other_state->alpha != new_other_state->alpha) 5746 return true; 5747 5748 /* Colorspace changes. */ 5749 if (old_other_state->color_range != new_other_state->color_range || 5750 old_other_state->color_encoding != new_other_state->color_encoding) 5751 return true; 5752 5753 /* HDR/Transfer Function changes. */ 5754 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 5755 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 5756 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 5757 dm_old_other_state->ctm != dm_new_other_state->ctm || 5758 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 5759 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 5760 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 5761 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 5762 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 5763 return true; 5764 5765 /* Framebuffer checks fall at the end. */ 5766 if (!old_other_state->fb || !new_other_state->fb) 5767 continue; 5768 5769 /* Pixel format changes can require bandwidth updates. */ 5770 if (old_other_state->fb->format != new_other_state->fb->format) 5771 return true; 5772 5773 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 5774 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 5775 5776 /* Tiling and DCC changes also require bandwidth updates. */ 5777 if (old_afb->base.modifier != new_afb->base.modifier) 5778 return true; 5779 } 5780 5781 return false; 5782 } 5783 5784 static int dm_update_plane_state(struct dc *dc, 5785 struct drm_atomic_commit *state, 5786 struct drm_plane *plane, 5787 struct drm_plane_state *old_plane_state, 5788 struct drm_plane_state *new_plane_state, 5789 bool enable, 5790 bool *lock_and_validation_needed, 5791 bool *is_top_most_overlay) 5792 { 5793 5794 struct dm_atomic_state *dm_state = NULL; 5795 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 5796 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5797 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 5798 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 5799 bool needs_reset, update_native_cursor; 5800 int ret = 0; 5801 5802 5803 new_plane_crtc = new_plane_state->crtc; 5804 old_plane_crtc = old_plane_state->crtc; 5805 dm_new_plane_state = to_dm_plane_state(new_plane_state); 5806 dm_old_plane_state = to_dm_plane_state(old_plane_state); 5807 5808 update_native_cursor = amdgpu_dm_should_update_native_cursor(state, 5809 old_plane_crtc, 5810 new_plane_crtc, 5811 enable); 5812 5813 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 5814 ret = amdgpu_dm_check_native_cursor_state(new_plane_crtc, plane, 5815 new_plane_state, enable); 5816 if (ret) 5817 return ret; 5818 5819 return 0; 5820 } 5821 5822 needs_reset = should_reset_plane(state, plane, old_plane_state, 5823 new_plane_state); 5824 5825 /* Remove any changed/removed planes */ 5826 if (!enable) { 5827 if (!needs_reset) 5828 return 0; 5829 5830 if (!old_plane_crtc) 5831 return 0; 5832 5833 old_crtc_state = drm_atomic_get_old_crtc_state( 5834 state, old_plane_crtc); 5835 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5836 5837 if (!dm_old_crtc_state->stream) 5838 return 0; 5839 5840 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 5841 plane->base.id, old_plane_crtc->base.id); 5842 5843 ret = dm_atomic_get_state(state, &dm_state); 5844 if (ret) 5845 return ret; 5846 5847 if (!dc_state_remove_plane( 5848 dc, 5849 dm_old_crtc_state->stream, 5850 dm_old_plane_state->dc_state, 5851 dm_state->context)) { 5852 5853 return -EINVAL; 5854 } 5855 5856 if (dm_old_plane_state->dc_state) 5857 dc_plane_state_release(dm_old_plane_state->dc_state); 5858 5859 dm_new_plane_state->dc_state = NULL; 5860 5861 *lock_and_validation_needed = true; 5862 5863 } else { /* Add new planes */ 5864 struct dc_plane_state *dc_new_plane_state; 5865 5866 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 5867 return 0; 5868 5869 if (!new_plane_crtc) 5870 return 0; 5871 5872 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 5873 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5874 5875 if (!dm_new_crtc_state->stream) 5876 return 0; 5877 5878 if (!needs_reset) 5879 return 0; 5880 5881 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 5882 if (ret) 5883 goto out; 5884 5885 WARN_ON(dm_new_plane_state->dc_state); 5886 5887 dc_new_plane_state = dc_create_plane_state(dc); 5888 if (!dc_new_plane_state) { 5889 ret = -ENOMEM; 5890 goto out; 5891 } 5892 5893 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 5894 plane->base.id, new_plane_crtc->base.id); 5895 5896 ret = fill_dc_plane_attributes( 5897 drm_to_adev(new_plane_crtc->dev), 5898 dc_new_plane_state, 5899 new_plane_state, 5900 new_crtc_state); 5901 if (ret) { 5902 dc_plane_state_release(dc_new_plane_state); 5903 goto out; 5904 } 5905 5906 ret = dm_atomic_get_state(state, &dm_state); 5907 if (ret) { 5908 dc_plane_state_release(dc_new_plane_state); 5909 goto out; 5910 } 5911 5912 /* 5913 * Any atomic check errors that occur after this will 5914 * not need a release. The plane state will be attached 5915 * to the stream, and therefore part of the atomic 5916 * state. It'll be released when the atomic state is 5917 * cleaned. 5918 */ 5919 if (!dc_state_add_plane( 5920 dc, 5921 dm_new_crtc_state->stream, 5922 dc_new_plane_state, 5923 dm_state->context)) { 5924 5925 dc_plane_state_release(dc_new_plane_state); 5926 ret = -EINVAL; 5927 goto out; 5928 } 5929 5930 dm_new_plane_state->dc_state = dc_new_plane_state; 5931 5932 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 5933 5934 /* Tell DC to do a full surface update every time there 5935 * is a plane change. Inefficient, but works for now. 5936 */ 5937 dm_new_plane_state->dc_state->update_bits.full_update = 1; 5938 5939 *lock_and_validation_needed = true; 5940 } 5941 5942 out: 5943 /* If enabling cursor overlay failed, attempt fallback to native mode */ 5944 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 5945 ret = amdgpu_dm_check_native_cursor_state(new_plane_crtc, plane, 5946 new_plane_state, enable); 5947 if (ret) 5948 return ret; 5949 5950 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 5951 } 5952 5953 return ret; 5954 } 5955 5956 /* 5957 * The normalized_zpos value cannot be used by this iterator directly. It's only 5958 * calculated for enabled planes, potentially causing normalized_zpos collisions 5959 * between enabled/disabled planes in the atomic state. We need a unique value 5960 * so that the iterator will not generate the same object twice, or loop 5961 * indefinitely. 5962 */ 5963 struct __drm_planes_state *amdgpu_dm_get_next_zpos( 5964 struct drm_atomic_commit *state, 5965 struct __drm_planes_state *prev) 5966 { 5967 unsigned int highest_zpos = 0, prev_zpos = 256; 5968 uint32_t highest_id = 0, prev_id = UINT_MAX; 5969 struct drm_plane_state *new_plane_state; 5970 struct drm_plane *plane; 5971 int i, highest_i = -1; 5972 5973 if (prev != NULL) { 5974 prev_zpos = prev->new_state->zpos; 5975 prev_id = prev->ptr->base.id; 5976 } 5977 5978 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 5979 /* Skip planes with higher zpos than the previously returned */ 5980 if (new_plane_state->zpos > prev_zpos || 5981 (new_plane_state->zpos == prev_zpos && 5982 plane->base.id >= prev_id)) 5983 continue; 5984 5985 /* Save the index of the plane with highest zpos */ 5986 if (new_plane_state->zpos > highest_zpos || 5987 (new_plane_state->zpos == highest_zpos && 5988 plane->base.id > highest_id)) { 5989 highest_zpos = new_plane_state->zpos; 5990 highest_id = plane->base.id; 5991 highest_i = i; 5992 } 5993 } 5994 5995 if (highest_i < 0) 5996 return NULL; 5997 5998 return &state->planes[highest_i]; 5999 } 6000 6001 static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) 6002 { 6003 struct drm_connector *connector; 6004 struct drm_connector_state *conn_state, *old_conn_state; 6005 struct amdgpu_dm_connector *aconnector = NULL; 6006 int i; 6007 6008 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6009 if (!conn_state->crtc) 6010 conn_state = old_conn_state; 6011 6012 if (conn_state->crtc != crtc) 6013 continue; 6014 6015 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6016 continue; 6017 6018 aconnector = to_amdgpu_dm_connector(connector); 6019 if (!aconnector->mst_output_port || !aconnector->mst_root) 6020 aconnector = NULL; 6021 else 6022 break; 6023 } 6024 6025 if (!aconnector) 6026 return 0; 6027 6028 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6029 } 6030 6031 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6032 struct drm_atomic_commit *state, 6033 struct drm_crtc_state *crtc_state) 6034 { 6035 struct drm_plane *plane; 6036 struct drm_plane_state *new_plane_state, *old_plane_state; 6037 6038 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6039 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6040 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6041 6042 if (!old_plane_state || !new_plane_state) 6043 continue; 6044 6045 if (old_plane_state->fb && new_plane_state->fb && 6046 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6047 return true; 6048 } 6049 6050 return false; 6051 } 6052 6053 /** 6054 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6055 * 6056 * @dev: The DRM device 6057 * @state: The atomic state to commit 6058 * 6059 * Validate that the given atomic state is programmable by DC into hardware. 6060 * This involves constructing a &struct dc_state reflecting the new hardware 6061 * state we wish to commit, then querying DC to see if it is programmable. It's 6062 * important not to modify the existing DC state. Otherwise, atomic_check 6063 * may unexpectedly commit hardware changes. 6064 * 6065 * When validating the DC state, it's important that the right locks are 6066 * acquired. For full updates case which removes/adds/updates streams on one 6067 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6068 * that any such full update commit will wait for completion of any outstanding 6069 * flip using DRMs synchronization events. 6070 * 6071 * Note that DM adds the affected connectors for all CRTCs in state, when that 6072 * might not seem necessary. This is because DC stream creation requires the 6073 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6074 * be possible but non-trivial - a possible TODO item. 6075 * 6076 * Return: -Error code if validation failed. 6077 */ 6078 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6079 struct drm_atomic_commit *state) 6080 { 6081 struct amdgpu_device *adev = drm_to_adev(dev); 6082 struct dm_atomic_state *dm_state = NULL; 6083 struct dc *dc = adev->dm.dc; 6084 struct drm_connector *connector; 6085 struct drm_connector_state *old_con_state, *new_con_state; 6086 struct drm_crtc *crtc; 6087 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6088 struct drm_plane *plane; 6089 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6090 enum dc_status status; 6091 int ret, i; 6092 bool lock_and_validation_needed = false; 6093 bool is_top_most_overlay = true; 6094 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6095 struct drm_dp_mst_topology_mgr *mgr; 6096 struct drm_dp_mst_topology_state *mst_state; 6097 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 6098 6099 trace_amdgpu_dm_atomic_check_begin(state); 6100 6101 ret = drm_atomic_helper_check_modeset(dev, state); 6102 if (ret) { 6103 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed: %pe\n", ERR_PTR(ret)); 6104 goto fail; 6105 } 6106 6107 /* Check connector changes */ 6108 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6109 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6110 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6111 6112 /* Skip connectors that are disabled or part of modeset already. */ 6113 if (!new_con_state->crtc) 6114 continue; 6115 6116 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 6117 if (IS_ERR(new_crtc_state)) { 6118 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed: %pe\n", new_crtc_state); 6119 ret = PTR_ERR(new_crtc_state); 6120 goto fail; 6121 } 6122 6123 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 6124 dm_old_con_state->scaling != dm_new_con_state->scaling) 6125 new_crtc_state->connectors_changed = true; 6126 } 6127 6128 if (dc_resource_is_dsc_encoding_supported(dc)) { 6129 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6130 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6131 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 6132 } 6133 6134 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6135 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6136 ret = add_affected_mst_dsc_crtcs(state, crtc); 6137 if (ret) { 6138 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed: %pe\n", ERR_PTR(ret)); 6139 goto fail; 6140 } 6141 } 6142 } 6143 } 6144 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6145 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6146 6147 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6148 !new_crtc_state->color_mgmt_changed && 6149 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 6150 dm_old_crtc_state->dsc_force_changed == false) 6151 continue; 6152 6153 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 6154 if (ret) { 6155 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed: %pe\n", ERR_PTR(ret)); 6156 goto fail; 6157 } 6158 6159 if (!new_crtc_state->enable) 6160 continue; 6161 6162 ret = drm_atomic_add_affected_connectors(state, crtc); 6163 if (ret) { 6164 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed: %pe\n", ERR_PTR(ret)); 6165 goto fail; 6166 } 6167 6168 ret = drm_atomic_add_affected_planes(state, crtc); 6169 if (ret) { 6170 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed: %pe\n", ERR_PTR(ret)); 6171 goto fail; 6172 } 6173 6174 if (dm_old_crtc_state->dsc_force_changed) 6175 new_crtc_state->mode_changed = true; 6176 } 6177 6178 /* 6179 * Add all primary and overlay planes on the CRTC to the state 6180 * whenever a plane is enabled to maintain correct z-ordering 6181 * and to enable fast surface updates. 6182 */ 6183 drm_for_each_crtc(crtc, dev) { 6184 bool modified = false; 6185 6186 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6187 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6188 continue; 6189 6190 if (new_plane_state->crtc == crtc || 6191 old_plane_state->crtc == crtc) { 6192 modified = true; 6193 break; 6194 } 6195 } 6196 6197 if (!modified) 6198 continue; 6199 6200 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6201 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6202 continue; 6203 6204 new_plane_state = 6205 drm_atomic_get_plane_state(state, plane); 6206 6207 if (IS_ERR(new_plane_state)) { 6208 ret = PTR_ERR(new_plane_state); 6209 drm_dbg_atomic(dev, "new_plane_state is BAD: %pe\n", new_plane_state); 6210 goto fail; 6211 } 6212 } 6213 } 6214 6215 /* 6216 * DC consults the zpos (layer_index in DC terminology) to determine the 6217 * hw plane on which to enable the hw cursor (see 6218 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 6219 * atomic state, so call drm helper to normalize zpos. 6220 */ 6221 ret = drm_atomic_normalize_zpos(dev, state); 6222 if (ret) { 6223 drm_dbg(dev, "drm_atomic_normalize_zpos() failed: %pe\n", ERR_PTR(ret)); 6224 goto fail; 6225 } 6226 6227 /* 6228 * Determine whether cursors on each CRTC should be enabled in native or 6229 * overlay mode. 6230 */ 6231 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6232 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6233 6234 ret = amdgpu_dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6235 &dm_new_crtc_state->cursor_mode); 6236 if (ret) { 6237 drm_dbg(dev, "Failed to determine cursor mode: %pe\n", ERR_PTR(ret)); 6238 goto fail; 6239 } 6240 6241 /* 6242 * If overlay cursor is needed, DC cannot go through the 6243 * native cursor update path. All enabled planes on the CRTC 6244 * need to be added for DC to not disable a plane by mistake 6245 */ 6246 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6247 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 6248 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 6249 ret = -EINVAL; 6250 goto fail; 6251 } 6252 6253 ret = drm_atomic_add_affected_planes(state, crtc); 6254 if (ret) 6255 goto fail; 6256 } 6257 } 6258 6259 /* Remove exiting planes if they are modified */ 6260 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6261 6262 ret = dm_update_plane_state(dc, state, plane, 6263 old_plane_state, 6264 new_plane_state, 6265 false, 6266 &lock_and_validation_needed, 6267 &is_top_most_overlay); 6268 if (ret) { 6269 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 6270 goto fail; 6271 } 6272 } 6273 6274 /* Disable all crtcs which require disable */ 6275 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6276 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6277 old_crtc_state, 6278 new_crtc_state, 6279 false, 6280 &lock_and_validation_needed); 6281 if (ret) { 6282 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 6283 goto fail; 6284 } 6285 } 6286 6287 /* Enable all crtcs which require enable */ 6288 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6289 ret = dm_update_crtc_state(&adev->dm, state, crtc, 6290 old_crtc_state, 6291 new_crtc_state, 6292 true, 6293 &lock_and_validation_needed); 6294 if (ret) { 6295 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 6296 goto fail; 6297 } 6298 } 6299 6300 /* Add new/modified planes */ 6301 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6302 ret = dm_update_plane_state(dc, state, plane, 6303 old_plane_state, 6304 new_plane_state, 6305 true, 6306 &lock_and_validation_needed, 6307 &is_top_most_overlay); 6308 if (ret) { 6309 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 6310 goto fail; 6311 } 6312 } 6313 6314 #if defined(CONFIG_DRM_AMD_DC_FP) 6315 if (dc_resource_is_dsc_encoding_supported(dc)) { 6316 ret = pre_validate_dsc(state, &dm_state, vars); 6317 if (ret != 0) 6318 goto fail; 6319 } 6320 #endif 6321 6322 /* Run this here since we want to validate the streams we created */ 6323 ret = drm_atomic_helper_check_planes(dev, state); 6324 if (ret) { 6325 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed: %pe\n", ERR_PTR(ret)); 6326 goto fail; 6327 } 6328 6329 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6330 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6331 if (dm_new_crtc_state->mpo_requested) 6332 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 6333 } 6334 6335 /* Check cursor restrictions */ 6336 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6337 enum amdgpu_dm_cursor_mode required_cursor_mode; 6338 int is_rotated, is_scaled; 6339 6340 /* Overlay cusor not subject to native cursor restrictions */ 6341 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6342 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 6343 continue; 6344 6345 /* Check if rotation or scaling is enabled on DCN 4x and above */ 6346 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 6347 (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1))) { 6348 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 6349 6350 is_rotated = new_cursor_state && 6351 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 6352 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 6353 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 6354 6355 if (is_rotated || is_scaled) { 6356 drm_dbg_driver( 6357 crtc->dev, 6358 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 6359 crtc->base.id, crtc->name); 6360 ret = -EINVAL; 6361 goto fail; 6362 } 6363 } 6364 6365 /* If HW can only do native cursor, check restrictions again */ 6366 ret = amdgpu_dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6367 &required_cursor_mode); 6368 if (ret) { 6369 drm_dbg_driver(crtc->dev, 6370 "[CRTC:%d:%s] Checking cursor mode failed\n", 6371 crtc->base.id, crtc->name); 6372 goto fail; 6373 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6374 drm_dbg_driver(crtc->dev, 6375 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 6376 crtc->base.id, crtc->name); 6377 ret = -EINVAL; 6378 goto fail; 6379 } 6380 } 6381 6382 if (state->legacy_cursor_update) { 6383 /* 6384 * This is a fast cursor update coming from the plane update 6385 * helper, check if it can be done asynchronously for better 6386 * performance. 6387 */ 6388 state->async_update = 6389 !drm_atomic_helper_async_check(dev, state); 6390 6391 /* 6392 * Skip the remaining global validation if this is an async 6393 * update. Cursor updates can be done without affecting 6394 * state or bandwidth calcs and this avoids the performance 6395 * penalty of locking the private state object and 6396 * allocating a new dc_state. 6397 */ 6398 if (state->async_update) 6399 return 0; 6400 } 6401 6402 /* Check scaling and underscan changes*/ 6403 /* TODO Removed scaling changes validation due to inability to commit 6404 * new stream into context w\o causing full reset. Need to 6405 * decide how to handle. 6406 */ 6407 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6408 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6409 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6410 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 6411 6412 /* Skip any modesets/resets */ 6413 if (!acrtc || drm_atomic_crtc_needs_modeset( 6414 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 6415 continue; 6416 6417 /* Skip any thing not scale or underscan changes */ 6418 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 6419 continue; 6420 6421 lock_and_validation_needed = true; 6422 } 6423 6424 /* set the slot info for each mst_state based on the link encoding format */ 6425 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 6426 struct amdgpu_dm_connector *aconnector; 6427 struct drm_connector *connector; 6428 struct drm_connector_list_iter iter; 6429 u8 link_coding_cap; 6430 6431 drm_connector_list_iter_begin(dev, &iter); 6432 drm_for_each_connector_iter(connector, &iter) { 6433 if (connector->index == mst_state->mgr->conn_base_id) { 6434 aconnector = to_amdgpu_dm_connector(connector); 6435 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 6436 drm_dp_mst_update_slots(mst_state, link_coding_cap); 6437 6438 break; 6439 } 6440 } 6441 drm_connector_list_iter_end(&iter); 6442 } 6443 6444 /** 6445 * Streams and planes are reset when there are changes that affect 6446 * bandwidth. Anything that affects bandwidth needs to go through 6447 * DC global validation to ensure that the configuration can be applied 6448 * to hardware. 6449 * 6450 * We have to currently stall out here in atomic_check for outstanding 6451 * commits to finish in this case because our IRQ handlers reference 6452 * DRM state directly - we can end up disabling interrupts too early 6453 * if we don't. 6454 * 6455 * TODO: Remove this stall and drop DM state private objects. 6456 */ 6457 if (lock_and_validation_needed) { 6458 ret = dm_atomic_get_state(state, &dm_state); 6459 if (ret) { 6460 drm_dbg_atomic(dev, "dm_atomic_get_state() failed: %pe\n", ERR_PTR(ret)); 6461 goto fail; 6462 } 6463 6464 ret = do_aquire_global_lock(dev, state); 6465 if (ret) { 6466 drm_dbg_atomic(dev, "do_aquire_global_lock() failed: %pe\n", ERR_PTR(ret)); 6467 goto fail; 6468 } 6469 6470 #if defined(CONFIG_DRM_AMD_DC_FP) 6471 if (dc_resource_is_dsc_encoding_supported(dc)) { 6472 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 6473 if (ret) { 6474 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed: %pe\n", ERR_PTR(ret)); 6475 ret = -EINVAL; 6476 goto fail; 6477 } 6478 } 6479 #endif 6480 6481 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 6482 if (ret) { 6483 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed: %pe\n", ERR_PTR(ret)); 6484 goto fail; 6485 } 6486 6487 /* 6488 * Perform validation of MST topology in the state: 6489 * We need to perform MST atomic check before calling 6490 * dc_validate_global_state(), or there is a chance 6491 * to get stuck in an infinite loop and hang eventually. 6492 */ 6493 ret = drm_dp_mst_atomic_check(state); 6494 if (ret) { 6495 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed: %pe\n", ERR_PTR(ret)); 6496 goto fail; 6497 } 6498 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 6499 if (status != DC_OK) { 6500 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 6501 dc_status_to_str(status), status); 6502 ret = -EINVAL; 6503 goto fail; 6504 } 6505 } else { 6506 /* 6507 * The commit is a fast update. Fast updates shouldn't change 6508 * the DC context, affect global validation, and can have their 6509 * commit work done in parallel with other commits not touching 6510 * the same resource. If we have a new DC context as part of 6511 * the DM atomic state from validation we need to free it and 6512 * retain the existing one instead. 6513 * 6514 * Furthermore, since the DM atomic state only contains the DC 6515 * context and can safely be annulled, we can free the state 6516 * and clear the associated private object now to free 6517 * some memory and avoid a possible use-after-free later. 6518 */ 6519 6520 for (i = 0; i < state->num_private_objs; i++) { 6521 struct drm_private_obj *obj = state->private_objs[i].ptr; 6522 6523 if (obj->funcs == adev->dm.atomic_obj.funcs) { 6524 int j = state->num_private_objs-1; 6525 6526 dm_atomic_destroy_state(obj, 6527 state->private_objs[i].state_to_destroy); 6528 6529 /* If i is not at the end of the array then the 6530 * last element needs to be moved to where i was 6531 * before the array can safely be truncated. 6532 */ 6533 if (i != j) 6534 state->private_objs[i] = 6535 state->private_objs[j]; 6536 6537 state->private_objs[j].ptr = NULL; 6538 state->private_objs[j].state_to_destroy = NULL; 6539 state->private_objs[j].old_state = NULL; 6540 state->private_objs[j].new_state = NULL; 6541 6542 state->num_private_objs = j; 6543 break; 6544 } 6545 } 6546 } 6547 6548 /* Store the overall update type for use later in atomic check. */ 6549 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6550 struct dm_crtc_state *dm_new_crtc_state = 6551 to_dm_crtc_state(new_crtc_state); 6552 6553 /* 6554 * Only allow async flips for fast updates that don't change 6555 * the FB pitch, the DCC state, rotation, mem_type, etc. 6556 */ 6557 if (new_crtc_state->async_flip && 6558 (lock_and_validation_needed || 6559 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 6560 drm_dbg_atomic(crtc->dev, 6561 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 6562 crtc->base.id, crtc->name); 6563 ret = -EINVAL; 6564 goto fail; 6565 } 6566 6567 dm_new_crtc_state->update_type = lock_and_validation_needed ? 6568 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 6569 } 6570 6571 /* Must be success */ 6572 WARN_ON(ret); 6573 6574 trace_amdgpu_dm_atomic_check_finish(state, ret); 6575 6576 return ret; 6577 6578 fail: 6579 if (ret == -EDEADLK) 6580 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 6581 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 6582 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 6583 else 6584 drm_dbg_atomic(dev, "Atomic check failed: %pe\n", ERR_PTR(ret)); 6585 6586 trace_amdgpu_dm_atomic_check_finish(state, ret); 6587 6588 return ret; 6589 } 6590 6591 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 6592 { 6593 struct amdgpu_device *adev = drm_to_adev(dev); 6594 struct dc *dc = adev->dm.dc; 6595 int i; 6596 6597 mutex_lock(&adev->dm.dc_lock); 6598 if (dc->current_state) { 6599 for (i = 0; i < dc->current_state->stream_count; ++i) 6600 dc->current_state->streams[i] 6601 ->triggered_crtc_reset.enabled = 6602 adev->dm.force_timing_sync; 6603 6604 dm_enable_per_frame_crtc_master_sync(dc->current_state); 6605 dc_trigger_sync(dc, dc->current_state); 6606 } 6607 mutex_unlock(&adev->dm.dc_lock); 6608 } 6609 6610 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 6611 u32 value, const char *func_name) 6612 { 6613 #ifdef DM_CHECK_ADDR_0 6614 if (address == 0) { 6615 drm_err(adev_to_drm(ctx->driver_context), 6616 "invalid register write. address = 0"); 6617 return; 6618 } 6619 #endif 6620 6621 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 6622 cgs_write_register(ctx->cgs_device, address, value); 6623 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 6624 } 6625 6626 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 6627 const char *func_name) 6628 { 6629 u32 value; 6630 #ifdef DM_CHECK_ADDR_0 6631 if (address == 0) { 6632 drm_err(adev_to_drm(ctx->driver_context), 6633 "invalid register read; address = 0\n"); 6634 return 0; 6635 } 6636 #endif 6637 6638 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 6639 6640 value = cgs_read_register(ctx->cgs_device, address); 6641 6642 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 6643 6644 return value; 6645 } 6646 6647 void dm_acpi_process_phy_transition_interlock( 6648 const struct dc_context *ctx, 6649 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 6650 { 6651 // Not yet implemented 6652 } 6653