1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "dc/dc_state.h" 41 #include "amdgpu_dm_trace.h" 42 #include "dpcd_defs.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "vid.h" 49 #include "amdgpu.h" 50 #include "amdgpu_display.h" 51 #include "amdgpu_ucode.h" 52 #include "atom.h" 53 #include "amdgpu_dm.h" 54 #include "amdgpu_dm_plane.h" 55 #include "amdgpu_dm_crtc.h" 56 #include "amdgpu_dm_hdcp.h" 57 #include <drm/display/drm_hdcp_helper.h> 58 #include "amdgpu_dm_wb.h" 59 #include "amdgpu_pm.h" 60 #include "amdgpu_atombios.h" 61 62 #include "amd_shared.h" 63 #include "amdgpu_dm_irq.h" 64 #include "dm_helpers.h" 65 #include "amdgpu_dm_mst_types.h" 66 #if defined(CONFIG_DEBUG_FS) 67 #include "amdgpu_dm_debugfs.h" 68 #endif 69 #include "amdgpu_dm_psr.h" 70 #include "amdgpu_dm_replay.h" 71 72 #include "ivsrcid/ivsrcid_vislands30.h" 73 74 #include <linux/backlight.h> 75 #include <linux/module.h> 76 #include <linux/moduleparam.h> 77 #include <linux/types.h> 78 #include <linux/pm_runtime.h> 79 #include <linux/pci.h> 80 #include <linux/firmware.h> 81 #include <linux/component.h> 82 #include <linux/dmi.h> 83 84 #include <drm/display/drm_dp_mst_helper.h> 85 #include <drm/display/drm_hdmi_helper.h> 86 #include <drm/drm_atomic.h> 87 #include <drm/drm_atomic_uapi.h> 88 #include <drm/drm_atomic_helper.h> 89 #include <drm/drm_blend.h> 90 #include <drm/drm_fixed.h> 91 #include <drm/drm_fourcc.h> 92 #include <drm/drm_edid.h> 93 #include <drm/drm_eld.h> 94 #include <drm/drm_vblank.h> 95 #include <drm/drm_audio_component.h> 96 #include <drm/drm_gem_atomic_helper.h> 97 98 #include <acpi/video.h> 99 100 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 101 102 #include "dcn/dcn_1_0_offset.h" 103 #include "dcn/dcn_1_0_sh_mask.h" 104 #include "soc15_hw_ip.h" 105 #include "soc15_common.h" 106 #include "vega10_ip_offset.h" 107 108 #include "gc/gc_11_0_0_offset.h" 109 #include "gc/gc_11_0_0_sh_mask.h" 110 111 #include "modules/inc/mod_freesync.h" 112 #include "modules/power/power_helpers.h" 113 114 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 115 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 116 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 118 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 120 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 122 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 124 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 126 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 128 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 130 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 132 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 133 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 134 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 135 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 136 137 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 138 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 139 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 140 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 141 142 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 143 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 144 145 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 146 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 147 148 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" 149 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); 150 151 #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" 152 MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); 153 154 /* Number of bytes in PSP header for firmware. */ 155 #define PSP_HEADER_BYTES 0x100 156 157 /* Number of bytes in PSP footer for firmware. */ 158 #define PSP_FOOTER_BYTES 0x100 159 160 /** 161 * DOC: overview 162 * 163 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 164 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 165 * requests into DC requests, and DC responses into DRM responses. 166 * 167 * The root control structure is &struct amdgpu_display_manager. 168 */ 169 170 /* basic init/fini API */ 171 static int amdgpu_dm_init(struct amdgpu_device *adev); 172 static void amdgpu_dm_fini(struct amdgpu_device *adev); 173 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 174 175 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 176 { 177 switch (link->dpcd_caps.dongle_type) { 178 case DISPLAY_DONGLE_NONE: 179 return DRM_MODE_SUBCONNECTOR_Native; 180 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 181 return DRM_MODE_SUBCONNECTOR_VGA; 182 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 183 case DISPLAY_DONGLE_DP_DVI_DONGLE: 184 return DRM_MODE_SUBCONNECTOR_DVID; 185 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 186 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 187 return DRM_MODE_SUBCONNECTOR_HDMIA; 188 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 189 default: 190 return DRM_MODE_SUBCONNECTOR_Unknown; 191 } 192 } 193 194 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 195 { 196 struct dc_link *link = aconnector->dc_link; 197 struct drm_connector *connector = &aconnector->base; 198 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 199 200 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 201 return; 202 203 if (aconnector->dc_sink) 204 subconnector = get_subconnector_type(link); 205 206 drm_object_property_set_value(&connector->base, 207 connector->dev->mode_config.dp_subconnector_property, 208 subconnector); 209 } 210 211 /* 212 * initializes drm_device display related structures, based on the information 213 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 214 * drm_encoder, drm_mode_config 215 * 216 * Returns 0 on success 217 */ 218 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 219 /* removes and deallocates the drm structures, created by the above function */ 220 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 221 222 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 223 struct amdgpu_dm_connector *amdgpu_dm_connector, 224 u32 link_index, 225 struct amdgpu_encoder *amdgpu_encoder); 226 static int amdgpu_dm_encoder_init(struct drm_device *dev, 227 struct amdgpu_encoder *aencoder, 228 uint32_t link_index); 229 230 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 231 232 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 233 234 static int amdgpu_dm_atomic_check(struct drm_device *dev, 235 struct drm_atomic_state *state); 236 237 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 238 static void handle_hpd_rx_irq(void *param); 239 240 static bool 241 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 242 struct drm_crtc_state *new_crtc_state); 243 /* 244 * dm_vblank_get_counter 245 * 246 * @brief 247 * Get counter for number of vertical blanks 248 * 249 * @param 250 * struct amdgpu_device *adev - [in] desired amdgpu device 251 * int disp_idx - [in] which CRTC to get the counter from 252 * 253 * @return 254 * Counter for vertical blanks 255 */ 256 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 257 { 258 struct amdgpu_crtc *acrtc = NULL; 259 260 if (crtc >= adev->mode_info.num_crtc) 261 return 0; 262 263 acrtc = adev->mode_info.crtcs[crtc]; 264 265 if (!acrtc->dm_irq_params.stream) { 266 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 267 crtc); 268 return 0; 269 } 270 271 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 272 } 273 274 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 275 u32 *vbl, u32 *position) 276 { 277 u32 v_blank_start, v_blank_end, h_position, v_position; 278 struct amdgpu_crtc *acrtc = NULL; 279 struct dc *dc = adev->dm.dc; 280 281 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 282 return -EINVAL; 283 284 acrtc = adev->mode_info.crtcs[crtc]; 285 286 if (!acrtc->dm_irq_params.stream) { 287 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 288 crtc); 289 return 0; 290 } 291 292 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 293 dc_allow_idle_optimizations(dc, false); 294 295 /* 296 * TODO rework base driver to use values directly. 297 * for now parse it back into reg-format 298 */ 299 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 300 &v_blank_start, 301 &v_blank_end, 302 &h_position, 303 &v_position); 304 305 *position = v_position | (h_position << 16); 306 *vbl = v_blank_start | (v_blank_end << 16); 307 308 return 0; 309 } 310 311 static bool dm_is_idle(void *handle) 312 { 313 /* XXX todo */ 314 return true; 315 } 316 317 static int dm_wait_for_idle(void *handle) 318 { 319 /* XXX todo */ 320 return 0; 321 } 322 323 static bool dm_check_soft_reset(void *handle) 324 { 325 return false; 326 } 327 328 static int dm_soft_reset(void *handle) 329 { 330 /* XXX todo */ 331 return 0; 332 } 333 334 static struct amdgpu_crtc * 335 get_crtc_by_otg_inst(struct amdgpu_device *adev, 336 int otg_inst) 337 { 338 struct drm_device *dev = adev_to_drm(adev); 339 struct drm_crtc *crtc; 340 struct amdgpu_crtc *amdgpu_crtc; 341 342 if (WARN_ON(otg_inst == -1)) 343 return adev->mode_info.crtcs[0]; 344 345 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 346 amdgpu_crtc = to_amdgpu_crtc(crtc); 347 348 if (amdgpu_crtc->otg_inst == otg_inst) 349 return amdgpu_crtc; 350 } 351 352 return NULL; 353 } 354 355 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 356 struct dm_crtc_state *new_state) 357 { 358 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 359 return true; 360 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 361 return true; 362 else 363 return false; 364 } 365 366 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, 367 int planes_count) 368 { 369 int i, j; 370 371 for (i = 0, j = planes_count - 1; i < j; i++, j--) 372 swap(array_of_surface_update[i], array_of_surface_update[j]); 373 } 374 375 /** 376 * update_planes_and_stream_adapter() - Send planes to be updated in DC 377 * 378 * DC has a generic way to update planes and stream via 379 * dc_update_planes_and_stream function; however, DM might need some 380 * adjustments and preparation before calling it. This function is a wrapper 381 * for the dc_update_planes_and_stream that does any required configuration 382 * before passing control to DC. 383 * 384 * @dc: Display Core control structure 385 * @update_type: specify whether it is FULL/MEDIUM/FAST update 386 * @planes_count: planes count to update 387 * @stream: stream state 388 * @stream_update: stream update 389 * @array_of_surface_update: dc surface update pointer 390 * 391 */ 392 static inline bool update_planes_and_stream_adapter(struct dc *dc, 393 int update_type, 394 int planes_count, 395 struct dc_stream_state *stream, 396 struct dc_stream_update *stream_update, 397 struct dc_surface_update *array_of_surface_update) 398 { 399 reverse_planes_order(array_of_surface_update, planes_count); 400 401 /* 402 * Previous frame finished and HW is ready for optimization. 403 */ 404 if (update_type == UPDATE_TYPE_FAST) 405 dc_post_update_surfaces_to_stream(dc); 406 407 return dc_update_planes_and_stream(dc, 408 array_of_surface_update, 409 planes_count, 410 stream, 411 stream_update); 412 } 413 414 /** 415 * dm_pflip_high_irq() - Handle pageflip interrupt 416 * @interrupt_params: ignored 417 * 418 * Handles the pageflip interrupt by notifying all interested parties 419 * that the pageflip has been completed. 420 */ 421 static void dm_pflip_high_irq(void *interrupt_params) 422 { 423 struct amdgpu_crtc *amdgpu_crtc; 424 struct common_irq_params *irq_params = interrupt_params; 425 struct amdgpu_device *adev = irq_params->adev; 426 struct drm_device *dev = adev_to_drm(adev); 427 unsigned long flags; 428 struct drm_pending_vblank_event *e; 429 u32 vpos, hpos, v_blank_start, v_blank_end; 430 bool vrr_active; 431 432 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 433 434 /* IRQ could occur when in initial stage */ 435 /* TODO work and BO cleanup */ 436 if (amdgpu_crtc == NULL) { 437 drm_dbg_state(dev, "CRTC is null, returning.\n"); 438 return; 439 } 440 441 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 442 443 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 444 drm_dbg_state(dev, 445 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 446 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, 447 amdgpu_crtc->crtc_id, amdgpu_crtc); 448 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 449 return; 450 } 451 452 /* page flip completed. */ 453 e = amdgpu_crtc->event; 454 amdgpu_crtc->event = NULL; 455 456 WARN_ON(!e); 457 458 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 459 460 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 461 if (!vrr_active || 462 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 463 &v_blank_end, &hpos, &vpos) || 464 (vpos < v_blank_start)) { 465 /* Update to correct count and vblank timestamp if racing with 466 * vblank irq. This also updates to the correct vblank timestamp 467 * even in VRR mode, as scanout is past the front-porch atm. 468 */ 469 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 470 471 /* Wake up userspace by sending the pageflip event with proper 472 * count and timestamp of vblank of flip completion. 473 */ 474 if (e) { 475 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 476 477 /* Event sent, so done with vblank for this flip */ 478 drm_crtc_vblank_put(&amdgpu_crtc->base); 479 } 480 } else if (e) { 481 /* VRR active and inside front-porch: vblank count and 482 * timestamp for pageflip event will only be up to date after 483 * drm_crtc_handle_vblank() has been executed from late vblank 484 * irq handler after start of back-porch (vline 0). We queue the 485 * pageflip event for send-out by drm_crtc_handle_vblank() with 486 * updated timestamp and count, once it runs after us. 487 * 488 * We need to open-code this instead of using the helper 489 * drm_crtc_arm_vblank_event(), as that helper would 490 * call drm_crtc_accurate_vblank_count(), which we must 491 * not call in VRR mode while we are in front-porch! 492 */ 493 494 /* sequence will be replaced by real count during send-out. */ 495 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 496 e->pipe = amdgpu_crtc->crtc_id; 497 498 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 499 e = NULL; 500 } 501 502 /* Keep track of vblank of this flip for flip throttling. We use the 503 * cooked hw counter, as that one incremented at start of this vblank 504 * of pageflip completion, so last_flip_vblank is the forbidden count 505 * for queueing new pageflips if vsync + VRR is enabled. 506 */ 507 amdgpu_crtc->dm_irq_params.last_flip_vblank = 508 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 509 510 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 511 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 512 513 drm_dbg_state(dev, 514 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 515 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); 516 } 517 518 static void dm_vupdate_high_irq(void *interrupt_params) 519 { 520 struct common_irq_params *irq_params = interrupt_params; 521 struct amdgpu_device *adev = irq_params->adev; 522 struct amdgpu_crtc *acrtc; 523 struct drm_device *drm_dev; 524 struct drm_vblank_crtc *vblank; 525 ktime_t frame_duration_ns, previous_timestamp; 526 unsigned long flags; 527 int vrr_active; 528 529 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 530 531 if (acrtc) { 532 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 533 drm_dev = acrtc->base.dev; 534 vblank = &drm_dev->vblank[acrtc->base.index]; 535 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 536 frame_duration_ns = vblank->time - previous_timestamp; 537 538 if (frame_duration_ns > 0) { 539 trace_amdgpu_refresh_rate_track(acrtc->base.index, 540 frame_duration_ns, 541 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 542 atomic64_set(&irq_params->previous_timestamp, vblank->time); 543 } 544 545 drm_dbg_vbl(drm_dev, 546 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 547 vrr_active); 548 549 /* Core vblank handling is done here after end of front-porch in 550 * vrr mode, as vblank timestamping will give valid results 551 * while now done after front-porch. This will also deliver 552 * page-flip completion events that have been queued to us 553 * if a pageflip happened inside front-porch. 554 */ 555 if (vrr_active) { 556 amdgpu_dm_crtc_handle_vblank(acrtc); 557 558 /* BTR processing for pre-DCE12 ASICs */ 559 if (acrtc->dm_irq_params.stream && 560 adev->family < AMDGPU_FAMILY_AI) { 561 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 562 mod_freesync_handle_v_update( 563 adev->dm.freesync_module, 564 acrtc->dm_irq_params.stream, 565 &acrtc->dm_irq_params.vrr_params); 566 567 dc_stream_adjust_vmin_vmax( 568 adev->dm.dc, 569 acrtc->dm_irq_params.stream, 570 &acrtc->dm_irq_params.vrr_params.adjust); 571 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 572 } 573 } 574 } 575 } 576 577 /** 578 * dm_crtc_high_irq() - Handles CRTC interrupt 579 * @interrupt_params: used for determining the CRTC instance 580 * 581 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 582 * event handler. 583 */ 584 static void dm_crtc_high_irq(void *interrupt_params) 585 { 586 struct common_irq_params *irq_params = interrupt_params; 587 struct amdgpu_device *adev = irq_params->adev; 588 struct drm_writeback_job *job; 589 struct amdgpu_crtc *acrtc; 590 unsigned long flags; 591 int vrr_active; 592 593 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 594 if (!acrtc) 595 return; 596 597 if (acrtc->wb_pending) { 598 if (acrtc->wb_conn) { 599 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 600 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, 601 struct drm_writeback_job, 602 list_entry); 603 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 604 605 if (job) { 606 unsigned int v_total, refresh_hz; 607 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; 608 609 v_total = stream->adjust.v_total_max ? 610 stream->adjust.v_total_max : stream->timing.v_total; 611 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * 612 100LL, (v_total * stream->timing.h_total)); 613 mdelay(1000 / refresh_hz); 614 615 drm_writeback_signal_completion(acrtc->wb_conn, 0); 616 dc_stream_fc_disable_writeback(adev->dm.dc, 617 acrtc->dm_irq_params.stream, 0); 618 } 619 } else 620 DRM_ERROR("%s: no amdgpu_crtc wb_conn\n", __func__); 621 acrtc->wb_pending = false; 622 } 623 624 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 625 626 drm_dbg_vbl(adev_to_drm(adev), 627 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 628 vrr_active, acrtc->dm_irq_params.active_planes); 629 630 /** 631 * Core vblank handling at start of front-porch is only possible 632 * in non-vrr mode, as only there vblank timestamping will give 633 * valid results while done in front-porch. Otherwise defer it 634 * to dm_vupdate_high_irq after end of front-porch. 635 */ 636 if (!vrr_active) 637 amdgpu_dm_crtc_handle_vblank(acrtc); 638 639 /** 640 * Following stuff must happen at start of vblank, for crc 641 * computation and below-the-range btr support in vrr mode. 642 */ 643 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 644 645 /* BTR updates need to happen before VUPDATE on Vega and above. */ 646 if (adev->family < AMDGPU_FAMILY_AI) 647 return; 648 649 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 650 651 if (acrtc->dm_irq_params.stream && 652 acrtc->dm_irq_params.vrr_params.supported && 653 acrtc->dm_irq_params.freesync_config.state == 654 VRR_STATE_ACTIVE_VARIABLE) { 655 mod_freesync_handle_v_update(adev->dm.freesync_module, 656 acrtc->dm_irq_params.stream, 657 &acrtc->dm_irq_params.vrr_params); 658 659 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 660 &acrtc->dm_irq_params.vrr_params.adjust); 661 } 662 663 /* 664 * If there aren't any active_planes then DCH HUBP may be clock-gated. 665 * In that case, pageflip completion interrupts won't fire and pageflip 666 * completion events won't get delivered. Prevent this by sending 667 * pending pageflip events from here if a flip is still pending. 668 * 669 * If any planes are enabled, use dm_pflip_high_irq() instead, to 670 * avoid race conditions between flip programming and completion, 671 * which could cause too early flip completion events. 672 */ 673 if (adev->family >= AMDGPU_FAMILY_RV && 674 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 675 acrtc->dm_irq_params.active_planes == 0) { 676 if (acrtc->event) { 677 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 678 acrtc->event = NULL; 679 drm_crtc_vblank_put(&acrtc->base); 680 } 681 acrtc->pflip_status = AMDGPU_FLIP_NONE; 682 } 683 684 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 685 } 686 687 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 688 /** 689 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 690 * DCN generation ASICs 691 * @interrupt_params: interrupt parameters 692 * 693 * Used to set crc window/read out crc value at vertical line 0 position 694 */ 695 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 696 { 697 struct common_irq_params *irq_params = interrupt_params; 698 struct amdgpu_device *adev = irq_params->adev; 699 struct amdgpu_crtc *acrtc; 700 701 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 702 703 if (!acrtc) 704 return; 705 706 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 707 } 708 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 709 710 /** 711 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 712 * @adev: amdgpu_device pointer 713 * @notify: dmub notification structure 714 * 715 * Dmub AUX or SET_CONFIG command completion processing callback 716 * Copies dmub notification to DM which is to be read by AUX command. 717 * issuing thread and also signals the event to wake up the thread. 718 */ 719 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 720 struct dmub_notification *notify) 721 { 722 if (adev->dm.dmub_notify) 723 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 724 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 725 complete(&adev->dm.dmub_aux_transfer_done); 726 } 727 728 /** 729 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 730 * @adev: amdgpu_device pointer 731 * @notify: dmub notification structure 732 * 733 * Dmub Hpd interrupt processing callback. Gets displayindex through the 734 * ink index and calls helper to do the processing. 735 */ 736 static void dmub_hpd_callback(struct amdgpu_device *adev, 737 struct dmub_notification *notify) 738 { 739 struct amdgpu_dm_connector *aconnector; 740 struct amdgpu_dm_connector *hpd_aconnector = NULL; 741 struct drm_connector *connector; 742 struct drm_connector_list_iter iter; 743 struct dc_link *link; 744 u8 link_index = 0; 745 struct drm_device *dev; 746 747 if (adev == NULL) 748 return; 749 750 if (notify == NULL) { 751 DRM_ERROR("DMUB HPD callback notification was NULL"); 752 return; 753 } 754 755 if (notify->link_index > adev->dm.dc->link_count) { 756 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 757 return; 758 } 759 760 link_index = notify->link_index; 761 link = adev->dm.dc->links[link_index]; 762 dev = adev->dm.ddev; 763 764 drm_connector_list_iter_begin(dev, &iter); 765 drm_for_each_connector_iter(connector, &iter) { 766 767 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 768 continue; 769 770 aconnector = to_amdgpu_dm_connector(connector); 771 if (link && aconnector->dc_link == link) { 772 if (notify->type == DMUB_NOTIFICATION_HPD) 773 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index); 774 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 775 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 776 else 777 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 778 notify->type, link_index); 779 780 hpd_aconnector = aconnector; 781 break; 782 } 783 } 784 drm_connector_list_iter_end(&iter); 785 786 if (hpd_aconnector) { 787 if (notify->type == DMUB_NOTIFICATION_HPD) 788 handle_hpd_irq_helper(hpd_aconnector); 789 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 790 handle_hpd_rx_irq(hpd_aconnector); 791 } 792 } 793 794 /** 795 * register_dmub_notify_callback - Sets callback for DMUB notify 796 * @adev: amdgpu_device pointer 797 * @type: Type of dmub notification 798 * @callback: Dmub interrupt callback function 799 * @dmub_int_thread_offload: offload indicator 800 * 801 * API to register a dmub callback handler for a dmub notification 802 * Also sets indicator whether callback processing to be offloaded. 803 * to dmub interrupt handling thread 804 * Return: true if successfully registered, false if there is existing registration 805 */ 806 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 807 enum dmub_notification_type type, 808 dmub_notify_interrupt_callback_t callback, 809 bool dmub_int_thread_offload) 810 { 811 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 812 adev->dm.dmub_callback[type] = callback; 813 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 814 } else 815 return false; 816 817 return true; 818 } 819 820 static void dm_handle_hpd_work(struct work_struct *work) 821 { 822 struct dmub_hpd_work *dmub_hpd_wrk; 823 824 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 825 826 if (!dmub_hpd_wrk->dmub_notify) { 827 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 828 return; 829 } 830 831 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 832 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 833 dmub_hpd_wrk->dmub_notify); 834 } 835 836 kfree(dmub_hpd_wrk->dmub_notify); 837 kfree(dmub_hpd_wrk); 838 839 } 840 841 #define DMUB_TRACE_MAX_READ 64 842 /** 843 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 844 * @interrupt_params: used for determining the Outbox instance 845 * 846 * Handles the Outbox Interrupt 847 * event handler. 848 */ 849 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 850 { 851 struct dmub_notification notify; 852 struct common_irq_params *irq_params = interrupt_params; 853 struct amdgpu_device *adev = irq_params->adev; 854 struct amdgpu_display_manager *dm = &adev->dm; 855 struct dmcub_trace_buf_entry entry = { 0 }; 856 u32 count = 0; 857 struct dmub_hpd_work *dmub_hpd_wrk; 858 struct dc_link *plink = NULL; 859 860 if (dc_enable_dmub_notifications(adev->dm.dc) && 861 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 862 863 do { 864 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 865 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 866 DRM_ERROR("DM: notify type %d invalid!", notify.type); 867 continue; 868 } 869 if (!dm->dmub_callback[notify.type]) { 870 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type); 871 continue; 872 } 873 if (dm->dmub_thread_offload[notify.type] == true) { 874 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 875 if (!dmub_hpd_wrk) { 876 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 877 return; 878 } 879 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 880 GFP_ATOMIC); 881 if (!dmub_hpd_wrk->dmub_notify) { 882 kfree(dmub_hpd_wrk); 883 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 884 return; 885 } 886 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 887 dmub_hpd_wrk->adev = adev; 888 if (notify.type == DMUB_NOTIFICATION_HPD) { 889 plink = adev->dm.dc->links[notify.link_index]; 890 if (plink) { 891 plink->hpd_status = 892 notify.hpd_status == DP_HPD_PLUG; 893 } 894 } 895 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 896 } else { 897 dm->dmub_callback[notify.type](adev, ¬ify); 898 } 899 } while (notify.pending_notification); 900 } 901 902 903 do { 904 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 905 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 906 entry.param0, entry.param1); 907 908 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 909 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 910 } else 911 break; 912 913 count++; 914 915 } while (count <= DMUB_TRACE_MAX_READ); 916 917 if (count > DMUB_TRACE_MAX_READ) 918 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 919 } 920 921 static int dm_set_clockgating_state(void *handle, 922 enum amd_clockgating_state state) 923 { 924 return 0; 925 } 926 927 static int dm_set_powergating_state(void *handle, 928 enum amd_powergating_state state) 929 { 930 return 0; 931 } 932 933 /* Prototypes of private functions */ 934 static int dm_early_init(void *handle); 935 936 /* Allocate memory for FBC compressed data */ 937 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 938 { 939 struct amdgpu_device *adev = drm_to_adev(connector->dev); 940 struct dm_compressor_info *compressor = &adev->dm.compressor; 941 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 942 struct drm_display_mode *mode; 943 unsigned long max_size = 0; 944 945 if (adev->dm.dc->fbc_compressor == NULL) 946 return; 947 948 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 949 return; 950 951 if (compressor->bo_ptr) 952 return; 953 954 955 list_for_each_entry(mode, &connector->modes, head) { 956 if (max_size < mode->htotal * mode->vtotal) 957 max_size = mode->htotal * mode->vtotal; 958 } 959 960 if (max_size) { 961 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 962 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 963 &compressor->gpu_addr, &compressor->cpu_addr); 964 965 if (r) 966 DRM_ERROR("DM: Failed to initialize FBC\n"); 967 else { 968 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 969 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 970 } 971 972 } 973 974 } 975 976 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 977 int pipe, bool *enabled, 978 unsigned char *buf, int max_bytes) 979 { 980 struct drm_device *dev = dev_get_drvdata(kdev); 981 struct amdgpu_device *adev = drm_to_adev(dev); 982 struct drm_connector *connector; 983 struct drm_connector_list_iter conn_iter; 984 struct amdgpu_dm_connector *aconnector; 985 int ret = 0; 986 987 *enabled = false; 988 989 mutex_lock(&adev->dm.audio_lock); 990 991 drm_connector_list_iter_begin(dev, &conn_iter); 992 drm_for_each_connector_iter(connector, &conn_iter) { 993 994 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 995 continue; 996 997 aconnector = to_amdgpu_dm_connector(connector); 998 if (aconnector->audio_inst != port) 999 continue; 1000 1001 *enabled = true; 1002 ret = drm_eld_size(connector->eld); 1003 memcpy(buf, connector->eld, min(max_bytes, ret)); 1004 1005 break; 1006 } 1007 drm_connector_list_iter_end(&conn_iter); 1008 1009 mutex_unlock(&adev->dm.audio_lock); 1010 1011 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1012 1013 return ret; 1014 } 1015 1016 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 1017 .get_eld = amdgpu_dm_audio_component_get_eld, 1018 }; 1019 1020 static int amdgpu_dm_audio_component_bind(struct device *kdev, 1021 struct device *hda_kdev, void *data) 1022 { 1023 struct drm_device *dev = dev_get_drvdata(kdev); 1024 struct amdgpu_device *adev = drm_to_adev(dev); 1025 struct drm_audio_component *acomp = data; 1026 1027 acomp->ops = &amdgpu_dm_audio_component_ops; 1028 acomp->dev = kdev; 1029 adev->dm.audio_component = acomp; 1030 1031 return 0; 1032 } 1033 1034 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 1035 struct device *hda_kdev, void *data) 1036 { 1037 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); 1038 struct drm_audio_component *acomp = data; 1039 1040 acomp->ops = NULL; 1041 acomp->dev = NULL; 1042 adev->dm.audio_component = NULL; 1043 } 1044 1045 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 1046 .bind = amdgpu_dm_audio_component_bind, 1047 .unbind = amdgpu_dm_audio_component_unbind, 1048 }; 1049 1050 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1051 { 1052 int i, ret; 1053 1054 if (!amdgpu_audio) 1055 return 0; 1056 1057 adev->mode_info.audio.enabled = true; 1058 1059 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1060 1061 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1062 adev->mode_info.audio.pin[i].channels = -1; 1063 adev->mode_info.audio.pin[i].rate = -1; 1064 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1065 adev->mode_info.audio.pin[i].status_bits = 0; 1066 adev->mode_info.audio.pin[i].category_code = 0; 1067 adev->mode_info.audio.pin[i].connected = false; 1068 adev->mode_info.audio.pin[i].id = 1069 adev->dm.dc->res_pool->audios[i]->inst; 1070 adev->mode_info.audio.pin[i].offset = 0; 1071 } 1072 1073 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1074 if (ret < 0) 1075 return ret; 1076 1077 adev->dm.audio_registered = true; 1078 1079 return 0; 1080 } 1081 1082 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1083 { 1084 if (!amdgpu_audio) 1085 return; 1086 1087 if (!adev->mode_info.audio.enabled) 1088 return; 1089 1090 if (adev->dm.audio_registered) { 1091 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1092 adev->dm.audio_registered = false; 1093 } 1094 1095 /* TODO: Disable audio? */ 1096 1097 adev->mode_info.audio.enabled = false; 1098 } 1099 1100 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1101 { 1102 struct drm_audio_component *acomp = adev->dm.audio_component; 1103 1104 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1105 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1106 1107 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1108 pin, -1); 1109 } 1110 } 1111 1112 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1113 { 1114 const struct dmcub_firmware_header_v1_0 *hdr; 1115 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1116 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1117 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1118 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1119 struct abm *abm = adev->dm.dc->res_pool->abm; 1120 struct dc_context *ctx = adev->dm.dc->ctx; 1121 struct dmub_srv_hw_params hw_params; 1122 enum dmub_status status; 1123 const unsigned char *fw_inst_const, *fw_bss_data; 1124 u32 i, fw_inst_const_size, fw_bss_data_size; 1125 bool has_hw_support; 1126 1127 if (!dmub_srv) 1128 /* DMUB isn't supported on the ASIC. */ 1129 return 0; 1130 1131 if (!fb_info) { 1132 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1133 return -EINVAL; 1134 } 1135 1136 if (!dmub_fw) { 1137 /* Firmware required for DMUB support. */ 1138 DRM_ERROR("No firmware provided for DMUB.\n"); 1139 return -EINVAL; 1140 } 1141 1142 /* initialize register offsets for ASICs with runtime initialization available */ 1143 if (dmub_srv->hw_funcs.init_reg_offsets) 1144 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); 1145 1146 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1147 if (status != DMUB_STATUS_OK) { 1148 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1149 return -EINVAL; 1150 } 1151 1152 if (!has_hw_support) { 1153 DRM_INFO("DMUB unsupported on ASIC\n"); 1154 return 0; 1155 } 1156 1157 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1158 status = dmub_srv_hw_reset(dmub_srv); 1159 if (status != DMUB_STATUS_OK) 1160 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1161 1162 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1163 1164 fw_inst_const = dmub_fw->data + 1165 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1166 PSP_HEADER_BYTES; 1167 1168 fw_bss_data = dmub_fw->data + 1169 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1170 le32_to_cpu(hdr->inst_const_bytes); 1171 1172 /* Copy firmware and bios info into FB memory. */ 1173 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1174 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1175 1176 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1177 1178 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1179 * amdgpu_ucode_init_single_fw will load dmub firmware 1180 * fw_inst_const part to cw0; otherwise, the firmware back door load 1181 * will be done by dm_dmub_hw_init 1182 */ 1183 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1184 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1185 fw_inst_const_size); 1186 } 1187 1188 if (fw_bss_data_size) 1189 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1190 fw_bss_data, fw_bss_data_size); 1191 1192 /* Copy firmware bios info into FB memory. */ 1193 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1194 adev->bios_size); 1195 1196 /* Reset regions that need to be reset. */ 1197 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1198 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1199 1200 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1201 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1202 1203 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1204 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1205 1206 /* Initialize hardware. */ 1207 memset(&hw_params, 0, sizeof(hw_params)); 1208 hw_params.fb_base = adev->gmc.fb_start; 1209 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1210 1211 /* backdoor load firmware and trigger dmub running */ 1212 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1213 hw_params.load_inst_const = true; 1214 1215 if (dmcu) 1216 hw_params.psp_version = dmcu->psp_version; 1217 1218 for (i = 0; i < fb_info->num_fb; ++i) 1219 hw_params.fb[i] = &fb_info->fb[i]; 1220 1221 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1222 case IP_VERSION(3, 1, 3): 1223 case IP_VERSION(3, 1, 4): 1224 case IP_VERSION(3, 5, 0): 1225 case IP_VERSION(3, 5, 1): 1226 hw_params.dpia_supported = true; 1227 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1228 break; 1229 default: 1230 break; 1231 } 1232 1233 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1234 case IP_VERSION(3, 5, 0): 1235 case IP_VERSION(3, 5, 1): 1236 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; 1237 break; 1238 default: 1239 break; 1240 } 1241 1242 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1243 if (status != DMUB_STATUS_OK) { 1244 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1245 return -EINVAL; 1246 } 1247 1248 /* Wait for firmware load to finish. */ 1249 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1250 if (status != DMUB_STATUS_OK) 1251 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1252 1253 /* Init DMCU and ABM if available. */ 1254 if (dmcu && abm) { 1255 dmcu->funcs->dmcu_init(dmcu); 1256 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1257 } 1258 1259 if (!adev->dm.dc->ctx->dmub_srv) 1260 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1261 if (!adev->dm.dc->ctx->dmub_srv) { 1262 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1263 return -ENOMEM; 1264 } 1265 1266 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1267 adev->dm.dmcub_fw_version); 1268 1269 return 0; 1270 } 1271 1272 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1273 { 1274 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1275 enum dmub_status status; 1276 bool init; 1277 1278 if (!dmub_srv) { 1279 /* DMUB isn't supported on the ASIC. */ 1280 return; 1281 } 1282 1283 status = dmub_srv_is_hw_init(dmub_srv, &init); 1284 if (status != DMUB_STATUS_OK) 1285 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1286 1287 if (status == DMUB_STATUS_OK && init) { 1288 /* Wait for firmware load to finish. */ 1289 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1290 if (status != DMUB_STATUS_OK) 1291 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1292 } else { 1293 /* Perform the full hardware initialization. */ 1294 dm_dmub_hw_init(adev); 1295 } 1296 } 1297 1298 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1299 { 1300 u64 pt_base; 1301 u32 logical_addr_low; 1302 u32 logical_addr_high; 1303 u32 agp_base, agp_bot, agp_top; 1304 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1305 1306 memset(pa_config, 0, sizeof(*pa_config)); 1307 1308 agp_base = 0; 1309 agp_bot = adev->gmc.agp_start >> 24; 1310 agp_top = adev->gmc.agp_end >> 24; 1311 1312 /* AGP aperture is disabled */ 1313 if (agp_bot > agp_top) { 1314 logical_addr_low = adev->gmc.fb_start >> 18; 1315 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1316 AMD_APU_IS_RENOIR | 1317 AMD_APU_IS_GREEN_SARDINE)) 1318 /* 1319 * Raven2 has a HW issue that it is unable to use the vram which 1320 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1321 * workaround that increase system aperture high address (add 1) 1322 * to get rid of the VM fault and hardware hang. 1323 */ 1324 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1325 else 1326 logical_addr_high = adev->gmc.fb_end >> 18; 1327 } else { 1328 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1329 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1330 AMD_APU_IS_RENOIR | 1331 AMD_APU_IS_GREEN_SARDINE)) 1332 /* 1333 * Raven2 has a HW issue that it is unable to use the vram which 1334 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1335 * workaround that increase system aperture high address (add 1) 1336 * to get rid of the VM fault and hardware hang. 1337 */ 1338 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1339 else 1340 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1341 } 1342 1343 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1344 1345 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1346 AMDGPU_GPU_PAGE_SHIFT); 1347 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1348 AMDGPU_GPU_PAGE_SHIFT); 1349 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1350 AMDGPU_GPU_PAGE_SHIFT); 1351 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1352 AMDGPU_GPU_PAGE_SHIFT); 1353 page_table_base.high_part = upper_32_bits(pt_base); 1354 page_table_base.low_part = lower_32_bits(pt_base); 1355 1356 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1357 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1358 1359 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1360 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1361 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1362 1363 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1364 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1365 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1366 1367 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1368 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1369 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1370 1371 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1372 1373 } 1374 1375 static void force_connector_state( 1376 struct amdgpu_dm_connector *aconnector, 1377 enum drm_connector_force force_state) 1378 { 1379 struct drm_connector *connector = &aconnector->base; 1380 1381 mutex_lock(&connector->dev->mode_config.mutex); 1382 aconnector->base.force = force_state; 1383 mutex_unlock(&connector->dev->mode_config.mutex); 1384 1385 mutex_lock(&aconnector->hpd_lock); 1386 drm_kms_helper_connector_hotplug_event(connector); 1387 mutex_unlock(&aconnector->hpd_lock); 1388 } 1389 1390 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1391 { 1392 struct hpd_rx_irq_offload_work *offload_work; 1393 struct amdgpu_dm_connector *aconnector; 1394 struct dc_link *dc_link; 1395 struct amdgpu_device *adev; 1396 enum dc_connection_type new_connection_type = dc_connection_none; 1397 unsigned long flags; 1398 union test_response test_response; 1399 1400 memset(&test_response, 0, sizeof(test_response)); 1401 1402 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1403 aconnector = offload_work->offload_wq->aconnector; 1404 1405 if (!aconnector) { 1406 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1407 goto skip; 1408 } 1409 1410 adev = drm_to_adev(aconnector->base.dev); 1411 dc_link = aconnector->dc_link; 1412 1413 mutex_lock(&aconnector->hpd_lock); 1414 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1415 DRM_ERROR("KMS: Failed to detect connector\n"); 1416 mutex_unlock(&aconnector->hpd_lock); 1417 1418 if (new_connection_type == dc_connection_none) 1419 goto skip; 1420 1421 if (amdgpu_in_reset(adev)) 1422 goto skip; 1423 1424 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1425 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1426 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1427 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1428 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1429 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1430 goto skip; 1431 } 1432 1433 mutex_lock(&adev->dm.dc_lock); 1434 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1435 dc_link_dp_handle_automated_test(dc_link); 1436 1437 if (aconnector->timing_changed) { 1438 /* force connector disconnect and reconnect */ 1439 force_connector_state(aconnector, DRM_FORCE_OFF); 1440 msleep(100); 1441 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1442 } 1443 1444 test_response.bits.ACK = 1; 1445 1446 core_link_write_dpcd( 1447 dc_link, 1448 DP_TEST_RESPONSE, 1449 &test_response.raw, 1450 sizeof(test_response)); 1451 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1452 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1453 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1454 /* offload_work->data is from handle_hpd_rx_irq-> 1455 * schedule_hpd_rx_offload_work.this is defer handle 1456 * for hpd short pulse. upon here, link status may be 1457 * changed, need get latest link status from dpcd 1458 * registers. if link status is good, skip run link 1459 * training again. 1460 */ 1461 union hpd_irq_data irq_data; 1462 1463 memset(&irq_data, 0, sizeof(irq_data)); 1464 1465 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1466 * request be added to work queue if link lost at end of dc_link_ 1467 * dp_handle_link_loss 1468 */ 1469 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1470 offload_work->offload_wq->is_handling_link_loss = false; 1471 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1472 1473 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1474 dc_link_check_link_loss_status(dc_link, &irq_data)) 1475 dc_link_dp_handle_link_loss(dc_link); 1476 } 1477 mutex_unlock(&adev->dm.dc_lock); 1478 1479 skip: 1480 kfree(offload_work); 1481 1482 } 1483 1484 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1485 { 1486 int max_caps = dc->caps.max_links; 1487 int i = 0; 1488 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1489 1490 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1491 1492 if (!hpd_rx_offload_wq) 1493 return NULL; 1494 1495 1496 for (i = 0; i < max_caps; i++) { 1497 hpd_rx_offload_wq[i].wq = 1498 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1499 1500 if (hpd_rx_offload_wq[i].wq == NULL) { 1501 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1502 goto out_err; 1503 } 1504 1505 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1506 } 1507 1508 return hpd_rx_offload_wq; 1509 1510 out_err: 1511 for (i = 0; i < max_caps; i++) { 1512 if (hpd_rx_offload_wq[i].wq) 1513 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1514 } 1515 kfree(hpd_rx_offload_wq); 1516 return NULL; 1517 } 1518 1519 struct amdgpu_stutter_quirk { 1520 u16 chip_vendor; 1521 u16 chip_device; 1522 u16 subsys_vendor; 1523 u16 subsys_device; 1524 u8 revision; 1525 }; 1526 1527 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1528 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1529 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1530 { 0, 0, 0, 0, 0 }, 1531 }; 1532 1533 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1534 { 1535 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1536 1537 while (p && p->chip_device != 0) { 1538 if (pdev->vendor == p->chip_vendor && 1539 pdev->device == p->chip_device && 1540 pdev->subsystem_vendor == p->subsys_vendor && 1541 pdev->subsystem_device == p->subsys_device && 1542 pdev->revision == p->revision) { 1543 return true; 1544 } 1545 ++p; 1546 } 1547 return false; 1548 } 1549 1550 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1551 { 1552 .matches = { 1553 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1554 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1555 }, 1556 }, 1557 { 1558 .matches = { 1559 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1560 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1561 }, 1562 }, 1563 { 1564 .matches = { 1565 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1566 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1567 }, 1568 }, 1569 { 1570 .matches = { 1571 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1572 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1573 }, 1574 }, 1575 { 1576 .matches = { 1577 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1578 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1579 }, 1580 }, 1581 { 1582 .matches = { 1583 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1584 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1585 }, 1586 }, 1587 { 1588 .matches = { 1589 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1590 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1591 }, 1592 }, 1593 { 1594 .matches = { 1595 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1596 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1597 }, 1598 }, 1599 { 1600 .matches = { 1601 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1602 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1603 }, 1604 }, 1605 {} 1606 /* TODO: refactor this from a fixed table to a dynamic option */ 1607 }; 1608 1609 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1610 { 1611 const struct dmi_system_id *dmi_id; 1612 1613 dm->aux_hpd_discon_quirk = false; 1614 1615 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1616 if (dmi_id) { 1617 dm->aux_hpd_discon_quirk = true; 1618 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1619 } 1620 } 1621 1622 static int amdgpu_dm_init(struct amdgpu_device *adev) 1623 { 1624 struct dc_init_data init_data; 1625 struct dc_callback_init init_params; 1626 int r; 1627 1628 adev->dm.ddev = adev_to_drm(adev); 1629 adev->dm.adev = adev; 1630 1631 /* Zero all the fields */ 1632 memset(&init_data, 0, sizeof(init_data)); 1633 memset(&init_params, 0, sizeof(init_params)); 1634 1635 mutex_init(&adev->dm.dpia_aux_lock); 1636 mutex_init(&adev->dm.dc_lock); 1637 mutex_init(&adev->dm.audio_lock); 1638 1639 if (amdgpu_dm_irq_init(adev)) { 1640 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1641 goto error; 1642 } 1643 1644 init_data.asic_id.chip_family = adev->family; 1645 1646 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1647 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1648 init_data.asic_id.chip_id = adev->pdev->device; 1649 1650 init_data.asic_id.vram_width = adev->gmc.vram_width; 1651 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1652 init_data.asic_id.atombios_base_address = 1653 adev->mode_info.atom_context->bios; 1654 1655 init_data.driver = adev; 1656 1657 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1658 1659 if (!adev->dm.cgs_device) { 1660 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 1661 goto error; 1662 } 1663 1664 init_data.cgs_device = adev->dm.cgs_device; 1665 1666 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1667 1668 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1669 case IP_VERSION(2, 1, 0): 1670 switch (adev->dm.dmcub_fw_version) { 1671 case 0: /* development */ 1672 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1673 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1674 init_data.flags.disable_dmcu = false; 1675 break; 1676 default: 1677 init_data.flags.disable_dmcu = true; 1678 } 1679 break; 1680 case IP_VERSION(2, 0, 3): 1681 init_data.flags.disable_dmcu = true; 1682 break; 1683 default: 1684 break; 1685 } 1686 1687 /* APU support S/G display by default except: 1688 * ASICs before Carrizo, 1689 * RAVEN1 (Users reported stability issue) 1690 */ 1691 1692 if (adev->asic_type < CHIP_CARRIZO) { 1693 init_data.flags.gpu_vm_support = false; 1694 } else if (adev->asic_type == CHIP_RAVEN) { 1695 if (adev->apu_flags & AMD_APU_IS_RAVEN) 1696 init_data.flags.gpu_vm_support = false; 1697 else 1698 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 1699 } else { 1700 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 1701 } 1702 1703 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 1704 1705 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1706 init_data.flags.fbc_support = true; 1707 1708 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1709 init_data.flags.multi_mon_pp_mclk_switch = true; 1710 1711 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1712 init_data.flags.disable_fractional_pwm = true; 1713 1714 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1715 init_data.flags.edp_no_power_sequencing = true; 1716 1717 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1718 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1719 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1720 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1721 1722 init_data.flags.seamless_boot_edp_requested = false; 1723 1724 if (amdgpu_device_seamless_boot_supported(adev)) { 1725 init_data.flags.seamless_boot_edp_requested = true; 1726 init_data.flags.allow_seamless_boot_optimization = true; 1727 DRM_INFO("Seamless boot condition check passed\n"); 1728 } 1729 1730 init_data.flags.enable_mipi_converter_optimization = true; 1731 1732 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1733 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1734 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 1735 1736 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 1737 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 1738 else 1739 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 1740 1741 init_data.flags.disable_ips_in_vpb = 0; 1742 1743 /* Enable DWB for tested platforms only */ 1744 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 1745 init_data.num_virtual_links = 1; 1746 1747 INIT_LIST_HEAD(&adev->dm.da_list); 1748 1749 retrieve_dmi_info(&adev->dm); 1750 1751 /* Display Core create. */ 1752 adev->dm.dc = dc_create(&init_data); 1753 1754 if (adev->dm.dc) { 1755 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1756 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1757 } else { 1758 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1759 goto error; 1760 } 1761 1762 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1763 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1764 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1765 } 1766 1767 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1768 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1769 if (dm_should_disable_stutter(adev->pdev)) 1770 adev->dm.dc->debug.disable_stutter = true; 1771 1772 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1773 adev->dm.dc->debug.disable_stutter = true; 1774 1775 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1776 adev->dm.dc->debug.disable_dsc = true; 1777 1778 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1779 adev->dm.dc->debug.disable_clock_gate = true; 1780 1781 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1782 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1783 1784 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) 1785 adev->dm.dc->debug.using_dml2 = true; 1786 1787 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1788 1789 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1790 adev->dm.dc->debug.ignore_cable_id = true; 1791 1792 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1793 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1794 1795 r = dm_dmub_hw_init(adev); 1796 if (r) { 1797 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1798 goto error; 1799 } 1800 1801 dc_hardware_init(adev->dm.dc); 1802 1803 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1804 if (!adev->dm.hpd_rx_offload_wq) { 1805 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1806 goto error; 1807 } 1808 1809 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1810 struct dc_phy_addr_space_config pa_config; 1811 1812 mmhub_read_system_context(adev, &pa_config); 1813 1814 // Call the DC init_memory func 1815 dc_setup_system_context(adev->dm.dc, &pa_config); 1816 } 1817 1818 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1819 if (!adev->dm.freesync_module) { 1820 DRM_ERROR( 1821 "amdgpu: failed to initialize freesync_module.\n"); 1822 } else 1823 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1824 adev->dm.freesync_module); 1825 1826 amdgpu_dm_init_color_mod(); 1827 1828 if (adev->dm.dc->caps.max_links > 0) { 1829 adev->dm.vblank_control_workqueue = 1830 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1831 if (!adev->dm.vblank_control_workqueue) 1832 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1833 } 1834 1835 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1836 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1837 1838 if (!adev->dm.hdcp_workqueue) 1839 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1840 else 1841 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1842 1843 dc_init_callbacks(adev->dm.dc, &init_params); 1844 } 1845 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1846 init_completion(&adev->dm.dmub_aux_transfer_done); 1847 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1848 if (!adev->dm.dmub_notify) { 1849 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1850 goto error; 1851 } 1852 1853 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1854 if (!adev->dm.delayed_hpd_wq) { 1855 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1856 goto error; 1857 } 1858 1859 amdgpu_dm_outbox_init(adev); 1860 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1861 dmub_aux_setconfig_callback, false)) { 1862 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1863 goto error; 1864 } 1865 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 1866 * It is expected that DMUB will resend any pending notifications at this point. Note 1867 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 1868 * align legacy interface initialization sequence. Connection status will be proactivly 1869 * detected once in the amdgpu_dm_initialize_drm_device. 1870 */ 1871 dc_enable_dmub_outbox(adev->dm.dc); 1872 1873 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 1874 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 1875 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 1876 } 1877 1878 if (amdgpu_dm_initialize_drm_device(adev)) { 1879 DRM_ERROR( 1880 "amdgpu: failed to initialize sw for display support.\n"); 1881 goto error; 1882 } 1883 1884 /* create fake encoders for MST */ 1885 dm_dp_create_fake_mst_encoders(adev); 1886 1887 /* TODO: Add_display_info? */ 1888 1889 /* TODO use dynamic cursor width */ 1890 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 1891 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 1892 1893 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 1894 DRM_ERROR( 1895 "amdgpu: failed to initialize sw for display support.\n"); 1896 goto error; 1897 } 1898 1899 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1900 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 1901 if (!adev->dm.secure_display_ctxs) 1902 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 1903 #endif 1904 1905 DRM_DEBUG_DRIVER("KMS initialized.\n"); 1906 1907 return 0; 1908 error: 1909 amdgpu_dm_fini(adev); 1910 1911 return -EINVAL; 1912 } 1913 1914 static int amdgpu_dm_early_fini(void *handle) 1915 { 1916 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1917 1918 amdgpu_dm_audio_fini(adev); 1919 1920 return 0; 1921 } 1922 1923 static void amdgpu_dm_fini(struct amdgpu_device *adev) 1924 { 1925 int i; 1926 1927 if (adev->dm.vblank_control_workqueue) { 1928 destroy_workqueue(adev->dm.vblank_control_workqueue); 1929 adev->dm.vblank_control_workqueue = NULL; 1930 } 1931 1932 amdgpu_dm_destroy_drm_device(&adev->dm); 1933 1934 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 1935 if (adev->dm.secure_display_ctxs) { 1936 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1937 if (adev->dm.secure_display_ctxs[i].crtc) { 1938 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 1939 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 1940 } 1941 } 1942 kfree(adev->dm.secure_display_ctxs); 1943 adev->dm.secure_display_ctxs = NULL; 1944 } 1945 #endif 1946 if (adev->dm.hdcp_workqueue) { 1947 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 1948 adev->dm.hdcp_workqueue = NULL; 1949 } 1950 1951 if (adev->dm.dc) { 1952 dc_deinit_callbacks(adev->dm.dc); 1953 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 1954 if (dc_enable_dmub_notifications(adev->dm.dc)) { 1955 kfree(adev->dm.dmub_notify); 1956 adev->dm.dmub_notify = NULL; 1957 destroy_workqueue(adev->dm.delayed_hpd_wq); 1958 adev->dm.delayed_hpd_wq = NULL; 1959 } 1960 } 1961 1962 if (adev->dm.dmub_bo) 1963 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1964 &adev->dm.dmub_bo_gpu_addr, 1965 &adev->dm.dmub_bo_cpu_addr); 1966 1967 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 1968 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1969 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1970 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1971 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1972 } 1973 } 1974 1975 kfree(adev->dm.hpd_rx_offload_wq); 1976 adev->dm.hpd_rx_offload_wq = NULL; 1977 } 1978 1979 /* DC Destroy TODO: Replace destroy DAL */ 1980 if (adev->dm.dc) 1981 dc_destroy(&adev->dm.dc); 1982 /* 1983 * TODO: pageflip, vlank interrupt 1984 * 1985 * amdgpu_dm_irq_fini(adev); 1986 */ 1987 1988 if (adev->dm.cgs_device) { 1989 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1990 adev->dm.cgs_device = NULL; 1991 } 1992 if (adev->dm.freesync_module) { 1993 mod_freesync_destroy(adev->dm.freesync_module); 1994 adev->dm.freesync_module = NULL; 1995 } 1996 1997 mutex_destroy(&adev->dm.audio_lock); 1998 mutex_destroy(&adev->dm.dc_lock); 1999 mutex_destroy(&adev->dm.dpia_aux_lock); 2000 } 2001 2002 static int load_dmcu_fw(struct amdgpu_device *adev) 2003 { 2004 const char *fw_name_dmcu = NULL; 2005 int r; 2006 const struct dmcu_firmware_header_v1_0 *hdr; 2007 2008 switch (adev->asic_type) { 2009 #if defined(CONFIG_DRM_AMD_DC_SI) 2010 case CHIP_TAHITI: 2011 case CHIP_PITCAIRN: 2012 case CHIP_VERDE: 2013 case CHIP_OLAND: 2014 #endif 2015 case CHIP_BONAIRE: 2016 case CHIP_HAWAII: 2017 case CHIP_KAVERI: 2018 case CHIP_KABINI: 2019 case CHIP_MULLINS: 2020 case CHIP_TONGA: 2021 case CHIP_FIJI: 2022 case CHIP_CARRIZO: 2023 case CHIP_STONEY: 2024 case CHIP_POLARIS11: 2025 case CHIP_POLARIS10: 2026 case CHIP_POLARIS12: 2027 case CHIP_VEGAM: 2028 case CHIP_VEGA10: 2029 case CHIP_VEGA12: 2030 case CHIP_VEGA20: 2031 return 0; 2032 case CHIP_NAVI12: 2033 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 2034 break; 2035 case CHIP_RAVEN: 2036 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 2037 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2038 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 2039 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2040 else 2041 return 0; 2042 break; 2043 default: 2044 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2045 case IP_VERSION(2, 0, 2): 2046 case IP_VERSION(2, 0, 3): 2047 case IP_VERSION(2, 0, 0): 2048 case IP_VERSION(2, 1, 0): 2049 case IP_VERSION(3, 0, 0): 2050 case IP_VERSION(3, 0, 2): 2051 case IP_VERSION(3, 0, 3): 2052 case IP_VERSION(3, 0, 1): 2053 case IP_VERSION(3, 1, 2): 2054 case IP_VERSION(3, 1, 3): 2055 case IP_VERSION(3, 1, 4): 2056 case IP_VERSION(3, 1, 5): 2057 case IP_VERSION(3, 1, 6): 2058 case IP_VERSION(3, 2, 0): 2059 case IP_VERSION(3, 2, 1): 2060 case IP_VERSION(3, 5, 0): 2061 case IP_VERSION(3, 5, 1): 2062 return 0; 2063 default: 2064 break; 2065 } 2066 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2067 return -EINVAL; 2068 } 2069 2070 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2071 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2072 return 0; 2073 } 2074 2075 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2076 if (r == -ENODEV) { 2077 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2078 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2079 adev->dm.fw_dmcu = NULL; 2080 return 0; 2081 } 2082 if (r) { 2083 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2084 fw_name_dmcu); 2085 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2086 return r; 2087 } 2088 2089 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2090 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2091 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2092 adev->firmware.fw_size += 2093 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2094 2095 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2096 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2097 adev->firmware.fw_size += 2098 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2099 2100 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2101 2102 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2103 2104 return 0; 2105 } 2106 2107 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2108 { 2109 struct amdgpu_device *adev = ctx; 2110 2111 return dm_read_reg(adev->dm.dc->ctx, address); 2112 } 2113 2114 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2115 uint32_t value) 2116 { 2117 struct amdgpu_device *adev = ctx; 2118 2119 return dm_write_reg(adev->dm.dc->ctx, address, value); 2120 } 2121 2122 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2123 { 2124 struct dmub_srv_create_params create_params; 2125 struct dmub_srv_region_params region_params; 2126 struct dmub_srv_region_info region_info; 2127 struct dmub_srv_memory_params memory_params; 2128 struct dmub_srv_fb_info *fb_info; 2129 struct dmub_srv *dmub_srv; 2130 const struct dmcub_firmware_header_v1_0 *hdr; 2131 enum dmub_asic dmub_asic; 2132 enum dmub_status status; 2133 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { 2134 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST 2135 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK 2136 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA 2137 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS 2138 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX 2139 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF 2140 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE 2141 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM 2142 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE 2143 }; 2144 int r; 2145 2146 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2147 case IP_VERSION(2, 1, 0): 2148 dmub_asic = DMUB_ASIC_DCN21; 2149 break; 2150 case IP_VERSION(3, 0, 0): 2151 dmub_asic = DMUB_ASIC_DCN30; 2152 break; 2153 case IP_VERSION(3, 0, 1): 2154 dmub_asic = DMUB_ASIC_DCN301; 2155 break; 2156 case IP_VERSION(3, 0, 2): 2157 dmub_asic = DMUB_ASIC_DCN302; 2158 break; 2159 case IP_VERSION(3, 0, 3): 2160 dmub_asic = DMUB_ASIC_DCN303; 2161 break; 2162 case IP_VERSION(3, 1, 2): 2163 case IP_VERSION(3, 1, 3): 2164 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2165 break; 2166 case IP_VERSION(3, 1, 4): 2167 dmub_asic = DMUB_ASIC_DCN314; 2168 break; 2169 case IP_VERSION(3, 1, 5): 2170 dmub_asic = DMUB_ASIC_DCN315; 2171 break; 2172 case IP_VERSION(3, 1, 6): 2173 dmub_asic = DMUB_ASIC_DCN316; 2174 break; 2175 case IP_VERSION(3, 2, 0): 2176 dmub_asic = DMUB_ASIC_DCN32; 2177 break; 2178 case IP_VERSION(3, 2, 1): 2179 dmub_asic = DMUB_ASIC_DCN321; 2180 break; 2181 case IP_VERSION(3, 5, 0): 2182 case IP_VERSION(3, 5, 1): 2183 dmub_asic = DMUB_ASIC_DCN35; 2184 break; 2185 default: 2186 /* ASIC doesn't support DMUB. */ 2187 return 0; 2188 } 2189 2190 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2191 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2192 2193 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2194 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2195 AMDGPU_UCODE_ID_DMCUB; 2196 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2197 adev->dm.dmub_fw; 2198 adev->firmware.fw_size += 2199 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2200 2201 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2202 adev->dm.dmcub_fw_version); 2203 } 2204 2205 2206 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2207 dmub_srv = adev->dm.dmub_srv; 2208 2209 if (!dmub_srv) { 2210 DRM_ERROR("Failed to allocate DMUB service!\n"); 2211 return -ENOMEM; 2212 } 2213 2214 memset(&create_params, 0, sizeof(create_params)); 2215 create_params.user_ctx = adev; 2216 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2217 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2218 create_params.asic = dmub_asic; 2219 2220 /* Create the DMUB service. */ 2221 status = dmub_srv_create(dmub_srv, &create_params); 2222 if (status != DMUB_STATUS_OK) { 2223 DRM_ERROR("Error creating DMUB service: %d\n", status); 2224 return -EINVAL; 2225 } 2226 2227 /* Calculate the size of all the regions for the DMUB service. */ 2228 memset(®ion_params, 0, sizeof(region_params)); 2229 2230 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2231 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2232 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2233 region_params.vbios_size = adev->bios_size; 2234 region_params.fw_bss_data = region_params.bss_data_size ? 2235 adev->dm.dmub_fw->data + 2236 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2237 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2238 region_params.fw_inst_const = 2239 adev->dm.dmub_fw->data + 2240 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2241 PSP_HEADER_BYTES; 2242 region_params.window_memory_type = window_memory_type; 2243 2244 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2245 ®ion_info); 2246 2247 if (status != DMUB_STATUS_OK) { 2248 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2249 return -EINVAL; 2250 } 2251 2252 /* 2253 * Allocate a framebuffer based on the total size of all the regions. 2254 * TODO: Move this into GART. 2255 */ 2256 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2257 AMDGPU_GEM_DOMAIN_VRAM | 2258 AMDGPU_GEM_DOMAIN_GTT, 2259 &adev->dm.dmub_bo, 2260 &adev->dm.dmub_bo_gpu_addr, 2261 &adev->dm.dmub_bo_cpu_addr); 2262 if (r) 2263 return r; 2264 2265 /* Rebase the regions on the framebuffer address. */ 2266 memset(&memory_params, 0, sizeof(memory_params)); 2267 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2268 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2269 memory_params.region_info = ®ion_info; 2270 memory_params.window_memory_type = window_memory_type; 2271 2272 adev->dm.dmub_fb_info = 2273 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2274 fb_info = adev->dm.dmub_fb_info; 2275 2276 if (!fb_info) { 2277 DRM_ERROR( 2278 "Failed to allocate framebuffer info for DMUB service!\n"); 2279 return -ENOMEM; 2280 } 2281 2282 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2283 if (status != DMUB_STATUS_OK) { 2284 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2285 return -EINVAL; 2286 } 2287 2288 return 0; 2289 } 2290 2291 static int dm_sw_init(void *handle) 2292 { 2293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2294 int r; 2295 2296 r = dm_dmub_sw_init(adev); 2297 if (r) 2298 return r; 2299 2300 return load_dmcu_fw(adev); 2301 } 2302 2303 static int dm_sw_fini(void *handle) 2304 { 2305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2306 2307 kfree(adev->dm.dmub_fb_info); 2308 adev->dm.dmub_fb_info = NULL; 2309 2310 if (adev->dm.dmub_srv) { 2311 dmub_srv_destroy(adev->dm.dmub_srv); 2312 kfree(adev->dm.dmub_srv); 2313 adev->dm.dmub_srv = NULL; 2314 } 2315 2316 amdgpu_ucode_release(&adev->dm.dmub_fw); 2317 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2318 2319 return 0; 2320 } 2321 2322 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2323 { 2324 struct amdgpu_dm_connector *aconnector; 2325 struct drm_connector *connector; 2326 struct drm_connector_list_iter iter; 2327 int ret = 0; 2328 2329 drm_connector_list_iter_begin(dev, &iter); 2330 drm_for_each_connector_iter(connector, &iter) { 2331 2332 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2333 continue; 2334 2335 aconnector = to_amdgpu_dm_connector(connector); 2336 if (aconnector->dc_link->type == dc_connection_mst_branch && 2337 aconnector->mst_mgr.aux) { 2338 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", 2339 aconnector, 2340 aconnector->base.base.id); 2341 2342 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2343 if (ret < 0) { 2344 DRM_ERROR("DM_MST: Failed to start MST\n"); 2345 aconnector->dc_link->type = 2346 dc_connection_single; 2347 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2348 aconnector->dc_link); 2349 break; 2350 } 2351 } 2352 } 2353 drm_connector_list_iter_end(&iter); 2354 2355 return ret; 2356 } 2357 2358 static int dm_late_init(void *handle) 2359 { 2360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2361 2362 struct dmcu_iram_parameters params; 2363 unsigned int linear_lut[16]; 2364 int i; 2365 struct dmcu *dmcu = NULL; 2366 2367 dmcu = adev->dm.dc->res_pool->dmcu; 2368 2369 for (i = 0; i < 16; i++) 2370 linear_lut[i] = 0xFFFF * i / 15; 2371 2372 params.set = 0; 2373 params.backlight_ramping_override = false; 2374 params.backlight_ramping_start = 0xCCCC; 2375 params.backlight_ramping_reduction = 0xCCCCCCCC; 2376 params.backlight_lut_array_size = 16; 2377 params.backlight_lut_array = linear_lut; 2378 2379 /* Min backlight level after ABM reduction, Don't allow below 1% 2380 * 0xFFFF x 0.01 = 0x28F 2381 */ 2382 params.min_abm_backlight = 0x28F; 2383 /* In the case where abm is implemented on dmcub, 2384 * dmcu object will be null. 2385 * ABM 2.4 and up are implemented on dmcub. 2386 */ 2387 if (dmcu) { 2388 if (!dmcu_load_iram(dmcu, params)) 2389 return -EINVAL; 2390 } else if (adev->dm.dc->ctx->dmub_srv) { 2391 struct dc_link *edp_links[MAX_NUM_EDP]; 2392 int edp_num; 2393 2394 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2395 for (i = 0; i < edp_num; i++) { 2396 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2397 return -EINVAL; 2398 } 2399 } 2400 2401 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2402 } 2403 2404 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2405 { 2406 int ret; 2407 u8 guid[16]; 2408 u64 tmp64; 2409 2410 mutex_lock(&mgr->lock); 2411 if (!mgr->mst_primary) 2412 goto out_fail; 2413 2414 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2415 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2416 goto out_fail; 2417 } 2418 2419 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2420 DP_MST_EN | 2421 DP_UP_REQ_EN | 2422 DP_UPSTREAM_IS_SRC); 2423 if (ret < 0) { 2424 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2425 goto out_fail; 2426 } 2427 2428 /* Some hubs forget their guids after they resume */ 2429 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); 2430 if (ret != 16) { 2431 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2432 goto out_fail; 2433 } 2434 2435 if (memchr_inv(guid, 0, 16) == NULL) { 2436 tmp64 = get_jiffies_64(); 2437 memcpy(&guid[0], &tmp64, sizeof(u64)); 2438 memcpy(&guid[8], &tmp64, sizeof(u64)); 2439 2440 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); 2441 2442 if (ret != 16) { 2443 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2444 goto out_fail; 2445 } 2446 } 2447 2448 memcpy(mgr->mst_primary->guid, guid, 16); 2449 2450 out_fail: 2451 mutex_unlock(&mgr->lock); 2452 } 2453 2454 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2455 { 2456 struct amdgpu_dm_connector *aconnector; 2457 struct drm_connector *connector; 2458 struct drm_connector_list_iter iter; 2459 struct drm_dp_mst_topology_mgr *mgr; 2460 2461 drm_connector_list_iter_begin(dev, &iter); 2462 drm_for_each_connector_iter(connector, &iter) { 2463 2464 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2465 continue; 2466 2467 aconnector = to_amdgpu_dm_connector(connector); 2468 if (aconnector->dc_link->type != dc_connection_mst_branch || 2469 aconnector->mst_root) 2470 continue; 2471 2472 mgr = &aconnector->mst_mgr; 2473 2474 if (suspend) { 2475 drm_dp_mst_topology_mgr_suspend(mgr); 2476 } else { 2477 /* if extended timeout is supported in hardware, 2478 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2479 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2480 */ 2481 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2482 if (!dp_is_lttpr_present(aconnector->dc_link)) 2483 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2484 2485 /* TODO: move resume_mst_branch_status() into drm mst resume again 2486 * once topology probing work is pulled out from mst resume into mst 2487 * resume 2nd step. mst resume 2nd step should be called after old 2488 * state getting restored (i.e. drm_atomic_helper_resume()). 2489 */ 2490 resume_mst_branch_status(mgr); 2491 } 2492 } 2493 drm_connector_list_iter_end(&iter); 2494 } 2495 2496 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2497 { 2498 int ret = 0; 2499 2500 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2501 * on window driver dc implementation. 2502 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2503 * should be passed to smu during boot up and resume from s3. 2504 * boot up: dc calculate dcn watermark clock settings within dc_create, 2505 * dcn20_resource_construct 2506 * then call pplib functions below to pass the settings to smu: 2507 * smu_set_watermarks_for_clock_ranges 2508 * smu_set_watermarks_table 2509 * navi10_set_watermarks_table 2510 * smu_write_watermarks_table 2511 * 2512 * For Renoir, clock settings of dcn watermark are also fixed values. 2513 * dc has implemented different flow for window driver: 2514 * dc_hardware_init / dc_set_power_state 2515 * dcn10_init_hw 2516 * notify_wm_ranges 2517 * set_wm_ranges 2518 * -- Linux 2519 * smu_set_watermarks_for_clock_ranges 2520 * renoir_set_watermarks_table 2521 * smu_write_watermarks_table 2522 * 2523 * For Linux, 2524 * dc_hardware_init -> amdgpu_dm_init 2525 * dc_set_power_state --> dm_resume 2526 * 2527 * therefore, this function apply to navi10/12/14 but not Renoir 2528 * * 2529 */ 2530 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2531 case IP_VERSION(2, 0, 2): 2532 case IP_VERSION(2, 0, 0): 2533 break; 2534 default: 2535 return 0; 2536 } 2537 2538 ret = amdgpu_dpm_write_watermarks_table(adev); 2539 if (ret) { 2540 DRM_ERROR("Failed to update WMTABLE!\n"); 2541 return ret; 2542 } 2543 2544 return 0; 2545 } 2546 2547 /** 2548 * dm_hw_init() - Initialize DC device 2549 * @handle: The base driver device containing the amdgpu_dm device. 2550 * 2551 * Initialize the &struct amdgpu_display_manager device. This involves calling 2552 * the initializers of each DM component, then populating the struct with them. 2553 * 2554 * Although the function implies hardware initialization, both hardware and 2555 * software are initialized here. Splitting them out to their relevant init 2556 * hooks is a future TODO item. 2557 * 2558 * Some notable things that are initialized here: 2559 * 2560 * - Display Core, both software and hardware 2561 * - DC modules that we need (freesync and color management) 2562 * - DRM software states 2563 * - Interrupt sources and handlers 2564 * - Vblank support 2565 * - Debug FS entries, if enabled 2566 */ 2567 static int dm_hw_init(void *handle) 2568 { 2569 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2570 /* Create DAL display manager */ 2571 amdgpu_dm_init(adev); 2572 amdgpu_dm_hpd_init(adev); 2573 2574 return 0; 2575 } 2576 2577 /** 2578 * dm_hw_fini() - Teardown DC device 2579 * @handle: The base driver device containing the amdgpu_dm device. 2580 * 2581 * Teardown components within &struct amdgpu_display_manager that require 2582 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2583 * were loaded. Also flush IRQ workqueues and disable them. 2584 */ 2585 static int dm_hw_fini(void *handle) 2586 { 2587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2588 2589 amdgpu_dm_hpd_fini(adev); 2590 2591 amdgpu_dm_irq_fini(adev); 2592 amdgpu_dm_fini(adev); 2593 return 0; 2594 } 2595 2596 2597 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2598 struct dc_state *state, bool enable) 2599 { 2600 enum dc_irq_source irq_source; 2601 struct amdgpu_crtc *acrtc; 2602 int rc = -EBUSY; 2603 int i = 0; 2604 2605 for (i = 0; i < state->stream_count; i++) { 2606 acrtc = get_crtc_by_otg_inst( 2607 adev, state->stream_status[i].primary_otg_inst); 2608 2609 if (acrtc && state->stream_status[i].plane_count != 0) { 2610 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2611 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2612 if (rc) 2613 DRM_WARN("Failed to %s pflip interrupts\n", 2614 enable ? "enable" : "disable"); 2615 2616 if (enable) { 2617 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2618 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2619 } else 2620 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2621 2622 if (rc) 2623 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2624 2625 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2626 /* During gpu-reset we disable and then enable vblank irq, so 2627 * don't use amdgpu_irq_get/put() to avoid refcount change. 2628 */ 2629 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2630 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2631 } 2632 } 2633 2634 } 2635 2636 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2637 { 2638 struct dc_state *context = NULL; 2639 enum dc_status res = DC_ERROR_UNEXPECTED; 2640 int i; 2641 struct dc_stream_state *del_streams[MAX_PIPES]; 2642 int del_streams_count = 0; 2643 struct dc_commit_streams_params params = {}; 2644 2645 memset(del_streams, 0, sizeof(del_streams)); 2646 2647 context = dc_state_create_current_copy(dc); 2648 if (context == NULL) 2649 goto context_alloc_fail; 2650 2651 /* First remove from context all streams */ 2652 for (i = 0; i < context->stream_count; i++) { 2653 struct dc_stream_state *stream = context->streams[i]; 2654 2655 del_streams[del_streams_count++] = stream; 2656 } 2657 2658 /* Remove all planes for removed streams and then remove the streams */ 2659 for (i = 0; i < del_streams_count; i++) { 2660 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2661 res = DC_FAIL_DETACH_SURFACES; 2662 goto fail; 2663 } 2664 2665 res = dc_state_remove_stream(dc, context, del_streams[i]); 2666 if (res != DC_OK) 2667 goto fail; 2668 } 2669 2670 params.streams = context->streams; 2671 params.stream_count = context->stream_count; 2672 res = dc_commit_streams(dc, ¶ms); 2673 2674 fail: 2675 dc_state_release(context); 2676 2677 context_alloc_fail: 2678 return res; 2679 } 2680 2681 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2682 { 2683 int i; 2684 2685 if (dm->hpd_rx_offload_wq) { 2686 for (i = 0; i < dm->dc->caps.max_links; i++) 2687 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2688 } 2689 } 2690 2691 static int dm_suspend(void *handle) 2692 { 2693 struct amdgpu_device *adev = handle; 2694 struct amdgpu_display_manager *dm = &adev->dm; 2695 int ret = 0; 2696 2697 if (amdgpu_in_reset(adev)) { 2698 mutex_lock(&dm->dc_lock); 2699 2700 dc_allow_idle_optimizations(adev->dm.dc, false); 2701 2702 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 2703 2704 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2705 2706 amdgpu_dm_commit_zero_streams(dm->dc); 2707 2708 amdgpu_dm_irq_suspend(adev); 2709 2710 hpd_rx_irq_work_suspend(dm); 2711 2712 return ret; 2713 } 2714 2715 WARN_ON(adev->dm.cached_state); 2716 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2717 if (IS_ERR(adev->dm.cached_state)) 2718 return PTR_ERR(adev->dm.cached_state); 2719 2720 s3_handle_mst(adev_to_drm(adev), true); 2721 2722 amdgpu_dm_irq_suspend(adev); 2723 2724 hpd_rx_irq_work_suspend(dm); 2725 2726 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2727 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 2728 2729 return 0; 2730 } 2731 2732 struct drm_connector * 2733 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2734 struct drm_crtc *crtc) 2735 { 2736 u32 i; 2737 struct drm_connector_state *new_con_state; 2738 struct drm_connector *connector; 2739 struct drm_crtc *crtc_from_state; 2740 2741 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2742 crtc_from_state = new_con_state->crtc; 2743 2744 if (crtc_from_state == crtc) 2745 return connector; 2746 } 2747 2748 return NULL; 2749 } 2750 2751 static void emulated_link_detect(struct dc_link *link) 2752 { 2753 struct dc_sink_init_data sink_init_data = { 0 }; 2754 struct display_sink_capability sink_caps = { 0 }; 2755 enum dc_edid_status edid_status; 2756 struct dc_context *dc_ctx = link->ctx; 2757 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 2758 struct dc_sink *sink = NULL; 2759 struct dc_sink *prev_sink = NULL; 2760 2761 link->type = dc_connection_none; 2762 prev_sink = link->local_sink; 2763 2764 if (prev_sink) 2765 dc_sink_release(prev_sink); 2766 2767 switch (link->connector_signal) { 2768 case SIGNAL_TYPE_HDMI_TYPE_A: { 2769 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2770 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2771 break; 2772 } 2773 2774 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2775 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2776 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2777 break; 2778 } 2779 2780 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2781 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2782 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2783 break; 2784 } 2785 2786 case SIGNAL_TYPE_LVDS: { 2787 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2788 sink_caps.signal = SIGNAL_TYPE_LVDS; 2789 break; 2790 } 2791 2792 case SIGNAL_TYPE_EDP: { 2793 sink_caps.transaction_type = 2794 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2795 sink_caps.signal = SIGNAL_TYPE_EDP; 2796 break; 2797 } 2798 2799 case SIGNAL_TYPE_DISPLAY_PORT: { 2800 sink_caps.transaction_type = 2801 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2802 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2803 break; 2804 } 2805 2806 default: 2807 drm_err(dev, "Invalid connector type! signal:%d\n", 2808 link->connector_signal); 2809 return; 2810 } 2811 2812 sink_init_data.link = link; 2813 sink_init_data.sink_signal = sink_caps.signal; 2814 2815 sink = dc_sink_create(&sink_init_data); 2816 if (!sink) { 2817 drm_err(dev, "Failed to create sink!\n"); 2818 return; 2819 } 2820 2821 /* dc_sink_create returns a new reference */ 2822 link->local_sink = sink; 2823 2824 edid_status = dm_helpers_read_local_edid( 2825 link->ctx, 2826 link, 2827 sink); 2828 2829 if (edid_status != EDID_OK) 2830 drm_err(dev, "Failed to read EDID\n"); 2831 2832 } 2833 2834 static void dm_gpureset_commit_state(struct dc_state *dc_state, 2835 struct amdgpu_display_manager *dm) 2836 { 2837 struct { 2838 struct dc_surface_update surface_updates[MAX_SURFACES]; 2839 struct dc_plane_info plane_infos[MAX_SURFACES]; 2840 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 2841 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 2842 struct dc_stream_update stream_update; 2843 } *bundle; 2844 int k, m; 2845 2846 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 2847 2848 if (!bundle) { 2849 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 2850 goto cleanup; 2851 } 2852 2853 for (k = 0; k < dc_state->stream_count; k++) { 2854 bundle->stream_update.stream = dc_state->streams[k]; 2855 2856 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 2857 bundle->surface_updates[m].surface = 2858 dc_state->stream_status->plane_states[m]; 2859 bundle->surface_updates[m].surface->force_full_update = 2860 true; 2861 } 2862 2863 update_planes_and_stream_adapter(dm->dc, 2864 UPDATE_TYPE_FULL, 2865 dc_state->stream_status->plane_count, 2866 dc_state->streams[k], 2867 &bundle->stream_update, 2868 bundle->surface_updates); 2869 } 2870 2871 cleanup: 2872 kfree(bundle); 2873 } 2874 2875 static int dm_resume(void *handle) 2876 { 2877 struct amdgpu_device *adev = handle; 2878 struct drm_device *ddev = adev_to_drm(adev); 2879 struct amdgpu_display_manager *dm = &adev->dm; 2880 struct amdgpu_dm_connector *aconnector; 2881 struct drm_connector *connector; 2882 struct drm_connector_list_iter iter; 2883 struct drm_crtc *crtc; 2884 struct drm_crtc_state *new_crtc_state; 2885 struct dm_crtc_state *dm_new_crtc_state; 2886 struct drm_plane *plane; 2887 struct drm_plane_state *new_plane_state; 2888 struct dm_plane_state *dm_new_plane_state; 2889 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 2890 enum dc_connection_type new_connection_type = dc_connection_none; 2891 struct dc_state *dc_state; 2892 int i, r, j, ret; 2893 bool need_hotplug = false; 2894 struct dc_commit_streams_params commit_params = {}; 2895 2896 if (dm->dc->caps.ips_support) { 2897 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 2898 } 2899 2900 if (amdgpu_in_reset(adev)) { 2901 dc_state = dm->cached_dc_state; 2902 2903 /* 2904 * The dc->current_state is backed up into dm->cached_dc_state 2905 * before we commit 0 streams. 2906 * 2907 * DC will clear link encoder assignments on the real state 2908 * but the changes won't propagate over to the copy we made 2909 * before the 0 streams commit. 2910 * 2911 * DC expects that link encoder assignments are *not* valid 2912 * when committing a state, so as a workaround we can copy 2913 * off of the current state. 2914 * 2915 * We lose the previous assignments, but we had already 2916 * commit 0 streams anyway. 2917 */ 2918 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2919 2920 r = dm_dmub_hw_init(adev); 2921 if (r) 2922 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 2923 2924 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2925 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2926 2927 dc_resume(dm->dc); 2928 2929 amdgpu_dm_irq_resume_early(adev); 2930 2931 for (i = 0; i < dc_state->stream_count; i++) { 2932 dc_state->streams[i]->mode_changed = true; 2933 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2934 dc_state->stream_status[i].plane_states[j]->update_flags.raw 2935 = 0xffffffff; 2936 } 2937 } 2938 2939 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2940 amdgpu_dm_outbox_init(adev); 2941 dc_enable_dmub_outbox(adev->dm.dc); 2942 } 2943 2944 commit_params.streams = dc_state->streams; 2945 commit_params.stream_count = dc_state->stream_count; 2946 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 2947 2948 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2949 2950 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2951 2952 dc_state_release(dm->cached_dc_state); 2953 dm->cached_dc_state = NULL; 2954 2955 amdgpu_dm_irq_resume_late(adev); 2956 2957 mutex_unlock(&dm->dc_lock); 2958 2959 return 0; 2960 } 2961 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2962 dc_state_release(dm_state->context); 2963 dm_state->context = dc_state_create(dm->dc, NULL); 2964 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2965 2966 /* Before powering on DC we need to re-initialize DMUB. */ 2967 dm_dmub_hw_resume(adev); 2968 2969 /* Re-enable outbox interrupts for DPIA. */ 2970 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2971 amdgpu_dm_outbox_init(adev); 2972 dc_enable_dmub_outbox(adev->dm.dc); 2973 } 2974 2975 /* power on hardware */ 2976 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2977 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2978 2979 /* program HPD filter */ 2980 dc_resume(dm->dc); 2981 2982 /* 2983 * early enable HPD Rx IRQ, should be done before set mode as short 2984 * pulse interrupts are used for MST 2985 */ 2986 amdgpu_dm_irq_resume_early(adev); 2987 2988 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2989 s3_handle_mst(ddev, false); 2990 2991 /* Do detection*/ 2992 drm_connector_list_iter_begin(ddev, &iter); 2993 drm_for_each_connector_iter(connector, &iter) { 2994 2995 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2996 continue; 2997 2998 aconnector = to_amdgpu_dm_connector(connector); 2999 3000 if (!aconnector->dc_link) 3001 continue; 3002 3003 /* 3004 * this is the case when traversing through already created end sink 3005 * MST connectors, should be skipped 3006 */ 3007 if (aconnector && aconnector->mst_root) 3008 continue; 3009 3010 mutex_lock(&aconnector->hpd_lock); 3011 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3012 DRM_ERROR("KMS: Failed to detect connector\n"); 3013 3014 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3015 emulated_link_detect(aconnector->dc_link); 3016 } else { 3017 mutex_lock(&dm->dc_lock); 3018 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3019 mutex_unlock(&dm->dc_lock); 3020 } 3021 3022 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 3023 aconnector->fake_enable = false; 3024 3025 if (aconnector->dc_sink) 3026 dc_sink_release(aconnector->dc_sink); 3027 aconnector->dc_sink = NULL; 3028 amdgpu_dm_update_connector_after_detect(aconnector); 3029 mutex_unlock(&aconnector->hpd_lock); 3030 } 3031 drm_connector_list_iter_end(&iter); 3032 3033 /* Force mode set in atomic commit */ 3034 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 3035 new_crtc_state->active_changed = true; 3036 3037 /* 3038 * atomic_check is expected to create the dc states. We need to release 3039 * them here, since they were duplicated as part of the suspend 3040 * procedure. 3041 */ 3042 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 3043 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 3044 if (dm_new_crtc_state->stream) { 3045 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 3046 dc_stream_release(dm_new_crtc_state->stream); 3047 dm_new_crtc_state->stream = NULL; 3048 } 3049 dm_new_crtc_state->base.color_mgmt_changed = true; 3050 } 3051 3052 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 3053 dm_new_plane_state = to_dm_plane_state(new_plane_state); 3054 if (dm_new_plane_state->dc_state) { 3055 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 3056 dc_plane_state_release(dm_new_plane_state->dc_state); 3057 dm_new_plane_state->dc_state = NULL; 3058 } 3059 } 3060 3061 drm_atomic_helper_resume(ddev, dm->cached_state); 3062 3063 dm->cached_state = NULL; 3064 3065 /* Do mst topology probing after resuming cached state*/ 3066 drm_connector_list_iter_begin(ddev, &iter); 3067 drm_for_each_connector_iter(connector, &iter) { 3068 3069 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3070 continue; 3071 3072 aconnector = to_amdgpu_dm_connector(connector); 3073 if (aconnector->dc_link->type != dc_connection_mst_branch || 3074 aconnector->mst_root) 3075 continue; 3076 3077 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 3078 3079 if (ret < 0) { 3080 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 3081 aconnector->dc_link); 3082 need_hotplug = true; 3083 } 3084 } 3085 drm_connector_list_iter_end(&iter); 3086 3087 if (need_hotplug) 3088 drm_kms_helper_hotplug_event(ddev); 3089 3090 amdgpu_dm_irq_resume_late(adev); 3091 3092 amdgpu_dm_smu_write_watermarks_table(adev); 3093 3094 return 0; 3095 } 3096 3097 /** 3098 * DOC: DM Lifecycle 3099 * 3100 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3101 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3102 * the base driver's device list to be initialized and torn down accordingly. 3103 * 3104 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3105 */ 3106 3107 static const struct amd_ip_funcs amdgpu_dm_funcs = { 3108 .name = "dm", 3109 .early_init = dm_early_init, 3110 .late_init = dm_late_init, 3111 .sw_init = dm_sw_init, 3112 .sw_fini = dm_sw_fini, 3113 .early_fini = amdgpu_dm_early_fini, 3114 .hw_init = dm_hw_init, 3115 .hw_fini = dm_hw_fini, 3116 .suspend = dm_suspend, 3117 .resume = dm_resume, 3118 .is_idle = dm_is_idle, 3119 .wait_for_idle = dm_wait_for_idle, 3120 .check_soft_reset = dm_check_soft_reset, 3121 .soft_reset = dm_soft_reset, 3122 .set_clockgating_state = dm_set_clockgating_state, 3123 .set_powergating_state = dm_set_powergating_state, 3124 }; 3125 3126 const struct amdgpu_ip_block_version dm_ip_block = { 3127 .type = AMD_IP_BLOCK_TYPE_DCE, 3128 .major = 1, 3129 .minor = 0, 3130 .rev = 0, 3131 .funcs = &amdgpu_dm_funcs, 3132 }; 3133 3134 3135 /** 3136 * DOC: atomic 3137 * 3138 * *WIP* 3139 */ 3140 3141 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3142 .fb_create = amdgpu_display_user_framebuffer_create, 3143 .get_format_info = amdgpu_dm_plane_get_format_info, 3144 .atomic_check = amdgpu_dm_atomic_check, 3145 .atomic_commit = drm_atomic_helper_commit, 3146 }; 3147 3148 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3149 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3150 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 3151 }; 3152 3153 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3154 { 3155 struct amdgpu_dm_backlight_caps *caps; 3156 struct drm_connector *conn_base; 3157 struct amdgpu_device *adev; 3158 struct drm_luminance_range_info *luminance_range; 3159 3160 if (aconnector->bl_idx == -1 || 3161 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3162 return; 3163 3164 conn_base = &aconnector->base; 3165 adev = drm_to_adev(conn_base->dev); 3166 3167 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3168 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3169 caps->aux_support = false; 3170 3171 if (caps->ext_caps->bits.oled == 1 3172 /* 3173 * || 3174 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3175 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3176 */) 3177 caps->aux_support = true; 3178 3179 if (amdgpu_backlight == 0) 3180 caps->aux_support = false; 3181 else if (amdgpu_backlight == 1) 3182 caps->aux_support = true; 3183 3184 luminance_range = &conn_base->display_info.luminance_range; 3185 3186 if (luminance_range->max_luminance) { 3187 caps->aux_min_input_signal = luminance_range->min_luminance; 3188 caps->aux_max_input_signal = luminance_range->max_luminance; 3189 } else { 3190 caps->aux_min_input_signal = 0; 3191 caps->aux_max_input_signal = 512; 3192 } 3193 } 3194 3195 void amdgpu_dm_update_connector_after_detect( 3196 struct amdgpu_dm_connector *aconnector) 3197 { 3198 struct drm_connector *connector = &aconnector->base; 3199 struct drm_device *dev = connector->dev; 3200 struct dc_sink *sink; 3201 3202 /* MST handled by drm_mst framework */ 3203 if (aconnector->mst_mgr.mst_state == true) 3204 return; 3205 3206 sink = aconnector->dc_link->local_sink; 3207 if (sink) 3208 dc_sink_retain(sink); 3209 3210 /* 3211 * Edid mgmt connector gets first update only in mode_valid hook and then 3212 * the connector sink is set to either fake or physical sink depends on link status. 3213 * Skip if already done during boot. 3214 */ 3215 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3216 && aconnector->dc_em_sink) { 3217 3218 /* 3219 * For S3 resume with headless use eml_sink to fake stream 3220 * because on resume connector->sink is set to NULL 3221 */ 3222 mutex_lock(&dev->mode_config.mutex); 3223 3224 if (sink) { 3225 if (aconnector->dc_sink) { 3226 amdgpu_dm_update_freesync_caps(connector, NULL); 3227 /* 3228 * retain and release below are used to 3229 * bump up refcount for sink because the link doesn't point 3230 * to it anymore after disconnect, so on next crtc to connector 3231 * reshuffle by UMD we will get into unwanted dc_sink release 3232 */ 3233 dc_sink_release(aconnector->dc_sink); 3234 } 3235 aconnector->dc_sink = sink; 3236 dc_sink_retain(aconnector->dc_sink); 3237 amdgpu_dm_update_freesync_caps(connector, 3238 aconnector->edid); 3239 } else { 3240 amdgpu_dm_update_freesync_caps(connector, NULL); 3241 if (!aconnector->dc_sink) { 3242 aconnector->dc_sink = aconnector->dc_em_sink; 3243 dc_sink_retain(aconnector->dc_sink); 3244 } 3245 } 3246 3247 mutex_unlock(&dev->mode_config.mutex); 3248 3249 if (sink) 3250 dc_sink_release(sink); 3251 return; 3252 } 3253 3254 /* 3255 * TODO: temporary guard to look for proper fix 3256 * if this sink is MST sink, we should not do anything 3257 */ 3258 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3259 dc_sink_release(sink); 3260 return; 3261 } 3262 3263 if (aconnector->dc_sink == sink) { 3264 /* 3265 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3266 * Do nothing!! 3267 */ 3268 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", 3269 aconnector->connector_id); 3270 if (sink) 3271 dc_sink_release(sink); 3272 return; 3273 } 3274 3275 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3276 aconnector->connector_id, aconnector->dc_sink, sink); 3277 3278 mutex_lock(&dev->mode_config.mutex); 3279 3280 /* 3281 * 1. Update status of the drm connector 3282 * 2. Send an event and let userspace tell us what to do 3283 */ 3284 if (sink) { 3285 /* 3286 * TODO: check if we still need the S3 mode update workaround. 3287 * If yes, put it here. 3288 */ 3289 if (aconnector->dc_sink) { 3290 amdgpu_dm_update_freesync_caps(connector, NULL); 3291 dc_sink_release(aconnector->dc_sink); 3292 } 3293 3294 aconnector->dc_sink = sink; 3295 dc_sink_retain(aconnector->dc_sink); 3296 if (sink->dc_edid.length == 0) { 3297 aconnector->edid = NULL; 3298 if (aconnector->dc_link->aux_mode) { 3299 drm_dp_cec_unset_edid( 3300 &aconnector->dm_dp_aux.aux); 3301 } 3302 } else { 3303 aconnector->edid = 3304 (struct edid *)sink->dc_edid.raw_edid; 3305 3306 if (aconnector->dc_link->aux_mode) 3307 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3308 aconnector->edid); 3309 } 3310 3311 if (!aconnector->timing_requested) { 3312 aconnector->timing_requested = 3313 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3314 if (!aconnector->timing_requested) 3315 drm_err(dev, 3316 "failed to create aconnector->requested_timing\n"); 3317 } 3318 3319 drm_connector_update_edid_property(connector, aconnector->edid); 3320 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3321 update_connector_ext_caps(aconnector); 3322 } else { 3323 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3324 amdgpu_dm_update_freesync_caps(connector, NULL); 3325 drm_connector_update_edid_property(connector, NULL); 3326 aconnector->num_modes = 0; 3327 dc_sink_release(aconnector->dc_sink); 3328 aconnector->dc_sink = NULL; 3329 aconnector->edid = NULL; 3330 kfree(aconnector->timing_requested); 3331 aconnector->timing_requested = NULL; 3332 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3333 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3334 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3335 } 3336 3337 mutex_unlock(&dev->mode_config.mutex); 3338 3339 update_subconnector_property(aconnector); 3340 3341 if (sink) 3342 dc_sink_release(sink); 3343 } 3344 3345 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3346 { 3347 struct drm_connector *connector = &aconnector->base; 3348 struct drm_device *dev = connector->dev; 3349 enum dc_connection_type new_connection_type = dc_connection_none; 3350 struct amdgpu_device *adev = drm_to_adev(dev); 3351 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3352 bool ret = false; 3353 3354 if (adev->dm.disable_hpd_irq) 3355 return; 3356 3357 /* 3358 * In case of failure or MST no need to update connector status or notify the OS 3359 * since (for MST case) MST does this in its own context. 3360 */ 3361 mutex_lock(&aconnector->hpd_lock); 3362 3363 if (adev->dm.hdcp_workqueue) { 3364 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3365 dm_con_state->update_hdcp = true; 3366 } 3367 if (aconnector->fake_enable) 3368 aconnector->fake_enable = false; 3369 3370 aconnector->timing_changed = false; 3371 3372 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3373 DRM_ERROR("KMS: Failed to detect connector\n"); 3374 3375 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3376 emulated_link_detect(aconnector->dc_link); 3377 3378 drm_modeset_lock_all(dev); 3379 dm_restore_drm_connector_state(dev, connector); 3380 drm_modeset_unlock_all(dev); 3381 3382 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3383 drm_kms_helper_connector_hotplug_event(connector); 3384 } else { 3385 mutex_lock(&adev->dm.dc_lock); 3386 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3387 mutex_unlock(&adev->dm.dc_lock); 3388 if (ret) { 3389 amdgpu_dm_update_connector_after_detect(aconnector); 3390 3391 drm_modeset_lock_all(dev); 3392 dm_restore_drm_connector_state(dev, connector); 3393 drm_modeset_unlock_all(dev); 3394 3395 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3396 drm_kms_helper_connector_hotplug_event(connector); 3397 } 3398 } 3399 mutex_unlock(&aconnector->hpd_lock); 3400 3401 } 3402 3403 static void handle_hpd_irq(void *param) 3404 { 3405 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3406 3407 handle_hpd_irq_helper(aconnector); 3408 3409 } 3410 3411 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3412 union hpd_irq_data hpd_irq_data) 3413 { 3414 struct hpd_rx_irq_offload_work *offload_work = 3415 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3416 3417 if (!offload_work) { 3418 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3419 return; 3420 } 3421 3422 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3423 offload_work->data = hpd_irq_data; 3424 offload_work->offload_wq = offload_wq; 3425 3426 queue_work(offload_wq->wq, &offload_work->work); 3427 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3428 } 3429 3430 static void handle_hpd_rx_irq(void *param) 3431 { 3432 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3433 struct drm_connector *connector = &aconnector->base; 3434 struct drm_device *dev = connector->dev; 3435 struct dc_link *dc_link = aconnector->dc_link; 3436 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3437 bool result = false; 3438 enum dc_connection_type new_connection_type = dc_connection_none; 3439 struct amdgpu_device *adev = drm_to_adev(dev); 3440 union hpd_irq_data hpd_irq_data; 3441 bool link_loss = false; 3442 bool has_left_work = false; 3443 int idx = dc_link->link_index; 3444 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3445 3446 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3447 3448 if (adev->dm.disable_hpd_irq) 3449 return; 3450 3451 /* 3452 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3453 * conflict, after implement i2c helper, this mutex should be 3454 * retired. 3455 */ 3456 mutex_lock(&aconnector->hpd_lock); 3457 3458 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3459 &link_loss, true, &has_left_work); 3460 3461 if (!has_left_work) 3462 goto out; 3463 3464 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3465 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3466 goto out; 3467 } 3468 3469 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3470 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3471 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3472 bool skip = false; 3473 3474 /* 3475 * DOWN_REP_MSG_RDY is also handled by polling method 3476 * mgr->cbs->poll_hpd_irq() 3477 */ 3478 spin_lock(&offload_wq->offload_lock); 3479 skip = offload_wq->is_handling_mst_msg_rdy_event; 3480 3481 if (!skip) 3482 offload_wq->is_handling_mst_msg_rdy_event = true; 3483 3484 spin_unlock(&offload_wq->offload_lock); 3485 3486 if (!skip) 3487 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3488 3489 goto out; 3490 } 3491 3492 if (link_loss) { 3493 bool skip = false; 3494 3495 spin_lock(&offload_wq->offload_lock); 3496 skip = offload_wq->is_handling_link_loss; 3497 3498 if (!skip) 3499 offload_wq->is_handling_link_loss = true; 3500 3501 spin_unlock(&offload_wq->offload_lock); 3502 3503 if (!skip) 3504 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3505 3506 goto out; 3507 } 3508 } 3509 3510 out: 3511 if (result && !is_mst_root_connector) { 3512 /* Downstream Port status changed. */ 3513 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3514 DRM_ERROR("KMS: Failed to detect connector\n"); 3515 3516 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3517 emulated_link_detect(dc_link); 3518 3519 if (aconnector->fake_enable) 3520 aconnector->fake_enable = false; 3521 3522 amdgpu_dm_update_connector_after_detect(aconnector); 3523 3524 3525 drm_modeset_lock_all(dev); 3526 dm_restore_drm_connector_state(dev, connector); 3527 drm_modeset_unlock_all(dev); 3528 3529 drm_kms_helper_connector_hotplug_event(connector); 3530 } else { 3531 bool ret = false; 3532 3533 mutex_lock(&adev->dm.dc_lock); 3534 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3535 mutex_unlock(&adev->dm.dc_lock); 3536 3537 if (ret) { 3538 if (aconnector->fake_enable) 3539 aconnector->fake_enable = false; 3540 3541 amdgpu_dm_update_connector_after_detect(aconnector); 3542 3543 drm_modeset_lock_all(dev); 3544 dm_restore_drm_connector_state(dev, connector); 3545 drm_modeset_unlock_all(dev); 3546 3547 drm_kms_helper_connector_hotplug_event(connector); 3548 } 3549 } 3550 } 3551 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3552 if (adev->dm.hdcp_workqueue) 3553 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3554 } 3555 3556 if (dc_link->type != dc_connection_mst_branch) 3557 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3558 3559 mutex_unlock(&aconnector->hpd_lock); 3560 } 3561 3562 static void register_hpd_handlers(struct amdgpu_device *adev) 3563 { 3564 struct drm_device *dev = adev_to_drm(adev); 3565 struct drm_connector *connector; 3566 struct amdgpu_dm_connector *aconnector; 3567 const struct dc_link *dc_link; 3568 struct dc_interrupt_params int_params = {0}; 3569 3570 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3571 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3572 3573 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3574 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) 3575 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3576 3577 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) 3578 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3579 } 3580 3581 list_for_each_entry(connector, 3582 &dev->mode_config.connector_list, head) { 3583 3584 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3585 continue; 3586 3587 aconnector = to_amdgpu_dm_connector(connector); 3588 dc_link = aconnector->dc_link; 3589 3590 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3591 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3592 int_params.irq_source = dc_link->irq_source_hpd; 3593 3594 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3595 handle_hpd_irq, 3596 (void *) aconnector); 3597 } 3598 3599 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3600 3601 /* Also register for DP short pulse (hpd_rx). */ 3602 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3603 int_params.irq_source = dc_link->irq_source_hpd_rx; 3604 3605 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3606 handle_hpd_rx_irq, 3607 (void *) aconnector); 3608 } 3609 } 3610 } 3611 3612 #if defined(CONFIG_DRM_AMD_DC_SI) 3613 /* Register IRQ sources and initialize IRQ callbacks */ 3614 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3615 { 3616 struct dc *dc = adev->dm.dc; 3617 struct common_irq_params *c_irq_params; 3618 struct dc_interrupt_params int_params = {0}; 3619 int r; 3620 int i; 3621 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3622 3623 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3624 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3625 3626 /* 3627 * Actions of amdgpu_irq_add_id(): 3628 * 1. Register a set() function with base driver. 3629 * Base driver will call set() function to enable/disable an 3630 * interrupt in DC hardware. 3631 * 2. Register amdgpu_dm_irq_handler(). 3632 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3633 * coming from DC hardware. 3634 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3635 * for acknowledging and handling. 3636 */ 3637 3638 /* Use VBLANK interrupt */ 3639 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3640 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3641 if (r) { 3642 DRM_ERROR("Failed to add crtc irq id!\n"); 3643 return r; 3644 } 3645 3646 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3647 int_params.irq_source = 3648 dc_interrupt_to_irq_source(dc, i + 1, 0); 3649 3650 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3651 3652 c_irq_params->adev = adev; 3653 c_irq_params->irq_src = int_params.irq_source; 3654 3655 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3656 dm_crtc_high_irq, c_irq_params); 3657 } 3658 3659 /* Use GRPH_PFLIP interrupt */ 3660 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3661 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3662 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3663 if (r) { 3664 DRM_ERROR("Failed to add page flip irq id!\n"); 3665 return r; 3666 } 3667 3668 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3669 int_params.irq_source = 3670 dc_interrupt_to_irq_source(dc, i, 0); 3671 3672 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3673 3674 c_irq_params->adev = adev; 3675 c_irq_params->irq_src = int_params.irq_source; 3676 3677 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3678 dm_pflip_high_irq, c_irq_params); 3679 3680 } 3681 3682 /* HPD */ 3683 r = amdgpu_irq_add_id(adev, client_id, 3684 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3685 if (r) { 3686 DRM_ERROR("Failed to add hpd irq id!\n"); 3687 return r; 3688 } 3689 3690 register_hpd_handlers(adev); 3691 3692 return 0; 3693 } 3694 #endif 3695 3696 /* Register IRQ sources and initialize IRQ callbacks */ 3697 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3698 { 3699 struct dc *dc = adev->dm.dc; 3700 struct common_irq_params *c_irq_params; 3701 struct dc_interrupt_params int_params = {0}; 3702 int r; 3703 int i; 3704 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3705 3706 if (adev->family >= AMDGPU_FAMILY_AI) 3707 client_id = SOC15_IH_CLIENTID_DCE; 3708 3709 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3710 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3711 3712 /* 3713 * Actions of amdgpu_irq_add_id(): 3714 * 1. Register a set() function with base driver. 3715 * Base driver will call set() function to enable/disable an 3716 * interrupt in DC hardware. 3717 * 2. Register amdgpu_dm_irq_handler(). 3718 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3719 * coming from DC hardware. 3720 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3721 * for acknowledging and handling. 3722 */ 3723 3724 /* Use VBLANK interrupt */ 3725 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3726 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3727 if (r) { 3728 DRM_ERROR("Failed to add crtc irq id!\n"); 3729 return r; 3730 } 3731 3732 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3733 int_params.irq_source = 3734 dc_interrupt_to_irq_source(dc, i, 0); 3735 3736 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3737 3738 c_irq_params->adev = adev; 3739 c_irq_params->irq_src = int_params.irq_source; 3740 3741 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3742 dm_crtc_high_irq, c_irq_params); 3743 } 3744 3745 /* Use VUPDATE interrupt */ 3746 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3747 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3748 if (r) { 3749 DRM_ERROR("Failed to add vupdate irq id!\n"); 3750 return r; 3751 } 3752 3753 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3754 int_params.irq_source = 3755 dc_interrupt_to_irq_source(dc, i, 0); 3756 3757 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3758 3759 c_irq_params->adev = adev; 3760 c_irq_params->irq_src = int_params.irq_source; 3761 3762 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3763 dm_vupdate_high_irq, c_irq_params); 3764 } 3765 3766 /* Use GRPH_PFLIP interrupt */ 3767 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3768 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3769 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3770 if (r) { 3771 DRM_ERROR("Failed to add page flip irq id!\n"); 3772 return r; 3773 } 3774 3775 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3776 int_params.irq_source = 3777 dc_interrupt_to_irq_source(dc, i, 0); 3778 3779 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3780 3781 c_irq_params->adev = adev; 3782 c_irq_params->irq_src = int_params.irq_source; 3783 3784 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3785 dm_pflip_high_irq, c_irq_params); 3786 3787 } 3788 3789 /* HPD */ 3790 r = amdgpu_irq_add_id(adev, client_id, 3791 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3792 if (r) { 3793 DRM_ERROR("Failed to add hpd irq id!\n"); 3794 return r; 3795 } 3796 3797 register_hpd_handlers(adev); 3798 3799 return 0; 3800 } 3801 3802 /* Register IRQ sources and initialize IRQ callbacks */ 3803 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 3804 { 3805 struct dc *dc = adev->dm.dc; 3806 struct common_irq_params *c_irq_params; 3807 struct dc_interrupt_params int_params = {0}; 3808 int r; 3809 int i; 3810 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3811 static const unsigned int vrtl_int_srcid[] = { 3812 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 3813 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 3814 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 3815 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 3816 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 3817 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 3818 }; 3819 #endif 3820 3821 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3822 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3823 3824 /* 3825 * Actions of amdgpu_irq_add_id(): 3826 * 1. Register a set() function with base driver. 3827 * Base driver will call set() function to enable/disable an 3828 * interrupt in DC hardware. 3829 * 2. Register amdgpu_dm_irq_handler(). 3830 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3831 * coming from DC hardware. 3832 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3833 * for acknowledging and handling. 3834 */ 3835 3836 /* Use VSTARTUP interrupt */ 3837 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 3838 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 3839 i++) { 3840 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 3841 3842 if (r) { 3843 DRM_ERROR("Failed to add crtc irq id!\n"); 3844 return r; 3845 } 3846 3847 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3848 int_params.irq_source = 3849 dc_interrupt_to_irq_source(dc, i, 0); 3850 3851 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3852 3853 c_irq_params->adev = adev; 3854 c_irq_params->irq_src = int_params.irq_source; 3855 3856 amdgpu_dm_irq_register_interrupt( 3857 adev, &int_params, dm_crtc_high_irq, c_irq_params); 3858 } 3859 3860 /* Use otg vertical line interrupt */ 3861 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3862 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 3863 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 3864 vrtl_int_srcid[i], &adev->vline0_irq); 3865 3866 if (r) { 3867 DRM_ERROR("Failed to add vline0 irq id!\n"); 3868 return r; 3869 } 3870 3871 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3872 int_params.irq_source = 3873 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 3874 3875 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { 3876 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]); 3877 break; 3878 } 3879 3880 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 3881 - DC_IRQ_SOURCE_DC1_VLINE0]; 3882 3883 c_irq_params->adev = adev; 3884 c_irq_params->irq_src = int_params.irq_source; 3885 3886 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3887 dm_dcn_vertical_interrupt0_high_irq, c_irq_params); 3888 } 3889 #endif 3890 3891 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 3892 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 3893 * to trigger at end of each vblank, regardless of state of the lock, 3894 * matching DCE behaviour. 3895 */ 3896 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 3897 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 3898 i++) { 3899 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 3900 3901 if (r) { 3902 DRM_ERROR("Failed to add vupdate irq id!\n"); 3903 return r; 3904 } 3905 3906 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3907 int_params.irq_source = 3908 dc_interrupt_to_irq_source(dc, i, 0); 3909 3910 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3911 3912 c_irq_params->adev = adev; 3913 c_irq_params->irq_src = int_params.irq_source; 3914 3915 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3916 dm_vupdate_high_irq, c_irq_params); 3917 } 3918 3919 /* Use GRPH_PFLIP interrupt */ 3920 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 3921 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 3922 i++) { 3923 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 3924 if (r) { 3925 DRM_ERROR("Failed to add page flip irq id!\n"); 3926 return r; 3927 } 3928 3929 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3930 int_params.irq_source = 3931 dc_interrupt_to_irq_source(dc, i, 0); 3932 3933 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3934 3935 c_irq_params->adev = adev; 3936 c_irq_params->irq_src = int_params.irq_source; 3937 3938 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3939 dm_pflip_high_irq, c_irq_params); 3940 3941 } 3942 3943 /* HPD */ 3944 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 3945 &adev->hpd_irq); 3946 if (r) { 3947 DRM_ERROR("Failed to add hpd irq id!\n"); 3948 return r; 3949 } 3950 3951 register_hpd_handlers(adev); 3952 3953 return 0; 3954 } 3955 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 3956 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 3957 { 3958 struct dc *dc = adev->dm.dc; 3959 struct common_irq_params *c_irq_params; 3960 struct dc_interrupt_params int_params = {0}; 3961 int r, i; 3962 3963 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3964 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3965 3966 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 3967 &adev->dmub_outbox_irq); 3968 if (r) { 3969 DRM_ERROR("Failed to add outbox irq id!\n"); 3970 return r; 3971 } 3972 3973 if (dc->ctx->dmub_srv) { 3974 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 3975 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3976 int_params.irq_source = 3977 dc_interrupt_to_irq_source(dc, i, 0); 3978 3979 c_irq_params = &adev->dm.dmub_outbox_params[0]; 3980 3981 c_irq_params->adev = adev; 3982 c_irq_params->irq_src = int_params.irq_source; 3983 3984 amdgpu_dm_irq_register_interrupt(adev, &int_params, 3985 dm_dmub_outbox1_low_irq, c_irq_params); 3986 } 3987 3988 return 0; 3989 } 3990 3991 /* 3992 * Acquires the lock for the atomic state object and returns 3993 * the new atomic state. 3994 * 3995 * This should only be called during atomic check. 3996 */ 3997 int dm_atomic_get_state(struct drm_atomic_state *state, 3998 struct dm_atomic_state **dm_state) 3999 { 4000 struct drm_device *dev = state->dev; 4001 struct amdgpu_device *adev = drm_to_adev(dev); 4002 struct amdgpu_display_manager *dm = &adev->dm; 4003 struct drm_private_state *priv_state; 4004 4005 if (*dm_state) 4006 return 0; 4007 4008 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 4009 if (IS_ERR(priv_state)) 4010 return PTR_ERR(priv_state); 4011 4012 *dm_state = to_dm_atomic_state(priv_state); 4013 4014 return 0; 4015 } 4016 4017 static struct dm_atomic_state * 4018 dm_atomic_get_new_state(struct drm_atomic_state *state) 4019 { 4020 struct drm_device *dev = state->dev; 4021 struct amdgpu_device *adev = drm_to_adev(dev); 4022 struct amdgpu_display_manager *dm = &adev->dm; 4023 struct drm_private_obj *obj; 4024 struct drm_private_state *new_obj_state; 4025 int i; 4026 4027 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 4028 if (obj->funcs == dm->atomic_obj.funcs) 4029 return to_dm_atomic_state(new_obj_state); 4030 } 4031 4032 return NULL; 4033 } 4034 4035 static struct drm_private_state * 4036 dm_atomic_duplicate_state(struct drm_private_obj *obj) 4037 { 4038 struct dm_atomic_state *old_state, *new_state; 4039 4040 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 4041 if (!new_state) 4042 return NULL; 4043 4044 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 4045 4046 old_state = to_dm_atomic_state(obj->state); 4047 4048 if (old_state && old_state->context) 4049 new_state->context = dc_state_create_copy(old_state->context); 4050 4051 if (!new_state->context) { 4052 kfree(new_state); 4053 return NULL; 4054 } 4055 4056 return &new_state->base; 4057 } 4058 4059 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 4060 struct drm_private_state *state) 4061 { 4062 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4063 4064 if (dm_state && dm_state->context) 4065 dc_state_release(dm_state->context); 4066 4067 kfree(dm_state); 4068 } 4069 4070 static struct drm_private_state_funcs dm_atomic_state_funcs = { 4071 .atomic_duplicate_state = dm_atomic_duplicate_state, 4072 .atomic_destroy_state = dm_atomic_destroy_state, 4073 }; 4074 4075 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 4076 { 4077 struct dm_atomic_state *state; 4078 int r; 4079 4080 adev->mode_info.mode_config_initialized = true; 4081 4082 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 4083 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 4084 4085 adev_to_drm(adev)->mode_config.max_width = 16384; 4086 adev_to_drm(adev)->mode_config.max_height = 16384; 4087 4088 adev_to_drm(adev)->mode_config.preferred_depth = 24; 4089 if (adev->asic_type == CHIP_HAWAII) 4090 /* disable prefer shadow for now due to hibernation issues */ 4091 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 4092 else 4093 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 4094 /* indicates support for immediate flip */ 4095 adev_to_drm(adev)->mode_config.async_page_flip = true; 4096 4097 state = kzalloc(sizeof(*state), GFP_KERNEL); 4098 if (!state) 4099 return -ENOMEM; 4100 4101 state->context = dc_state_create_current_copy(adev->dm.dc); 4102 if (!state->context) { 4103 kfree(state); 4104 return -ENOMEM; 4105 } 4106 4107 drm_atomic_private_obj_init(adev_to_drm(adev), 4108 &adev->dm.atomic_obj, 4109 &state->base, 4110 &dm_atomic_state_funcs); 4111 4112 r = amdgpu_display_modeset_create_props(adev); 4113 if (r) { 4114 dc_state_release(state->context); 4115 kfree(state); 4116 return r; 4117 } 4118 4119 #ifdef AMD_PRIVATE_COLOR 4120 if (amdgpu_dm_create_color_properties(adev)) 4121 return -ENOMEM; 4122 #endif 4123 4124 r = amdgpu_dm_audio_init(adev); 4125 if (r) { 4126 dc_state_release(state->context); 4127 kfree(state); 4128 return r; 4129 } 4130 4131 return 0; 4132 } 4133 4134 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4135 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4136 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4137 4138 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4139 int bl_idx) 4140 { 4141 #if defined(CONFIG_ACPI) 4142 struct amdgpu_dm_backlight_caps caps; 4143 4144 memset(&caps, 0, sizeof(caps)); 4145 4146 if (dm->backlight_caps[bl_idx].caps_valid) 4147 return; 4148 4149 amdgpu_acpi_get_backlight_caps(&caps); 4150 if (caps.caps_valid) { 4151 dm->backlight_caps[bl_idx].caps_valid = true; 4152 if (caps.aux_support) 4153 return; 4154 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4155 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4156 } else { 4157 dm->backlight_caps[bl_idx].min_input_signal = 4158 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4159 dm->backlight_caps[bl_idx].max_input_signal = 4160 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4161 } 4162 #else 4163 if (dm->backlight_caps[bl_idx].aux_support) 4164 return; 4165 4166 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4167 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4168 #endif 4169 } 4170 4171 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4172 unsigned int *min, unsigned int *max) 4173 { 4174 if (!caps) 4175 return 0; 4176 4177 if (caps->aux_support) { 4178 // Firmware limits are in nits, DC API wants millinits. 4179 *max = 1000 * caps->aux_max_input_signal; 4180 *min = 1000 * caps->aux_min_input_signal; 4181 } else { 4182 // Firmware limits are 8-bit, PWM control is 16-bit. 4183 *max = 0x101 * caps->max_input_signal; 4184 *min = 0x101 * caps->min_input_signal; 4185 } 4186 return 1; 4187 } 4188 4189 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4190 uint32_t brightness) 4191 { 4192 unsigned int min, max; 4193 4194 if (!get_brightness_range(caps, &min, &max)) 4195 return brightness; 4196 4197 // Rescale 0..255 to min..max 4198 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4199 AMDGPU_MAX_BL_LEVEL); 4200 } 4201 4202 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4203 uint32_t brightness) 4204 { 4205 unsigned int min, max; 4206 4207 if (!get_brightness_range(caps, &min, &max)) 4208 return brightness; 4209 4210 if (brightness < min) 4211 return 0; 4212 // Rescale min..max to 0..255 4213 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4214 max - min); 4215 } 4216 4217 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4218 int bl_idx, 4219 u32 user_brightness) 4220 { 4221 struct amdgpu_dm_backlight_caps caps; 4222 struct dc_link *link; 4223 u32 brightness; 4224 bool rc; 4225 4226 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4227 caps = dm->backlight_caps[bl_idx]; 4228 4229 dm->brightness[bl_idx] = user_brightness; 4230 /* update scratch register */ 4231 if (bl_idx == 0) 4232 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4233 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4234 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4235 4236 /* Change brightness based on AUX property */ 4237 if (caps.aux_support) { 4238 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4239 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4240 if (!rc) 4241 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4242 } else { 4243 rc = dc_link_set_backlight_level(link, brightness, 0); 4244 if (!rc) 4245 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4246 } 4247 4248 if (rc) 4249 dm->actual_brightness[bl_idx] = user_brightness; 4250 } 4251 4252 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4253 { 4254 struct amdgpu_display_manager *dm = bl_get_data(bd); 4255 int i; 4256 4257 for (i = 0; i < dm->num_of_edps; i++) { 4258 if (bd == dm->backlight_dev[i]) 4259 break; 4260 } 4261 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4262 i = 0; 4263 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4264 4265 return 0; 4266 } 4267 4268 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4269 int bl_idx) 4270 { 4271 int ret; 4272 struct amdgpu_dm_backlight_caps caps; 4273 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4274 4275 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4276 caps = dm->backlight_caps[bl_idx]; 4277 4278 if (caps.aux_support) { 4279 u32 avg, peak; 4280 bool rc; 4281 4282 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4283 if (!rc) 4284 return dm->brightness[bl_idx]; 4285 return convert_brightness_to_user(&caps, avg); 4286 } 4287 4288 ret = dc_link_get_backlight_level(link); 4289 4290 if (ret == DC_ERROR_UNEXPECTED) 4291 return dm->brightness[bl_idx]; 4292 4293 return convert_brightness_to_user(&caps, ret); 4294 } 4295 4296 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4297 { 4298 struct amdgpu_display_manager *dm = bl_get_data(bd); 4299 int i; 4300 4301 for (i = 0; i < dm->num_of_edps; i++) { 4302 if (bd == dm->backlight_dev[i]) 4303 break; 4304 } 4305 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4306 i = 0; 4307 return amdgpu_dm_backlight_get_level(dm, i); 4308 } 4309 4310 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4311 .options = BL_CORE_SUSPENDRESUME, 4312 .get_brightness = amdgpu_dm_backlight_get_brightness, 4313 .update_status = amdgpu_dm_backlight_update_status, 4314 }; 4315 4316 static void 4317 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4318 { 4319 struct drm_device *drm = aconnector->base.dev; 4320 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4321 struct backlight_properties props = { 0 }; 4322 char bl_name[16]; 4323 4324 if (aconnector->bl_idx == -1) 4325 return; 4326 4327 if (!acpi_video_backlight_use_native()) { 4328 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4329 /* Try registering an ACPI video backlight device instead. */ 4330 acpi_video_register_backlight(); 4331 return; 4332 } 4333 4334 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4335 props.brightness = AMDGPU_MAX_BL_LEVEL; 4336 props.type = BACKLIGHT_RAW; 4337 4338 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4339 drm->primary->index + aconnector->bl_idx); 4340 4341 dm->backlight_dev[aconnector->bl_idx] = 4342 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4343 &amdgpu_dm_backlight_ops, &props); 4344 4345 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4346 DRM_ERROR("DM: Backlight registration failed!\n"); 4347 dm->backlight_dev[aconnector->bl_idx] = NULL; 4348 } else 4349 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4350 } 4351 4352 static int initialize_plane(struct amdgpu_display_manager *dm, 4353 struct amdgpu_mode_info *mode_info, int plane_id, 4354 enum drm_plane_type plane_type, 4355 const struct dc_plane_cap *plane_cap) 4356 { 4357 struct drm_plane *plane; 4358 unsigned long possible_crtcs; 4359 int ret = 0; 4360 4361 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4362 if (!plane) { 4363 DRM_ERROR("KMS: Failed to allocate plane\n"); 4364 return -ENOMEM; 4365 } 4366 plane->type = plane_type; 4367 4368 /* 4369 * HACK: IGT tests expect that the primary plane for a CRTC 4370 * can only have one possible CRTC. Only expose support for 4371 * any CRTC if they're not going to be used as a primary plane 4372 * for a CRTC - like overlay or underlay planes. 4373 */ 4374 possible_crtcs = 1 << plane_id; 4375 if (plane_id >= dm->dc->caps.max_streams) 4376 possible_crtcs = 0xff; 4377 4378 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4379 4380 if (ret) { 4381 DRM_ERROR("KMS: Failed to initialize plane\n"); 4382 kfree(plane); 4383 return ret; 4384 } 4385 4386 if (mode_info) 4387 mode_info->planes[plane_id] = plane; 4388 4389 return ret; 4390 } 4391 4392 4393 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4394 struct amdgpu_dm_connector *aconnector) 4395 { 4396 struct dc_link *link = aconnector->dc_link; 4397 int bl_idx = dm->num_of_edps; 4398 4399 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4400 link->type == dc_connection_none) 4401 return; 4402 4403 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4404 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4405 return; 4406 } 4407 4408 aconnector->bl_idx = bl_idx; 4409 4410 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4411 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4412 dm->backlight_link[bl_idx] = link; 4413 dm->num_of_edps++; 4414 4415 update_connector_ext_caps(aconnector); 4416 } 4417 4418 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4419 4420 /* 4421 * In this architecture, the association 4422 * connector -> encoder -> crtc 4423 * id not really requried. The crtc and connector will hold the 4424 * display_index as an abstraction to use with DAL component 4425 * 4426 * Returns 0 on success 4427 */ 4428 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4429 { 4430 struct amdgpu_display_manager *dm = &adev->dm; 4431 s32 i; 4432 struct amdgpu_dm_connector *aconnector = NULL; 4433 struct amdgpu_encoder *aencoder = NULL; 4434 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4435 u32 link_cnt; 4436 s32 primary_planes; 4437 enum dc_connection_type new_connection_type = dc_connection_none; 4438 const struct dc_plane_cap *plane; 4439 bool psr_feature_enabled = false; 4440 bool replay_feature_enabled = false; 4441 int max_overlay = dm->dc->caps.max_slave_planes; 4442 4443 dm->display_indexes_num = dm->dc->caps.max_streams; 4444 /* Update the actual used number of crtc */ 4445 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4446 4447 amdgpu_dm_set_irq_funcs(adev); 4448 4449 link_cnt = dm->dc->caps.max_links; 4450 if (amdgpu_dm_mode_config_init(dm->adev)) { 4451 DRM_ERROR("DM: Failed to initialize mode config\n"); 4452 return -EINVAL; 4453 } 4454 4455 /* There is one primary plane per CRTC */ 4456 primary_planes = dm->dc->caps.max_streams; 4457 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 4458 4459 /* 4460 * Initialize primary planes, implicit planes for legacy IOCTLS. 4461 * Order is reversed to match iteration order in atomic check. 4462 */ 4463 for (i = (primary_planes - 1); i >= 0; i--) { 4464 plane = &dm->dc->caps.planes[i]; 4465 4466 if (initialize_plane(dm, mode_info, i, 4467 DRM_PLANE_TYPE_PRIMARY, plane)) { 4468 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4469 goto fail; 4470 } 4471 } 4472 4473 /* 4474 * Initialize overlay planes, index starting after primary planes. 4475 * These planes have a higher DRM index than the primary planes since 4476 * they should be considered as having a higher z-order. 4477 * Order is reversed to match iteration order in atomic check. 4478 * 4479 * Only support DCN for now, and only expose one so we don't encourage 4480 * userspace to use up all the pipes. 4481 */ 4482 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4483 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4484 4485 /* Do not create overlay if MPO disabled */ 4486 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4487 break; 4488 4489 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4490 continue; 4491 4492 if (!plane->pixel_format_support.argb8888) 4493 continue; 4494 4495 if (max_overlay-- == 0) 4496 break; 4497 4498 if (initialize_plane(dm, NULL, primary_planes + i, 4499 DRM_PLANE_TYPE_OVERLAY, plane)) { 4500 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4501 goto fail; 4502 } 4503 } 4504 4505 for (i = 0; i < dm->dc->caps.max_streams; i++) 4506 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4507 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4508 goto fail; 4509 } 4510 4511 /* Use Outbox interrupt */ 4512 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4513 case IP_VERSION(3, 0, 0): 4514 case IP_VERSION(3, 1, 2): 4515 case IP_VERSION(3, 1, 3): 4516 case IP_VERSION(3, 1, 4): 4517 case IP_VERSION(3, 1, 5): 4518 case IP_VERSION(3, 1, 6): 4519 case IP_VERSION(3, 2, 0): 4520 case IP_VERSION(3, 2, 1): 4521 case IP_VERSION(2, 1, 0): 4522 case IP_VERSION(3, 5, 0): 4523 case IP_VERSION(3, 5, 1): 4524 if (register_outbox_irq_handlers(dm->adev)) { 4525 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4526 goto fail; 4527 } 4528 break; 4529 default: 4530 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4531 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4532 } 4533 4534 /* Determine whether to enable PSR support by default. */ 4535 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4536 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4537 case IP_VERSION(3, 1, 2): 4538 case IP_VERSION(3, 1, 3): 4539 case IP_VERSION(3, 1, 4): 4540 case IP_VERSION(3, 1, 5): 4541 case IP_VERSION(3, 1, 6): 4542 case IP_VERSION(3, 2, 0): 4543 case IP_VERSION(3, 2, 1): 4544 case IP_VERSION(3, 5, 0): 4545 case IP_VERSION(3, 5, 1): 4546 psr_feature_enabled = true; 4547 break; 4548 default: 4549 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4550 break; 4551 } 4552 } 4553 4554 /* Determine whether to enable Replay support by default. */ 4555 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 4556 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4557 case IP_VERSION(3, 1, 4): 4558 case IP_VERSION(3, 1, 5): 4559 case IP_VERSION(3, 1, 6): 4560 case IP_VERSION(3, 2, 0): 4561 case IP_VERSION(3, 2, 1): 4562 case IP_VERSION(3, 5, 0): 4563 case IP_VERSION(3, 5, 1): 4564 replay_feature_enabled = true; 4565 break; 4566 default: 4567 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 4568 break; 4569 } 4570 } 4571 4572 /* loops over all connectors on the board */ 4573 for (i = 0; i < link_cnt; i++) { 4574 struct dc_link *link = NULL; 4575 4576 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { 4577 DRM_ERROR( 4578 "KMS: Cannot support more than %d display indexes\n", 4579 AMDGPU_DM_MAX_DISPLAY_INDEX); 4580 continue; 4581 } 4582 4583 link = dc_get_link_at_index(dm->dc, i); 4584 4585 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 4586 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); 4587 4588 if (!wbcon) { 4589 DRM_ERROR("KMS: Failed to allocate writeback connector\n"); 4590 continue; 4591 } 4592 4593 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 4594 DRM_ERROR("KMS: Failed to initialize writeback connector\n"); 4595 kfree(wbcon); 4596 continue; 4597 } 4598 4599 link->psr_settings.psr_feature_enabled = false; 4600 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 4601 4602 continue; 4603 } 4604 4605 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4606 if (!aconnector) 4607 goto fail; 4608 4609 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4610 if (!aencoder) 4611 goto fail; 4612 4613 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4614 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4615 goto fail; 4616 } 4617 4618 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4619 DRM_ERROR("KMS: Failed to initialize connector\n"); 4620 goto fail; 4621 } 4622 4623 if (dm->hpd_rx_offload_wq) 4624 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 4625 aconnector; 4626 4627 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4628 DRM_ERROR("KMS: Failed to detect connector\n"); 4629 4630 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4631 emulated_link_detect(link); 4632 amdgpu_dm_update_connector_after_detect(aconnector); 4633 } else { 4634 bool ret = false; 4635 4636 mutex_lock(&dm->dc_lock); 4637 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4638 mutex_unlock(&dm->dc_lock); 4639 4640 if (ret) { 4641 amdgpu_dm_update_connector_after_detect(aconnector); 4642 setup_backlight_device(dm, aconnector); 4643 4644 /* Disable PSR if Replay can be enabled */ 4645 if (replay_feature_enabled) 4646 if (amdgpu_dm_set_replay_caps(link, aconnector)) 4647 psr_feature_enabled = false; 4648 4649 if (psr_feature_enabled) 4650 amdgpu_dm_set_psr_caps(link); 4651 4652 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4653 * PSR is also supported. 4654 */ 4655 if (link->psr_settings.psr_feature_enabled) 4656 adev_to_drm(adev)->vblank_disable_immediate = false; 4657 } 4658 } 4659 amdgpu_set_panel_orientation(&aconnector->base); 4660 } 4661 4662 /* Software is initialized. Now we can register interrupt handlers. */ 4663 switch (adev->asic_type) { 4664 #if defined(CONFIG_DRM_AMD_DC_SI) 4665 case CHIP_TAHITI: 4666 case CHIP_PITCAIRN: 4667 case CHIP_VERDE: 4668 case CHIP_OLAND: 4669 if (dce60_register_irq_handlers(dm->adev)) { 4670 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4671 goto fail; 4672 } 4673 break; 4674 #endif 4675 case CHIP_BONAIRE: 4676 case CHIP_HAWAII: 4677 case CHIP_KAVERI: 4678 case CHIP_KABINI: 4679 case CHIP_MULLINS: 4680 case CHIP_TONGA: 4681 case CHIP_FIJI: 4682 case CHIP_CARRIZO: 4683 case CHIP_STONEY: 4684 case CHIP_POLARIS11: 4685 case CHIP_POLARIS10: 4686 case CHIP_POLARIS12: 4687 case CHIP_VEGAM: 4688 case CHIP_VEGA10: 4689 case CHIP_VEGA12: 4690 case CHIP_VEGA20: 4691 if (dce110_register_irq_handlers(dm->adev)) { 4692 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4693 goto fail; 4694 } 4695 break; 4696 default: 4697 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4698 case IP_VERSION(1, 0, 0): 4699 case IP_VERSION(1, 0, 1): 4700 case IP_VERSION(2, 0, 2): 4701 case IP_VERSION(2, 0, 3): 4702 case IP_VERSION(2, 0, 0): 4703 case IP_VERSION(2, 1, 0): 4704 case IP_VERSION(3, 0, 0): 4705 case IP_VERSION(3, 0, 2): 4706 case IP_VERSION(3, 0, 3): 4707 case IP_VERSION(3, 0, 1): 4708 case IP_VERSION(3, 1, 2): 4709 case IP_VERSION(3, 1, 3): 4710 case IP_VERSION(3, 1, 4): 4711 case IP_VERSION(3, 1, 5): 4712 case IP_VERSION(3, 1, 6): 4713 case IP_VERSION(3, 2, 0): 4714 case IP_VERSION(3, 2, 1): 4715 case IP_VERSION(3, 5, 0): 4716 case IP_VERSION(3, 5, 1): 4717 if (dcn10_register_irq_handlers(dm->adev)) { 4718 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4719 goto fail; 4720 } 4721 break; 4722 default: 4723 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 4724 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4725 goto fail; 4726 } 4727 break; 4728 } 4729 4730 return 0; 4731 fail: 4732 kfree(aencoder); 4733 kfree(aconnector); 4734 4735 return -EINVAL; 4736 } 4737 4738 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 4739 { 4740 drm_atomic_private_obj_fini(&dm->atomic_obj); 4741 } 4742 4743 /****************************************************************************** 4744 * amdgpu_display_funcs functions 4745 *****************************************************************************/ 4746 4747 /* 4748 * dm_bandwidth_update - program display watermarks 4749 * 4750 * @adev: amdgpu_device pointer 4751 * 4752 * Calculate and program the display watermarks and line buffer allocation. 4753 */ 4754 static void dm_bandwidth_update(struct amdgpu_device *adev) 4755 { 4756 /* TODO: implement later */ 4757 } 4758 4759 static const struct amdgpu_display_funcs dm_display_funcs = { 4760 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 4761 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 4762 .backlight_set_level = NULL, /* never called for DC */ 4763 .backlight_get_level = NULL, /* never called for DC */ 4764 .hpd_sense = NULL,/* called unconditionally */ 4765 .hpd_set_polarity = NULL, /* called unconditionally */ 4766 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 4767 .page_flip_get_scanoutpos = 4768 dm_crtc_get_scanoutpos,/* called unconditionally */ 4769 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 4770 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 4771 }; 4772 4773 #if defined(CONFIG_DEBUG_KERNEL_DC) 4774 4775 static ssize_t s3_debug_store(struct device *device, 4776 struct device_attribute *attr, 4777 const char *buf, 4778 size_t count) 4779 { 4780 int ret; 4781 int s3_state; 4782 struct drm_device *drm_dev = dev_get_drvdata(device); 4783 struct amdgpu_device *adev = drm_to_adev(drm_dev); 4784 4785 ret = kstrtoint(buf, 0, &s3_state); 4786 4787 if (ret == 0) { 4788 if (s3_state) { 4789 dm_resume(adev); 4790 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 4791 } else 4792 dm_suspend(adev); 4793 } 4794 4795 return ret == 0 ? count : 0; 4796 } 4797 4798 DEVICE_ATTR_WO(s3_debug); 4799 4800 #endif 4801 4802 static int dm_init_microcode(struct amdgpu_device *adev) 4803 { 4804 char *fw_name_dmub; 4805 int r; 4806 4807 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4808 case IP_VERSION(2, 1, 0): 4809 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 4810 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 4811 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 4812 break; 4813 case IP_VERSION(3, 0, 0): 4814 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 4815 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 4816 else 4817 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 4818 break; 4819 case IP_VERSION(3, 0, 1): 4820 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 4821 break; 4822 case IP_VERSION(3, 0, 2): 4823 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 4824 break; 4825 case IP_VERSION(3, 0, 3): 4826 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 4827 break; 4828 case IP_VERSION(3, 1, 2): 4829 case IP_VERSION(3, 1, 3): 4830 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 4831 break; 4832 case IP_VERSION(3, 1, 4): 4833 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 4834 break; 4835 case IP_VERSION(3, 1, 5): 4836 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 4837 break; 4838 case IP_VERSION(3, 1, 6): 4839 fw_name_dmub = FIRMWARE_DCN316_DMUB; 4840 break; 4841 case IP_VERSION(3, 2, 0): 4842 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 4843 break; 4844 case IP_VERSION(3, 2, 1): 4845 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 4846 break; 4847 case IP_VERSION(3, 5, 0): 4848 fw_name_dmub = FIRMWARE_DCN_35_DMUB; 4849 break; 4850 case IP_VERSION(3, 5, 1): 4851 fw_name_dmub = FIRMWARE_DCN_351_DMUB; 4852 break; 4853 default: 4854 /* ASIC doesn't support DMUB. */ 4855 return 0; 4856 } 4857 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 4858 return r; 4859 } 4860 4861 static int dm_early_init(void *handle) 4862 { 4863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4864 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4865 struct atom_context *ctx = mode_info->atom_context; 4866 int index = GetIndexIntoMasterTable(DATA, Object_Header); 4867 u16 data_offset; 4868 4869 /* if there is no object header, skip DM */ 4870 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 4871 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 4872 dev_info(adev->dev, "No object header, skipping DM\n"); 4873 return -ENOENT; 4874 } 4875 4876 switch (adev->asic_type) { 4877 #if defined(CONFIG_DRM_AMD_DC_SI) 4878 case CHIP_TAHITI: 4879 case CHIP_PITCAIRN: 4880 case CHIP_VERDE: 4881 adev->mode_info.num_crtc = 6; 4882 adev->mode_info.num_hpd = 6; 4883 adev->mode_info.num_dig = 6; 4884 break; 4885 case CHIP_OLAND: 4886 adev->mode_info.num_crtc = 2; 4887 adev->mode_info.num_hpd = 2; 4888 adev->mode_info.num_dig = 2; 4889 break; 4890 #endif 4891 case CHIP_BONAIRE: 4892 case CHIP_HAWAII: 4893 adev->mode_info.num_crtc = 6; 4894 adev->mode_info.num_hpd = 6; 4895 adev->mode_info.num_dig = 6; 4896 break; 4897 case CHIP_KAVERI: 4898 adev->mode_info.num_crtc = 4; 4899 adev->mode_info.num_hpd = 6; 4900 adev->mode_info.num_dig = 7; 4901 break; 4902 case CHIP_KABINI: 4903 case CHIP_MULLINS: 4904 adev->mode_info.num_crtc = 2; 4905 adev->mode_info.num_hpd = 6; 4906 adev->mode_info.num_dig = 6; 4907 break; 4908 case CHIP_FIJI: 4909 case CHIP_TONGA: 4910 adev->mode_info.num_crtc = 6; 4911 adev->mode_info.num_hpd = 6; 4912 adev->mode_info.num_dig = 7; 4913 break; 4914 case CHIP_CARRIZO: 4915 adev->mode_info.num_crtc = 3; 4916 adev->mode_info.num_hpd = 6; 4917 adev->mode_info.num_dig = 9; 4918 break; 4919 case CHIP_STONEY: 4920 adev->mode_info.num_crtc = 2; 4921 adev->mode_info.num_hpd = 6; 4922 adev->mode_info.num_dig = 9; 4923 break; 4924 case CHIP_POLARIS11: 4925 case CHIP_POLARIS12: 4926 adev->mode_info.num_crtc = 5; 4927 adev->mode_info.num_hpd = 5; 4928 adev->mode_info.num_dig = 5; 4929 break; 4930 case CHIP_POLARIS10: 4931 case CHIP_VEGAM: 4932 adev->mode_info.num_crtc = 6; 4933 adev->mode_info.num_hpd = 6; 4934 adev->mode_info.num_dig = 6; 4935 break; 4936 case CHIP_VEGA10: 4937 case CHIP_VEGA12: 4938 case CHIP_VEGA20: 4939 adev->mode_info.num_crtc = 6; 4940 adev->mode_info.num_hpd = 6; 4941 adev->mode_info.num_dig = 6; 4942 break; 4943 default: 4944 4945 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4946 case IP_VERSION(2, 0, 2): 4947 case IP_VERSION(3, 0, 0): 4948 adev->mode_info.num_crtc = 6; 4949 adev->mode_info.num_hpd = 6; 4950 adev->mode_info.num_dig = 6; 4951 break; 4952 case IP_VERSION(2, 0, 0): 4953 case IP_VERSION(3, 0, 2): 4954 adev->mode_info.num_crtc = 5; 4955 adev->mode_info.num_hpd = 5; 4956 adev->mode_info.num_dig = 5; 4957 break; 4958 case IP_VERSION(2, 0, 3): 4959 case IP_VERSION(3, 0, 3): 4960 adev->mode_info.num_crtc = 2; 4961 adev->mode_info.num_hpd = 2; 4962 adev->mode_info.num_dig = 2; 4963 break; 4964 case IP_VERSION(1, 0, 0): 4965 case IP_VERSION(1, 0, 1): 4966 case IP_VERSION(3, 0, 1): 4967 case IP_VERSION(2, 1, 0): 4968 case IP_VERSION(3, 1, 2): 4969 case IP_VERSION(3, 1, 3): 4970 case IP_VERSION(3, 1, 4): 4971 case IP_VERSION(3, 1, 5): 4972 case IP_VERSION(3, 1, 6): 4973 case IP_VERSION(3, 2, 0): 4974 case IP_VERSION(3, 2, 1): 4975 case IP_VERSION(3, 5, 0): 4976 case IP_VERSION(3, 5, 1): 4977 adev->mode_info.num_crtc = 4; 4978 adev->mode_info.num_hpd = 4; 4979 adev->mode_info.num_dig = 4; 4980 break; 4981 default: 4982 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 4983 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4984 return -EINVAL; 4985 } 4986 break; 4987 } 4988 4989 if (adev->mode_info.funcs == NULL) 4990 adev->mode_info.funcs = &dm_display_funcs; 4991 4992 /* 4993 * Note: Do NOT change adev->audio_endpt_rreg and 4994 * adev->audio_endpt_wreg because they are initialised in 4995 * amdgpu_device_init() 4996 */ 4997 #if defined(CONFIG_DEBUG_KERNEL_DC) 4998 device_create_file( 4999 adev_to_drm(adev)->dev, 5000 &dev_attr_s3_debug); 5001 #endif 5002 adev->dc_enabled = true; 5003 5004 return dm_init_microcode(adev); 5005 } 5006 5007 static bool modereset_required(struct drm_crtc_state *crtc_state) 5008 { 5009 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 5010 } 5011 5012 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 5013 { 5014 drm_encoder_cleanup(encoder); 5015 kfree(encoder); 5016 } 5017 5018 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 5019 .destroy = amdgpu_dm_encoder_destroy, 5020 }; 5021 5022 static int 5023 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 5024 const enum surface_pixel_format format, 5025 enum dc_color_space *color_space) 5026 { 5027 bool full_range; 5028 5029 *color_space = COLOR_SPACE_SRGB; 5030 5031 /* DRM color properties only affect non-RGB formats. */ 5032 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 5033 return 0; 5034 5035 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 5036 5037 switch (plane_state->color_encoding) { 5038 case DRM_COLOR_YCBCR_BT601: 5039 if (full_range) 5040 *color_space = COLOR_SPACE_YCBCR601; 5041 else 5042 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 5043 break; 5044 5045 case DRM_COLOR_YCBCR_BT709: 5046 if (full_range) 5047 *color_space = COLOR_SPACE_YCBCR709; 5048 else 5049 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 5050 break; 5051 5052 case DRM_COLOR_YCBCR_BT2020: 5053 if (full_range) 5054 *color_space = COLOR_SPACE_2020_YCBCR; 5055 else 5056 return -EINVAL; 5057 break; 5058 5059 default: 5060 return -EINVAL; 5061 } 5062 5063 return 0; 5064 } 5065 5066 static int 5067 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 5068 const struct drm_plane_state *plane_state, 5069 const u64 tiling_flags, 5070 struct dc_plane_info *plane_info, 5071 struct dc_plane_address *address, 5072 bool tmz_surface, 5073 bool force_disable_dcc) 5074 { 5075 const struct drm_framebuffer *fb = plane_state->fb; 5076 const struct amdgpu_framebuffer *afb = 5077 to_amdgpu_framebuffer(plane_state->fb); 5078 int ret; 5079 5080 memset(plane_info, 0, sizeof(*plane_info)); 5081 5082 switch (fb->format->format) { 5083 case DRM_FORMAT_C8: 5084 plane_info->format = 5085 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 5086 break; 5087 case DRM_FORMAT_RGB565: 5088 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 5089 break; 5090 case DRM_FORMAT_XRGB8888: 5091 case DRM_FORMAT_ARGB8888: 5092 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 5093 break; 5094 case DRM_FORMAT_XRGB2101010: 5095 case DRM_FORMAT_ARGB2101010: 5096 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 5097 break; 5098 case DRM_FORMAT_XBGR2101010: 5099 case DRM_FORMAT_ABGR2101010: 5100 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 5101 break; 5102 case DRM_FORMAT_XBGR8888: 5103 case DRM_FORMAT_ABGR8888: 5104 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 5105 break; 5106 case DRM_FORMAT_NV21: 5107 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 5108 break; 5109 case DRM_FORMAT_NV12: 5110 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 5111 break; 5112 case DRM_FORMAT_P010: 5113 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 5114 break; 5115 case DRM_FORMAT_XRGB16161616F: 5116 case DRM_FORMAT_ARGB16161616F: 5117 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 5118 break; 5119 case DRM_FORMAT_XBGR16161616F: 5120 case DRM_FORMAT_ABGR16161616F: 5121 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 5122 break; 5123 case DRM_FORMAT_XRGB16161616: 5124 case DRM_FORMAT_ARGB16161616: 5125 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 5126 break; 5127 case DRM_FORMAT_XBGR16161616: 5128 case DRM_FORMAT_ABGR16161616: 5129 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 5130 break; 5131 default: 5132 DRM_ERROR( 5133 "Unsupported screen format %p4cc\n", 5134 &fb->format->format); 5135 return -EINVAL; 5136 } 5137 5138 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 5139 case DRM_MODE_ROTATE_0: 5140 plane_info->rotation = ROTATION_ANGLE_0; 5141 break; 5142 case DRM_MODE_ROTATE_90: 5143 plane_info->rotation = ROTATION_ANGLE_90; 5144 break; 5145 case DRM_MODE_ROTATE_180: 5146 plane_info->rotation = ROTATION_ANGLE_180; 5147 break; 5148 case DRM_MODE_ROTATE_270: 5149 plane_info->rotation = ROTATION_ANGLE_270; 5150 break; 5151 default: 5152 plane_info->rotation = ROTATION_ANGLE_0; 5153 break; 5154 } 5155 5156 5157 plane_info->visible = true; 5158 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5159 5160 plane_info->layer_index = plane_state->normalized_zpos; 5161 5162 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5163 &plane_info->color_space); 5164 if (ret) 5165 return ret; 5166 5167 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 5168 plane_info->rotation, tiling_flags, 5169 &plane_info->tiling_info, 5170 &plane_info->plane_size, 5171 &plane_info->dcc, address, 5172 tmz_surface, force_disable_dcc); 5173 if (ret) 5174 return ret; 5175 5176 amdgpu_dm_plane_fill_blending_from_plane_state( 5177 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5178 &plane_info->global_alpha, &plane_info->global_alpha_value); 5179 5180 return 0; 5181 } 5182 5183 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5184 struct dc_plane_state *dc_plane_state, 5185 struct drm_plane_state *plane_state, 5186 struct drm_crtc_state *crtc_state) 5187 { 5188 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5189 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5190 struct dc_scaling_info scaling_info; 5191 struct dc_plane_info plane_info; 5192 int ret; 5193 bool force_disable_dcc = false; 5194 5195 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5196 if (ret) 5197 return ret; 5198 5199 dc_plane_state->src_rect = scaling_info.src_rect; 5200 dc_plane_state->dst_rect = scaling_info.dst_rect; 5201 dc_plane_state->clip_rect = scaling_info.clip_rect; 5202 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5203 5204 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5205 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5206 afb->tiling_flags, 5207 &plane_info, 5208 &dc_plane_state->address, 5209 afb->tmz_surface, 5210 force_disable_dcc); 5211 if (ret) 5212 return ret; 5213 5214 dc_plane_state->format = plane_info.format; 5215 dc_plane_state->color_space = plane_info.color_space; 5216 dc_plane_state->format = plane_info.format; 5217 dc_plane_state->plane_size = plane_info.plane_size; 5218 dc_plane_state->rotation = plane_info.rotation; 5219 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5220 dc_plane_state->stereo_format = plane_info.stereo_format; 5221 dc_plane_state->tiling_info = plane_info.tiling_info; 5222 dc_plane_state->visible = plane_info.visible; 5223 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5224 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5225 dc_plane_state->global_alpha = plane_info.global_alpha; 5226 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5227 dc_plane_state->dcc = plane_info.dcc; 5228 dc_plane_state->layer_index = plane_info.layer_index; 5229 dc_plane_state->flip_int_enabled = true; 5230 5231 /* 5232 * Always set input transfer function, since plane state is refreshed 5233 * every time. 5234 */ 5235 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 5236 plane_state, 5237 dc_plane_state); 5238 if (ret) 5239 return ret; 5240 5241 return 0; 5242 } 5243 5244 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5245 struct rect *dirty_rect, int32_t x, 5246 s32 y, s32 width, s32 height, 5247 int *i, bool ffu) 5248 { 5249 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 5250 5251 dirty_rect->x = x; 5252 dirty_rect->y = y; 5253 dirty_rect->width = width; 5254 dirty_rect->height = height; 5255 5256 if (ffu) 5257 drm_dbg(plane->dev, 5258 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5259 plane->base.id, width, height); 5260 else 5261 drm_dbg(plane->dev, 5262 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5263 plane->base.id, x, y, width, height); 5264 5265 (*i)++; 5266 } 5267 5268 /** 5269 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5270 * 5271 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5272 * remote fb 5273 * @old_plane_state: Old state of @plane 5274 * @new_plane_state: New state of @plane 5275 * @crtc_state: New state of CRTC connected to the @plane 5276 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5277 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 5278 * If PSR SU is enabled and damage clips are available, only the regions of the screen 5279 * that have changed will be updated. If PSR SU is not enabled, 5280 * or if damage clips are not available, the entire screen will be updated. 5281 * @dirty_regions_changed: dirty regions changed 5282 * 5283 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5284 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5285 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5286 * amdgpu_dm's. 5287 * 5288 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5289 * plane with regions that require flushing to the eDP remote buffer. In 5290 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5291 * implicitly provide damage clips without any client support via the plane 5292 * bounds. 5293 */ 5294 static void fill_dc_dirty_rects(struct drm_plane *plane, 5295 struct drm_plane_state *old_plane_state, 5296 struct drm_plane_state *new_plane_state, 5297 struct drm_crtc_state *crtc_state, 5298 struct dc_flip_addrs *flip_addrs, 5299 bool is_psr_su, 5300 bool *dirty_regions_changed) 5301 { 5302 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5303 struct rect *dirty_rects = flip_addrs->dirty_rects; 5304 u32 num_clips; 5305 struct drm_mode_rect *clips; 5306 bool bb_changed; 5307 bool fb_changed; 5308 u32 i = 0; 5309 *dirty_regions_changed = false; 5310 5311 /* 5312 * Cursor plane has it's own dirty rect update interface. See 5313 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5314 */ 5315 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5316 return; 5317 5318 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 5319 goto ffu; 5320 5321 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5322 clips = drm_plane_get_damage_clips(new_plane_state); 5323 5324 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 5325 is_psr_su))) 5326 goto ffu; 5327 5328 if (!dm_crtc_state->mpo_requested) { 5329 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5330 goto ffu; 5331 5332 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5333 fill_dc_dirty_rect(new_plane_state->plane, 5334 &dirty_rects[flip_addrs->dirty_rect_count], 5335 clips->x1, clips->y1, 5336 clips->x2 - clips->x1, clips->y2 - clips->y1, 5337 &flip_addrs->dirty_rect_count, 5338 false); 5339 return; 5340 } 5341 5342 /* 5343 * MPO is requested. Add entire plane bounding box to dirty rects if 5344 * flipped to or damaged. 5345 * 5346 * If plane is moved or resized, also add old bounding box to dirty 5347 * rects. 5348 */ 5349 fb_changed = old_plane_state->fb->base.id != 5350 new_plane_state->fb->base.id; 5351 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5352 old_plane_state->crtc_y != new_plane_state->crtc_y || 5353 old_plane_state->crtc_w != new_plane_state->crtc_w || 5354 old_plane_state->crtc_h != new_plane_state->crtc_h); 5355 5356 drm_dbg(plane->dev, 5357 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5358 new_plane_state->plane->base.id, 5359 bb_changed, fb_changed, num_clips); 5360 5361 *dirty_regions_changed = bb_changed; 5362 5363 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 5364 goto ffu; 5365 5366 if (bb_changed) { 5367 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5368 new_plane_state->crtc_x, 5369 new_plane_state->crtc_y, 5370 new_plane_state->crtc_w, 5371 new_plane_state->crtc_h, &i, false); 5372 5373 /* Add old plane bounding-box if plane is moved or resized */ 5374 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5375 old_plane_state->crtc_x, 5376 old_plane_state->crtc_y, 5377 old_plane_state->crtc_w, 5378 old_plane_state->crtc_h, &i, false); 5379 } 5380 5381 if (num_clips) { 5382 for (; i < num_clips; clips++) 5383 fill_dc_dirty_rect(new_plane_state->plane, 5384 &dirty_rects[i], clips->x1, 5385 clips->y1, clips->x2 - clips->x1, 5386 clips->y2 - clips->y1, &i, false); 5387 } else if (fb_changed && !bb_changed) { 5388 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5389 new_plane_state->crtc_x, 5390 new_plane_state->crtc_y, 5391 new_plane_state->crtc_w, 5392 new_plane_state->crtc_h, &i, false); 5393 } 5394 5395 flip_addrs->dirty_rect_count = i; 5396 return; 5397 5398 ffu: 5399 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5400 dm_crtc_state->base.mode.crtc_hdisplay, 5401 dm_crtc_state->base.mode.crtc_vdisplay, 5402 &flip_addrs->dirty_rect_count, true); 5403 } 5404 5405 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5406 const struct dm_connector_state *dm_state, 5407 struct dc_stream_state *stream) 5408 { 5409 enum amdgpu_rmx_type rmx_type; 5410 5411 struct rect src = { 0 }; /* viewport in composition space*/ 5412 struct rect dst = { 0 }; /* stream addressable area */ 5413 5414 /* no mode. nothing to be done */ 5415 if (!mode) 5416 return; 5417 5418 /* Full screen scaling by default */ 5419 src.width = mode->hdisplay; 5420 src.height = mode->vdisplay; 5421 dst.width = stream->timing.h_addressable; 5422 dst.height = stream->timing.v_addressable; 5423 5424 if (dm_state) { 5425 rmx_type = dm_state->scaling; 5426 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5427 if (src.width * dst.height < 5428 src.height * dst.width) { 5429 /* height needs less upscaling/more downscaling */ 5430 dst.width = src.width * 5431 dst.height / src.height; 5432 } else { 5433 /* width needs less upscaling/more downscaling */ 5434 dst.height = src.height * 5435 dst.width / src.width; 5436 } 5437 } else if (rmx_type == RMX_CENTER) { 5438 dst = src; 5439 } 5440 5441 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5442 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5443 5444 if (dm_state->underscan_enable) { 5445 dst.x += dm_state->underscan_hborder / 2; 5446 dst.y += dm_state->underscan_vborder / 2; 5447 dst.width -= dm_state->underscan_hborder; 5448 dst.height -= dm_state->underscan_vborder; 5449 } 5450 } 5451 5452 stream->src = src; 5453 stream->dst = dst; 5454 5455 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5456 dst.x, dst.y, dst.width, dst.height); 5457 5458 } 5459 5460 static enum dc_color_depth 5461 convert_color_depth_from_display_info(const struct drm_connector *connector, 5462 bool is_y420, int requested_bpc) 5463 { 5464 u8 bpc; 5465 5466 if (is_y420) { 5467 bpc = 8; 5468 5469 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5470 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5471 bpc = 16; 5472 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5473 bpc = 12; 5474 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5475 bpc = 10; 5476 } else { 5477 bpc = (uint8_t)connector->display_info.bpc; 5478 /* Assume 8 bpc by default if no bpc is specified. */ 5479 bpc = bpc ? bpc : 8; 5480 } 5481 5482 if (requested_bpc > 0) { 5483 /* 5484 * Cap display bpc based on the user requested value. 5485 * 5486 * The value for state->max_bpc may not correctly updated 5487 * depending on when the connector gets added to the state 5488 * or if this was called outside of atomic check, so it 5489 * can't be used directly. 5490 */ 5491 bpc = min_t(u8, bpc, requested_bpc); 5492 5493 /* Round down to the nearest even number. */ 5494 bpc = bpc - (bpc & 1); 5495 } 5496 5497 switch (bpc) { 5498 case 0: 5499 /* 5500 * Temporary Work around, DRM doesn't parse color depth for 5501 * EDID revision before 1.4 5502 * TODO: Fix edid parsing 5503 */ 5504 return COLOR_DEPTH_888; 5505 case 6: 5506 return COLOR_DEPTH_666; 5507 case 8: 5508 return COLOR_DEPTH_888; 5509 case 10: 5510 return COLOR_DEPTH_101010; 5511 case 12: 5512 return COLOR_DEPTH_121212; 5513 case 14: 5514 return COLOR_DEPTH_141414; 5515 case 16: 5516 return COLOR_DEPTH_161616; 5517 default: 5518 return COLOR_DEPTH_UNDEFINED; 5519 } 5520 } 5521 5522 static enum dc_aspect_ratio 5523 get_aspect_ratio(const struct drm_display_mode *mode_in) 5524 { 5525 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5526 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5527 } 5528 5529 static enum dc_color_space 5530 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5531 const struct drm_connector_state *connector_state) 5532 { 5533 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5534 5535 switch (connector_state->colorspace) { 5536 case DRM_MODE_COLORIMETRY_BT601_YCC: 5537 if (dc_crtc_timing->flags.Y_ONLY) 5538 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5539 else 5540 color_space = COLOR_SPACE_YCBCR601; 5541 break; 5542 case DRM_MODE_COLORIMETRY_BT709_YCC: 5543 if (dc_crtc_timing->flags.Y_ONLY) 5544 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5545 else 5546 color_space = COLOR_SPACE_YCBCR709; 5547 break; 5548 case DRM_MODE_COLORIMETRY_OPRGB: 5549 color_space = COLOR_SPACE_ADOBERGB; 5550 break; 5551 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5552 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5553 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5554 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5555 else 5556 color_space = COLOR_SPACE_2020_YCBCR; 5557 break; 5558 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5559 default: 5560 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5561 color_space = COLOR_SPACE_SRGB; 5562 /* 5563 * 27030khz is the separation point between HDTV and SDTV 5564 * according to HDMI spec, we use YCbCr709 and YCbCr601 5565 * respectively 5566 */ 5567 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5568 if (dc_crtc_timing->flags.Y_ONLY) 5569 color_space = 5570 COLOR_SPACE_YCBCR709_LIMITED; 5571 else 5572 color_space = COLOR_SPACE_YCBCR709; 5573 } else { 5574 if (dc_crtc_timing->flags.Y_ONLY) 5575 color_space = 5576 COLOR_SPACE_YCBCR601_LIMITED; 5577 else 5578 color_space = COLOR_SPACE_YCBCR601; 5579 } 5580 break; 5581 } 5582 5583 return color_space; 5584 } 5585 5586 static enum display_content_type 5587 get_output_content_type(const struct drm_connector_state *connector_state) 5588 { 5589 switch (connector_state->content_type) { 5590 default: 5591 case DRM_MODE_CONTENT_TYPE_NO_DATA: 5592 return DISPLAY_CONTENT_TYPE_NO_DATA; 5593 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 5594 return DISPLAY_CONTENT_TYPE_GRAPHICS; 5595 case DRM_MODE_CONTENT_TYPE_PHOTO: 5596 return DISPLAY_CONTENT_TYPE_PHOTO; 5597 case DRM_MODE_CONTENT_TYPE_CINEMA: 5598 return DISPLAY_CONTENT_TYPE_CINEMA; 5599 case DRM_MODE_CONTENT_TYPE_GAME: 5600 return DISPLAY_CONTENT_TYPE_GAME; 5601 } 5602 } 5603 5604 static bool adjust_colour_depth_from_display_info( 5605 struct dc_crtc_timing *timing_out, 5606 const struct drm_display_info *info) 5607 { 5608 enum dc_color_depth depth = timing_out->display_color_depth; 5609 int normalized_clk; 5610 5611 do { 5612 normalized_clk = timing_out->pix_clk_100hz / 10; 5613 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5614 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5615 normalized_clk /= 2; 5616 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5617 switch (depth) { 5618 case COLOR_DEPTH_888: 5619 break; 5620 case COLOR_DEPTH_101010: 5621 normalized_clk = (normalized_clk * 30) / 24; 5622 break; 5623 case COLOR_DEPTH_121212: 5624 normalized_clk = (normalized_clk * 36) / 24; 5625 break; 5626 case COLOR_DEPTH_161616: 5627 normalized_clk = (normalized_clk * 48) / 24; 5628 break; 5629 default: 5630 /* The above depths are the only ones valid for HDMI. */ 5631 return false; 5632 } 5633 if (normalized_clk <= info->max_tmds_clock) { 5634 timing_out->display_color_depth = depth; 5635 return true; 5636 } 5637 } while (--depth > COLOR_DEPTH_666); 5638 return false; 5639 } 5640 5641 static void fill_stream_properties_from_drm_display_mode( 5642 struct dc_stream_state *stream, 5643 const struct drm_display_mode *mode_in, 5644 const struct drm_connector *connector, 5645 const struct drm_connector_state *connector_state, 5646 const struct dc_stream_state *old_stream, 5647 int requested_bpc) 5648 { 5649 struct dc_crtc_timing *timing_out = &stream->timing; 5650 const struct drm_display_info *info = &connector->display_info; 5651 struct amdgpu_dm_connector *aconnector = NULL; 5652 struct hdmi_vendor_infoframe hv_frame; 5653 struct hdmi_avi_infoframe avi_frame; 5654 5655 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5656 aconnector = to_amdgpu_dm_connector(connector); 5657 5658 memset(&hv_frame, 0, sizeof(hv_frame)); 5659 memset(&avi_frame, 0, sizeof(avi_frame)); 5660 5661 timing_out->h_border_left = 0; 5662 timing_out->h_border_right = 0; 5663 timing_out->v_border_top = 0; 5664 timing_out->v_border_bottom = 0; 5665 /* TODO: un-hardcode */ 5666 if (drm_mode_is_420_only(info, mode_in) 5667 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5668 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5669 else if (drm_mode_is_420_also(info, mode_in) 5670 && aconnector 5671 && aconnector->force_yuv420_output) 5672 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5673 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5674 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5675 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5676 else 5677 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5678 5679 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5680 timing_out->display_color_depth = convert_color_depth_from_display_info( 5681 connector, 5682 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5683 requested_bpc); 5684 timing_out->scan_type = SCANNING_TYPE_NODATA; 5685 timing_out->hdmi_vic = 0; 5686 5687 if (old_stream) { 5688 timing_out->vic = old_stream->timing.vic; 5689 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5690 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5691 } else { 5692 timing_out->vic = drm_match_cea_mode(mode_in); 5693 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5694 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5695 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5696 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5697 } 5698 5699 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5700 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 5701 timing_out->vic = avi_frame.video_code; 5702 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 5703 timing_out->hdmi_vic = hv_frame.vic; 5704 } 5705 5706 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { 5707 timing_out->h_addressable = mode_in->hdisplay; 5708 timing_out->h_total = mode_in->htotal; 5709 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 5710 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 5711 timing_out->v_total = mode_in->vtotal; 5712 timing_out->v_addressable = mode_in->vdisplay; 5713 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 5714 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 5715 timing_out->pix_clk_100hz = mode_in->clock * 10; 5716 } else { 5717 timing_out->h_addressable = mode_in->crtc_hdisplay; 5718 timing_out->h_total = mode_in->crtc_htotal; 5719 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 5720 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 5721 timing_out->v_total = mode_in->crtc_vtotal; 5722 timing_out->v_addressable = mode_in->crtc_vdisplay; 5723 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 5724 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 5725 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 5726 } 5727 5728 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 5729 5730 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 5731 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 5732 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 5733 if (!adjust_colour_depth_from_display_info(timing_out, info) && 5734 drm_mode_is_420_also(info, mode_in) && 5735 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 5736 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5737 adjust_colour_depth_from_display_info(timing_out, info); 5738 } 5739 } 5740 5741 stream->output_color_space = get_output_color_space(timing_out, connector_state); 5742 stream->content_type = get_output_content_type(connector_state); 5743 } 5744 5745 static void fill_audio_info(struct audio_info *audio_info, 5746 const struct drm_connector *drm_connector, 5747 const struct dc_sink *dc_sink) 5748 { 5749 int i = 0; 5750 int cea_revision = 0; 5751 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 5752 5753 audio_info->manufacture_id = edid_caps->manufacturer_id; 5754 audio_info->product_id = edid_caps->product_id; 5755 5756 cea_revision = drm_connector->display_info.cea_rev; 5757 5758 strscpy(audio_info->display_name, 5759 edid_caps->display_name, 5760 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 5761 5762 if (cea_revision >= 3) { 5763 audio_info->mode_count = edid_caps->audio_mode_count; 5764 5765 for (i = 0; i < audio_info->mode_count; ++i) { 5766 audio_info->modes[i].format_code = 5767 (enum audio_format_code) 5768 (edid_caps->audio_modes[i].format_code); 5769 audio_info->modes[i].channel_count = 5770 edid_caps->audio_modes[i].channel_count; 5771 audio_info->modes[i].sample_rates.all = 5772 edid_caps->audio_modes[i].sample_rate; 5773 audio_info->modes[i].sample_size = 5774 edid_caps->audio_modes[i].sample_size; 5775 } 5776 } 5777 5778 audio_info->flags.all = edid_caps->speaker_flags; 5779 5780 /* TODO: We only check for the progressive mode, check for interlace mode too */ 5781 if (drm_connector->latency_present[0]) { 5782 audio_info->video_latency = drm_connector->video_latency[0]; 5783 audio_info->audio_latency = drm_connector->audio_latency[0]; 5784 } 5785 5786 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 5787 5788 } 5789 5790 static void 5791 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 5792 struct drm_display_mode *dst_mode) 5793 { 5794 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 5795 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 5796 dst_mode->crtc_clock = src_mode->crtc_clock; 5797 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 5798 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 5799 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 5800 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 5801 dst_mode->crtc_htotal = src_mode->crtc_htotal; 5802 dst_mode->crtc_hskew = src_mode->crtc_hskew; 5803 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 5804 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 5805 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 5806 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 5807 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 5808 } 5809 5810 static void 5811 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 5812 const struct drm_display_mode *native_mode, 5813 bool scale_enabled) 5814 { 5815 if (scale_enabled) { 5816 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5817 } else if (native_mode->clock == drm_mode->clock && 5818 native_mode->htotal == drm_mode->htotal && 5819 native_mode->vtotal == drm_mode->vtotal) { 5820 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 5821 } else { 5822 /* no scaling nor amdgpu inserted, no need to patch */ 5823 } 5824 } 5825 5826 static struct dc_sink * 5827 create_fake_sink(struct dc_link *link) 5828 { 5829 struct dc_sink_init_data sink_init_data = { 0 }; 5830 struct dc_sink *sink = NULL; 5831 5832 sink_init_data.link = link; 5833 sink_init_data.sink_signal = link->connector_signal; 5834 5835 sink = dc_sink_create(&sink_init_data); 5836 if (!sink) { 5837 DRM_ERROR("Failed to create sink!\n"); 5838 return NULL; 5839 } 5840 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 5841 5842 return sink; 5843 } 5844 5845 static void set_multisync_trigger_params( 5846 struct dc_stream_state *stream) 5847 { 5848 struct dc_stream_state *master = NULL; 5849 5850 if (stream->triggered_crtc_reset.enabled) { 5851 master = stream->triggered_crtc_reset.event_source; 5852 stream->triggered_crtc_reset.event = 5853 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5854 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5855 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5856 } 5857 } 5858 5859 static void set_master_stream(struct dc_stream_state *stream_set[], 5860 int stream_count) 5861 { 5862 int j, highest_rfr = 0, master_stream = 0; 5863 5864 for (j = 0; j < stream_count; j++) { 5865 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5866 int refresh_rate = 0; 5867 5868 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5869 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5870 if (refresh_rate > highest_rfr) { 5871 highest_rfr = refresh_rate; 5872 master_stream = j; 5873 } 5874 } 5875 } 5876 for (j = 0; j < stream_count; j++) { 5877 if (stream_set[j]) 5878 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5879 } 5880 } 5881 5882 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5883 { 5884 int i = 0; 5885 struct dc_stream_state *stream; 5886 5887 if (context->stream_count < 2) 5888 return; 5889 for (i = 0; i < context->stream_count ; i++) { 5890 if (!context->streams[i]) 5891 continue; 5892 /* 5893 * TODO: add a function to read AMD VSDB bits and set 5894 * crtc_sync_master.multi_sync_enabled flag 5895 * For now it's set to false 5896 */ 5897 } 5898 5899 set_master_stream(context->streams, context->stream_count); 5900 5901 for (i = 0; i < context->stream_count ; i++) { 5902 stream = context->streams[i]; 5903 5904 if (!stream) 5905 continue; 5906 5907 set_multisync_trigger_params(stream); 5908 } 5909 } 5910 5911 /** 5912 * DOC: FreeSync Video 5913 * 5914 * When a userspace application wants to play a video, the content follows a 5915 * standard format definition that usually specifies the FPS for that format. 5916 * The below list illustrates some video format and the expected FPS, 5917 * respectively: 5918 * 5919 * - TV/NTSC (23.976 FPS) 5920 * - Cinema (24 FPS) 5921 * - TV/PAL (25 FPS) 5922 * - TV/NTSC (29.97 FPS) 5923 * - TV/NTSC (30 FPS) 5924 * - Cinema HFR (48 FPS) 5925 * - TV/PAL (50 FPS) 5926 * - Commonly used (60 FPS) 5927 * - Multiples of 24 (48,72,96 FPS) 5928 * 5929 * The list of standards video format is not huge and can be added to the 5930 * connector modeset list beforehand. With that, userspace can leverage 5931 * FreeSync to extends the front porch in order to attain the target refresh 5932 * rate. Such a switch will happen seamlessly, without screen blanking or 5933 * reprogramming of the output in any other way. If the userspace requests a 5934 * modesetting change compatible with FreeSync modes that only differ in the 5935 * refresh rate, DC will skip the full update and avoid blink during the 5936 * transition. For example, the video player can change the modesetting from 5937 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 5938 * causing any display blink. This same concept can be applied to a mode 5939 * setting change. 5940 */ 5941 static struct drm_display_mode * 5942 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 5943 bool use_probed_modes) 5944 { 5945 struct drm_display_mode *m, *m_pref = NULL; 5946 u16 current_refresh, highest_refresh; 5947 struct list_head *list_head = use_probed_modes ? 5948 &aconnector->base.probed_modes : 5949 &aconnector->base.modes; 5950 5951 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5952 return NULL; 5953 5954 if (aconnector->freesync_vid_base.clock != 0) 5955 return &aconnector->freesync_vid_base; 5956 5957 /* Find the preferred mode */ 5958 list_for_each_entry(m, list_head, head) { 5959 if (m->type & DRM_MODE_TYPE_PREFERRED) { 5960 m_pref = m; 5961 break; 5962 } 5963 } 5964 5965 if (!m_pref) { 5966 /* Probably an EDID with no preferred mode. Fallback to first entry */ 5967 m_pref = list_first_entry_or_null( 5968 &aconnector->base.modes, struct drm_display_mode, head); 5969 if (!m_pref) { 5970 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 5971 return NULL; 5972 } 5973 } 5974 5975 highest_refresh = drm_mode_vrefresh(m_pref); 5976 5977 /* 5978 * Find the mode with highest refresh rate with same resolution. 5979 * For some monitors, preferred mode is not the mode with highest 5980 * supported refresh rate. 5981 */ 5982 list_for_each_entry(m, list_head, head) { 5983 current_refresh = drm_mode_vrefresh(m); 5984 5985 if (m->hdisplay == m_pref->hdisplay && 5986 m->vdisplay == m_pref->vdisplay && 5987 highest_refresh < current_refresh) { 5988 highest_refresh = current_refresh; 5989 m_pref = m; 5990 } 5991 } 5992 5993 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 5994 return m_pref; 5995 } 5996 5997 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 5998 struct amdgpu_dm_connector *aconnector) 5999 { 6000 struct drm_display_mode *high_mode; 6001 int timing_diff; 6002 6003 high_mode = get_highest_refresh_rate_mode(aconnector, false); 6004 if (!high_mode || !mode) 6005 return false; 6006 6007 timing_diff = high_mode->vtotal - mode->vtotal; 6008 6009 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 6010 high_mode->hdisplay != mode->hdisplay || 6011 high_mode->vdisplay != mode->vdisplay || 6012 high_mode->hsync_start != mode->hsync_start || 6013 high_mode->hsync_end != mode->hsync_end || 6014 high_mode->htotal != mode->htotal || 6015 high_mode->hskew != mode->hskew || 6016 high_mode->vscan != mode->vscan || 6017 high_mode->vsync_start - mode->vsync_start != timing_diff || 6018 high_mode->vsync_end - mode->vsync_end != timing_diff) 6019 return false; 6020 else 6021 return true; 6022 } 6023 6024 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 6025 struct dc_sink *sink, struct dc_stream_state *stream, 6026 struct dsc_dec_dpcd_caps *dsc_caps) 6027 { 6028 stream->timing.flags.DSC = 0; 6029 dsc_caps->is_dsc_supported = false; 6030 6031 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 6032 sink->sink_signal == SIGNAL_TYPE_EDP)) { 6033 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 6034 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 6035 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 6036 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 6037 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 6038 dsc_caps); 6039 } 6040 } 6041 6042 6043 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 6044 struct dc_sink *sink, struct dc_stream_state *stream, 6045 struct dsc_dec_dpcd_caps *dsc_caps, 6046 uint32_t max_dsc_target_bpp_limit_override) 6047 { 6048 const struct dc_link_settings *verified_link_cap = NULL; 6049 u32 link_bw_in_kbps; 6050 u32 edp_min_bpp_x16, edp_max_bpp_x16; 6051 struct dc *dc = sink->ctx->dc; 6052 struct dc_dsc_bw_range bw_range = {0}; 6053 struct dc_dsc_config dsc_cfg = {0}; 6054 struct dc_dsc_config_options dsc_options = {0}; 6055 6056 dc_dsc_get_default_config_option(dc, &dsc_options); 6057 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6058 6059 verified_link_cap = dc_link_get_link_cap(stream->link); 6060 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 6061 edp_min_bpp_x16 = 8 * 16; 6062 edp_max_bpp_x16 = 8 * 16; 6063 6064 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 6065 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 6066 6067 if (edp_max_bpp_x16 < edp_min_bpp_x16) 6068 edp_min_bpp_x16 = edp_max_bpp_x16; 6069 6070 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 6071 dc->debug.dsc_min_slice_height_override, 6072 edp_min_bpp_x16, edp_max_bpp_x16, 6073 dsc_caps, 6074 &stream->timing, 6075 dc_link_get_highest_encoding_format(aconnector->dc_link), 6076 &bw_range)) { 6077 6078 if (bw_range.max_kbps < link_bw_in_kbps) { 6079 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6080 dsc_caps, 6081 &dsc_options, 6082 0, 6083 &stream->timing, 6084 dc_link_get_highest_encoding_format(aconnector->dc_link), 6085 &dsc_cfg)) { 6086 stream->timing.dsc_cfg = dsc_cfg; 6087 stream->timing.flags.DSC = 1; 6088 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 6089 } 6090 return; 6091 } 6092 } 6093 6094 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6095 dsc_caps, 6096 &dsc_options, 6097 link_bw_in_kbps, 6098 &stream->timing, 6099 dc_link_get_highest_encoding_format(aconnector->dc_link), 6100 &dsc_cfg)) { 6101 stream->timing.dsc_cfg = dsc_cfg; 6102 stream->timing.flags.DSC = 1; 6103 } 6104 } 6105 6106 6107 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 6108 struct dc_sink *sink, struct dc_stream_state *stream, 6109 struct dsc_dec_dpcd_caps *dsc_caps) 6110 { 6111 struct drm_connector *drm_connector = &aconnector->base; 6112 u32 link_bandwidth_kbps; 6113 struct dc *dc = sink->ctx->dc; 6114 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 6115 u32 dsc_max_supported_bw_in_kbps; 6116 u32 max_dsc_target_bpp_limit_override = 6117 drm_connector->display_info.max_dsc_bpp; 6118 struct dc_dsc_config_options dsc_options = {0}; 6119 6120 dc_dsc_get_default_config_option(dc, &dsc_options); 6121 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6122 6123 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 6124 dc_link_get_link_cap(aconnector->dc_link)); 6125 6126 /* Set DSC policy according to dsc_clock_en */ 6127 dc_dsc_policy_set_enable_dsc_when_not_needed( 6128 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 6129 6130 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && 6131 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 6132 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 6133 6134 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 6135 6136 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6137 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 6138 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6139 dsc_caps, 6140 &dsc_options, 6141 link_bandwidth_kbps, 6142 &stream->timing, 6143 dc_link_get_highest_encoding_format(aconnector->dc_link), 6144 &stream->timing.dsc_cfg)) { 6145 stream->timing.flags.DSC = 1; 6146 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 6147 } 6148 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 6149 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 6150 dc_link_get_highest_encoding_format(aconnector->dc_link)); 6151 max_supported_bw_in_kbps = link_bandwidth_kbps; 6152 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 6153 6154 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 6155 max_supported_bw_in_kbps > 0 && 6156 dsc_max_supported_bw_in_kbps > 0) 6157 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6158 dsc_caps, 6159 &dsc_options, 6160 dsc_max_supported_bw_in_kbps, 6161 &stream->timing, 6162 dc_link_get_highest_encoding_format(aconnector->dc_link), 6163 &stream->timing.dsc_cfg)) { 6164 stream->timing.flags.DSC = 1; 6165 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 6166 __func__, drm_connector->name); 6167 } 6168 } 6169 } 6170 6171 /* Overwrite the stream flag if DSC is enabled through debugfs */ 6172 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 6173 stream->timing.flags.DSC = 1; 6174 6175 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 6176 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 6177 6178 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 6179 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 6180 6181 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 6182 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 6183 } 6184 6185 static struct dc_stream_state * 6186 create_stream_for_sink(struct drm_connector *connector, 6187 const struct drm_display_mode *drm_mode, 6188 const struct dm_connector_state *dm_state, 6189 const struct dc_stream_state *old_stream, 6190 int requested_bpc) 6191 { 6192 struct amdgpu_dm_connector *aconnector = NULL; 6193 struct drm_display_mode *preferred_mode = NULL; 6194 const struct drm_connector_state *con_state = &dm_state->base; 6195 struct dc_stream_state *stream = NULL; 6196 struct drm_display_mode mode; 6197 struct drm_display_mode saved_mode; 6198 struct drm_display_mode *freesync_mode = NULL; 6199 bool native_mode_found = false; 6200 bool recalculate_timing = false; 6201 bool scale = dm_state->scaling != RMX_OFF; 6202 int mode_refresh; 6203 int preferred_refresh = 0; 6204 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 6205 struct dsc_dec_dpcd_caps dsc_caps; 6206 6207 struct dc_link *link = NULL; 6208 struct dc_sink *sink = NULL; 6209 6210 drm_mode_init(&mode, drm_mode); 6211 memset(&saved_mode, 0, sizeof(saved_mode)); 6212 6213 if (connector == NULL) { 6214 DRM_ERROR("connector is NULL!\n"); 6215 return stream; 6216 } 6217 6218 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 6219 aconnector = NULL; 6220 aconnector = to_amdgpu_dm_connector(connector); 6221 link = aconnector->dc_link; 6222 } else { 6223 struct drm_writeback_connector *wbcon = NULL; 6224 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 6225 6226 wbcon = drm_connector_to_writeback(connector); 6227 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 6228 link = dm_wbcon->link; 6229 } 6230 6231 if (!aconnector || !aconnector->dc_sink) { 6232 sink = create_fake_sink(link); 6233 if (!sink) 6234 return stream; 6235 6236 } else { 6237 sink = aconnector->dc_sink; 6238 dc_sink_retain(sink); 6239 } 6240 6241 stream = dc_create_stream_for_sink(sink); 6242 6243 if (stream == NULL) { 6244 DRM_ERROR("Failed to create stream for sink!\n"); 6245 goto finish; 6246 } 6247 6248 /* We leave this NULL for writeback connectors */ 6249 stream->dm_stream_context = aconnector; 6250 6251 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6252 connector->display_info.hdmi.scdc.scrambling.low_rates; 6253 6254 list_for_each_entry(preferred_mode, &connector->modes, head) { 6255 /* Search for preferred mode */ 6256 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6257 native_mode_found = true; 6258 break; 6259 } 6260 } 6261 if (!native_mode_found) 6262 preferred_mode = list_first_entry_or_null( 6263 &connector->modes, 6264 struct drm_display_mode, 6265 head); 6266 6267 mode_refresh = drm_mode_vrefresh(&mode); 6268 6269 if (preferred_mode == NULL) { 6270 /* 6271 * This may not be an error, the use case is when we have no 6272 * usermode calls to reset and set mode upon hotplug. In this 6273 * case, we call set mode ourselves to restore the previous mode 6274 * and the modelist may not be filled in time. 6275 */ 6276 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6277 } else if (aconnector) { 6278 recalculate_timing = amdgpu_freesync_vid_mode && 6279 is_freesync_video_mode(&mode, aconnector); 6280 if (recalculate_timing) { 6281 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6282 drm_mode_copy(&saved_mode, &mode); 6283 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 6284 drm_mode_copy(&mode, freesync_mode); 6285 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 6286 } else { 6287 decide_crtc_timing_for_drm_display_mode( 6288 &mode, preferred_mode, scale); 6289 6290 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6291 } 6292 } 6293 6294 if (recalculate_timing) 6295 drm_mode_set_crtcinfo(&saved_mode, 0); 6296 6297 /* 6298 * If scaling is enabled and refresh rate didn't change 6299 * we copy the vic and polarities of the old timings 6300 */ 6301 if (!scale || mode_refresh != preferred_refresh) 6302 fill_stream_properties_from_drm_display_mode( 6303 stream, &mode, connector, con_state, NULL, 6304 requested_bpc); 6305 else 6306 fill_stream_properties_from_drm_display_mode( 6307 stream, &mode, connector, con_state, old_stream, 6308 requested_bpc); 6309 6310 /* The rest isn't needed for writeback connectors */ 6311 if (!aconnector) 6312 goto finish; 6313 6314 if (aconnector->timing_changed) { 6315 drm_dbg(aconnector->base.dev, 6316 "overriding timing for automated test, bpc %d, changing to %d\n", 6317 stream->timing.display_color_depth, 6318 aconnector->timing_requested->display_color_depth); 6319 stream->timing = *aconnector->timing_requested; 6320 } 6321 6322 /* SST DSC determination policy */ 6323 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6324 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6325 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6326 6327 update_stream_scaling_settings(&mode, dm_state, stream); 6328 6329 fill_audio_info( 6330 &stream->audio_info, 6331 connector, 6332 sink); 6333 6334 update_stream_signal(stream, sink); 6335 6336 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6337 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6338 6339 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6340 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6341 stream->signal == SIGNAL_TYPE_EDP) { 6342 // 6343 // should decide stream support vsc sdp colorimetry capability 6344 // before building vsc info packet 6345 // 6346 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 6347 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED; 6348 6349 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 6350 tf = TRANSFER_FUNC_GAMMA_22; 6351 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6352 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6353 6354 } 6355 finish: 6356 dc_sink_release(sink); 6357 6358 return stream; 6359 } 6360 6361 static enum drm_connector_status 6362 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6363 { 6364 bool connected; 6365 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6366 6367 /* 6368 * Notes: 6369 * 1. This interface is NOT called in context of HPD irq. 6370 * 2. This interface *is called* in context of user-mode ioctl. Which 6371 * makes it a bad place for *any* MST-related activity. 6372 */ 6373 6374 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6375 !aconnector->fake_enable) 6376 connected = (aconnector->dc_sink != NULL); 6377 else 6378 connected = (aconnector->base.force == DRM_FORCE_ON || 6379 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6380 6381 update_subconnector_property(aconnector); 6382 6383 return (connected ? connector_status_connected : 6384 connector_status_disconnected); 6385 } 6386 6387 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6388 struct drm_connector_state *connector_state, 6389 struct drm_property *property, 6390 uint64_t val) 6391 { 6392 struct drm_device *dev = connector->dev; 6393 struct amdgpu_device *adev = drm_to_adev(dev); 6394 struct dm_connector_state *dm_old_state = 6395 to_dm_connector_state(connector->state); 6396 struct dm_connector_state *dm_new_state = 6397 to_dm_connector_state(connector_state); 6398 6399 int ret = -EINVAL; 6400 6401 if (property == dev->mode_config.scaling_mode_property) { 6402 enum amdgpu_rmx_type rmx_type; 6403 6404 switch (val) { 6405 case DRM_MODE_SCALE_CENTER: 6406 rmx_type = RMX_CENTER; 6407 break; 6408 case DRM_MODE_SCALE_ASPECT: 6409 rmx_type = RMX_ASPECT; 6410 break; 6411 case DRM_MODE_SCALE_FULLSCREEN: 6412 rmx_type = RMX_FULL; 6413 break; 6414 case DRM_MODE_SCALE_NONE: 6415 default: 6416 rmx_type = RMX_OFF; 6417 break; 6418 } 6419 6420 if (dm_old_state->scaling == rmx_type) 6421 return 0; 6422 6423 dm_new_state->scaling = rmx_type; 6424 ret = 0; 6425 } else if (property == adev->mode_info.underscan_hborder_property) { 6426 dm_new_state->underscan_hborder = val; 6427 ret = 0; 6428 } else if (property == adev->mode_info.underscan_vborder_property) { 6429 dm_new_state->underscan_vborder = val; 6430 ret = 0; 6431 } else if (property == adev->mode_info.underscan_property) { 6432 dm_new_state->underscan_enable = val; 6433 ret = 0; 6434 } 6435 6436 return ret; 6437 } 6438 6439 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6440 const struct drm_connector_state *state, 6441 struct drm_property *property, 6442 uint64_t *val) 6443 { 6444 struct drm_device *dev = connector->dev; 6445 struct amdgpu_device *adev = drm_to_adev(dev); 6446 struct dm_connector_state *dm_state = 6447 to_dm_connector_state(state); 6448 int ret = -EINVAL; 6449 6450 if (property == dev->mode_config.scaling_mode_property) { 6451 switch (dm_state->scaling) { 6452 case RMX_CENTER: 6453 *val = DRM_MODE_SCALE_CENTER; 6454 break; 6455 case RMX_ASPECT: 6456 *val = DRM_MODE_SCALE_ASPECT; 6457 break; 6458 case RMX_FULL: 6459 *val = DRM_MODE_SCALE_FULLSCREEN; 6460 break; 6461 case RMX_OFF: 6462 default: 6463 *val = DRM_MODE_SCALE_NONE; 6464 break; 6465 } 6466 ret = 0; 6467 } else if (property == adev->mode_info.underscan_hborder_property) { 6468 *val = dm_state->underscan_hborder; 6469 ret = 0; 6470 } else if (property == adev->mode_info.underscan_vborder_property) { 6471 *val = dm_state->underscan_vborder; 6472 ret = 0; 6473 } else if (property == adev->mode_info.underscan_property) { 6474 *val = dm_state->underscan_enable; 6475 ret = 0; 6476 } 6477 6478 return ret; 6479 } 6480 6481 /** 6482 * DOC: panel power savings 6483 * 6484 * The display manager allows you to set your desired **panel power savings** 6485 * level (between 0-4, with 0 representing off), e.g. using the following:: 6486 * 6487 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings 6488 * 6489 * Modifying this value can have implications on color accuracy, so tread 6490 * carefully. 6491 */ 6492 6493 static ssize_t panel_power_savings_show(struct device *device, 6494 struct device_attribute *attr, 6495 char *buf) 6496 { 6497 struct drm_connector *connector = dev_get_drvdata(device); 6498 struct drm_device *dev = connector->dev; 6499 u8 val; 6500 6501 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6502 val = to_dm_connector_state(connector->state)->abm_level == 6503 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : 6504 to_dm_connector_state(connector->state)->abm_level; 6505 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6506 6507 return sysfs_emit(buf, "%u\n", val); 6508 } 6509 6510 static ssize_t panel_power_savings_store(struct device *device, 6511 struct device_attribute *attr, 6512 const char *buf, size_t count) 6513 { 6514 struct drm_connector *connector = dev_get_drvdata(device); 6515 struct drm_device *dev = connector->dev; 6516 long val; 6517 int ret; 6518 6519 ret = kstrtol(buf, 0, &val); 6520 6521 if (ret) 6522 return ret; 6523 6524 if (val < 0 || val > 4) 6525 return -EINVAL; 6526 6527 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6528 to_dm_connector_state(connector->state)->abm_level = val ?: 6529 ABM_LEVEL_IMMEDIATE_DISABLE; 6530 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6531 6532 drm_kms_helper_hotplug_event(dev); 6533 6534 return count; 6535 } 6536 6537 static DEVICE_ATTR_RW(panel_power_savings); 6538 6539 static struct attribute *amdgpu_attrs[] = { 6540 &dev_attr_panel_power_savings.attr, 6541 NULL 6542 }; 6543 6544 static const struct attribute_group amdgpu_group = { 6545 .name = "amdgpu", 6546 .attrs = amdgpu_attrs 6547 }; 6548 6549 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6550 { 6551 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6552 6553 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && 6554 amdgpu_dm_abm_level < 0) 6555 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 6556 6557 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6558 } 6559 6560 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6561 { 6562 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6563 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6564 struct amdgpu_display_manager *dm = &adev->dm; 6565 6566 /* 6567 * Call only if mst_mgr was initialized before since it's not done 6568 * for all connector types. 6569 */ 6570 if (aconnector->mst_mgr.dev) 6571 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6572 6573 if (aconnector->bl_idx != -1) { 6574 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6575 dm->backlight_dev[aconnector->bl_idx] = NULL; 6576 } 6577 6578 if (aconnector->dc_em_sink) 6579 dc_sink_release(aconnector->dc_em_sink); 6580 aconnector->dc_em_sink = NULL; 6581 if (aconnector->dc_sink) 6582 dc_sink_release(aconnector->dc_sink); 6583 aconnector->dc_sink = NULL; 6584 6585 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6586 drm_connector_unregister(connector); 6587 drm_connector_cleanup(connector); 6588 if (aconnector->i2c) { 6589 i2c_del_adapter(&aconnector->i2c->base); 6590 kfree(aconnector->i2c); 6591 } 6592 kfree(aconnector->dm_dp_aux.aux.name); 6593 6594 kfree(connector); 6595 } 6596 6597 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6598 { 6599 struct dm_connector_state *state = 6600 to_dm_connector_state(connector->state); 6601 6602 if (connector->state) 6603 __drm_atomic_helper_connector_destroy_state(connector->state); 6604 6605 kfree(state); 6606 6607 state = kzalloc(sizeof(*state), GFP_KERNEL); 6608 6609 if (state) { 6610 state->scaling = RMX_OFF; 6611 state->underscan_enable = false; 6612 state->underscan_hborder = 0; 6613 state->underscan_vborder = 0; 6614 state->base.max_requested_bpc = 8; 6615 state->vcpi_slots = 0; 6616 state->pbn = 0; 6617 6618 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 6619 if (amdgpu_dm_abm_level <= 0) 6620 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 6621 else 6622 state->abm_level = amdgpu_dm_abm_level; 6623 } 6624 6625 __drm_atomic_helper_connector_reset(connector, &state->base); 6626 } 6627 } 6628 6629 struct drm_connector_state * 6630 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6631 { 6632 struct dm_connector_state *state = 6633 to_dm_connector_state(connector->state); 6634 6635 struct dm_connector_state *new_state = 6636 kmemdup(state, sizeof(*state), GFP_KERNEL); 6637 6638 if (!new_state) 6639 return NULL; 6640 6641 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6642 6643 new_state->freesync_capable = state->freesync_capable; 6644 new_state->abm_level = state->abm_level; 6645 new_state->scaling = state->scaling; 6646 new_state->underscan_enable = state->underscan_enable; 6647 new_state->underscan_hborder = state->underscan_hborder; 6648 new_state->underscan_vborder = state->underscan_vborder; 6649 new_state->vcpi_slots = state->vcpi_slots; 6650 new_state->pbn = state->pbn; 6651 return &new_state->base; 6652 } 6653 6654 static int 6655 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6656 { 6657 struct amdgpu_dm_connector *amdgpu_dm_connector = 6658 to_amdgpu_dm_connector(connector); 6659 int r; 6660 6661 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && 6662 amdgpu_dm_abm_level < 0) { 6663 r = sysfs_create_group(&connector->kdev->kobj, 6664 &amdgpu_group); 6665 if (r) 6666 return r; 6667 } 6668 6669 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6670 6671 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6672 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6673 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6674 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6675 if (r) 6676 return r; 6677 } 6678 6679 #if defined(CONFIG_DEBUG_FS) 6680 connector_debugfs_init(amdgpu_dm_connector); 6681 #endif 6682 6683 return 0; 6684 } 6685 6686 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 6687 { 6688 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6689 struct dc_link *dc_link = aconnector->dc_link; 6690 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 6691 struct edid *edid; 6692 struct i2c_adapter *ddc; 6693 6694 if (dc_link && dc_link->aux_mode) 6695 ddc = &aconnector->dm_dp_aux.aux.ddc; 6696 else 6697 ddc = &aconnector->i2c->base; 6698 6699 /* 6700 * Note: drm_get_edid gets edid in the following order: 6701 * 1) override EDID if set via edid_override debugfs, 6702 * 2) firmware EDID if set via edid_firmware module parameter 6703 * 3) regular DDC read. 6704 */ 6705 edid = drm_get_edid(connector, ddc); 6706 if (!edid) { 6707 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 6708 return; 6709 } 6710 6711 aconnector->edid = edid; 6712 6713 /* Update emulated (virtual) sink's EDID */ 6714 if (dc_em_sink && dc_link) { 6715 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 6716 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 6717 dm_helpers_parse_edid_caps( 6718 dc_link, 6719 &dc_em_sink->dc_edid, 6720 &dc_em_sink->edid_caps); 6721 } 6722 } 6723 6724 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 6725 .reset = amdgpu_dm_connector_funcs_reset, 6726 .detect = amdgpu_dm_connector_detect, 6727 .fill_modes = drm_helper_probe_single_connector_modes, 6728 .destroy = amdgpu_dm_connector_destroy, 6729 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 6730 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6731 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 6732 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 6733 .late_register = amdgpu_dm_connector_late_register, 6734 .early_unregister = amdgpu_dm_connector_unregister, 6735 .force = amdgpu_dm_connector_funcs_force 6736 }; 6737 6738 static int get_modes(struct drm_connector *connector) 6739 { 6740 return amdgpu_dm_connector_get_modes(connector); 6741 } 6742 6743 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 6744 { 6745 struct drm_connector *connector = &aconnector->base; 6746 struct dc_link *dc_link = aconnector->dc_link; 6747 struct dc_sink_init_data init_params = { 6748 .link = aconnector->dc_link, 6749 .sink_signal = SIGNAL_TYPE_VIRTUAL 6750 }; 6751 struct edid *edid; 6752 struct i2c_adapter *ddc; 6753 6754 if (dc_link->aux_mode) 6755 ddc = &aconnector->dm_dp_aux.aux.ddc; 6756 else 6757 ddc = &aconnector->i2c->base; 6758 6759 /* 6760 * Note: drm_get_edid gets edid in the following order: 6761 * 1) override EDID if set via edid_override debugfs, 6762 * 2) firmware EDID if set via edid_firmware module parameter 6763 * 3) regular DDC read. 6764 */ 6765 edid = drm_get_edid(connector, ddc); 6766 if (!edid) { 6767 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 6768 return; 6769 } 6770 6771 if (drm_detect_hdmi_monitor(edid)) 6772 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 6773 6774 aconnector->edid = edid; 6775 6776 aconnector->dc_em_sink = dc_link_add_remote_sink( 6777 aconnector->dc_link, 6778 (uint8_t *)edid, 6779 (edid->extensions + 1) * EDID_LENGTH, 6780 &init_params); 6781 6782 if (aconnector->base.force == DRM_FORCE_ON) { 6783 aconnector->dc_sink = aconnector->dc_link->local_sink ? 6784 aconnector->dc_link->local_sink : 6785 aconnector->dc_em_sink; 6786 dc_sink_retain(aconnector->dc_sink); 6787 } 6788 } 6789 6790 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 6791 { 6792 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 6793 6794 /* 6795 * In case of headless boot with force on for DP managed connector 6796 * Those settings have to be != 0 to get initial modeset 6797 */ 6798 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6799 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 6800 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 6801 } 6802 6803 create_eml_sink(aconnector); 6804 } 6805 6806 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 6807 struct dc_stream_state *stream) 6808 { 6809 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 6810 struct dc_plane_state *dc_plane_state = NULL; 6811 struct dc_state *dc_state = NULL; 6812 6813 if (!stream) 6814 goto cleanup; 6815 6816 dc_plane_state = dc_create_plane_state(dc); 6817 if (!dc_plane_state) 6818 goto cleanup; 6819 6820 dc_state = dc_state_create(dc, NULL); 6821 if (!dc_state) 6822 goto cleanup; 6823 6824 /* populate stream to plane */ 6825 dc_plane_state->src_rect.height = stream->src.height; 6826 dc_plane_state->src_rect.width = stream->src.width; 6827 dc_plane_state->dst_rect.height = stream->src.height; 6828 dc_plane_state->dst_rect.width = stream->src.width; 6829 dc_plane_state->clip_rect.height = stream->src.height; 6830 dc_plane_state->clip_rect.width = stream->src.width; 6831 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 6832 dc_plane_state->plane_size.surface_size.height = stream->src.height; 6833 dc_plane_state->plane_size.surface_size.width = stream->src.width; 6834 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 6835 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 6836 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 6837 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 6838 dc_plane_state->rotation = ROTATION_ANGLE_0; 6839 dc_plane_state->is_tiling_rotated = false; 6840 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 6841 6842 dc_result = dc_validate_stream(dc, stream); 6843 if (dc_result == DC_OK) 6844 dc_result = dc_validate_plane(dc, dc_plane_state); 6845 6846 if (dc_result == DC_OK) 6847 dc_result = dc_state_add_stream(dc, dc_state, stream); 6848 6849 if (dc_result == DC_OK && !dc_state_add_plane( 6850 dc, 6851 stream, 6852 dc_plane_state, 6853 dc_state)) 6854 dc_result = DC_FAIL_ATTACH_SURFACES; 6855 6856 if (dc_result == DC_OK) 6857 dc_result = dc_validate_global_state(dc, dc_state, true); 6858 6859 cleanup: 6860 if (dc_state) 6861 dc_state_release(dc_state); 6862 6863 if (dc_plane_state) 6864 dc_plane_state_release(dc_plane_state); 6865 6866 return dc_result; 6867 } 6868 6869 struct dc_stream_state * 6870 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 6871 const struct drm_display_mode *drm_mode, 6872 const struct dm_connector_state *dm_state, 6873 const struct dc_stream_state *old_stream) 6874 { 6875 struct drm_connector *connector = &aconnector->base; 6876 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6877 struct dc_stream_state *stream; 6878 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 6879 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 6880 enum dc_status dc_result = DC_OK; 6881 6882 do { 6883 stream = create_stream_for_sink(connector, drm_mode, 6884 dm_state, old_stream, 6885 requested_bpc); 6886 if (stream == NULL) { 6887 DRM_ERROR("Failed to create stream for sink!\n"); 6888 break; 6889 } 6890 6891 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6892 return stream; 6893 6894 dc_result = dc_validate_stream(adev->dm.dc, stream); 6895 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 6896 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 6897 6898 if (dc_result == DC_OK) 6899 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 6900 6901 if (dc_result != DC_OK) { 6902 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 6903 drm_mode->hdisplay, 6904 drm_mode->vdisplay, 6905 drm_mode->clock, 6906 dc_result, 6907 dc_status_to_str(dc_result)); 6908 6909 dc_stream_release(stream); 6910 stream = NULL; 6911 requested_bpc -= 2; /* lower bpc to retry validation */ 6912 } 6913 6914 } while (stream == NULL && requested_bpc >= 6); 6915 6916 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 6917 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 6918 6919 aconnector->force_yuv420_output = true; 6920 stream = create_validate_stream_for_sink(aconnector, drm_mode, 6921 dm_state, old_stream); 6922 aconnector->force_yuv420_output = false; 6923 } 6924 6925 return stream; 6926 } 6927 6928 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 6929 struct drm_display_mode *mode) 6930 { 6931 int result = MODE_ERROR; 6932 struct dc_sink *dc_sink; 6933 /* TODO: Unhardcode stream count */ 6934 struct dc_stream_state *stream; 6935 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6936 6937 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 6938 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 6939 return result; 6940 6941 /* 6942 * Only run this the first time mode_valid is called to initilialize 6943 * EDID mgmt 6944 */ 6945 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 6946 !aconnector->dc_em_sink) 6947 handle_edid_mgmt(aconnector); 6948 6949 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 6950 6951 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 6952 aconnector->base.force != DRM_FORCE_ON) { 6953 DRM_ERROR("dc_sink is NULL!\n"); 6954 goto fail; 6955 } 6956 6957 drm_mode_set_crtcinfo(mode, 0); 6958 6959 stream = create_validate_stream_for_sink(aconnector, mode, 6960 to_dm_connector_state(connector->state), 6961 NULL); 6962 if (stream) { 6963 dc_stream_release(stream); 6964 result = MODE_OK; 6965 } 6966 6967 fail: 6968 /* TODO: error handling*/ 6969 return result; 6970 } 6971 6972 static int fill_hdr_info_packet(const struct drm_connector_state *state, 6973 struct dc_info_packet *out) 6974 { 6975 struct hdmi_drm_infoframe frame; 6976 unsigned char buf[30]; /* 26 + 4 */ 6977 ssize_t len; 6978 int ret, i; 6979 6980 memset(out, 0, sizeof(*out)); 6981 6982 if (!state->hdr_output_metadata) 6983 return 0; 6984 6985 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 6986 if (ret) 6987 return ret; 6988 6989 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 6990 if (len < 0) 6991 return (int)len; 6992 6993 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 6994 if (len != 30) 6995 return -EINVAL; 6996 6997 /* Prepare the infopacket for DC. */ 6998 switch (state->connector->connector_type) { 6999 case DRM_MODE_CONNECTOR_HDMIA: 7000 out->hb0 = 0x87; /* type */ 7001 out->hb1 = 0x01; /* version */ 7002 out->hb2 = 0x1A; /* length */ 7003 out->sb[0] = buf[3]; /* checksum */ 7004 i = 1; 7005 break; 7006 7007 case DRM_MODE_CONNECTOR_DisplayPort: 7008 case DRM_MODE_CONNECTOR_eDP: 7009 out->hb0 = 0x00; /* sdp id, zero */ 7010 out->hb1 = 0x87; /* type */ 7011 out->hb2 = 0x1D; /* payload len - 1 */ 7012 out->hb3 = (0x13 << 2); /* sdp version */ 7013 out->sb[0] = 0x01; /* version */ 7014 out->sb[1] = 0x1A; /* length */ 7015 i = 2; 7016 break; 7017 7018 default: 7019 return -EINVAL; 7020 } 7021 7022 memcpy(&out->sb[i], &buf[4], 26); 7023 out->valid = true; 7024 7025 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 7026 sizeof(out->sb), false); 7027 7028 return 0; 7029 } 7030 7031 static int 7032 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 7033 struct drm_atomic_state *state) 7034 { 7035 struct drm_connector_state *new_con_state = 7036 drm_atomic_get_new_connector_state(state, conn); 7037 struct drm_connector_state *old_con_state = 7038 drm_atomic_get_old_connector_state(state, conn); 7039 struct drm_crtc *crtc = new_con_state->crtc; 7040 struct drm_crtc_state *new_crtc_state; 7041 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 7042 int ret; 7043 7044 trace_amdgpu_dm_connector_atomic_check(new_con_state); 7045 7046 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 7047 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 7048 if (ret < 0) 7049 return ret; 7050 } 7051 7052 if (!crtc) 7053 return 0; 7054 7055 if (new_con_state->colorspace != old_con_state->colorspace) { 7056 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7057 if (IS_ERR(new_crtc_state)) 7058 return PTR_ERR(new_crtc_state); 7059 7060 new_crtc_state->mode_changed = true; 7061 } 7062 7063 if (new_con_state->content_type != old_con_state->content_type) { 7064 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7065 if (IS_ERR(new_crtc_state)) 7066 return PTR_ERR(new_crtc_state); 7067 7068 new_crtc_state->mode_changed = true; 7069 } 7070 7071 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 7072 struct dc_info_packet hdr_infopacket; 7073 7074 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 7075 if (ret) 7076 return ret; 7077 7078 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7079 if (IS_ERR(new_crtc_state)) 7080 return PTR_ERR(new_crtc_state); 7081 7082 /* 7083 * DC considers the stream backends changed if the 7084 * static metadata changes. Forcing the modeset also 7085 * gives a simple way for userspace to switch from 7086 * 8bpc to 10bpc when setting the metadata to enter 7087 * or exit HDR. 7088 * 7089 * Changing the static metadata after it's been 7090 * set is permissible, however. So only force a 7091 * modeset if we're entering or exiting HDR. 7092 */ 7093 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 7094 !old_con_state->hdr_output_metadata || 7095 !new_con_state->hdr_output_metadata; 7096 } 7097 7098 return 0; 7099 } 7100 7101 static const struct drm_connector_helper_funcs 7102 amdgpu_dm_connector_helper_funcs = { 7103 /* 7104 * If hotplugging a second bigger display in FB Con mode, bigger resolution 7105 * modes will be filtered by drm_mode_validate_size(), and those modes 7106 * are missing after user start lightdm. So we need to renew modes list. 7107 * in get_modes call back, not just return the modes count 7108 */ 7109 .get_modes = get_modes, 7110 .mode_valid = amdgpu_dm_connector_mode_valid, 7111 .atomic_check = amdgpu_dm_connector_atomic_check, 7112 }; 7113 7114 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 7115 { 7116 7117 } 7118 7119 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 7120 { 7121 switch (display_color_depth) { 7122 case COLOR_DEPTH_666: 7123 return 6; 7124 case COLOR_DEPTH_888: 7125 return 8; 7126 case COLOR_DEPTH_101010: 7127 return 10; 7128 case COLOR_DEPTH_121212: 7129 return 12; 7130 case COLOR_DEPTH_141414: 7131 return 14; 7132 case COLOR_DEPTH_161616: 7133 return 16; 7134 default: 7135 break; 7136 } 7137 return 0; 7138 } 7139 7140 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 7141 struct drm_crtc_state *crtc_state, 7142 struct drm_connector_state *conn_state) 7143 { 7144 struct drm_atomic_state *state = crtc_state->state; 7145 struct drm_connector *connector = conn_state->connector; 7146 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7147 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 7148 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 7149 struct drm_dp_mst_topology_mgr *mst_mgr; 7150 struct drm_dp_mst_port *mst_port; 7151 struct drm_dp_mst_topology_state *mst_state; 7152 enum dc_color_depth color_depth; 7153 int clock, bpp = 0; 7154 bool is_y420 = false; 7155 7156 if (!aconnector->mst_output_port) 7157 return 0; 7158 7159 mst_port = aconnector->mst_output_port; 7160 mst_mgr = &aconnector->mst_root->mst_mgr; 7161 7162 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 7163 return 0; 7164 7165 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 7166 if (IS_ERR(mst_state)) 7167 return PTR_ERR(mst_state); 7168 7169 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); 7170 7171 if (!state->duplicated) { 7172 int max_bpc = conn_state->max_requested_bpc; 7173 7174 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 7175 aconnector->force_yuv420_output; 7176 color_depth = convert_color_depth_from_display_info(connector, 7177 is_y420, 7178 max_bpc); 7179 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 7180 clock = adjusted_mode->clock; 7181 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 7182 } 7183 7184 dm_new_connector_state->vcpi_slots = 7185 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 7186 dm_new_connector_state->pbn); 7187 if (dm_new_connector_state->vcpi_slots < 0) { 7188 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 7189 return dm_new_connector_state->vcpi_slots; 7190 } 7191 return 0; 7192 } 7193 7194 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 7195 .disable = dm_encoder_helper_disable, 7196 .atomic_check = dm_encoder_helper_atomic_check 7197 }; 7198 7199 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 7200 struct dc_state *dc_state, 7201 struct dsc_mst_fairness_vars *vars) 7202 { 7203 struct dc_stream_state *stream = NULL; 7204 struct drm_connector *connector; 7205 struct drm_connector_state *new_con_state; 7206 struct amdgpu_dm_connector *aconnector; 7207 struct dm_connector_state *dm_conn_state; 7208 int i, j, ret; 7209 int vcpi, pbn_div, pbn, slot_num = 0; 7210 7211 for_each_new_connector_in_state(state, connector, new_con_state, i) { 7212 7213 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7214 continue; 7215 7216 aconnector = to_amdgpu_dm_connector(connector); 7217 7218 if (!aconnector->mst_output_port) 7219 continue; 7220 7221 if (!new_con_state || !new_con_state->crtc) 7222 continue; 7223 7224 dm_conn_state = to_dm_connector_state(new_con_state); 7225 7226 for (j = 0; j < dc_state->stream_count; j++) { 7227 stream = dc_state->streams[j]; 7228 if (!stream) 7229 continue; 7230 7231 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 7232 break; 7233 7234 stream = NULL; 7235 } 7236 7237 if (!stream) 7238 continue; 7239 7240 pbn_div = dm_mst_get_pbn_divider(stream->link); 7241 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 7242 for (j = 0; j < dc_state->stream_count; j++) { 7243 if (vars[j].aconnector == aconnector) { 7244 pbn = vars[j].pbn; 7245 break; 7246 } 7247 } 7248 7249 if (j == dc_state->stream_count) 7250 continue; 7251 7252 slot_num = DIV_ROUND_UP(pbn, pbn_div); 7253 7254 if (stream->timing.flags.DSC != 1) { 7255 dm_conn_state->pbn = pbn; 7256 dm_conn_state->vcpi_slots = slot_num; 7257 7258 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 7259 dm_conn_state->pbn, false); 7260 if (ret < 0) 7261 return ret; 7262 7263 continue; 7264 } 7265 7266 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 7267 if (vcpi < 0) 7268 return vcpi; 7269 7270 dm_conn_state->pbn = pbn; 7271 dm_conn_state->vcpi_slots = vcpi; 7272 } 7273 return 0; 7274 } 7275 7276 static int to_drm_connector_type(enum signal_type st) 7277 { 7278 switch (st) { 7279 case SIGNAL_TYPE_HDMI_TYPE_A: 7280 return DRM_MODE_CONNECTOR_HDMIA; 7281 case SIGNAL_TYPE_EDP: 7282 return DRM_MODE_CONNECTOR_eDP; 7283 case SIGNAL_TYPE_LVDS: 7284 return DRM_MODE_CONNECTOR_LVDS; 7285 case SIGNAL_TYPE_RGB: 7286 return DRM_MODE_CONNECTOR_VGA; 7287 case SIGNAL_TYPE_DISPLAY_PORT: 7288 case SIGNAL_TYPE_DISPLAY_PORT_MST: 7289 return DRM_MODE_CONNECTOR_DisplayPort; 7290 case SIGNAL_TYPE_DVI_DUAL_LINK: 7291 case SIGNAL_TYPE_DVI_SINGLE_LINK: 7292 return DRM_MODE_CONNECTOR_DVID; 7293 case SIGNAL_TYPE_VIRTUAL: 7294 return DRM_MODE_CONNECTOR_VIRTUAL; 7295 7296 default: 7297 return DRM_MODE_CONNECTOR_Unknown; 7298 } 7299 } 7300 7301 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 7302 { 7303 struct drm_encoder *encoder; 7304 7305 /* There is only one encoder per connector */ 7306 drm_connector_for_each_possible_encoder(connector, encoder) 7307 return encoder; 7308 7309 return NULL; 7310 } 7311 7312 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 7313 { 7314 struct drm_encoder *encoder; 7315 struct amdgpu_encoder *amdgpu_encoder; 7316 7317 encoder = amdgpu_dm_connector_to_encoder(connector); 7318 7319 if (encoder == NULL) 7320 return; 7321 7322 amdgpu_encoder = to_amdgpu_encoder(encoder); 7323 7324 amdgpu_encoder->native_mode.clock = 0; 7325 7326 if (!list_empty(&connector->probed_modes)) { 7327 struct drm_display_mode *preferred_mode = NULL; 7328 7329 list_for_each_entry(preferred_mode, 7330 &connector->probed_modes, 7331 head) { 7332 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7333 amdgpu_encoder->native_mode = *preferred_mode; 7334 7335 break; 7336 } 7337 7338 } 7339 } 7340 7341 static struct drm_display_mode * 7342 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7343 char *name, 7344 int hdisplay, int vdisplay) 7345 { 7346 struct drm_device *dev = encoder->dev; 7347 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7348 struct drm_display_mode *mode = NULL; 7349 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7350 7351 mode = drm_mode_duplicate(dev, native_mode); 7352 7353 if (mode == NULL) 7354 return NULL; 7355 7356 mode->hdisplay = hdisplay; 7357 mode->vdisplay = vdisplay; 7358 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7359 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7360 7361 return mode; 7362 7363 } 7364 7365 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7366 struct drm_connector *connector) 7367 { 7368 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7369 struct drm_display_mode *mode = NULL; 7370 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7371 struct amdgpu_dm_connector *amdgpu_dm_connector = 7372 to_amdgpu_dm_connector(connector); 7373 int i; 7374 int n; 7375 struct mode_size { 7376 char name[DRM_DISPLAY_MODE_LEN]; 7377 int w; 7378 int h; 7379 } common_modes[] = { 7380 { "640x480", 640, 480}, 7381 { "800x600", 800, 600}, 7382 { "1024x768", 1024, 768}, 7383 { "1280x720", 1280, 720}, 7384 { "1280x800", 1280, 800}, 7385 {"1280x1024", 1280, 1024}, 7386 { "1440x900", 1440, 900}, 7387 {"1680x1050", 1680, 1050}, 7388 {"1600x1200", 1600, 1200}, 7389 {"1920x1080", 1920, 1080}, 7390 {"1920x1200", 1920, 1200} 7391 }; 7392 7393 n = ARRAY_SIZE(common_modes); 7394 7395 for (i = 0; i < n; i++) { 7396 struct drm_display_mode *curmode = NULL; 7397 bool mode_existed = false; 7398 7399 if (common_modes[i].w > native_mode->hdisplay || 7400 common_modes[i].h > native_mode->vdisplay || 7401 (common_modes[i].w == native_mode->hdisplay && 7402 common_modes[i].h == native_mode->vdisplay)) 7403 continue; 7404 7405 list_for_each_entry(curmode, &connector->probed_modes, head) { 7406 if (common_modes[i].w == curmode->hdisplay && 7407 common_modes[i].h == curmode->vdisplay) { 7408 mode_existed = true; 7409 break; 7410 } 7411 } 7412 7413 if (mode_existed) 7414 continue; 7415 7416 mode = amdgpu_dm_create_common_mode(encoder, 7417 common_modes[i].name, common_modes[i].w, 7418 common_modes[i].h); 7419 if (!mode) 7420 continue; 7421 7422 drm_mode_probed_add(connector, mode); 7423 amdgpu_dm_connector->num_modes++; 7424 } 7425 } 7426 7427 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7428 { 7429 struct drm_encoder *encoder; 7430 struct amdgpu_encoder *amdgpu_encoder; 7431 const struct drm_display_mode *native_mode; 7432 7433 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7434 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7435 return; 7436 7437 mutex_lock(&connector->dev->mode_config.mutex); 7438 amdgpu_dm_connector_get_modes(connector); 7439 mutex_unlock(&connector->dev->mode_config.mutex); 7440 7441 encoder = amdgpu_dm_connector_to_encoder(connector); 7442 if (!encoder) 7443 return; 7444 7445 amdgpu_encoder = to_amdgpu_encoder(encoder); 7446 7447 native_mode = &amdgpu_encoder->native_mode; 7448 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7449 return; 7450 7451 drm_connector_set_panel_orientation_with_quirk(connector, 7452 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7453 native_mode->hdisplay, 7454 native_mode->vdisplay); 7455 } 7456 7457 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7458 struct edid *edid) 7459 { 7460 struct amdgpu_dm_connector *amdgpu_dm_connector = 7461 to_amdgpu_dm_connector(connector); 7462 7463 if (edid) { 7464 /* empty probed_modes */ 7465 INIT_LIST_HEAD(&connector->probed_modes); 7466 amdgpu_dm_connector->num_modes = 7467 drm_add_edid_modes(connector, edid); 7468 7469 /* sorting the probed modes before calling function 7470 * amdgpu_dm_get_native_mode() since EDID can have 7471 * more than one preferred mode. The modes that are 7472 * later in the probed mode list could be of higher 7473 * and preferred resolution. For example, 3840x2160 7474 * resolution in base EDID preferred timing and 4096x2160 7475 * preferred resolution in DID extension block later. 7476 */ 7477 drm_mode_sort(&connector->probed_modes); 7478 amdgpu_dm_get_native_mode(connector); 7479 7480 /* Freesync capabilities are reset by calling 7481 * drm_add_edid_modes() and need to be 7482 * restored here. 7483 */ 7484 amdgpu_dm_update_freesync_caps(connector, edid); 7485 } else { 7486 amdgpu_dm_connector->num_modes = 0; 7487 } 7488 } 7489 7490 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7491 struct drm_display_mode *mode) 7492 { 7493 struct drm_display_mode *m; 7494 7495 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7496 if (drm_mode_equal(m, mode)) 7497 return true; 7498 } 7499 7500 return false; 7501 } 7502 7503 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7504 { 7505 const struct drm_display_mode *m; 7506 struct drm_display_mode *new_mode; 7507 uint i; 7508 u32 new_modes_count = 0; 7509 7510 /* Standard FPS values 7511 * 7512 * 23.976 - TV/NTSC 7513 * 24 - Cinema 7514 * 25 - TV/PAL 7515 * 29.97 - TV/NTSC 7516 * 30 - TV/NTSC 7517 * 48 - Cinema HFR 7518 * 50 - TV/PAL 7519 * 60 - Commonly used 7520 * 48,72,96,120 - Multiples of 24 7521 */ 7522 static const u32 common_rates[] = { 7523 23976, 24000, 25000, 29970, 30000, 7524 48000, 50000, 60000, 72000, 96000, 120000 7525 }; 7526 7527 /* 7528 * Find mode with highest refresh rate with the same resolution 7529 * as the preferred mode. Some monitors report a preferred mode 7530 * with lower resolution than the highest refresh rate supported. 7531 */ 7532 7533 m = get_highest_refresh_rate_mode(aconnector, true); 7534 if (!m) 7535 return 0; 7536 7537 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7538 u64 target_vtotal, target_vtotal_diff; 7539 u64 num, den; 7540 7541 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7542 continue; 7543 7544 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7545 common_rates[i] > aconnector->max_vfreq * 1000) 7546 continue; 7547 7548 num = (unsigned long long)m->clock * 1000 * 1000; 7549 den = common_rates[i] * (unsigned long long)m->htotal; 7550 target_vtotal = div_u64(num, den); 7551 target_vtotal_diff = target_vtotal - m->vtotal; 7552 7553 /* Check for illegal modes */ 7554 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7555 m->vsync_end + target_vtotal_diff < m->vsync_start || 7556 m->vtotal + target_vtotal_diff < m->vsync_end) 7557 continue; 7558 7559 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7560 if (!new_mode) 7561 goto out; 7562 7563 new_mode->vtotal += (u16)target_vtotal_diff; 7564 new_mode->vsync_start += (u16)target_vtotal_diff; 7565 new_mode->vsync_end += (u16)target_vtotal_diff; 7566 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7567 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7568 7569 if (!is_duplicate_mode(aconnector, new_mode)) { 7570 drm_mode_probed_add(&aconnector->base, new_mode); 7571 new_modes_count += 1; 7572 } else 7573 drm_mode_destroy(aconnector->base.dev, new_mode); 7574 } 7575 out: 7576 return new_modes_count; 7577 } 7578 7579 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7580 struct edid *edid) 7581 { 7582 struct amdgpu_dm_connector *amdgpu_dm_connector = 7583 to_amdgpu_dm_connector(connector); 7584 7585 if (!(amdgpu_freesync_vid_mode && edid)) 7586 return; 7587 7588 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7589 amdgpu_dm_connector->num_modes += 7590 add_fs_modes(amdgpu_dm_connector); 7591 } 7592 7593 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7594 { 7595 struct amdgpu_dm_connector *amdgpu_dm_connector = 7596 to_amdgpu_dm_connector(connector); 7597 struct drm_encoder *encoder; 7598 struct edid *edid = amdgpu_dm_connector->edid; 7599 struct dc_link_settings *verified_link_cap = 7600 &amdgpu_dm_connector->dc_link->verified_link_cap; 7601 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7602 7603 encoder = amdgpu_dm_connector_to_encoder(connector); 7604 7605 if (!drm_edid_is_valid(edid)) { 7606 amdgpu_dm_connector->num_modes = 7607 drm_add_modes_noedid(connector, 640, 480); 7608 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7609 amdgpu_dm_connector->num_modes += 7610 drm_add_modes_noedid(connector, 1920, 1080); 7611 } else { 7612 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7613 amdgpu_dm_connector_add_common_modes(encoder, connector); 7614 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7615 } 7616 amdgpu_dm_fbc_init(connector); 7617 7618 return amdgpu_dm_connector->num_modes; 7619 } 7620 7621 static const u32 supported_colorspaces = 7622 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7623 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7624 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7625 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7626 7627 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7628 struct amdgpu_dm_connector *aconnector, 7629 int connector_type, 7630 struct dc_link *link, 7631 int link_index) 7632 { 7633 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7634 7635 /* 7636 * Some of the properties below require access to state, like bpc. 7637 * Allocate some default initial connector state with our reset helper. 7638 */ 7639 if (aconnector->base.funcs->reset) 7640 aconnector->base.funcs->reset(&aconnector->base); 7641 7642 aconnector->connector_id = link_index; 7643 aconnector->bl_idx = -1; 7644 aconnector->dc_link = link; 7645 aconnector->base.interlace_allowed = false; 7646 aconnector->base.doublescan_allowed = false; 7647 aconnector->base.stereo_allowed = false; 7648 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7649 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7650 aconnector->audio_inst = -1; 7651 aconnector->pack_sdp_v1_3 = false; 7652 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7653 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7654 mutex_init(&aconnector->hpd_lock); 7655 mutex_init(&aconnector->handle_mst_msg_ready); 7656 7657 /* 7658 * configure support HPD hot plug connector_>polled default value is 0 7659 * which means HPD hot plug not supported 7660 */ 7661 switch (connector_type) { 7662 case DRM_MODE_CONNECTOR_HDMIA: 7663 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7664 aconnector->base.ycbcr_420_allowed = 7665 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7666 break; 7667 case DRM_MODE_CONNECTOR_DisplayPort: 7668 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7669 link->link_enc = link_enc_cfg_get_link_enc(link); 7670 ASSERT(link->link_enc); 7671 if (link->link_enc) 7672 aconnector->base.ycbcr_420_allowed = 7673 link->link_enc->features.dp_ycbcr420_supported ? true : false; 7674 break; 7675 case DRM_MODE_CONNECTOR_DVID: 7676 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7677 break; 7678 default: 7679 break; 7680 } 7681 7682 drm_object_attach_property(&aconnector->base.base, 7683 dm->ddev->mode_config.scaling_mode_property, 7684 DRM_MODE_SCALE_NONE); 7685 7686 drm_object_attach_property(&aconnector->base.base, 7687 adev->mode_info.underscan_property, 7688 UNDERSCAN_OFF); 7689 drm_object_attach_property(&aconnector->base.base, 7690 adev->mode_info.underscan_hborder_property, 7691 0); 7692 drm_object_attach_property(&aconnector->base.base, 7693 adev->mode_info.underscan_vborder_property, 7694 0); 7695 7696 if (!aconnector->mst_root) 7697 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 7698 7699 aconnector->base.state->max_bpc = 16; 7700 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 7701 7702 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7703 /* Content Type is currently only implemented for HDMI. */ 7704 drm_connector_attach_content_type_property(&aconnector->base); 7705 } 7706 7707 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 7708 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 7709 drm_connector_attach_colorspace_property(&aconnector->base); 7710 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 7711 connector_type == DRM_MODE_CONNECTOR_eDP) { 7712 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 7713 drm_connector_attach_colorspace_property(&aconnector->base); 7714 } 7715 7716 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 7717 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 7718 connector_type == DRM_MODE_CONNECTOR_eDP) { 7719 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 7720 7721 if (!aconnector->mst_root) 7722 drm_connector_attach_vrr_capable_property(&aconnector->base); 7723 7724 if (adev->dm.hdcp_workqueue) 7725 drm_connector_attach_content_protection_property(&aconnector->base, true); 7726 } 7727 } 7728 7729 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 7730 struct i2c_msg *msgs, int num) 7731 { 7732 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 7733 struct ddc_service *ddc_service = i2c->ddc_service; 7734 struct i2c_command cmd; 7735 int i; 7736 int result = -EIO; 7737 7738 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) 7739 return result; 7740 7741 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 7742 7743 if (!cmd.payloads) 7744 return result; 7745 7746 cmd.number_of_payloads = num; 7747 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 7748 cmd.speed = 100; 7749 7750 for (i = 0; i < num; i++) { 7751 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 7752 cmd.payloads[i].address = msgs[i].addr; 7753 cmd.payloads[i].length = msgs[i].len; 7754 cmd.payloads[i].data = msgs[i].buf; 7755 } 7756 7757 if (dc_submit_i2c( 7758 ddc_service->ctx->dc, 7759 ddc_service->link->link_index, 7760 &cmd)) 7761 result = num; 7762 7763 kfree(cmd.payloads); 7764 return result; 7765 } 7766 7767 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 7768 { 7769 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 7770 } 7771 7772 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 7773 .master_xfer = amdgpu_dm_i2c_xfer, 7774 .functionality = amdgpu_dm_i2c_func, 7775 }; 7776 7777 static struct amdgpu_i2c_adapter * 7778 create_i2c(struct ddc_service *ddc_service, 7779 int link_index, 7780 int *res) 7781 { 7782 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 7783 struct amdgpu_i2c_adapter *i2c; 7784 7785 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 7786 if (!i2c) 7787 return NULL; 7788 i2c->base.owner = THIS_MODULE; 7789 i2c->base.dev.parent = &adev->pdev->dev; 7790 i2c->base.algo = &amdgpu_dm_i2c_algo; 7791 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 7792 i2c_set_adapdata(&i2c->base, i2c); 7793 i2c->ddc_service = ddc_service; 7794 7795 return i2c; 7796 } 7797 7798 7799 /* 7800 * Note: this function assumes that dc_link_detect() was called for the 7801 * dc_link which will be represented by this aconnector. 7802 */ 7803 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 7804 struct amdgpu_dm_connector *aconnector, 7805 u32 link_index, 7806 struct amdgpu_encoder *aencoder) 7807 { 7808 int res = 0; 7809 int connector_type; 7810 struct dc *dc = dm->dc; 7811 struct dc_link *link = dc_get_link_at_index(dc, link_index); 7812 struct amdgpu_i2c_adapter *i2c; 7813 7814 /* Not needed for writeback connector */ 7815 link->priv = aconnector; 7816 7817 7818 i2c = create_i2c(link->ddc, link->link_index, &res); 7819 if (!i2c) { 7820 DRM_ERROR("Failed to create i2c adapter data\n"); 7821 return -ENOMEM; 7822 } 7823 7824 aconnector->i2c = i2c; 7825 res = i2c_add_adapter(&i2c->base); 7826 7827 if (res) { 7828 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 7829 goto out_free; 7830 } 7831 7832 connector_type = to_drm_connector_type(link->connector_signal); 7833 7834 res = drm_connector_init_with_ddc( 7835 dm->ddev, 7836 &aconnector->base, 7837 &amdgpu_dm_connector_funcs, 7838 connector_type, 7839 &i2c->base); 7840 7841 if (res) { 7842 DRM_ERROR("connector_init failed\n"); 7843 aconnector->connector_id = -1; 7844 goto out_free; 7845 } 7846 7847 drm_connector_helper_add( 7848 &aconnector->base, 7849 &amdgpu_dm_connector_helper_funcs); 7850 7851 amdgpu_dm_connector_init_helper( 7852 dm, 7853 aconnector, 7854 connector_type, 7855 link, 7856 link_index); 7857 7858 drm_connector_attach_encoder( 7859 &aconnector->base, &aencoder->base); 7860 7861 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 7862 || connector_type == DRM_MODE_CONNECTOR_eDP) 7863 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 7864 7865 out_free: 7866 if (res) { 7867 kfree(i2c); 7868 aconnector->i2c = NULL; 7869 } 7870 return res; 7871 } 7872 7873 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 7874 { 7875 switch (adev->mode_info.num_crtc) { 7876 case 1: 7877 return 0x1; 7878 case 2: 7879 return 0x3; 7880 case 3: 7881 return 0x7; 7882 case 4: 7883 return 0xf; 7884 case 5: 7885 return 0x1f; 7886 case 6: 7887 default: 7888 return 0x3f; 7889 } 7890 } 7891 7892 static int amdgpu_dm_encoder_init(struct drm_device *dev, 7893 struct amdgpu_encoder *aencoder, 7894 uint32_t link_index) 7895 { 7896 struct amdgpu_device *adev = drm_to_adev(dev); 7897 7898 int res = drm_encoder_init(dev, 7899 &aencoder->base, 7900 &amdgpu_dm_encoder_funcs, 7901 DRM_MODE_ENCODER_TMDS, 7902 NULL); 7903 7904 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 7905 7906 if (!res) 7907 aencoder->encoder_id = link_index; 7908 else 7909 aencoder->encoder_id = -1; 7910 7911 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 7912 7913 return res; 7914 } 7915 7916 static void manage_dm_interrupts(struct amdgpu_device *adev, 7917 struct amdgpu_crtc *acrtc, 7918 bool enable) 7919 { 7920 /* 7921 * We have no guarantee that the frontend index maps to the same 7922 * backend index - some even map to more than one. 7923 * 7924 * TODO: Use a different interrupt or check DC itself for the mapping. 7925 */ 7926 int irq_type = 7927 amdgpu_display_crtc_idx_to_irq_type( 7928 adev, 7929 acrtc->crtc_id); 7930 7931 if (enable) { 7932 drm_crtc_vblank_on(&acrtc->base); 7933 amdgpu_irq_get( 7934 adev, 7935 &adev->pageflip_irq, 7936 irq_type); 7937 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7938 amdgpu_irq_get( 7939 adev, 7940 &adev->vline0_irq, 7941 irq_type); 7942 #endif 7943 } else { 7944 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 7945 amdgpu_irq_put( 7946 adev, 7947 &adev->vline0_irq, 7948 irq_type); 7949 #endif 7950 amdgpu_irq_put( 7951 adev, 7952 &adev->pageflip_irq, 7953 irq_type); 7954 drm_crtc_vblank_off(&acrtc->base); 7955 } 7956 } 7957 7958 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 7959 struct amdgpu_crtc *acrtc) 7960 { 7961 int irq_type = 7962 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 7963 7964 /** 7965 * This reads the current state for the IRQ and force reapplies 7966 * the setting to hardware. 7967 */ 7968 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 7969 } 7970 7971 static bool 7972 is_scaling_state_different(const struct dm_connector_state *dm_state, 7973 const struct dm_connector_state *old_dm_state) 7974 { 7975 if (dm_state->scaling != old_dm_state->scaling) 7976 return true; 7977 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 7978 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 7979 return true; 7980 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 7981 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 7982 return true; 7983 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 7984 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 7985 return true; 7986 return false; 7987 } 7988 7989 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 7990 struct drm_crtc_state *old_crtc_state, 7991 struct drm_connector_state *new_conn_state, 7992 struct drm_connector_state *old_conn_state, 7993 const struct drm_connector *connector, 7994 struct hdcp_workqueue *hdcp_w) 7995 { 7996 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7997 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 7998 7999 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8000 connector->index, connector->status, connector->dpms); 8001 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8002 old_conn_state->content_protection, new_conn_state->content_protection); 8003 8004 if (old_crtc_state) 8005 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8006 old_crtc_state->enable, 8007 old_crtc_state->active, 8008 old_crtc_state->mode_changed, 8009 old_crtc_state->active_changed, 8010 old_crtc_state->connectors_changed); 8011 8012 if (new_crtc_state) 8013 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8014 new_crtc_state->enable, 8015 new_crtc_state->active, 8016 new_crtc_state->mode_changed, 8017 new_crtc_state->active_changed, 8018 new_crtc_state->connectors_changed); 8019 8020 /* hdcp content type change */ 8021 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 8022 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 8023 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8024 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 8025 return true; 8026 } 8027 8028 /* CP is being re enabled, ignore this */ 8029 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 8030 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8031 if (new_crtc_state && new_crtc_state->mode_changed) { 8032 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8033 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 8034 return true; 8035 } 8036 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 8037 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 8038 return false; 8039 } 8040 8041 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 8042 * 8043 * Handles: UNDESIRED -> ENABLED 8044 */ 8045 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 8046 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 8047 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8048 8049 /* Stream removed and re-enabled 8050 * 8051 * Can sometimes overlap with the HPD case, 8052 * thus set update_hdcp to false to avoid 8053 * setting HDCP multiple times. 8054 * 8055 * Handles: DESIRED -> DESIRED (Special case) 8056 */ 8057 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 8058 new_conn_state->crtc && new_conn_state->crtc->enabled && 8059 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8060 dm_con_state->update_hdcp = false; 8061 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 8062 __func__); 8063 return true; 8064 } 8065 8066 /* Hot-plug, headless s3, dpms 8067 * 8068 * Only start HDCP if the display is connected/enabled. 8069 * update_hdcp flag will be set to false until the next 8070 * HPD comes in. 8071 * 8072 * Handles: DESIRED -> DESIRED (Special case) 8073 */ 8074 if (dm_con_state->update_hdcp && 8075 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 8076 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 8077 dm_con_state->update_hdcp = false; 8078 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 8079 __func__); 8080 return true; 8081 } 8082 8083 if (old_conn_state->content_protection == new_conn_state->content_protection) { 8084 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8085 if (new_crtc_state && new_crtc_state->mode_changed) { 8086 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 8087 __func__); 8088 return true; 8089 } 8090 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 8091 __func__); 8092 return false; 8093 } 8094 8095 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 8096 return false; 8097 } 8098 8099 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8100 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 8101 __func__); 8102 return true; 8103 } 8104 8105 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 8106 return false; 8107 } 8108 8109 static void remove_stream(struct amdgpu_device *adev, 8110 struct amdgpu_crtc *acrtc, 8111 struct dc_stream_state *stream) 8112 { 8113 /* this is the update mode case */ 8114 8115 acrtc->otg_inst = -1; 8116 acrtc->enabled = false; 8117 } 8118 8119 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 8120 { 8121 8122 assert_spin_locked(&acrtc->base.dev->event_lock); 8123 WARN_ON(acrtc->event); 8124 8125 acrtc->event = acrtc->base.state->event; 8126 8127 /* Set the flip status */ 8128 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 8129 8130 /* Mark this event as consumed */ 8131 acrtc->base.state->event = NULL; 8132 8133 drm_dbg_state(acrtc->base.dev, 8134 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 8135 acrtc->crtc_id); 8136 } 8137 8138 static void update_freesync_state_on_stream( 8139 struct amdgpu_display_manager *dm, 8140 struct dm_crtc_state *new_crtc_state, 8141 struct dc_stream_state *new_stream, 8142 struct dc_plane_state *surface, 8143 u32 flip_timestamp_in_us) 8144 { 8145 struct mod_vrr_params vrr_params; 8146 struct dc_info_packet vrr_infopacket = {0}; 8147 struct amdgpu_device *adev = dm->adev; 8148 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8149 unsigned long flags; 8150 bool pack_sdp_v1_3 = false; 8151 struct amdgpu_dm_connector *aconn; 8152 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 8153 8154 if (!new_stream) 8155 return; 8156 8157 /* 8158 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8159 * For now it's sufficient to just guard against these conditions. 8160 */ 8161 8162 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8163 return; 8164 8165 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8166 vrr_params = acrtc->dm_irq_params.vrr_params; 8167 8168 if (surface) { 8169 mod_freesync_handle_preflip( 8170 dm->freesync_module, 8171 surface, 8172 new_stream, 8173 flip_timestamp_in_us, 8174 &vrr_params); 8175 8176 if (adev->family < AMDGPU_FAMILY_AI && 8177 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 8178 mod_freesync_handle_v_update(dm->freesync_module, 8179 new_stream, &vrr_params); 8180 8181 /* Need to call this before the frame ends. */ 8182 dc_stream_adjust_vmin_vmax(dm->dc, 8183 new_crtc_state->stream, 8184 &vrr_params.adjust); 8185 } 8186 } 8187 8188 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 8189 8190 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 8191 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 8192 8193 if (aconn->vsdb_info.amd_vsdb_version == 1) 8194 packet_type = PACKET_TYPE_FS_V1; 8195 else if (aconn->vsdb_info.amd_vsdb_version == 2) 8196 packet_type = PACKET_TYPE_FS_V2; 8197 else if (aconn->vsdb_info.amd_vsdb_version == 3) 8198 packet_type = PACKET_TYPE_FS_V3; 8199 8200 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 8201 &new_stream->adaptive_sync_infopacket); 8202 } 8203 8204 mod_freesync_build_vrr_infopacket( 8205 dm->freesync_module, 8206 new_stream, 8207 &vrr_params, 8208 packet_type, 8209 TRANSFER_FUNC_UNKNOWN, 8210 &vrr_infopacket, 8211 pack_sdp_v1_3); 8212 8213 new_crtc_state->freesync_vrr_info_changed |= 8214 (memcmp(&new_crtc_state->vrr_infopacket, 8215 &vrr_infopacket, 8216 sizeof(vrr_infopacket)) != 0); 8217 8218 acrtc->dm_irq_params.vrr_params = vrr_params; 8219 new_crtc_state->vrr_infopacket = vrr_infopacket; 8220 8221 new_stream->vrr_infopacket = vrr_infopacket; 8222 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 8223 8224 if (new_crtc_state->freesync_vrr_info_changed) 8225 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 8226 new_crtc_state->base.crtc->base.id, 8227 (int)new_crtc_state->base.vrr_enabled, 8228 (int)vrr_params.state); 8229 8230 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8231 } 8232 8233 static void update_stream_irq_parameters( 8234 struct amdgpu_display_manager *dm, 8235 struct dm_crtc_state *new_crtc_state) 8236 { 8237 struct dc_stream_state *new_stream = new_crtc_state->stream; 8238 struct mod_vrr_params vrr_params; 8239 struct mod_freesync_config config = new_crtc_state->freesync_config; 8240 struct amdgpu_device *adev = dm->adev; 8241 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8242 unsigned long flags; 8243 8244 if (!new_stream) 8245 return; 8246 8247 /* 8248 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8249 * For now it's sufficient to just guard against these conditions. 8250 */ 8251 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8252 return; 8253 8254 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8255 vrr_params = acrtc->dm_irq_params.vrr_params; 8256 8257 if (new_crtc_state->vrr_supported && 8258 config.min_refresh_in_uhz && 8259 config.max_refresh_in_uhz) { 8260 /* 8261 * if freesync compatible mode was set, config.state will be set 8262 * in atomic check 8263 */ 8264 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 8265 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 8266 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 8267 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 8268 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 8269 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 8270 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 8271 } else { 8272 config.state = new_crtc_state->base.vrr_enabled ? 8273 VRR_STATE_ACTIVE_VARIABLE : 8274 VRR_STATE_INACTIVE; 8275 } 8276 } else { 8277 config.state = VRR_STATE_UNSUPPORTED; 8278 } 8279 8280 mod_freesync_build_vrr_params(dm->freesync_module, 8281 new_stream, 8282 &config, &vrr_params); 8283 8284 new_crtc_state->freesync_config = config; 8285 /* Copy state for access from DM IRQ handler */ 8286 acrtc->dm_irq_params.freesync_config = config; 8287 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 8288 acrtc->dm_irq_params.vrr_params = vrr_params; 8289 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8290 } 8291 8292 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 8293 struct dm_crtc_state *new_state) 8294 { 8295 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 8296 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 8297 8298 if (!old_vrr_active && new_vrr_active) { 8299 /* Transition VRR inactive -> active: 8300 * While VRR is active, we must not disable vblank irq, as a 8301 * reenable after disable would compute bogus vblank/pflip 8302 * timestamps if it likely happened inside display front-porch. 8303 * 8304 * We also need vupdate irq for the actual core vblank handling 8305 * at end of vblank. 8306 */ 8307 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 8308 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 8309 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 8310 __func__, new_state->base.crtc->base.id); 8311 } else if (old_vrr_active && !new_vrr_active) { 8312 /* Transition VRR active -> inactive: 8313 * Allow vblank irq disable again for fixed refresh rate. 8314 */ 8315 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 8316 drm_crtc_vblank_put(new_state->base.crtc); 8317 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8318 __func__, new_state->base.crtc->base.id); 8319 } 8320 } 8321 8322 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8323 { 8324 struct drm_plane *plane; 8325 struct drm_plane_state *old_plane_state; 8326 int i; 8327 8328 /* 8329 * TODO: Make this per-stream so we don't issue redundant updates for 8330 * commits with multiple streams. 8331 */ 8332 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8333 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8334 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 8335 } 8336 8337 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 8338 { 8339 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 8340 8341 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 8342 } 8343 8344 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8345 struct drm_device *dev, 8346 struct amdgpu_display_manager *dm, 8347 struct drm_crtc *pcrtc, 8348 bool wait_for_vblank) 8349 { 8350 u32 i; 8351 u64 timestamp_ns = ktime_get_ns(); 8352 struct drm_plane *plane; 8353 struct drm_plane_state *old_plane_state, *new_plane_state; 8354 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8355 struct drm_crtc_state *new_pcrtc_state = 8356 drm_atomic_get_new_crtc_state(state, pcrtc); 8357 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8358 struct dm_crtc_state *dm_old_crtc_state = 8359 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8360 int planes_count = 0, vpos, hpos; 8361 unsigned long flags; 8362 u32 target_vblank, last_flip_vblank; 8363 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8364 bool cursor_update = false; 8365 bool pflip_present = false; 8366 bool dirty_rects_changed = false; 8367 struct { 8368 struct dc_surface_update surface_updates[MAX_SURFACES]; 8369 struct dc_plane_info plane_infos[MAX_SURFACES]; 8370 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8371 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8372 struct dc_stream_update stream_update; 8373 } *bundle; 8374 8375 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8376 8377 if (!bundle) { 8378 drm_err(dev, "Failed to allocate update bundle\n"); 8379 goto cleanup; 8380 } 8381 8382 /* 8383 * Disable the cursor first if we're disabling all the planes. 8384 * It'll remain on the screen after the planes are re-enabled 8385 * if we don't. 8386 */ 8387 if (acrtc_state->active_planes == 0) 8388 amdgpu_dm_commit_cursors(state); 8389 8390 /* update planes when needed */ 8391 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8392 struct drm_crtc *crtc = new_plane_state->crtc; 8393 struct drm_crtc_state *new_crtc_state; 8394 struct drm_framebuffer *fb = new_plane_state->fb; 8395 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8396 bool plane_needs_flip; 8397 struct dc_plane_state *dc_plane; 8398 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8399 8400 /* Cursor plane is handled after stream updates */ 8401 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 8402 if ((fb && crtc == pcrtc) || 8403 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) 8404 cursor_update = true; 8405 8406 continue; 8407 } 8408 8409 if (!fb || !crtc || pcrtc != crtc) 8410 continue; 8411 8412 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8413 if (!new_crtc_state->active) 8414 continue; 8415 8416 dc_plane = dm_new_plane_state->dc_state; 8417 if (!dc_plane) 8418 continue; 8419 8420 bundle->surface_updates[planes_count].surface = dc_plane; 8421 if (new_pcrtc_state->color_mgmt_changed) { 8422 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 8423 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 8424 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8425 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 8426 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func; 8427 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func; 8428 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf; 8429 } 8430 8431 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8432 &bundle->scaling_infos[planes_count]); 8433 8434 bundle->surface_updates[planes_count].scaling_info = 8435 &bundle->scaling_infos[planes_count]; 8436 8437 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8438 8439 pflip_present = pflip_present || plane_needs_flip; 8440 8441 if (!plane_needs_flip) { 8442 planes_count += 1; 8443 continue; 8444 } 8445 8446 fill_dc_plane_info_and_addr( 8447 dm->adev, new_plane_state, 8448 afb->tiling_flags, 8449 &bundle->plane_infos[planes_count], 8450 &bundle->flip_addrs[planes_count].address, 8451 afb->tmz_surface, false); 8452 8453 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8454 new_plane_state->plane->index, 8455 bundle->plane_infos[planes_count].dcc.enable); 8456 8457 bundle->surface_updates[planes_count].plane_info = 8458 &bundle->plane_infos[planes_count]; 8459 8460 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 8461 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8462 fill_dc_dirty_rects(plane, old_plane_state, 8463 new_plane_state, new_crtc_state, 8464 &bundle->flip_addrs[planes_count], 8465 acrtc_state->stream->link->psr_settings.psr_version == 8466 DC_PSR_VERSION_SU_1, 8467 &dirty_rects_changed); 8468 8469 /* 8470 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8471 * and enabled it again after dirty regions are stable to avoid video glitch. 8472 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8473 * during the PSR-SU was disabled. 8474 */ 8475 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8476 acrtc_attach->dm_irq_params.allow_psr_entry && 8477 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8478 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8479 #endif 8480 dirty_rects_changed) { 8481 mutex_lock(&dm->dc_lock); 8482 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8483 timestamp_ns; 8484 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8485 amdgpu_dm_psr_disable(acrtc_state->stream); 8486 mutex_unlock(&dm->dc_lock); 8487 } 8488 } 8489 8490 /* 8491 * Only allow immediate flips for fast updates that don't 8492 * change memory domain, FB pitch, DCC state, rotation or 8493 * mirroring. 8494 * 8495 * dm_crtc_helper_atomic_check() only accepts async flips with 8496 * fast updates. 8497 */ 8498 if (crtc->state->async_flip && 8499 (acrtc_state->update_type != UPDATE_TYPE_FAST || 8500 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 8501 drm_warn_once(state->dev, 8502 "[PLANE:%d:%s] async flip with non-fast update\n", 8503 plane->base.id, plane->name); 8504 8505 bundle->flip_addrs[planes_count].flip_immediate = 8506 crtc->state->async_flip && 8507 acrtc_state->update_type == UPDATE_TYPE_FAST && 8508 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8509 8510 timestamp_ns = ktime_get_ns(); 8511 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8512 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8513 bundle->surface_updates[planes_count].surface = dc_plane; 8514 8515 if (!bundle->surface_updates[planes_count].surface) { 8516 DRM_ERROR("No surface for CRTC: id=%d\n", 8517 acrtc_attach->crtc_id); 8518 continue; 8519 } 8520 8521 if (plane == pcrtc->primary) 8522 update_freesync_state_on_stream( 8523 dm, 8524 acrtc_state, 8525 acrtc_state->stream, 8526 dc_plane, 8527 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8528 8529 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8530 __func__, 8531 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8532 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8533 8534 planes_count += 1; 8535 8536 } 8537 8538 if (pflip_present) { 8539 if (!vrr_active) { 8540 /* Use old throttling in non-vrr fixed refresh rate mode 8541 * to keep flip scheduling based on target vblank counts 8542 * working in a backwards compatible way, e.g., for 8543 * clients using the GLX_OML_sync_control extension or 8544 * DRI3/Present extension with defined target_msc. 8545 */ 8546 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8547 } else { 8548 /* For variable refresh rate mode only: 8549 * Get vblank of last completed flip to avoid > 1 vrr 8550 * flips per video frame by use of throttling, but allow 8551 * flip programming anywhere in the possibly large 8552 * variable vrr vblank interval for fine-grained flip 8553 * timing control and more opportunity to avoid stutter 8554 * on late submission of flips. 8555 */ 8556 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8557 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8558 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8559 } 8560 8561 target_vblank = last_flip_vblank + wait_for_vblank; 8562 8563 /* 8564 * Wait until we're out of the vertical blank period before the one 8565 * targeted by the flip 8566 */ 8567 while ((acrtc_attach->enabled && 8568 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8569 0, &vpos, &hpos, NULL, 8570 NULL, &pcrtc->hwmode) 8571 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8572 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8573 (int)(target_vblank - 8574 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8575 usleep_range(1000, 1100); 8576 } 8577 8578 /** 8579 * Prepare the flip event for the pageflip interrupt to handle. 8580 * 8581 * This only works in the case where we've already turned on the 8582 * appropriate hardware blocks (eg. HUBP) so in the transition case 8583 * from 0 -> n planes we have to skip a hardware generated event 8584 * and rely on sending it from software. 8585 */ 8586 if (acrtc_attach->base.state->event && 8587 acrtc_state->active_planes > 0) { 8588 drm_crtc_vblank_get(pcrtc); 8589 8590 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8591 8592 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8593 prepare_flip_isr(acrtc_attach); 8594 8595 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8596 } 8597 8598 if (acrtc_state->stream) { 8599 if (acrtc_state->freesync_vrr_info_changed) 8600 bundle->stream_update.vrr_infopacket = 8601 &acrtc_state->stream->vrr_infopacket; 8602 } 8603 } else if (cursor_update && acrtc_state->active_planes > 0 && 8604 acrtc_attach->base.state->event) { 8605 drm_crtc_vblank_get(pcrtc); 8606 8607 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8608 8609 acrtc_attach->event = acrtc_attach->base.state->event; 8610 acrtc_attach->base.state->event = NULL; 8611 8612 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8613 } 8614 8615 /* Update the planes if changed or disable if we don't have any. */ 8616 if ((planes_count || acrtc_state->active_planes == 0) && 8617 acrtc_state->stream) { 8618 /* 8619 * If PSR or idle optimizations are enabled then flush out 8620 * any pending work before hardware programming. 8621 */ 8622 if (dm->vblank_control_workqueue) 8623 flush_workqueue(dm->vblank_control_workqueue); 8624 8625 bundle->stream_update.stream = acrtc_state->stream; 8626 if (new_pcrtc_state->mode_changed) { 8627 bundle->stream_update.src = acrtc_state->stream->src; 8628 bundle->stream_update.dst = acrtc_state->stream->dst; 8629 } 8630 8631 if (new_pcrtc_state->color_mgmt_changed) { 8632 /* 8633 * TODO: This isn't fully correct since we've actually 8634 * already modified the stream in place. 8635 */ 8636 bundle->stream_update.gamut_remap = 8637 &acrtc_state->stream->gamut_remap_matrix; 8638 bundle->stream_update.output_csc_transform = 8639 &acrtc_state->stream->csc_color_matrix; 8640 bundle->stream_update.out_transfer_func = 8641 &acrtc_state->stream->out_transfer_func; 8642 bundle->stream_update.lut3d_func = 8643 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 8644 bundle->stream_update.func_shaper = 8645 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 8646 } 8647 8648 acrtc_state->stream->abm_level = acrtc_state->abm_level; 8649 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 8650 bundle->stream_update.abm_level = &acrtc_state->abm_level; 8651 8652 mutex_lock(&dm->dc_lock); 8653 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 8654 acrtc_state->stream->link->psr_settings.psr_allow_active) 8655 amdgpu_dm_psr_disable(acrtc_state->stream); 8656 mutex_unlock(&dm->dc_lock); 8657 8658 /* 8659 * If FreeSync state on the stream has changed then we need to 8660 * re-adjust the min/max bounds now that DC doesn't handle this 8661 * as part of commit. 8662 */ 8663 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 8664 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8665 dc_stream_adjust_vmin_vmax( 8666 dm->dc, acrtc_state->stream, 8667 &acrtc_attach->dm_irq_params.vrr_params.adjust); 8668 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8669 } 8670 mutex_lock(&dm->dc_lock); 8671 update_planes_and_stream_adapter(dm->dc, 8672 acrtc_state->update_type, 8673 planes_count, 8674 acrtc_state->stream, 8675 &bundle->stream_update, 8676 bundle->surface_updates); 8677 8678 /** 8679 * Enable or disable the interrupts on the backend. 8680 * 8681 * Most pipes are put into power gating when unused. 8682 * 8683 * When power gating is enabled on a pipe we lose the 8684 * interrupt enablement state when power gating is disabled. 8685 * 8686 * So we need to update the IRQ control state in hardware 8687 * whenever the pipe turns on (since it could be previously 8688 * power gated) or off (since some pipes can't be power gated 8689 * on some ASICs). 8690 */ 8691 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 8692 dm_update_pflip_irq_state(drm_to_adev(dev), 8693 acrtc_attach); 8694 8695 if (acrtc_state->update_type > UPDATE_TYPE_FAST) { 8696 if (acrtc_state->stream->link->replay_settings.config.replay_supported && 8697 !acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8698 struct amdgpu_dm_connector *aconn = 8699 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8700 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); 8701 } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 8702 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8703 8704 struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *) 8705 acrtc_state->stream->dm_stream_context; 8706 8707 if (!aconn->disallow_edp_enter_psr) 8708 amdgpu_dm_link_setup_psr(acrtc_state->stream); 8709 } 8710 } 8711 8712 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 8713 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 8714 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 8715 struct amdgpu_dm_connector *aconn = 8716 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 8717 8718 if (aconn->psr_skip_count > 0) 8719 aconn->psr_skip_count--; 8720 8721 /* Allow PSR when skip count is 0. */ 8722 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 8723 8724 /* 8725 * If sink supports PSR SU, there is no need to rely on 8726 * a vblank event disable request to enable PSR. PSR SU 8727 * can be enabled immediately once OS demonstrates an 8728 * adequate number of fast atomic commits to notify KMD 8729 * of update events. See `vblank_control_worker()`. 8730 */ 8731 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8732 acrtc_attach->dm_irq_params.allow_psr_entry && 8733 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8734 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8735 #endif 8736 !acrtc_state->stream->link->psr_settings.psr_allow_active && 8737 !aconn->disallow_edp_enter_psr && 8738 (timestamp_ns - 8739 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 8740 500000000) 8741 amdgpu_dm_psr_enable(acrtc_state->stream); 8742 } else { 8743 acrtc_attach->dm_irq_params.allow_psr_entry = false; 8744 } 8745 8746 mutex_unlock(&dm->dc_lock); 8747 } 8748 8749 /* 8750 * Update cursor state *after* programming all the planes. 8751 * This avoids redundant programming in the case where we're going 8752 * to be disabling a single plane - those pipes are being disabled. 8753 */ 8754 if (acrtc_state->active_planes) 8755 amdgpu_dm_commit_cursors(state); 8756 8757 cleanup: 8758 kfree(bundle); 8759 } 8760 8761 static void amdgpu_dm_commit_audio(struct drm_device *dev, 8762 struct drm_atomic_state *state) 8763 { 8764 struct amdgpu_device *adev = drm_to_adev(dev); 8765 struct amdgpu_dm_connector *aconnector; 8766 struct drm_connector *connector; 8767 struct drm_connector_state *old_con_state, *new_con_state; 8768 struct drm_crtc_state *new_crtc_state; 8769 struct dm_crtc_state *new_dm_crtc_state; 8770 const struct dc_stream_status *status; 8771 int i, inst; 8772 8773 /* Notify device removals. */ 8774 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 8775 if (old_con_state->crtc != new_con_state->crtc) { 8776 /* CRTC changes require notification. */ 8777 goto notify; 8778 } 8779 8780 if (!new_con_state->crtc) 8781 continue; 8782 8783 new_crtc_state = drm_atomic_get_new_crtc_state( 8784 state, new_con_state->crtc); 8785 8786 if (!new_crtc_state) 8787 continue; 8788 8789 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8790 continue; 8791 8792 notify: 8793 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 8794 continue; 8795 8796 aconnector = to_amdgpu_dm_connector(connector); 8797 8798 mutex_lock(&adev->dm.audio_lock); 8799 inst = aconnector->audio_inst; 8800 aconnector->audio_inst = -1; 8801 mutex_unlock(&adev->dm.audio_lock); 8802 8803 amdgpu_dm_audio_eld_notify(adev, inst); 8804 } 8805 8806 /* Notify audio device additions. */ 8807 for_each_new_connector_in_state(state, connector, new_con_state, i) { 8808 if (!new_con_state->crtc) 8809 continue; 8810 8811 new_crtc_state = drm_atomic_get_new_crtc_state( 8812 state, new_con_state->crtc); 8813 8814 if (!new_crtc_state) 8815 continue; 8816 8817 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 8818 continue; 8819 8820 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 8821 if (!new_dm_crtc_state->stream) 8822 continue; 8823 8824 status = dc_stream_get_status(new_dm_crtc_state->stream); 8825 if (!status) 8826 continue; 8827 8828 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 8829 continue; 8830 8831 aconnector = to_amdgpu_dm_connector(connector); 8832 8833 mutex_lock(&adev->dm.audio_lock); 8834 inst = status->audio_inst; 8835 aconnector->audio_inst = inst; 8836 mutex_unlock(&adev->dm.audio_lock); 8837 8838 amdgpu_dm_audio_eld_notify(adev, inst); 8839 } 8840 } 8841 8842 /* 8843 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 8844 * @crtc_state: the DRM CRTC state 8845 * @stream_state: the DC stream state. 8846 * 8847 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 8848 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 8849 */ 8850 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 8851 struct dc_stream_state *stream_state) 8852 { 8853 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 8854 } 8855 8856 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 8857 struct dm_crtc_state *crtc_state) 8858 { 8859 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 8860 } 8861 8862 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 8863 struct dc_state *dc_state) 8864 { 8865 struct drm_device *dev = state->dev; 8866 struct amdgpu_device *adev = drm_to_adev(dev); 8867 struct amdgpu_display_manager *dm = &adev->dm; 8868 struct drm_crtc *crtc; 8869 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 8870 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 8871 struct drm_connector_state *old_con_state; 8872 struct drm_connector *connector; 8873 bool mode_set_reset_required = false; 8874 u32 i; 8875 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 8876 8877 /* Disable writeback */ 8878 for_each_old_connector_in_state(state, connector, old_con_state, i) { 8879 struct dm_connector_state *dm_old_con_state; 8880 struct amdgpu_crtc *acrtc; 8881 8882 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 8883 continue; 8884 8885 old_crtc_state = NULL; 8886 8887 dm_old_con_state = to_dm_connector_state(old_con_state); 8888 if (!dm_old_con_state->base.crtc) 8889 continue; 8890 8891 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 8892 if (acrtc) 8893 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 8894 8895 if (!acrtc->wb_enabled) 8896 continue; 8897 8898 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8899 8900 dm_clear_writeback(dm, dm_old_crtc_state); 8901 acrtc->wb_enabled = false; 8902 } 8903 8904 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 8905 new_crtc_state, i) { 8906 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8907 8908 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8909 8910 if (old_crtc_state->active && 8911 (!new_crtc_state->active || 8912 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 8913 manage_dm_interrupts(adev, acrtc, false); 8914 dc_stream_release(dm_old_crtc_state->stream); 8915 } 8916 } 8917 8918 drm_atomic_helper_calc_timestamping_constants(state); 8919 8920 /* update changed items */ 8921 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 8922 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 8923 8924 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 8925 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 8926 8927 drm_dbg_state(state->dev, 8928 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 8929 acrtc->crtc_id, 8930 new_crtc_state->enable, 8931 new_crtc_state->active, 8932 new_crtc_state->planes_changed, 8933 new_crtc_state->mode_changed, 8934 new_crtc_state->active_changed, 8935 new_crtc_state->connectors_changed); 8936 8937 /* Disable cursor if disabling crtc */ 8938 if (old_crtc_state->active && !new_crtc_state->active) { 8939 struct dc_cursor_position position; 8940 8941 memset(&position, 0, sizeof(position)); 8942 mutex_lock(&dm->dc_lock); 8943 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position); 8944 mutex_unlock(&dm->dc_lock); 8945 } 8946 8947 /* Copy all transient state flags into dc state */ 8948 if (dm_new_crtc_state->stream) { 8949 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 8950 dm_new_crtc_state->stream); 8951 } 8952 8953 /* handles headless hotplug case, updating new_state and 8954 * aconnector as needed 8955 */ 8956 8957 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 8958 8959 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); 8960 8961 if (!dm_new_crtc_state->stream) { 8962 /* 8963 * this could happen because of issues with 8964 * userspace notifications delivery. 8965 * In this case userspace tries to set mode on 8966 * display which is disconnected in fact. 8967 * dc_sink is NULL in this case on aconnector. 8968 * We expect reset mode will come soon. 8969 * 8970 * This can also happen when unplug is done 8971 * during resume sequence ended 8972 * 8973 * In this case, we want to pretend we still 8974 * have a sink to keep the pipe running so that 8975 * hw state is consistent with the sw state 8976 */ 8977 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 8978 __func__, acrtc->base.base.id); 8979 continue; 8980 } 8981 8982 if (dm_old_crtc_state->stream) 8983 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8984 8985 pm_runtime_get_noresume(dev->dev); 8986 8987 acrtc->enabled = true; 8988 acrtc->hw_mode = new_crtc_state->mode; 8989 crtc->hwmode = new_crtc_state->mode; 8990 mode_set_reset_required = true; 8991 } else if (modereset_required(new_crtc_state)) { 8992 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 8993 /* i.e. reset mode */ 8994 if (dm_old_crtc_state->stream) 8995 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 8996 8997 mode_set_reset_required = true; 8998 } 8999 } /* for_each_crtc_in_state() */ 9000 9001 /* if there mode set or reset, disable eDP PSR, Replay */ 9002 if (mode_set_reset_required) { 9003 if (dm->vblank_control_workqueue) 9004 flush_workqueue(dm->vblank_control_workqueue); 9005 9006 amdgpu_dm_replay_disable_all(dm); 9007 amdgpu_dm_psr_disable_all(dm); 9008 } 9009 9010 dm_enable_per_frame_crtc_master_sync(dc_state); 9011 mutex_lock(&dm->dc_lock); 9012 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 9013 9014 /* Allow idle optimization when vblank count is 0 for display off */ 9015 if (dm->active_vblank_irq_count == 0) 9016 dc_allow_idle_optimizations(dm->dc, true); 9017 mutex_unlock(&dm->dc_lock); 9018 9019 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9020 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9021 9022 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9023 9024 if (dm_new_crtc_state->stream != NULL) { 9025 const struct dc_stream_status *status = 9026 dc_stream_get_status(dm_new_crtc_state->stream); 9027 9028 if (!status) 9029 status = dc_state_get_stream_status(dc_state, 9030 dm_new_crtc_state->stream); 9031 if (!status) 9032 drm_err(dev, 9033 "got no status for stream %p on acrtc%p\n", 9034 dm_new_crtc_state->stream, acrtc); 9035 else 9036 acrtc->otg_inst = status->primary_otg_inst; 9037 } 9038 } 9039 } 9040 9041 static void dm_set_writeback(struct amdgpu_display_manager *dm, 9042 struct dm_crtc_state *crtc_state, 9043 struct drm_connector *connector, 9044 struct drm_connector_state *new_con_state) 9045 { 9046 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 9047 struct amdgpu_device *adev = dm->adev; 9048 struct amdgpu_crtc *acrtc; 9049 struct dc_writeback_info *wb_info; 9050 struct pipe_ctx *pipe = NULL; 9051 struct amdgpu_framebuffer *afb; 9052 int i = 0; 9053 9054 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 9055 if (!wb_info) { 9056 DRM_ERROR("Failed to allocate wb_info\n"); 9057 return; 9058 } 9059 9060 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 9061 if (!acrtc) { 9062 DRM_ERROR("no amdgpu_crtc found\n"); 9063 kfree(wb_info); 9064 return; 9065 } 9066 9067 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 9068 if (!afb) { 9069 DRM_ERROR("No amdgpu_framebuffer found\n"); 9070 kfree(wb_info); 9071 return; 9072 } 9073 9074 for (i = 0; i < MAX_PIPES; i++) { 9075 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 9076 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 9077 break; 9078 } 9079 } 9080 9081 /* fill in wb_info */ 9082 wb_info->wb_enabled = true; 9083 9084 wb_info->dwb_pipe_inst = 0; 9085 wb_info->dwb_params.dwbscl_black_color = 0; 9086 wb_info->dwb_params.hdr_mult = 0x1F000; 9087 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 9088 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 9089 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 9090 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 9091 9092 /* width & height from crtc */ 9093 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 9094 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 9095 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 9096 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 9097 9098 wb_info->dwb_params.cnv_params.crop_en = false; 9099 wb_info->dwb_params.stereo_params.stereo_enabled = false; 9100 9101 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 9102 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 9103 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 9104 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 9105 9106 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 9107 9108 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 9109 9110 wb_info->dwb_params.scaler_taps.h_taps = 4; 9111 wb_info->dwb_params.scaler_taps.v_taps = 4; 9112 wb_info->dwb_params.scaler_taps.h_taps_c = 2; 9113 wb_info->dwb_params.scaler_taps.v_taps_c = 2; 9114 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 9115 9116 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 9117 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 9118 9119 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 9120 wb_info->mcif_buf_params.luma_address[i] = afb->address; 9121 wb_info->mcif_buf_params.chroma_address[i] = 0; 9122 } 9123 9124 wb_info->mcif_buf_params.p_vmid = 1; 9125 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 9126 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 9127 wb_info->mcif_warmup_params.region_size = 9128 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 9129 } 9130 wb_info->mcif_warmup_params.p_vmid = 1; 9131 wb_info->writeback_source_plane = pipe->plane_state; 9132 9133 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 9134 9135 acrtc->wb_pending = true; 9136 acrtc->wb_conn = wb_conn; 9137 drm_writeback_queue_job(wb_conn, new_con_state); 9138 } 9139 9140 /** 9141 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 9142 * @state: The atomic state to commit 9143 * 9144 * This will tell DC to commit the constructed DC state from atomic_check, 9145 * programming the hardware. Any failures here implies a hardware failure, since 9146 * atomic check should have filtered anything non-kosher. 9147 */ 9148 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 9149 { 9150 struct drm_device *dev = state->dev; 9151 struct amdgpu_device *adev = drm_to_adev(dev); 9152 struct amdgpu_display_manager *dm = &adev->dm; 9153 struct dm_atomic_state *dm_state; 9154 struct dc_state *dc_state = NULL; 9155 u32 i, j; 9156 struct drm_crtc *crtc; 9157 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9158 unsigned long flags; 9159 bool wait_for_vblank = true; 9160 struct drm_connector *connector; 9161 struct drm_connector_state *old_con_state, *new_con_state; 9162 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9163 int crtc_disable_count = 0; 9164 9165 trace_amdgpu_dm_atomic_commit_tail_begin(state); 9166 9167 if (dm->dc->caps.ips_support && dm->dc->idle_optimizations_allowed) 9168 dc_allow_idle_optimizations(dm->dc, false); 9169 9170 drm_atomic_helper_update_legacy_modeset_state(dev, state); 9171 drm_dp_mst_atomic_wait_for_dependencies(state); 9172 9173 dm_state = dm_atomic_get_new_state(state); 9174 if (dm_state && dm_state->context) { 9175 dc_state = dm_state->context; 9176 amdgpu_dm_commit_streams(state, dc_state); 9177 } 9178 9179 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9180 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9181 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9182 struct amdgpu_dm_connector *aconnector; 9183 9184 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9185 continue; 9186 9187 aconnector = to_amdgpu_dm_connector(connector); 9188 9189 if (!adev->dm.hdcp_workqueue) 9190 continue; 9191 9192 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 9193 9194 if (!connector) 9195 continue; 9196 9197 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 9198 connector->index, connector->status, connector->dpms); 9199 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 9200 old_con_state->content_protection, new_con_state->content_protection); 9201 9202 if (aconnector->dc_sink) { 9203 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 9204 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 9205 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 9206 aconnector->dc_sink->edid_caps.display_name); 9207 } 9208 } 9209 9210 new_crtc_state = NULL; 9211 old_crtc_state = NULL; 9212 9213 if (acrtc) { 9214 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9215 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9216 } 9217 9218 if (old_crtc_state) 9219 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9220 old_crtc_state->enable, 9221 old_crtc_state->active, 9222 old_crtc_state->mode_changed, 9223 old_crtc_state->active_changed, 9224 old_crtc_state->connectors_changed); 9225 9226 if (new_crtc_state) 9227 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9228 new_crtc_state->enable, 9229 new_crtc_state->active, 9230 new_crtc_state->mode_changed, 9231 new_crtc_state->active_changed, 9232 new_crtc_state->connectors_changed); 9233 } 9234 9235 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9236 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9237 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9238 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9239 9240 if (!adev->dm.hdcp_workqueue) 9241 continue; 9242 9243 new_crtc_state = NULL; 9244 old_crtc_state = NULL; 9245 9246 if (acrtc) { 9247 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9248 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9249 } 9250 9251 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9252 9253 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 9254 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9255 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 9256 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9257 dm_new_con_state->update_hdcp = true; 9258 continue; 9259 } 9260 9261 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 9262 old_con_state, connector, adev->dm.hdcp_workqueue)) { 9263 /* when display is unplugged from mst hub, connctor will 9264 * be destroyed within dm_dp_mst_connector_destroy. connector 9265 * hdcp perperties, like type, undesired, desired, enabled, 9266 * will be lost. So, save hdcp properties into hdcp_work within 9267 * amdgpu_dm_atomic_commit_tail. if the same display is 9268 * plugged back with same display index, its hdcp properties 9269 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 9270 */ 9271 9272 bool enable_encryption = false; 9273 9274 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 9275 enable_encryption = true; 9276 9277 if (aconnector->dc_link && aconnector->dc_sink && 9278 aconnector->dc_link->type == dc_connection_mst_branch) { 9279 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 9280 struct hdcp_workqueue *hdcp_w = 9281 &hdcp_work[aconnector->dc_link->link_index]; 9282 9283 hdcp_w->hdcp_content_type[connector->index] = 9284 new_con_state->hdcp_content_type; 9285 hdcp_w->content_protection[connector->index] = 9286 new_con_state->content_protection; 9287 } 9288 9289 if (new_crtc_state && new_crtc_state->mode_changed && 9290 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 9291 enable_encryption = true; 9292 9293 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 9294 9295 hdcp_update_display( 9296 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 9297 new_con_state->hdcp_content_type, enable_encryption); 9298 } 9299 } 9300 9301 /* Handle connector state changes */ 9302 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9303 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9304 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9305 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9306 struct dc_surface_update *dummy_updates; 9307 struct dc_stream_update stream_update; 9308 struct dc_info_packet hdr_packet; 9309 struct dc_stream_status *status = NULL; 9310 bool abm_changed, hdr_changed, scaling_changed; 9311 9312 memset(&stream_update, 0, sizeof(stream_update)); 9313 9314 if (acrtc) { 9315 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9316 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9317 } 9318 9319 /* Skip any modesets/resets */ 9320 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 9321 continue; 9322 9323 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9324 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9325 9326 scaling_changed = is_scaling_state_different(dm_new_con_state, 9327 dm_old_con_state); 9328 9329 abm_changed = dm_new_crtc_state->abm_level != 9330 dm_old_crtc_state->abm_level; 9331 9332 hdr_changed = 9333 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 9334 9335 if (!scaling_changed && !abm_changed && !hdr_changed) 9336 continue; 9337 9338 stream_update.stream = dm_new_crtc_state->stream; 9339 if (scaling_changed) { 9340 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 9341 dm_new_con_state, dm_new_crtc_state->stream); 9342 9343 stream_update.src = dm_new_crtc_state->stream->src; 9344 stream_update.dst = dm_new_crtc_state->stream->dst; 9345 } 9346 9347 if (abm_changed) { 9348 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 9349 9350 stream_update.abm_level = &dm_new_crtc_state->abm_level; 9351 } 9352 9353 if (hdr_changed) { 9354 fill_hdr_info_packet(new_con_state, &hdr_packet); 9355 stream_update.hdr_static_metadata = &hdr_packet; 9356 } 9357 9358 status = dc_stream_get_status(dm_new_crtc_state->stream); 9359 9360 if (WARN_ON(!status)) 9361 continue; 9362 9363 WARN_ON(!status->plane_count); 9364 9365 /* 9366 * TODO: DC refuses to perform stream updates without a dc_surface_update. 9367 * Here we create an empty update on each plane. 9368 * To fix this, DC should permit updating only stream properties. 9369 */ 9370 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 9371 if (!dummy_updates) { 9372 DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); 9373 continue; 9374 } 9375 for (j = 0; j < status->plane_count; j++) 9376 dummy_updates[j].surface = status->plane_states[0]; 9377 9378 9379 mutex_lock(&dm->dc_lock); 9380 dc_update_planes_and_stream(dm->dc, 9381 dummy_updates, 9382 status->plane_count, 9383 dm_new_crtc_state->stream, 9384 &stream_update); 9385 mutex_unlock(&dm->dc_lock); 9386 kfree(dummy_updates); 9387 } 9388 9389 /** 9390 * Enable interrupts for CRTCs that are newly enabled or went through 9391 * a modeset. It was intentionally deferred until after the front end 9392 * state was modified to wait until the OTG was on and so the IRQ 9393 * handlers didn't access stale or invalid state. 9394 */ 9395 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9396 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9397 #ifdef CONFIG_DEBUG_FS 9398 enum amdgpu_dm_pipe_crc_source cur_crc_src; 9399 #endif 9400 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 9401 if (old_crtc_state->active && !new_crtc_state->active) 9402 crtc_disable_count++; 9403 9404 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9405 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9406 9407 /* For freesync config update on crtc state and params for irq */ 9408 update_stream_irq_parameters(dm, dm_new_crtc_state); 9409 9410 #ifdef CONFIG_DEBUG_FS 9411 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9412 cur_crc_src = acrtc->dm_irq_params.crc_src; 9413 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9414 #endif 9415 9416 if (new_crtc_state->active && 9417 (!old_crtc_state->active || 9418 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9419 dc_stream_retain(dm_new_crtc_state->stream); 9420 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 9421 manage_dm_interrupts(adev, acrtc, true); 9422 } 9423 /* Handle vrr on->off / off->on transitions */ 9424 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 9425 9426 #ifdef CONFIG_DEBUG_FS 9427 if (new_crtc_state->active && 9428 (!old_crtc_state->active || 9429 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9430 /** 9431 * Frontend may have changed so reapply the CRC capture 9432 * settings for the stream. 9433 */ 9434 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 9435 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9436 if (amdgpu_dm_crc_window_is_activated(crtc)) { 9437 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9438 acrtc->dm_irq_params.window_param.update_win = true; 9439 9440 /** 9441 * It takes 2 frames for HW to stably generate CRC when 9442 * resuming from suspend, so we set skip_frame_cnt 2. 9443 */ 9444 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 9445 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9446 } 9447 #endif 9448 if (amdgpu_dm_crtc_configure_crc_source( 9449 crtc, dm_new_crtc_state, cur_crc_src)) 9450 DRM_DEBUG_DRIVER("Failed to configure crc source"); 9451 } 9452 } 9453 #endif 9454 } 9455 9456 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 9457 if (new_crtc_state->async_flip) 9458 wait_for_vblank = false; 9459 9460 /* update planes when needed per crtc*/ 9461 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 9462 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9463 9464 if (dm_new_crtc_state->stream) 9465 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 9466 } 9467 9468 /* Enable writeback */ 9469 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9470 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9471 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9472 9473 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9474 continue; 9475 9476 if (!new_con_state->writeback_job) 9477 continue; 9478 9479 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9480 9481 if (!new_crtc_state) 9482 continue; 9483 9484 if (acrtc->wb_enabled) 9485 continue; 9486 9487 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9488 9489 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 9490 acrtc->wb_enabled = true; 9491 } 9492 9493 /* Update audio instances for each connector. */ 9494 amdgpu_dm_commit_audio(dev, state); 9495 9496 /* restore the backlight level */ 9497 for (i = 0; i < dm->num_of_edps; i++) { 9498 if (dm->backlight_dev[i] && 9499 (dm->actual_brightness[i] != dm->brightness[i])) 9500 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9501 } 9502 9503 /* 9504 * send vblank event on all events not handled in flip and 9505 * mark consumed event for drm_atomic_helper_commit_hw_done 9506 */ 9507 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9508 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9509 9510 if (new_crtc_state->event) 9511 drm_send_event_locked(dev, &new_crtc_state->event->base); 9512 9513 new_crtc_state->event = NULL; 9514 } 9515 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9516 9517 /* Signal HW programming completion */ 9518 drm_atomic_helper_commit_hw_done(state); 9519 9520 if (wait_for_vblank) 9521 drm_atomic_helper_wait_for_flip_done(dev, state); 9522 9523 drm_atomic_helper_cleanup_planes(dev, state); 9524 9525 /* Don't free the memory if we are hitting this as part of suspend. 9526 * This way we don't free any memory during suspend; see 9527 * amdgpu_bo_free_kernel(). The memory will be freed in the first 9528 * non-suspend modeset or when the driver is torn down. 9529 */ 9530 if (!adev->in_suspend) { 9531 /* return the stolen vga memory back to VRAM */ 9532 if (!adev->mman.keep_stolen_vga_memory) 9533 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9534 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9535 } 9536 9537 /* 9538 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9539 * so we can put the GPU into runtime suspend if we're not driving any 9540 * displays anymore 9541 */ 9542 for (i = 0; i < crtc_disable_count; i++) 9543 pm_runtime_put_autosuspend(dev->dev); 9544 pm_runtime_mark_last_busy(dev->dev); 9545 } 9546 9547 static int dm_force_atomic_commit(struct drm_connector *connector) 9548 { 9549 int ret = 0; 9550 struct drm_device *ddev = connector->dev; 9551 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9552 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9553 struct drm_plane *plane = disconnected_acrtc->base.primary; 9554 struct drm_connector_state *conn_state; 9555 struct drm_crtc_state *crtc_state; 9556 struct drm_plane_state *plane_state; 9557 9558 if (!state) 9559 return -ENOMEM; 9560 9561 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9562 9563 /* Construct an atomic state to restore previous display setting */ 9564 9565 /* 9566 * Attach connectors to drm_atomic_state 9567 */ 9568 conn_state = drm_atomic_get_connector_state(state, connector); 9569 9570 ret = PTR_ERR_OR_ZERO(conn_state); 9571 if (ret) 9572 goto out; 9573 9574 /* Attach crtc to drm_atomic_state*/ 9575 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9576 9577 ret = PTR_ERR_OR_ZERO(crtc_state); 9578 if (ret) 9579 goto out; 9580 9581 /* force a restore */ 9582 crtc_state->mode_changed = true; 9583 9584 /* Attach plane to drm_atomic_state */ 9585 plane_state = drm_atomic_get_plane_state(state, plane); 9586 9587 ret = PTR_ERR_OR_ZERO(plane_state); 9588 if (ret) 9589 goto out; 9590 9591 /* Call commit internally with the state we just constructed */ 9592 ret = drm_atomic_commit(state); 9593 9594 out: 9595 drm_atomic_state_put(state); 9596 if (ret) 9597 DRM_ERROR("Restoring old state failed with %i\n", ret); 9598 9599 return ret; 9600 } 9601 9602 /* 9603 * This function handles all cases when set mode does not come upon hotplug. 9604 * This includes when a display is unplugged then plugged back into the 9605 * same port and when running without usermode desktop manager supprot 9606 */ 9607 void dm_restore_drm_connector_state(struct drm_device *dev, 9608 struct drm_connector *connector) 9609 { 9610 struct amdgpu_dm_connector *aconnector; 9611 struct amdgpu_crtc *disconnected_acrtc; 9612 struct dm_crtc_state *acrtc_state; 9613 9614 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9615 return; 9616 9617 aconnector = to_amdgpu_dm_connector(connector); 9618 9619 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 9620 return; 9621 9622 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9623 if (!disconnected_acrtc) 9624 return; 9625 9626 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 9627 if (!acrtc_state->stream) 9628 return; 9629 9630 /* 9631 * If the previous sink is not released and different from the current, 9632 * we deduce we are in a state where we can not rely on usermode call 9633 * to turn on the display, so we do it here 9634 */ 9635 if (acrtc_state->stream->sink != aconnector->dc_sink) 9636 dm_force_atomic_commit(&aconnector->base); 9637 } 9638 9639 /* 9640 * Grabs all modesetting locks to serialize against any blocking commits, 9641 * Waits for completion of all non blocking commits. 9642 */ 9643 static int do_aquire_global_lock(struct drm_device *dev, 9644 struct drm_atomic_state *state) 9645 { 9646 struct drm_crtc *crtc; 9647 struct drm_crtc_commit *commit; 9648 long ret; 9649 9650 /* 9651 * Adding all modeset locks to aquire_ctx will 9652 * ensure that when the framework release it the 9653 * extra locks we are locking here will get released to 9654 */ 9655 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 9656 if (ret) 9657 return ret; 9658 9659 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9660 spin_lock(&crtc->commit_lock); 9661 commit = list_first_entry_or_null(&crtc->commit_list, 9662 struct drm_crtc_commit, commit_entry); 9663 if (commit) 9664 drm_crtc_commit_get(commit); 9665 spin_unlock(&crtc->commit_lock); 9666 9667 if (!commit) 9668 continue; 9669 9670 /* 9671 * Make sure all pending HW programming completed and 9672 * page flips done 9673 */ 9674 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 9675 9676 if (ret > 0) 9677 ret = wait_for_completion_interruptible_timeout( 9678 &commit->flip_done, 10*HZ); 9679 9680 if (ret == 0) 9681 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 9682 crtc->base.id, crtc->name); 9683 9684 drm_crtc_commit_put(commit); 9685 } 9686 9687 return ret < 0 ? ret : 0; 9688 } 9689 9690 static void get_freesync_config_for_crtc( 9691 struct dm_crtc_state *new_crtc_state, 9692 struct dm_connector_state *new_con_state) 9693 { 9694 struct mod_freesync_config config = {0}; 9695 struct amdgpu_dm_connector *aconnector; 9696 struct drm_display_mode *mode = &new_crtc_state->base.mode; 9697 int vrefresh = drm_mode_vrefresh(mode); 9698 bool fs_vid_mode = false; 9699 9700 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9701 return; 9702 9703 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 9704 9705 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 9706 vrefresh >= aconnector->min_vfreq && 9707 vrefresh <= aconnector->max_vfreq; 9708 9709 if (new_crtc_state->vrr_supported) { 9710 new_crtc_state->stream->ignore_msa_timing_param = true; 9711 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 9712 9713 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 9714 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 9715 config.vsif_supported = true; 9716 config.btr = true; 9717 9718 if (fs_vid_mode) { 9719 config.state = VRR_STATE_ACTIVE_FIXED; 9720 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 9721 goto out; 9722 } else if (new_crtc_state->base.vrr_enabled) { 9723 config.state = VRR_STATE_ACTIVE_VARIABLE; 9724 } else { 9725 config.state = VRR_STATE_INACTIVE; 9726 } 9727 } 9728 out: 9729 new_crtc_state->freesync_config = config; 9730 } 9731 9732 static void reset_freesync_config_for_crtc( 9733 struct dm_crtc_state *new_crtc_state) 9734 { 9735 new_crtc_state->vrr_supported = false; 9736 9737 memset(&new_crtc_state->vrr_infopacket, 0, 9738 sizeof(new_crtc_state->vrr_infopacket)); 9739 } 9740 9741 static bool 9742 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 9743 struct drm_crtc_state *new_crtc_state) 9744 { 9745 const struct drm_display_mode *old_mode, *new_mode; 9746 9747 if (!old_crtc_state || !new_crtc_state) 9748 return false; 9749 9750 old_mode = &old_crtc_state->mode; 9751 new_mode = &new_crtc_state->mode; 9752 9753 if (old_mode->clock == new_mode->clock && 9754 old_mode->hdisplay == new_mode->hdisplay && 9755 old_mode->vdisplay == new_mode->vdisplay && 9756 old_mode->htotal == new_mode->htotal && 9757 old_mode->vtotal != new_mode->vtotal && 9758 old_mode->hsync_start == new_mode->hsync_start && 9759 old_mode->vsync_start != new_mode->vsync_start && 9760 old_mode->hsync_end == new_mode->hsync_end && 9761 old_mode->vsync_end != new_mode->vsync_end && 9762 old_mode->hskew == new_mode->hskew && 9763 old_mode->vscan == new_mode->vscan && 9764 (old_mode->vsync_end - old_mode->vsync_start) == 9765 (new_mode->vsync_end - new_mode->vsync_start)) 9766 return true; 9767 9768 return false; 9769 } 9770 9771 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 9772 { 9773 u64 num, den, res; 9774 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 9775 9776 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 9777 9778 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 9779 den = (unsigned long long)new_crtc_state->mode.htotal * 9780 (unsigned long long)new_crtc_state->mode.vtotal; 9781 9782 res = div_u64(num, den); 9783 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 9784 } 9785 9786 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 9787 struct drm_atomic_state *state, 9788 struct drm_crtc *crtc, 9789 struct drm_crtc_state *old_crtc_state, 9790 struct drm_crtc_state *new_crtc_state, 9791 bool enable, 9792 bool *lock_and_validation_needed) 9793 { 9794 struct dm_atomic_state *dm_state = NULL; 9795 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9796 struct dc_stream_state *new_stream; 9797 int ret = 0; 9798 9799 /* 9800 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 9801 * update changed items 9802 */ 9803 struct amdgpu_crtc *acrtc = NULL; 9804 struct drm_connector *connector = NULL; 9805 struct amdgpu_dm_connector *aconnector = NULL; 9806 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 9807 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 9808 9809 new_stream = NULL; 9810 9811 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9812 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9813 acrtc = to_amdgpu_crtc(crtc); 9814 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 9815 if (connector) 9816 aconnector = to_amdgpu_dm_connector(connector); 9817 9818 /* TODO This hack should go away */ 9819 if (connector && enable) { 9820 /* Make sure fake sink is created in plug-in scenario */ 9821 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 9822 connector); 9823 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 9824 connector); 9825 9826 if (IS_ERR(drm_new_conn_state)) { 9827 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 9828 goto fail; 9829 } 9830 9831 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 9832 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 9833 9834 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9835 goto skip_modeset; 9836 9837 new_stream = create_validate_stream_for_sink(aconnector, 9838 &new_crtc_state->mode, 9839 dm_new_conn_state, 9840 dm_old_crtc_state->stream); 9841 9842 /* 9843 * we can have no stream on ACTION_SET if a display 9844 * was disconnected during S3, in this case it is not an 9845 * error, the OS will be updated after detection, and 9846 * will do the right thing on next atomic commit 9847 */ 9848 9849 if (!new_stream) { 9850 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 9851 __func__, acrtc->base.base.id); 9852 ret = -ENOMEM; 9853 goto fail; 9854 } 9855 9856 /* 9857 * TODO: Check VSDB bits to decide whether this should 9858 * be enabled or not. 9859 */ 9860 new_stream->triggered_crtc_reset.enabled = 9861 dm->force_timing_sync; 9862 9863 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 9864 9865 ret = fill_hdr_info_packet(drm_new_conn_state, 9866 &new_stream->hdr_static_metadata); 9867 if (ret) 9868 goto fail; 9869 9870 /* 9871 * If we already removed the old stream from the context 9872 * (and set the new stream to NULL) then we can't reuse 9873 * the old stream even if the stream and scaling are unchanged. 9874 * We'll hit the BUG_ON and black screen. 9875 * 9876 * TODO: Refactor this function to allow this check to work 9877 * in all conditions. 9878 */ 9879 if (amdgpu_freesync_vid_mode && 9880 dm_new_crtc_state->stream && 9881 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 9882 goto skip_modeset; 9883 9884 if (dm_new_crtc_state->stream && 9885 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9886 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 9887 new_crtc_state->mode_changed = false; 9888 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 9889 new_crtc_state->mode_changed); 9890 } 9891 } 9892 9893 /* mode_changed flag may get updated above, need to check again */ 9894 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9895 goto skip_modeset; 9896 9897 drm_dbg_state(state->dev, 9898 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9899 acrtc->crtc_id, 9900 new_crtc_state->enable, 9901 new_crtc_state->active, 9902 new_crtc_state->planes_changed, 9903 new_crtc_state->mode_changed, 9904 new_crtc_state->active_changed, 9905 new_crtc_state->connectors_changed); 9906 9907 /* Remove stream for any changed/disabled CRTC */ 9908 if (!enable) { 9909 9910 if (!dm_old_crtc_state->stream) 9911 goto skip_modeset; 9912 9913 /* Unset freesync video if it was active before */ 9914 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 9915 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 9916 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 9917 } 9918 9919 /* Now check if we should set freesync video mode */ 9920 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 9921 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 9922 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 9923 is_timing_unchanged_for_freesync(new_crtc_state, 9924 old_crtc_state)) { 9925 new_crtc_state->mode_changed = false; 9926 DRM_DEBUG_DRIVER( 9927 "Mode change not required for front porch change, setting mode_changed to %d", 9928 new_crtc_state->mode_changed); 9929 9930 set_freesync_fixed_config(dm_new_crtc_state); 9931 9932 goto skip_modeset; 9933 } else if (amdgpu_freesync_vid_mode && aconnector && 9934 is_freesync_video_mode(&new_crtc_state->mode, 9935 aconnector)) { 9936 struct drm_display_mode *high_mode; 9937 9938 high_mode = get_highest_refresh_rate_mode(aconnector, false); 9939 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 9940 set_freesync_fixed_config(dm_new_crtc_state); 9941 } 9942 9943 ret = dm_atomic_get_state(state, &dm_state); 9944 if (ret) 9945 goto fail; 9946 9947 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 9948 crtc->base.id); 9949 9950 /* i.e. reset mode */ 9951 if (dc_state_remove_stream( 9952 dm->dc, 9953 dm_state->context, 9954 dm_old_crtc_state->stream) != DC_OK) { 9955 ret = -EINVAL; 9956 goto fail; 9957 } 9958 9959 dc_stream_release(dm_old_crtc_state->stream); 9960 dm_new_crtc_state->stream = NULL; 9961 9962 reset_freesync_config_for_crtc(dm_new_crtc_state); 9963 9964 *lock_and_validation_needed = true; 9965 9966 } else {/* Add stream for any updated/enabled CRTC */ 9967 /* 9968 * Quick fix to prevent NULL pointer on new_stream when 9969 * added MST connectors not found in existing crtc_state in the chained mode 9970 * TODO: need to dig out the root cause of that 9971 */ 9972 if (!connector) 9973 goto skip_modeset; 9974 9975 if (modereset_required(new_crtc_state)) 9976 goto skip_modeset; 9977 9978 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 9979 dm_old_crtc_state->stream)) { 9980 9981 WARN_ON(dm_new_crtc_state->stream); 9982 9983 ret = dm_atomic_get_state(state, &dm_state); 9984 if (ret) 9985 goto fail; 9986 9987 dm_new_crtc_state->stream = new_stream; 9988 9989 dc_stream_retain(new_stream); 9990 9991 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 9992 crtc->base.id); 9993 9994 if (dc_state_add_stream( 9995 dm->dc, 9996 dm_state->context, 9997 dm_new_crtc_state->stream) != DC_OK) { 9998 ret = -EINVAL; 9999 goto fail; 10000 } 10001 10002 *lock_and_validation_needed = true; 10003 } 10004 } 10005 10006 skip_modeset: 10007 /* Release extra reference */ 10008 if (new_stream) 10009 dc_stream_release(new_stream); 10010 10011 /* 10012 * We want to do dc stream updates that do not require a 10013 * full modeset below. 10014 */ 10015 if (!(enable && connector && new_crtc_state->active)) 10016 return 0; 10017 /* 10018 * Given above conditions, the dc state cannot be NULL because: 10019 * 1. We're in the process of enabling CRTCs (just been added 10020 * to the dc context, or already is on the context) 10021 * 2. Has a valid connector attached, and 10022 * 3. Is currently active and enabled. 10023 * => The dc stream state currently exists. 10024 */ 10025 BUG_ON(dm_new_crtc_state->stream == NULL); 10026 10027 /* Scaling or underscan settings */ 10028 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 10029 drm_atomic_crtc_needs_modeset(new_crtc_state)) 10030 update_stream_scaling_settings( 10031 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 10032 10033 /* ABM settings */ 10034 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10035 10036 /* 10037 * Color management settings. We also update color properties 10038 * when a modeset is needed, to ensure it gets reprogrammed. 10039 */ 10040 if (dm_new_crtc_state->base.color_mgmt_changed || 10041 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 10042 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10043 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 10044 if (ret) 10045 goto fail; 10046 } 10047 10048 /* Update Freesync settings. */ 10049 get_freesync_config_for_crtc(dm_new_crtc_state, 10050 dm_new_conn_state); 10051 10052 return ret; 10053 10054 fail: 10055 if (new_stream) 10056 dc_stream_release(new_stream); 10057 return ret; 10058 } 10059 10060 static bool should_reset_plane(struct drm_atomic_state *state, 10061 struct drm_plane *plane, 10062 struct drm_plane_state *old_plane_state, 10063 struct drm_plane_state *new_plane_state) 10064 { 10065 struct drm_plane *other; 10066 struct drm_plane_state *old_other_state, *new_other_state; 10067 struct drm_crtc_state *new_crtc_state; 10068 struct amdgpu_device *adev = drm_to_adev(plane->dev); 10069 int i; 10070 10071 /* 10072 * TODO: Remove this hack for all asics once it proves that the 10073 * fast updates works fine on DCN3.2+. 10074 */ 10075 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 10076 state->allow_modeset) 10077 return true; 10078 10079 /* Exit early if we know that we're adding or removing the plane. */ 10080 if (old_plane_state->crtc != new_plane_state->crtc) 10081 return true; 10082 10083 /* old crtc == new_crtc == NULL, plane not in context. */ 10084 if (!new_plane_state->crtc) 10085 return false; 10086 10087 new_crtc_state = 10088 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 10089 10090 if (!new_crtc_state) 10091 return true; 10092 10093 /* CRTC Degamma changes currently require us to recreate planes. */ 10094 if (new_crtc_state->color_mgmt_changed) 10095 return true; 10096 10097 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 10098 return true; 10099 10100 /* 10101 * If there are any new primary or overlay planes being added or 10102 * removed then the z-order can potentially change. To ensure 10103 * correct z-order and pipe acquisition the current DC architecture 10104 * requires us to remove and recreate all existing planes. 10105 * 10106 * TODO: Come up with a more elegant solution for this. 10107 */ 10108 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 10109 struct amdgpu_framebuffer *old_afb, *new_afb; 10110 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 10111 10112 dm_new_other_state = to_dm_plane_state(new_other_state); 10113 dm_old_other_state = to_dm_plane_state(old_other_state); 10114 10115 if (other->type == DRM_PLANE_TYPE_CURSOR) 10116 continue; 10117 10118 if (old_other_state->crtc != new_plane_state->crtc && 10119 new_other_state->crtc != new_plane_state->crtc) 10120 continue; 10121 10122 if (old_other_state->crtc != new_other_state->crtc) 10123 return true; 10124 10125 /* Src/dst size and scaling updates. */ 10126 if (old_other_state->src_w != new_other_state->src_w || 10127 old_other_state->src_h != new_other_state->src_h || 10128 old_other_state->crtc_w != new_other_state->crtc_w || 10129 old_other_state->crtc_h != new_other_state->crtc_h) 10130 return true; 10131 10132 /* Rotation / mirroring updates. */ 10133 if (old_other_state->rotation != new_other_state->rotation) 10134 return true; 10135 10136 /* Blending updates. */ 10137 if (old_other_state->pixel_blend_mode != 10138 new_other_state->pixel_blend_mode) 10139 return true; 10140 10141 /* Alpha updates. */ 10142 if (old_other_state->alpha != new_other_state->alpha) 10143 return true; 10144 10145 /* Colorspace changes. */ 10146 if (old_other_state->color_range != new_other_state->color_range || 10147 old_other_state->color_encoding != new_other_state->color_encoding) 10148 return true; 10149 10150 /* HDR/Transfer Function changes. */ 10151 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 10152 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 10153 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 10154 dm_old_other_state->ctm != dm_new_other_state->ctm || 10155 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 10156 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 10157 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 10158 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 10159 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 10160 return true; 10161 10162 /* Framebuffer checks fall at the end. */ 10163 if (!old_other_state->fb || !new_other_state->fb) 10164 continue; 10165 10166 /* Pixel format changes can require bandwidth updates. */ 10167 if (old_other_state->fb->format != new_other_state->fb->format) 10168 return true; 10169 10170 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 10171 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 10172 10173 /* Tiling and DCC changes also require bandwidth updates. */ 10174 if (old_afb->tiling_flags != new_afb->tiling_flags || 10175 old_afb->base.modifier != new_afb->base.modifier) 10176 return true; 10177 } 10178 10179 return false; 10180 } 10181 10182 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 10183 struct drm_plane_state *new_plane_state, 10184 struct drm_framebuffer *fb) 10185 { 10186 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 10187 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 10188 unsigned int pitch; 10189 bool linear; 10190 10191 if (fb->width > new_acrtc->max_cursor_width || 10192 fb->height > new_acrtc->max_cursor_height) { 10193 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 10194 new_plane_state->fb->width, 10195 new_plane_state->fb->height); 10196 return -EINVAL; 10197 } 10198 if (new_plane_state->src_w != fb->width << 16 || 10199 new_plane_state->src_h != fb->height << 16) { 10200 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10201 return -EINVAL; 10202 } 10203 10204 /* Pitch in pixels */ 10205 pitch = fb->pitches[0] / fb->format->cpp[0]; 10206 10207 if (fb->width != pitch) { 10208 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 10209 fb->width, pitch); 10210 return -EINVAL; 10211 } 10212 10213 switch (pitch) { 10214 case 64: 10215 case 128: 10216 case 256: 10217 /* FB pitch is supported by cursor plane */ 10218 break; 10219 default: 10220 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 10221 return -EINVAL; 10222 } 10223 10224 /* Core DRM takes care of checking FB modifiers, so we only need to 10225 * check tiling flags when the FB doesn't have a modifier. 10226 */ 10227 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 10228 if (adev->family < AMDGPU_FAMILY_AI) { 10229 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 10230 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 10231 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 10232 } else { 10233 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 10234 } 10235 if (!linear) { 10236 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 10237 return -EINVAL; 10238 } 10239 } 10240 10241 return 0; 10242 } 10243 10244 static int dm_update_plane_state(struct dc *dc, 10245 struct drm_atomic_state *state, 10246 struct drm_plane *plane, 10247 struct drm_plane_state *old_plane_state, 10248 struct drm_plane_state *new_plane_state, 10249 bool enable, 10250 bool *lock_and_validation_needed, 10251 bool *is_top_most_overlay) 10252 { 10253 10254 struct dm_atomic_state *dm_state = NULL; 10255 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 10256 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10257 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 10258 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 10259 struct amdgpu_crtc *new_acrtc; 10260 bool needs_reset; 10261 int ret = 0; 10262 10263 10264 new_plane_crtc = new_plane_state->crtc; 10265 old_plane_crtc = old_plane_state->crtc; 10266 dm_new_plane_state = to_dm_plane_state(new_plane_state); 10267 dm_old_plane_state = to_dm_plane_state(old_plane_state); 10268 10269 if (plane->type == DRM_PLANE_TYPE_CURSOR) { 10270 if (!enable || !new_plane_crtc || 10271 drm_atomic_plane_disabling(plane->state, new_plane_state)) 10272 return 0; 10273 10274 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 10275 10276 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 10277 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10278 return -EINVAL; 10279 } 10280 10281 if (new_plane_state->fb) { 10282 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 10283 new_plane_state->fb); 10284 if (ret) 10285 return ret; 10286 } 10287 10288 return 0; 10289 } 10290 10291 needs_reset = should_reset_plane(state, plane, old_plane_state, 10292 new_plane_state); 10293 10294 /* Remove any changed/removed planes */ 10295 if (!enable) { 10296 if (!needs_reset) 10297 return 0; 10298 10299 if (!old_plane_crtc) 10300 return 0; 10301 10302 old_crtc_state = drm_atomic_get_old_crtc_state( 10303 state, old_plane_crtc); 10304 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10305 10306 if (!dm_old_crtc_state->stream) 10307 return 0; 10308 10309 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 10310 plane->base.id, old_plane_crtc->base.id); 10311 10312 ret = dm_atomic_get_state(state, &dm_state); 10313 if (ret) 10314 return ret; 10315 10316 if (!dc_state_remove_plane( 10317 dc, 10318 dm_old_crtc_state->stream, 10319 dm_old_plane_state->dc_state, 10320 dm_state->context)) { 10321 10322 return -EINVAL; 10323 } 10324 10325 if (dm_old_plane_state->dc_state) 10326 dc_plane_state_release(dm_old_plane_state->dc_state); 10327 10328 dm_new_plane_state->dc_state = NULL; 10329 10330 *lock_and_validation_needed = true; 10331 10332 } else { /* Add new planes */ 10333 struct dc_plane_state *dc_new_plane_state; 10334 10335 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10336 return 0; 10337 10338 if (!new_plane_crtc) 10339 return 0; 10340 10341 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 10342 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10343 10344 if (!dm_new_crtc_state->stream) 10345 return 0; 10346 10347 if (!needs_reset) 10348 return 0; 10349 10350 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 10351 if (ret) 10352 return ret; 10353 10354 WARN_ON(dm_new_plane_state->dc_state); 10355 10356 dc_new_plane_state = dc_create_plane_state(dc); 10357 if (!dc_new_plane_state) 10358 return -ENOMEM; 10359 10360 /* Block top most plane from being a video plane */ 10361 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 10362 if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay) 10363 return -EINVAL; 10364 10365 *is_top_most_overlay = false; 10366 } 10367 10368 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 10369 plane->base.id, new_plane_crtc->base.id); 10370 10371 ret = fill_dc_plane_attributes( 10372 drm_to_adev(new_plane_crtc->dev), 10373 dc_new_plane_state, 10374 new_plane_state, 10375 new_crtc_state); 10376 if (ret) { 10377 dc_plane_state_release(dc_new_plane_state); 10378 return ret; 10379 } 10380 10381 ret = dm_atomic_get_state(state, &dm_state); 10382 if (ret) { 10383 dc_plane_state_release(dc_new_plane_state); 10384 return ret; 10385 } 10386 10387 /* 10388 * Any atomic check errors that occur after this will 10389 * not need a release. The plane state will be attached 10390 * to the stream, and therefore part of the atomic 10391 * state. It'll be released when the atomic state is 10392 * cleaned. 10393 */ 10394 if (!dc_state_add_plane( 10395 dc, 10396 dm_new_crtc_state->stream, 10397 dc_new_plane_state, 10398 dm_state->context)) { 10399 10400 dc_plane_state_release(dc_new_plane_state); 10401 return -EINVAL; 10402 } 10403 10404 dm_new_plane_state->dc_state = dc_new_plane_state; 10405 10406 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 10407 10408 /* Tell DC to do a full surface update every time there 10409 * is a plane change. Inefficient, but works for now. 10410 */ 10411 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 10412 10413 *lock_and_validation_needed = true; 10414 } 10415 10416 10417 return ret; 10418 } 10419 10420 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 10421 int *src_w, int *src_h) 10422 { 10423 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 10424 case DRM_MODE_ROTATE_90: 10425 case DRM_MODE_ROTATE_270: 10426 *src_w = plane_state->src_h >> 16; 10427 *src_h = plane_state->src_w >> 16; 10428 break; 10429 case DRM_MODE_ROTATE_0: 10430 case DRM_MODE_ROTATE_180: 10431 default: 10432 *src_w = plane_state->src_w >> 16; 10433 *src_h = plane_state->src_h >> 16; 10434 break; 10435 } 10436 } 10437 10438 static void 10439 dm_get_plane_scale(struct drm_plane_state *plane_state, 10440 int *out_plane_scale_w, int *out_plane_scale_h) 10441 { 10442 int plane_src_w, plane_src_h; 10443 10444 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 10445 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; 10446 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; 10447 } 10448 10449 static int dm_check_crtc_cursor(struct drm_atomic_state *state, 10450 struct drm_crtc *crtc, 10451 struct drm_crtc_state *new_crtc_state) 10452 { 10453 struct drm_plane *cursor = crtc->cursor, *plane, *underlying; 10454 struct drm_plane_state *old_plane_state, *new_plane_state; 10455 struct drm_plane_state *new_cursor_state, *new_underlying_state; 10456 int i; 10457 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h; 10458 bool any_relevant_change = false; 10459 10460 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a 10461 * cursor per pipe but it's going to inherit the scaling and 10462 * positioning from the underlying pipe. Check the cursor plane's 10463 * blending properties match the underlying planes'. 10464 */ 10465 10466 /* If no plane was enabled or changed scaling, no need to check again */ 10467 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10468 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 10469 10470 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc) 10471 continue; 10472 10473 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) { 10474 any_relevant_change = true; 10475 break; 10476 } 10477 10478 if (new_plane_state->fb == old_plane_state->fb && 10479 new_plane_state->crtc_w == old_plane_state->crtc_w && 10480 new_plane_state->crtc_h == old_plane_state->crtc_h) 10481 continue; 10482 10483 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h); 10484 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 10485 10486 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 10487 any_relevant_change = true; 10488 break; 10489 } 10490 } 10491 10492 if (!any_relevant_change) 10493 return 0; 10494 10495 new_cursor_state = drm_atomic_get_plane_state(state, cursor); 10496 if (IS_ERR(new_cursor_state)) 10497 return PTR_ERR(new_cursor_state); 10498 10499 if (!new_cursor_state->fb) 10500 return 0; 10501 10502 dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h); 10503 10504 /* Need to check all enabled planes, even if this commit doesn't change 10505 * their state 10506 */ 10507 i = drm_atomic_add_affected_planes(state, crtc); 10508 if (i) 10509 return i; 10510 10511 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) { 10512 /* Narrow down to non-cursor planes on the same CRTC as the cursor */ 10513 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor) 10514 continue; 10515 10516 /* Ignore disabled planes */ 10517 if (!new_underlying_state->fb) 10518 continue; 10519 10520 dm_get_plane_scale(new_underlying_state, 10521 &underlying_scale_w, &underlying_scale_h); 10522 10523 if (cursor_scale_w != underlying_scale_w || 10524 cursor_scale_h != underlying_scale_h) { 10525 drm_dbg_atomic(crtc->dev, 10526 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n", 10527 cursor->base.id, cursor->name, underlying->base.id, underlying->name); 10528 return -EINVAL; 10529 } 10530 10531 /* If this plane covers the whole CRTC, no need to check planes underneath */ 10532 if (new_underlying_state->crtc_x <= 0 && 10533 new_underlying_state->crtc_y <= 0 && 10534 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay && 10535 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay) 10536 break; 10537 } 10538 10539 return 0; 10540 } 10541 10542 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 10543 { 10544 struct drm_connector *connector; 10545 struct drm_connector_state *conn_state, *old_conn_state; 10546 struct amdgpu_dm_connector *aconnector = NULL; 10547 int i; 10548 10549 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 10550 if (!conn_state->crtc) 10551 conn_state = old_conn_state; 10552 10553 if (conn_state->crtc != crtc) 10554 continue; 10555 10556 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10557 continue; 10558 10559 aconnector = to_amdgpu_dm_connector(connector); 10560 if (!aconnector->mst_output_port || !aconnector->mst_root) 10561 aconnector = NULL; 10562 else 10563 break; 10564 } 10565 10566 if (!aconnector) 10567 return 0; 10568 10569 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 10570 } 10571 10572 /** 10573 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 10574 * 10575 * @dev: The DRM device 10576 * @state: The atomic state to commit 10577 * 10578 * Validate that the given atomic state is programmable by DC into hardware. 10579 * This involves constructing a &struct dc_state reflecting the new hardware 10580 * state we wish to commit, then querying DC to see if it is programmable. It's 10581 * important not to modify the existing DC state. Otherwise, atomic_check 10582 * may unexpectedly commit hardware changes. 10583 * 10584 * When validating the DC state, it's important that the right locks are 10585 * acquired. For full updates case which removes/adds/updates streams on one 10586 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 10587 * that any such full update commit will wait for completion of any outstanding 10588 * flip using DRMs synchronization events. 10589 * 10590 * Note that DM adds the affected connectors for all CRTCs in state, when that 10591 * might not seem necessary. This is because DC stream creation requires the 10592 * DC sink, which is tied to the DRM connector state. Cleaning this up should 10593 * be possible but non-trivial - a possible TODO item. 10594 * 10595 * Return: -Error code if validation failed. 10596 */ 10597 static int amdgpu_dm_atomic_check(struct drm_device *dev, 10598 struct drm_atomic_state *state) 10599 { 10600 struct amdgpu_device *adev = drm_to_adev(dev); 10601 struct dm_atomic_state *dm_state = NULL; 10602 struct dc *dc = adev->dm.dc; 10603 struct drm_connector *connector; 10604 struct drm_connector_state *old_con_state, *new_con_state; 10605 struct drm_crtc *crtc; 10606 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10607 struct drm_plane *plane; 10608 struct drm_plane_state *old_plane_state, *new_plane_state; 10609 enum dc_status status; 10610 int ret, i; 10611 bool lock_and_validation_needed = false; 10612 bool is_top_most_overlay = true; 10613 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10614 struct drm_dp_mst_topology_mgr *mgr; 10615 struct drm_dp_mst_topology_state *mst_state; 10616 struct dsc_mst_fairness_vars vars[MAX_PIPES]; 10617 10618 trace_amdgpu_dm_atomic_check_begin(state); 10619 10620 ret = drm_atomic_helper_check_modeset(dev, state); 10621 if (ret) { 10622 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n"); 10623 goto fail; 10624 } 10625 10626 /* Check connector changes */ 10627 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10628 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10629 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10630 10631 /* Skip connectors that are disabled or part of modeset already. */ 10632 if (!new_con_state->crtc) 10633 continue; 10634 10635 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 10636 if (IS_ERR(new_crtc_state)) { 10637 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n"); 10638 ret = PTR_ERR(new_crtc_state); 10639 goto fail; 10640 } 10641 10642 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 10643 dm_old_con_state->scaling != dm_new_con_state->scaling) 10644 new_crtc_state->connectors_changed = true; 10645 } 10646 10647 if (dc_resource_is_dsc_encoding_supported(dc)) { 10648 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10649 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10650 ret = add_affected_mst_dsc_crtcs(state, crtc); 10651 if (ret) { 10652 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n"); 10653 goto fail; 10654 } 10655 } 10656 } 10657 } 10658 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10659 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10660 10661 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 10662 !new_crtc_state->color_mgmt_changed && 10663 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 10664 dm_old_crtc_state->dsc_force_changed == false) 10665 continue; 10666 10667 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 10668 if (ret) { 10669 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); 10670 goto fail; 10671 } 10672 10673 if (!new_crtc_state->enable) 10674 continue; 10675 10676 ret = drm_atomic_add_affected_connectors(state, crtc); 10677 if (ret) { 10678 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n"); 10679 goto fail; 10680 } 10681 10682 ret = drm_atomic_add_affected_planes(state, crtc); 10683 if (ret) { 10684 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n"); 10685 goto fail; 10686 } 10687 10688 if (dm_old_crtc_state->dsc_force_changed) 10689 new_crtc_state->mode_changed = true; 10690 } 10691 10692 /* 10693 * Add all primary and overlay planes on the CRTC to the state 10694 * whenever a plane is enabled to maintain correct z-ordering 10695 * and to enable fast surface updates. 10696 */ 10697 drm_for_each_crtc(crtc, dev) { 10698 bool modified = false; 10699 10700 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 10701 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10702 continue; 10703 10704 if (new_plane_state->crtc == crtc || 10705 old_plane_state->crtc == crtc) { 10706 modified = true; 10707 break; 10708 } 10709 } 10710 10711 if (!modified) 10712 continue; 10713 10714 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 10715 if (plane->type == DRM_PLANE_TYPE_CURSOR) 10716 continue; 10717 10718 new_plane_state = 10719 drm_atomic_get_plane_state(state, plane); 10720 10721 if (IS_ERR(new_plane_state)) { 10722 ret = PTR_ERR(new_plane_state); 10723 DRM_DEBUG_DRIVER("new_plane_state is BAD\n"); 10724 goto fail; 10725 } 10726 } 10727 } 10728 10729 /* 10730 * DC consults the zpos (layer_index in DC terminology) to determine the 10731 * hw plane on which to enable the hw cursor (see 10732 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 10733 * atomic state, so call drm helper to normalize zpos. 10734 */ 10735 ret = drm_atomic_normalize_zpos(dev, state); 10736 if (ret) { 10737 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 10738 goto fail; 10739 } 10740 10741 /* Remove exiting planes if they are modified */ 10742 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10743 if (old_plane_state->fb && new_plane_state->fb && 10744 get_mem_type(old_plane_state->fb) != 10745 get_mem_type(new_plane_state->fb)) 10746 lock_and_validation_needed = true; 10747 10748 ret = dm_update_plane_state(dc, state, plane, 10749 old_plane_state, 10750 new_plane_state, 10751 false, 10752 &lock_and_validation_needed, 10753 &is_top_most_overlay); 10754 if (ret) { 10755 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10756 goto fail; 10757 } 10758 } 10759 10760 /* Disable all crtcs which require disable */ 10761 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10762 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10763 old_crtc_state, 10764 new_crtc_state, 10765 false, 10766 &lock_and_validation_needed); 10767 if (ret) { 10768 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n"); 10769 goto fail; 10770 } 10771 } 10772 10773 /* Enable all crtcs which require enable */ 10774 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 10775 ret = dm_update_crtc_state(&adev->dm, state, crtc, 10776 old_crtc_state, 10777 new_crtc_state, 10778 true, 10779 &lock_and_validation_needed); 10780 if (ret) { 10781 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n"); 10782 goto fail; 10783 } 10784 } 10785 10786 /* Add new/modified planes */ 10787 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) { 10788 ret = dm_update_plane_state(dc, state, plane, 10789 old_plane_state, 10790 new_plane_state, 10791 true, 10792 &lock_and_validation_needed, 10793 &is_top_most_overlay); 10794 if (ret) { 10795 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n"); 10796 goto fail; 10797 } 10798 } 10799 10800 if (dc_resource_is_dsc_encoding_supported(dc)) { 10801 ret = pre_validate_dsc(state, &dm_state, vars); 10802 if (ret != 0) 10803 goto fail; 10804 } 10805 10806 /* Run this here since we want to validate the streams we created */ 10807 ret = drm_atomic_helper_check_planes(dev, state); 10808 if (ret) { 10809 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n"); 10810 goto fail; 10811 } 10812 10813 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10814 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10815 if (dm_new_crtc_state->mpo_requested) 10816 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc); 10817 } 10818 10819 /* Check cursor planes scaling */ 10820 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10821 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state); 10822 if (ret) { 10823 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n"); 10824 goto fail; 10825 } 10826 } 10827 10828 if (state->legacy_cursor_update) { 10829 /* 10830 * This is a fast cursor update coming from the plane update 10831 * helper, check if it can be done asynchronously for better 10832 * performance. 10833 */ 10834 state->async_update = 10835 !drm_atomic_helper_async_check(dev, state); 10836 10837 /* 10838 * Skip the remaining global validation if this is an async 10839 * update. Cursor updates can be done without affecting 10840 * state or bandwidth calcs and this avoids the performance 10841 * penalty of locking the private state object and 10842 * allocating a new dc_state. 10843 */ 10844 if (state->async_update) 10845 return 0; 10846 } 10847 10848 /* Check scaling and underscan changes*/ 10849 /* TODO Removed scaling changes validation due to inability to commit 10850 * new stream into context w\o causing full reset. Need to 10851 * decide how to handle. 10852 */ 10853 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 10854 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 10855 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 10856 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 10857 10858 /* Skip any modesets/resets */ 10859 if (!acrtc || drm_atomic_crtc_needs_modeset( 10860 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 10861 continue; 10862 10863 /* Skip any thing not scale or underscan changes */ 10864 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 10865 continue; 10866 10867 lock_and_validation_needed = true; 10868 } 10869 10870 /* set the slot info for each mst_state based on the link encoding format */ 10871 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 10872 struct amdgpu_dm_connector *aconnector; 10873 struct drm_connector *connector; 10874 struct drm_connector_list_iter iter; 10875 u8 link_coding_cap; 10876 10877 drm_connector_list_iter_begin(dev, &iter); 10878 drm_for_each_connector_iter(connector, &iter) { 10879 if (connector->index == mst_state->mgr->conn_base_id) { 10880 aconnector = to_amdgpu_dm_connector(connector); 10881 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 10882 drm_dp_mst_update_slots(mst_state, link_coding_cap); 10883 10884 break; 10885 } 10886 } 10887 drm_connector_list_iter_end(&iter); 10888 } 10889 10890 /** 10891 * Streams and planes are reset when there are changes that affect 10892 * bandwidth. Anything that affects bandwidth needs to go through 10893 * DC global validation to ensure that the configuration can be applied 10894 * to hardware. 10895 * 10896 * We have to currently stall out here in atomic_check for outstanding 10897 * commits to finish in this case because our IRQ handlers reference 10898 * DRM state directly - we can end up disabling interrupts too early 10899 * if we don't. 10900 * 10901 * TODO: Remove this stall and drop DM state private objects. 10902 */ 10903 if (lock_and_validation_needed) { 10904 ret = dm_atomic_get_state(state, &dm_state); 10905 if (ret) { 10906 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n"); 10907 goto fail; 10908 } 10909 10910 ret = do_aquire_global_lock(dev, state); 10911 if (ret) { 10912 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n"); 10913 goto fail; 10914 } 10915 10916 if (dc_resource_is_dsc_encoding_supported(dc)) { 10917 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 10918 if (ret) { 10919 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n"); 10920 ret = -EINVAL; 10921 goto fail; 10922 } 10923 } 10924 10925 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 10926 if (ret) { 10927 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n"); 10928 goto fail; 10929 } 10930 10931 /* 10932 * Perform validation of MST topology in the state: 10933 * We need to perform MST atomic check before calling 10934 * dc_validate_global_state(), or there is a chance 10935 * to get stuck in an infinite loop and hang eventually. 10936 */ 10937 ret = drm_dp_mst_atomic_check(state); 10938 if (ret) { 10939 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n"); 10940 goto fail; 10941 } 10942 status = dc_validate_global_state(dc, dm_state->context, true); 10943 if (status != DC_OK) { 10944 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)", 10945 dc_status_to_str(status), status); 10946 ret = -EINVAL; 10947 goto fail; 10948 } 10949 } else { 10950 /* 10951 * The commit is a fast update. Fast updates shouldn't change 10952 * the DC context, affect global validation, and can have their 10953 * commit work done in parallel with other commits not touching 10954 * the same resource. If we have a new DC context as part of 10955 * the DM atomic state from validation we need to free it and 10956 * retain the existing one instead. 10957 * 10958 * Furthermore, since the DM atomic state only contains the DC 10959 * context and can safely be annulled, we can free the state 10960 * and clear the associated private object now to free 10961 * some memory and avoid a possible use-after-free later. 10962 */ 10963 10964 for (i = 0; i < state->num_private_objs; i++) { 10965 struct drm_private_obj *obj = state->private_objs[i].ptr; 10966 10967 if (obj->funcs == adev->dm.atomic_obj.funcs) { 10968 int j = state->num_private_objs-1; 10969 10970 dm_atomic_destroy_state(obj, 10971 state->private_objs[i].state); 10972 10973 /* If i is not at the end of the array then the 10974 * last element needs to be moved to where i was 10975 * before the array can safely be truncated. 10976 */ 10977 if (i != j) 10978 state->private_objs[i] = 10979 state->private_objs[j]; 10980 10981 state->private_objs[j].ptr = NULL; 10982 state->private_objs[j].state = NULL; 10983 state->private_objs[j].old_state = NULL; 10984 state->private_objs[j].new_state = NULL; 10985 10986 state->num_private_objs = j; 10987 break; 10988 } 10989 } 10990 } 10991 10992 /* Store the overall update type for use later in atomic check. */ 10993 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 10994 struct dm_crtc_state *dm_new_crtc_state = 10995 to_dm_crtc_state(new_crtc_state); 10996 10997 /* 10998 * Only allow async flips for fast updates that don't change 10999 * the FB pitch, the DCC state, rotation, etc. 11000 */ 11001 if (new_crtc_state->async_flip && lock_and_validation_needed) { 11002 drm_dbg_atomic(crtc->dev, 11003 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 11004 crtc->base.id, crtc->name); 11005 ret = -EINVAL; 11006 goto fail; 11007 } 11008 11009 dm_new_crtc_state->update_type = lock_and_validation_needed ? 11010 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 11011 } 11012 11013 /* Must be success */ 11014 WARN_ON(ret); 11015 11016 trace_amdgpu_dm_atomic_check_finish(state, ret); 11017 11018 return ret; 11019 11020 fail: 11021 if (ret == -EDEADLK) 11022 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); 11023 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 11024 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); 11025 else 11026 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret); 11027 11028 trace_amdgpu_dm_atomic_check_finish(state, ret); 11029 11030 return ret; 11031 } 11032 11033 static bool is_dp_capable_without_timing_msa(struct dc *dc, 11034 struct amdgpu_dm_connector *amdgpu_dm_connector) 11035 { 11036 u8 dpcd_data; 11037 bool capable = false; 11038 11039 if (amdgpu_dm_connector->dc_link && 11040 dm_helpers_dp_read_dpcd( 11041 NULL, 11042 amdgpu_dm_connector->dc_link, 11043 DP_DOWN_STREAM_PORT_COUNT, 11044 &dpcd_data, 11045 sizeof(dpcd_data))) { 11046 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; 11047 } 11048 11049 return capable; 11050 } 11051 11052 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 11053 unsigned int offset, 11054 unsigned int total_length, 11055 u8 *data, 11056 unsigned int length, 11057 struct amdgpu_hdmi_vsdb_info *vsdb) 11058 { 11059 bool res; 11060 union dmub_rb_cmd cmd; 11061 struct dmub_cmd_send_edid_cea *input; 11062 struct dmub_cmd_edid_cea_output *output; 11063 11064 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 11065 return false; 11066 11067 memset(&cmd, 0, sizeof(cmd)); 11068 11069 input = &cmd.edid_cea.data.input; 11070 11071 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 11072 cmd.edid_cea.header.sub_type = 0; 11073 cmd.edid_cea.header.payload_bytes = 11074 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 11075 input->offset = offset; 11076 input->length = length; 11077 input->cea_total_length = total_length; 11078 memcpy(input->payload, data, length); 11079 11080 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 11081 if (!res) { 11082 DRM_ERROR("EDID CEA parser failed\n"); 11083 return false; 11084 } 11085 11086 output = &cmd.edid_cea.data.output; 11087 11088 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 11089 if (!output->ack.success) { 11090 DRM_ERROR("EDID CEA ack failed at offset %d\n", 11091 output->ack.offset); 11092 } 11093 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 11094 if (!output->amd_vsdb.vsdb_found) 11095 return false; 11096 11097 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 11098 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 11099 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 11100 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 11101 } else { 11102 DRM_WARN("Unknown EDID CEA parser results\n"); 11103 return false; 11104 } 11105 11106 return true; 11107 } 11108 11109 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 11110 u8 *edid_ext, int len, 11111 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11112 { 11113 int i; 11114 11115 /* send extension block to DMCU for parsing */ 11116 for (i = 0; i < len; i += 8) { 11117 bool res; 11118 int offset; 11119 11120 /* send 8 bytes a time */ 11121 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 11122 return false; 11123 11124 if (i+8 == len) { 11125 /* EDID block sent completed, expect result */ 11126 int version, min_rate, max_rate; 11127 11128 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 11129 if (res) { 11130 /* amd vsdb found */ 11131 vsdb_info->freesync_supported = 1; 11132 vsdb_info->amd_vsdb_version = version; 11133 vsdb_info->min_refresh_rate_hz = min_rate; 11134 vsdb_info->max_refresh_rate_hz = max_rate; 11135 return true; 11136 } 11137 /* not amd vsdb */ 11138 return false; 11139 } 11140 11141 /* check for ack*/ 11142 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 11143 if (!res) 11144 return false; 11145 } 11146 11147 return false; 11148 } 11149 11150 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 11151 u8 *edid_ext, int len, 11152 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11153 { 11154 int i; 11155 11156 /* send extension block to DMCU for parsing */ 11157 for (i = 0; i < len; i += 8) { 11158 /* send 8 bytes a time */ 11159 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 11160 return false; 11161 } 11162 11163 return vsdb_info->freesync_supported; 11164 } 11165 11166 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 11167 u8 *edid_ext, int len, 11168 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11169 { 11170 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 11171 bool ret; 11172 11173 mutex_lock(&adev->dm.dc_lock); 11174 if (adev->dm.dmub_srv) 11175 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 11176 else 11177 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 11178 mutex_unlock(&adev->dm.dc_lock); 11179 return ret; 11180 } 11181 11182 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11183 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11184 { 11185 u8 *edid_ext = NULL; 11186 int i; 11187 int j = 0; 11188 11189 if (edid == NULL || edid->extensions == 0) 11190 return -ENODEV; 11191 11192 /* Find DisplayID extension */ 11193 for (i = 0; i < edid->extensions; i++) { 11194 edid_ext = (void *)(edid + (i + 1)); 11195 if (edid_ext[0] == DISPLAYID_EXT) 11196 break; 11197 } 11198 11199 while (j < EDID_LENGTH) { 11200 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 11201 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 11202 11203 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 11204 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 11205 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 11206 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 11207 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 11208 11209 return true; 11210 } 11211 j++; 11212 } 11213 11214 return false; 11215 } 11216 11217 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11218 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11219 { 11220 u8 *edid_ext = NULL; 11221 int i; 11222 bool valid_vsdb_found = false; 11223 11224 /*----- drm_find_cea_extension() -----*/ 11225 /* No EDID or EDID extensions */ 11226 if (edid == NULL || edid->extensions == 0) 11227 return -ENODEV; 11228 11229 /* Find CEA extension */ 11230 for (i = 0; i < edid->extensions; i++) { 11231 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 11232 if (edid_ext[0] == CEA_EXT) 11233 break; 11234 } 11235 11236 if (i == edid->extensions) 11237 return -ENODEV; 11238 11239 /*----- cea_db_offsets() -----*/ 11240 if (edid_ext[0] != CEA_EXT) 11241 return -ENODEV; 11242 11243 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 11244 11245 return valid_vsdb_found ? i : -ENODEV; 11246 } 11247 11248 /** 11249 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 11250 * 11251 * @connector: Connector to query. 11252 * @edid: EDID from monitor 11253 * 11254 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 11255 * track of some of the display information in the internal data struct used by 11256 * amdgpu_dm. This function checks which type of connector we need to set the 11257 * FreeSync parameters. 11258 */ 11259 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 11260 struct edid *edid) 11261 { 11262 int i = 0; 11263 struct detailed_timing *timing; 11264 struct detailed_non_pixel *data; 11265 struct detailed_data_monitor_range *range; 11266 struct amdgpu_dm_connector *amdgpu_dm_connector = 11267 to_amdgpu_dm_connector(connector); 11268 struct dm_connector_state *dm_con_state = NULL; 11269 struct dc_sink *sink; 11270 11271 struct amdgpu_device *adev = drm_to_adev(connector->dev); 11272 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 11273 bool freesync_capable = false; 11274 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 11275 11276 if (!connector->state) { 11277 DRM_ERROR("%s - Connector has no state", __func__); 11278 goto update; 11279 } 11280 11281 sink = amdgpu_dm_connector->dc_sink ? 11282 amdgpu_dm_connector->dc_sink : 11283 amdgpu_dm_connector->dc_em_sink; 11284 11285 if (!edid || !sink) { 11286 dm_con_state = to_dm_connector_state(connector->state); 11287 11288 amdgpu_dm_connector->min_vfreq = 0; 11289 amdgpu_dm_connector->max_vfreq = 0; 11290 amdgpu_dm_connector->pixel_clock_mhz = 0; 11291 connector->display_info.monitor_range.min_vfreq = 0; 11292 connector->display_info.monitor_range.max_vfreq = 0; 11293 freesync_capable = false; 11294 11295 goto update; 11296 } 11297 11298 dm_con_state = to_dm_connector_state(connector->state); 11299 11300 if (!adev->dm.freesync_module) 11301 goto update; 11302 11303 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 11304 sink->sink_signal == SIGNAL_TYPE_EDP)) { 11305 bool edid_check_required = false; 11306 11307 if (is_dp_capable_without_timing_msa(adev->dm.dc, 11308 amdgpu_dm_connector)) { 11309 if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { 11310 freesync_capable = true; 11311 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 11312 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 11313 } else { 11314 edid_check_required = edid->version > 1 || 11315 (edid->version == 1 && 11316 edid->revision > 1); 11317 } 11318 } 11319 11320 if (edid_check_required) { 11321 for (i = 0; i < 4; i++) { 11322 11323 timing = &edid->detailed_timings[i]; 11324 data = &timing->data.other_data; 11325 range = &data->data.range; 11326 /* 11327 * Check if monitor has continuous frequency mode 11328 */ 11329 if (data->type != EDID_DETAIL_MONITOR_RANGE) 11330 continue; 11331 /* 11332 * Check for flag range limits only. If flag == 1 then 11333 * no additional timing information provided. 11334 * Default GTF, GTF Secondary curve and CVT are not 11335 * supported 11336 */ 11337 if (range->flags != 1) 11338 continue; 11339 11340 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 11341 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 11342 11343 if (edid->revision >= 4) { 11344 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 11345 connector->display_info.monitor_range.min_vfreq += 255; 11346 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 11347 connector->display_info.monitor_range.max_vfreq += 255; 11348 } 11349 11350 amdgpu_dm_connector->min_vfreq = 11351 connector->display_info.monitor_range.min_vfreq; 11352 amdgpu_dm_connector->max_vfreq = 11353 connector->display_info.monitor_range.max_vfreq; 11354 amdgpu_dm_connector->pixel_clock_mhz = 11355 range->pixel_clock_mhz * 10; 11356 11357 break; 11358 } 11359 11360 if (amdgpu_dm_connector->max_vfreq - 11361 amdgpu_dm_connector->min_vfreq > 10) { 11362 11363 freesync_capable = true; 11364 } 11365 } 11366 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11367 11368 if (vsdb_info.replay_mode) { 11369 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 11370 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 11371 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 11372 } 11373 11374 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 11375 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11376 if (i >= 0 && vsdb_info.freesync_supported) { 11377 timing = &edid->detailed_timings[i]; 11378 data = &timing->data.other_data; 11379 11380 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 11381 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 11382 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 11383 freesync_capable = true; 11384 11385 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 11386 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 11387 } 11388 } 11389 11390 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 11391 11392 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 11393 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 11394 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 11395 11396 amdgpu_dm_connector->pack_sdp_v1_3 = true; 11397 amdgpu_dm_connector->as_type = as_type; 11398 amdgpu_dm_connector->vsdb_info = vsdb_info; 11399 11400 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 11401 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 11402 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 11403 freesync_capable = true; 11404 11405 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 11406 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 11407 } 11408 } 11409 11410 update: 11411 if (dm_con_state) 11412 dm_con_state->freesync_capable = freesync_capable; 11413 11414 if (connector->vrr_capable_property) 11415 drm_connector_set_vrr_capable_property(connector, 11416 freesync_capable); 11417 } 11418 11419 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 11420 { 11421 struct amdgpu_device *adev = drm_to_adev(dev); 11422 struct dc *dc = adev->dm.dc; 11423 int i; 11424 11425 mutex_lock(&adev->dm.dc_lock); 11426 if (dc->current_state) { 11427 for (i = 0; i < dc->current_state->stream_count; ++i) 11428 dc->current_state->streams[i] 11429 ->triggered_crtc_reset.enabled = 11430 adev->dm.force_timing_sync; 11431 11432 dm_enable_per_frame_crtc_master_sync(dc->current_state); 11433 dc_trigger_sync(dc, dc->current_state); 11434 } 11435 mutex_unlock(&adev->dm.dc_lock); 11436 } 11437 11438 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 11439 u32 value, const char *func_name) 11440 { 11441 #ifdef DM_CHECK_ADDR_0 11442 if (address == 0) { 11443 drm_err(adev_to_drm(ctx->driver_context), 11444 "invalid register write. address = 0"); 11445 return; 11446 } 11447 #endif 11448 cgs_write_register(ctx->cgs_device, address, value); 11449 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 11450 } 11451 11452 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 11453 const char *func_name) 11454 { 11455 u32 value; 11456 #ifdef DM_CHECK_ADDR_0 11457 if (address == 0) { 11458 drm_err(adev_to_drm(ctx->driver_context), 11459 "invalid register read; address = 0\n"); 11460 return 0; 11461 } 11462 #endif 11463 11464 if (ctx->dmub_srv && 11465 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 11466 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 11467 ASSERT(false); 11468 return 0; 11469 } 11470 11471 value = cgs_read_register(ctx->cgs_device, address); 11472 11473 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 11474 11475 return value; 11476 } 11477 11478 int amdgpu_dm_process_dmub_aux_transfer_sync( 11479 struct dc_context *ctx, 11480 unsigned int link_index, 11481 struct aux_payload *payload, 11482 enum aux_return_code_type *operation_result) 11483 { 11484 struct amdgpu_device *adev = ctx->driver_context; 11485 struct dmub_notification *p_notify = adev->dm.dmub_notify; 11486 int ret = -1; 11487 11488 mutex_lock(&adev->dm.dpia_aux_lock); 11489 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 11490 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 11491 goto out; 11492 } 11493 11494 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 11495 DRM_ERROR("wait_for_completion_timeout timeout!"); 11496 *operation_result = AUX_RET_ERROR_TIMEOUT; 11497 goto out; 11498 } 11499 11500 if (p_notify->result != AUX_RET_SUCCESS) { 11501 /* 11502 * Transient states before tunneling is enabled could 11503 * lead to this error. We can ignore this for now. 11504 */ 11505 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 11506 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 11507 payload->address, payload->length, 11508 p_notify->result); 11509 } 11510 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 11511 goto out; 11512 } 11513 11514 11515 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 11516 if (!payload->write && p_notify->aux_reply.length && 11517 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 11518 11519 if (payload->length != p_notify->aux_reply.length) { 11520 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 11521 p_notify->aux_reply.length, 11522 payload->address, payload->length); 11523 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 11524 goto out; 11525 } 11526 11527 memcpy(payload->data, p_notify->aux_reply.data, 11528 p_notify->aux_reply.length); 11529 } 11530 11531 /* success */ 11532 ret = p_notify->aux_reply.length; 11533 *operation_result = p_notify->result; 11534 out: 11535 reinit_completion(&adev->dm.dmub_aux_transfer_done); 11536 mutex_unlock(&adev->dm.dpia_aux_lock); 11537 return ret; 11538 } 11539 11540 int amdgpu_dm_process_dmub_set_config_sync( 11541 struct dc_context *ctx, 11542 unsigned int link_index, 11543 struct set_config_cmd_payload *payload, 11544 enum set_config_status *operation_result) 11545 { 11546 struct amdgpu_device *adev = ctx->driver_context; 11547 bool is_cmd_complete; 11548 int ret; 11549 11550 mutex_lock(&adev->dm.dpia_aux_lock); 11551 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 11552 link_index, payload, adev->dm.dmub_notify); 11553 11554 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 11555 ret = 0; 11556 *operation_result = adev->dm.dmub_notify->sc_status; 11557 } else { 11558 DRM_ERROR("wait_for_completion_timeout timeout!"); 11559 ret = -1; 11560 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 11561 } 11562 11563 if (!is_cmd_complete) 11564 reinit_completion(&adev->dm.dmub_aux_transfer_done); 11565 mutex_unlock(&adev->dm.dpia_aux_lock); 11566 return ret; 11567 } 11568 11569 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11570 { 11571 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 11572 } 11573 11574 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 11575 { 11576 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 11577 } 11578