1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* The caprices of the preprocessor require that this be declared right here */ 27 #define CREATE_TRACE_POINTS 28 29 #include "dm_services_types.h" 30 #include "dc.h" 31 #include "link_enc_cfg.h" 32 #include "dc/inc/core_types.h" 33 #include "dal_asic_id.h" 34 #include "dmub/dmub_srv.h" 35 #include "dc/inc/hw/dmcu.h" 36 #include "dc/inc/hw/abm.h" 37 #include "dc/dc_dmub_srv.h" 38 #include "dc/dc_edid_parser.h" 39 #include "dc/dc_stat.h" 40 #include "dc/dc_state.h" 41 #include "amdgpu_dm_trace.h" 42 #include "dpcd_defs.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "vid.h" 49 #include "amdgpu.h" 50 #include "amdgpu_display.h" 51 #include "amdgpu_ucode.h" 52 #include "atom.h" 53 #include "amdgpu_dm.h" 54 #include "amdgpu_dm_plane.h" 55 #include "amdgpu_dm_crtc.h" 56 #include "amdgpu_dm_hdcp.h" 57 #include <drm/display/drm_hdcp_helper.h> 58 #include "amdgpu_dm_wb.h" 59 #include "amdgpu_pm.h" 60 #include "amdgpu_atombios.h" 61 62 #include "amd_shared.h" 63 #include "amdgpu_dm_irq.h" 64 #include "dm_helpers.h" 65 #include "amdgpu_dm_mst_types.h" 66 #if defined(CONFIG_DEBUG_FS) 67 #include "amdgpu_dm_debugfs.h" 68 #endif 69 #include "amdgpu_dm_psr.h" 70 #include "amdgpu_dm_replay.h" 71 72 #include "ivsrcid/ivsrcid_vislands30.h" 73 74 #include <linux/backlight.h> 75 #include <linux/module.h> 76 #include <linux/moduleparam.h> 77 #include <linux/types.h> 78 #include <linux/pm_runtime.h> 79 #include <linux/pci.h> 80 #include <linux/power_supply.h> 81 #include <linux/firmware.h> 82 #include <linux/component.h> 83 #include <linux/dmi.h> 84 #include <linux/sort.h> 85 86 #include <drm/display/drm_dp_mst_helper.h> 87 #include <drm/display/drm_hdmi_helper.h> 88 #include <drm/drm_atomic.h> 89 #include <drm/drm_atomic_uapi.h> 90 #include <drm/drm_atomic_helper.h> 91 #include <drm/drm_blend.h> 92 #include <drm/drm_fixed.h> 93 #include <drm/drm_fourcc.h> 94 #include <drm/drm_edid.h> 95 #include <drm/drm_eld.h> 96 #include <drm/drm_vblank.h> 97 #include <drm/drm_audio_component.h> 98 #include <drm/drm_gem_atomic_helper.h> 99 100 #include <acpi/video.h> 101 102 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 103 104 #include "dcn/dcn_1_0_offset.h" 105 #include "dcn/dcn_1_0_sh_mask.h" 106 #include "soc15_hw_ip.h" 107 #include "soc15_common.h" 108 #include "vega10_ip_offset.h" 109 110 #include "gc/gc_11_0_0_offset.h" 111 #include "gc/gc_11_0_0_sh_mask.h" 112 113 #include "modules/inc/mod_freesync.h" 114 #include "modules/power/power_helpers.h" 115 116 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin" 117 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); 118 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin" 119 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); 120 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin" 121 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); 122 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin" 123 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); 124 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin" 125 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); 126 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin" 127 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); 128 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin" 129 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); 130 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin" 131 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); 132 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin" 133 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); 134 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin" 135 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); 136 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin" 137 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); 138 139 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin" 140 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); 141 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin" 142 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); 143 144 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin" 145 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 146 147 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin" 148 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 149 150 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin" 151 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB); 152 153 #define FIRMWARE_DCN_351_DMUB "amdgpu/dcn_3_5_1_dmcub.bin" 154 MODULE_FIRMWARE(FIRMWARE_DCN_351_DMUB); 155 156 #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" 157 MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); 158 159 /* Number of bytes in PSP header for firmware. */ 160 #define PSP_HEADER_BYTES 0x100 161 162 /* Number of bytes in PSP footer for firmware. */ 163 #define PSP_FOOTER_BYTES 0x100 164 165 /** 166 * DOC: overview 167 * 168 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 169 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 170 * requests into DC requests, and DC responses into DRM responses. 171 * 172 * The root control structure is &struct amdgpu_display_manager. 173 */ 174 175 /* basic init/fini API */ 176 static int amdgpu_dm_init(struct amdgpu_device *adev); 177 static void amdgpu_dm_fini(struct amdgpu_device *adev); 178 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); 179 180 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) 181 { 182 switch (link->dpcd_caps.dongle_type) { 183 case DISPLAY_DONGLE_NONE: 184 return DRM_MODE_SUBCONNECTOR_Native; 185 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 186 return DRM_MODE_SUBCONNECTOR_VGA; 187 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 188 case DISPLAY_DONGLE_DP_DVI_DONGLE: 189 return DRM_MODE_SUBCONNECTOR_DVID; 190 case DISPLAY_DONGLE_DP_HDMI_CONVERTER: 191 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 192 return DRM_MODE_SUBCONNECTOR_HDMIA; 193 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 194 default: 195 return DRM_MODE_SUBCONNECTOR_Unknown; 196 } 197 } 198 199 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) 200 { 201 struct dc_link *link = aconnector->dc_link; 202 struct drm_connector *connector = &aconnector->base; 203 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 204 205 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 206 return; 207 208 if (aconnector->dc_sink) 209 subconnector = get_subconnector_type(link); 210 211 drm_object_property_set_value(&connector->base, 212 connector->dev->mode_config.dp_subconnector_property, 213 subconnector); 214 } 215 216 /* 217 * initializes drm_device display related structures, based on the information 218 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 219 * drm_encoder, drm_mode_config 220 * 221 * Returns 0 on success 222 */ 223 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 224 /* removes and deallocates the drm structures, created by the above function */ 225 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 226 227 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 228 struct amdgpu_dm_connector *amdgpu_dm_connector, 229 u32 link_index, 230 struct amdgpu_encoder *amdgpu_encoder); 231 static int amdgpu_dm_encoder_init(struct drm_device *dev, 232 struct amdgpu_encoder *aencoder, 233 uint32_t link_index); 234 235 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); 236 237 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); 238 239 static int amdgpu_dm_atomic_check(struct drm_device *dev, 240 struct drm_atomic_state *state); 241 242 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); 243 static void handle_hpd_rx_irq(void *param); 244 245 static bool 246 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 247 struct drm_crtc_state *new_crtc_state); 248 /* 249 * dm_vblank_get_counter 250 * 251 * @brief 252 * Get counter for number of vertical blanks 253 * 254 * @param 255 * struct amdgpu_device *adev - [in] desired amdgpu device 256 * int disp_idx - [in] which CRTC to get the counter from 257 * 258 * @return 259 * Counter for vertical blanks 260 */ 261 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 262 { 263 struct amdgpu_crtc *acrtc = NULL; 264 265 if (crtc >= adev->mode_info.num_crtc) 266 return 0; 267 268 acrtc = adev->mode_info.crtcs[crtc]; 269 270 if (!acrtc->dm_irq_params.stream) { 271 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 272 crtc); 273 return 0; 274 } 275 276 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 277 } 278 279 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 280 u32 *vbl, u32 *position) 281 { 282 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 283 struct amdgpu_crtc *acrtc = NULL; 284 struct dc *dc = adev->dm.dc; 285 286 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 287 return -EINVAL; 288 289 acrtc = adev->mode_info.crtcs[crtc]; 290 291 if (!acrtc->dm_irq_params.stream) { 292 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", 293 crtc); 294 return 0; 295 } 296 297 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 298 dc_allow_idle_optimizations(dc, false); 299 300 /* 301 * TODO rework base driver to use values directly. 302 * for now parse it back into reg-format 303 */ 304 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 305 &v_blank_start, 306 &v_blank_end, 307 &h_position, 308 &v_position); 309 310 *position = v_position | (h_position << 16); 311 *vbl = v_blank_start | (v_blank_end << 16); 312 313 return 0; 314 } 315 316 static bool dm_is_idle(void *handle) 317 { 318 /* XXX todo */ 319 return true; 320 } 321 322 static int dm_wait_for_idle(void *handle) 323 { 324 /* XXX todo */ 325 return 0; 326 } 327 328 static bool dm_check_soft_reset(void *handle) 329 { 330 return false; 331 } 332 333 static int dm_soft_reset(void *handle) 334 { 335 /* XXX todo */ 336 return 0; 337 } 338 339 static struct amdgpu_crtc * 340 get_crtc_by_otg_inst(struct amdgpu_device *adev, 341 int otg_inst) 342 { 343 struct drm_device *dev = adev_to_drm(adev); 344 struct drm_crtc *crtc; 345 struct amdgpu_crtc *amdgpu_crtc; 346 347 if (WARN_ON(otg_inst == -1)) 348 return adev->mode_info.crtcs[0]; 349 350 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 351 amdgpu_crtc = to_amdgpu_crtc(crtc); 352 353 if (amdgpu_crtc->otg_inst == otg_inst) 354 return amdgpu_crtc; 355 } 356 357 return NULL; 358 } 359 360 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 361 struct dm_crtc_state *new_state) 362 { 363 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 364 return true; 365 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 366 return true; 367 else 368 return false; 369 } 370 371 /* 372 * DC will program planes with their z-order determined by their ordering 373 * in the dc_surface_updates array. This comparator is used to sort them 374 * by descending zpos. 375 */ 376 static int dm_plane_layer_index_cmp(const void *a, const void *b) 377 { 378 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 379 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 380 381 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 382 return sb->surface->layer_index - sa->surface->layer_index; 383 } 384 385 /** 386 * update_planes_and_stream_adapter() - Send planes to be updated in DC 387 * 388 * DC has a generic way to update planes and stream via 389 * dc_update_planes_and_stream function; however, DM might need some 390 * adjustments and preparation before calling it. This function is a wrapper 391 * for the dc_update_planes_and_stream that does any required configuration 392 * before passing control to DC. 393 * 394 * @dc: Display Core control structure 395 * @update_type: specify whether it is FULL/MEDIUM/FAST update 396 * @planes_count: planes count to update 397 * @stream: stream state 398 * @stream_update: stream update 399 * @array_of_surface_update: dc surface update pointer 400 * 401 */ 402 static inline bool update_planes_and_stream_adapter(struct dc *dc, 403 int update_type, 404 int planes_count, 405 struct dc_stream_state *stream, 406 struct dc_stream_update *stream_update, 407 struct dc_surface_update *array_of_surface_update) 408 { 409 sort(array_of_surface_update, planes_count, 410 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 411 412 /* 413 * Previous frame finished and HW is ready for optimization. 414 */ 415 if (update_type == UPDATE_TYPE_FAST) 416 dc_post_update_surfaces_to_stream(dc); 417 418 return dc_update_planes_and_stream(dc, 419 array_of_surface_update, 420 planes_count, 421 stream, 422 stream_update); 423 } 424 425 /** 426 * dm_pflip_high_irq() - Handle pageflip interrupt 427 * @interrupt_params: ignored 428 * 429 * Handles the pageflip interrupt by notifying all interested parties 430 * that the pageflip has been completed. 431 */ 432 static void dm_pflip_high_irq(void *interrupt_params) 433 { 434 struct amdgpu_crtc *amdgpu_crtc; 435 struct common_irq_params *irq_params = interrupt_params; 436 struct amdgpu_device *adev = irq_params->adev; 437 struct drm_device *dev = adev_to_drm(adev); 438 unsigned long flags; 439 struct drm_pending_vblank_event *e; 440 u32 vpos, hpos, v_blank_start, v_blank_end; 441 bool vrr_active; 442 443 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); 444 445 /* IRQ could occur when in initial stage */ 446 /* TODO work and BO cleanup */ 447 if (amdgpu_crtc == NULL) { 448 drm_dbg_state(dev, "CRTC is null, returning.\n"); 449 return; 450 } 451 452 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 453 454 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 455 drm_dbg_state(dev, 456 "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n", 457 amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, 458 amdgpu_crtc->crtc_id, amdgpu_crtc); 459 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 460 return; 461 } 462 463 /* page flip completed. */ 464 e = amdgpu_crtc->event; 465 amdgpu_crtc->event = NULL; 466 467 WARN_ON(!e); 468 469 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); 470 471 /* Fixed refresh rate, or VRR scanout position outside front-porch? */ 472 if (!vrr_active || 473 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, 474 &v_blank_end, &hpos, &vpos) || 475 (vpos < v_blank_start)) { 476 /* Update to correct count and vblank timestamp if racing with 477 * vblank irq. This also updates to the correct vblank timestamp 478 * even in VRR mode, as scanout is past the front-porch atm. 479 */ 480 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); 481 482 /* Wake up userspace by sending the pageflip event with proper 483 * count and timestamp of vblank of flip completion. 484 */ 485 if (e) { 486 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); 487 488 /* Event sent, so done with vblank for this flip */ 489 drm_crtc_vblank_put(&amdgpu_crtc->base); 490 } 491 } else if (e) { 492 /* VRR active and inside front-porch: vblank count and 493 * timestamp for pageflip event will only be up to date after 494 * drm_crtc_handle_vblank() has been executed from late vblank 495 * irq handler after start of back-porch (vline 0). We queue the 496 * pageflip event for send-out by drm_crtc_handle_vblank() with 497 * updated timestamp and count, once it runs after us. 498 * 499 * We need to open-code this instead of using the helper 500 * drm_crtc_arm_vblank_event(), as that helper would 501 * call drm_crtc_accurate_vblank_count(), which we must 502 * not call in VRR mode while we are in front-porch! 503 */ 504 505 /* sequence will be replaced by real count during send-out. */ 506 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); 507 e->pipe = amdgpu_crtc->crtc_id; 508 509 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); 510 e = NULL; 511 } 512 513 /* Keep track of vblank of this flip for flip throttling. We use the 514 * cooked hw counter, as that one incremented at start of this vblank 515 * of pageflip completion, so last_flip_vblank is the forbidden count 516 * for queueing new pageflips if vsync + VRR is enabled. 517 */ 518 amdgpu_crtc->dm_irq_params.last_flip_vblank = 519 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); 520 521 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 522 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 523 524 drm_dbg_state(dev, 525 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n", 526 amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); 527 } 528 529 static void dm_vupdate_high_irq(void *interrupt_params) 530 { 531 struct common_irq_params *irq_params = interrupt_params; 532 struct amdgpu_device *adev = irq_params->adev; 533 struct amdgpu_crtc *acrtc; 534 struct drm_device *drm_dev; 535 struct drm_vblank_crtc *vblank; 536 ktime_t frame_duration_ns, previous_timestamp; 537 unsigned long flags; 538 int vrr_active; 539 540 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); 541 542 if (acrtc) { 543 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 544 drm_dev = acrtc->base.dev; 545 vblank = drm_crtc_vblank_crtc(&acrtc->base); 546 previous_timestamp = atomic64_read(&irq_params->previous_timestamp); 547 frame_duration_ns = vblank->time - previous_timestamp; 548 549 if (frame_duration_ns > 0) { 550 trace_amdgpu_refresh_rate_track(acrtc->base.index, 551 frame_duration_ns, 552 ktime_divns(NSEC_PER_SEC, frame_duration_ns)); 553 atomic64_set(&irq_params->previous_timestamp, vblank->time); 554 } 555 556 drm_dbg_vbl(drm_dev, 557 "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, 558 vrr_active); 559 560 /* Core vblank handling is done here after end of front-porch in 561 * vrr mode, as vblank timestamping will give valid results 562 * while now done after front-porch. This will also deliver 563 * page-flip completion events that have been queued to us 564 * if a pageflip happened inside front-porch. 565 */ 566 if (vrr_active) { 567 amdgpu_dm_crtc_handle_vblank(acrtc); 568 569 /* BTR processing for pre-DCE12 ASICs */ 570 if (acrtc->dm_irq_params.stream && 571 adev->family < AMDGPU_FAMILY_AI) { 572 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 573 mod_freesync_handle_v_update( 574 adev->dm.freesync_module, 575 acrtc->dm_irq_params.stream, 576 &acrtc->dm_irq_params.vrr_params); 577 578 dc_stream_adjust_vmin_vmax( 579 adev->dm.dc, 580 acrtc->dm_irq_params.stream, 581 &acrtc->dm_irq_params.vrr_params.adjust); 582 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 583 } 584 } 585 } 586 } 587 588 /** 589 * dm_crtc_high_irq() - Handles CRTC interrupt 590 * @interrupt_params: used for determining the CRTC instance 591 * 592 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK 593 * event handler. 594 */ 595 static void dm_crtc_high_irq(void *interrupt_params) 596 { 597 struct common_irq_params *irq_params = interrupt_params; 598 struct amdgpu_device *adev = irq_params->adev; 599 struct drm_writeback_job *job; 600 struct amdgpu_crtc *acrtc; 601 unsigned long flags; 602 int vrr_active; 603 604 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); 605 if (!acrtc) 606 return; 607 608 if (acrtc->wb_conn) { 609 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 610 611 if (acrtc->wb_pending) { 612 job = list_first_entry_or_null(&acrtc->wb_conn->job_queue, 613 struct drm_writeback_job, 614 list_entry); 615 acrtc->wb_pending = false; 616 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 617 618 if (job) { 619 unsigned int v_total, refresh_hz; 620 struct dc_stream_state *stream = acrtc->dm_irq_params.stream; 621 622 v_total = stream->adjust.v_total_max ? 623 stream->adjust.v_total_max : stream->timing.v_total; 624 refresh_hz = div_u64((uint64_t) stream->timing.pix_clk_100hz * 625 100LL, (v_total * stream->timing.h_total)); 626 mdelay(1000 / refresh_hz); 627 628 drm_writeback_signal_completion(acrtc->wb_conn, 0); 629 dc_stream_fc_disable_writeback(adev->dm.dc, 630 acrtc->dm_irq_params.stream, 0); 631 } 632 } else 633 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 634 } 635 636 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); 637 638 drm_dbg_vbl(adev_to_drm(adev), 639 "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id, 640 vrr_active, acrtc->dm_irq_params.active_planes); 641 642 /** 643 * Core vblank handling at start of front-porch is only possible 644 * in non-vrr mode, as only there vblank timestamping will give 645 * valid results while done in front-porch. Otherwise defer it 646 * to dm_vupdate_high_irq after end of front-porch. 647 */ 648 if (!vrr_active) 649 amdgpu_dm_crtc_handle_vblank(acrtc); 650 651 /** 652 * Following stuff must happen at start of vblank, for crc 653 * computation and below-the-range btr support in vrr mode. 654 */ 655 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); 656 657 /* BTR updates need to happen before VUPDATE on Vega and above. */ 658 if (adev->family < AMDGPU_FAMILY_AI) 659 return; 660 661 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 662 663 if (acrtc->dm_irq_params.stream && 664 acrtc->dm_irq_params.vrr_params.supported && 665 acrtc->dm_irq_params.freesync_config.state == 666 VRR_STATE_ACTIVE_VARIABLE) { 667 mod_freesync_handle_v_update(adev->dm.freesync_module, 668 acrtc->dm_irq_params.stream, 669 &acrtc->dm_irq_params.vrr_params); 670 671 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, 672 &acrtc->dm_irq_params.vrr_params.adjust); 673 } 674 675 /* 676 * If there aren't any active_planes then DCH HUBP may be clock-gated. 677 * In that case, pageflip completion interrupts won't fire and pageflip 678 * completion events won't get delivered. Prevent this by sending 679 * pending pageflip events from here if a flip is still pending. 680 * 681 * If any planes are enabled, use dm_pflip_high_irq() instead, to 682 * avoid race conditions between flip programming and completion, 683 * which could cause too early flip completion events. 684 */ 685 if (adev->family >= AMDGPU_FAMILY_RV && 686 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && 687 acrtc->dm_irq_params.active_planes == 0) { 688 if (acrtc->event) { 689 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); 690 acrtc->event = NULL; 691 drm_crtc_vblank_put(&acrtc->base); 692 } 693 acrtc->pflip_status = AMDGPU_FLIP_NONE; 694 } 695 696 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 697 } 698 699 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 700 /** 701 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for 702 * DCN generation ASICs 703 * @interrupt_params: interrupt parameters 704 * 705 * Used to set crc window/read out crc value at vertical line 0 position 706 */ 707 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) 708 { 709 struct common_irq_params *irq_params = interrupt_params; 710 struct amdgpu_device *adev = irq_params->adev; 711 struct amdgpu_crtc *acrtc; 712 713 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); 714 715 if (!acrtc) 716 return; 717 718 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); 719 } 720 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ 721 722 /** 723 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. 724 * @adev: amdgpu_device pointer 725 * @notify: dmub notification structure 726 * 727 * Dmub AUX or SET_CONFIG command completion processing callback 728 * Copies dmub notification to DM which is to be read by AUX command. 729 * issuing thread and also signals the event to wake up the thread. 730 */ 731 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, 732 struct dmub_notification *notify) 733 { 734 if (adev->dm.dmub_notify) 735 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification)); 736 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) 737 complete(&adev->dm.dmub_aux_transfer_done); 738 } 739 740 /** 741 * dmub_hpd_callback - DMUB HPD interrupt processing callback. 742 * @adev: amdgpu_device pointer 743 * @notify: dmub notification structure 744 * 745 * Dmub Hpd interrupt processing callback. Gets displayindex through the 746 * ink index and calls helper to do the processing. 747 */ 748 static void dmub_hpd_callback(struct amdgpu_device *adev, 749 struct dmub_notification *notify) 750 { 751 struct amdgpu_dm_connector *aconnector; 752 struct amdgpu_dm_connector *hpd_aconnector = NULL; 753 struct drm_connector *connector; 754 struct drm_connector_list_iter iter; 755 struct dc_link *link; 756 u8 link_index = 0; 757 struct drm_device *dev; 758 759 if (adev == NULL) 760 return; 761 762 if (notify == NULL) { 763 DRM_ERROR("DMUB HPD callback notification was NULL"); 764 return; 765 } 766 767 if (notify->link_index > adev->dm.dc->link_count) { 768 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index); 769 return; 770 } 771 772 link_index = notify->link_index; 773 link = adev->dm.dc->links[link_index]; 774 dev = adev->dm.ddev; 775 776 drm_connector_list_iter_begin(dev, &iter); 777 drm_for_each_connector_iter(connector, &iter) { 778 779 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 780 continue; 781 782 aconnector = to_amdgpu_dm_connector(connector); 783 if (link && aconnector->dc_link == link) { 784 if (notify->type == DMUB_NOTIFICATION_HPD) 785 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index); 786 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) 787 DRM_INFO("DMUB HPD RX IRQ callback: link_index=%u\n", link_index); 788 else 789 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n", 790 notify->type, link_index); 791 792 hpd_aconnector = aconnector; 793 break; 794 } 795 } 796 drm_connector_list_iter_end(&iter); 797 798 if (hpd_aconnector) { 799 if (notify->type == DMUB_NOTIFICATION_HPD) { 800 if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG)) 801 DRM_WARN("DMUB reported hpd status unchanged. link_index=%u\n", link_index); 802 handle_hpd_irq_helper(hpd_aconnector); 803 } else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) { 804 handle_hpd_rx_irq(hpd_aconnector); 805 } 806 } 807 } 808 809 /** 810 * register_dmub_notify_callback - Sets callback for DMUB notify 811 * @adev: amdgpu_device pointer 812 * @type: Type of dmub notification 813 * @callback: Dmub interrupt callback function 814 * @dmub_int_thread_offload: offload indicator 815 * 816 * API to register a dmub callback handler for a dmub notification 817 * Also sets indicator whether callback processing to be offloaded. 818 * to dmub interrupt handling thread 819 * Return: true if successfully registered, false if there is existing registration 820 */ 821 static bool register_dmub_notify_callback(struct amdgpu_device *adev, 822 enum dmub_notification_type type, 823 dmub_notify_interrupt_callback_t callback, 824 bool dmub_int_thread_offload) 825 { 826 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) { 827 adev->dm.dmub_callback[type] = callback; 828 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; 829 } else 830 return false; 831 832 return true; 833 } 834 835 static void dm_handle_hpd_work(struct work_struct *work) 836 { 837 struct dmub_hpd_work *dmub_hpd_wrk; 838 839 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work); 840 841 if (!dmub_hpd_wrk->dmub_notify) { 842 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL"); 843 return; 844 } 845 846 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) { 847 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, 848 dmub_hpd_wrk->dmub_notify); 849 } 850 851 kfree(dmub_hpd_wrk->dmub_notify); 852 kfree(dmub_hpd_wrk); 853 854 } 855 856 #define DMUB_TRACE_MAX_READ 64 857 /** 858 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt 859 * @interrupt_params: used for determining the Outbox instance 860 * 861 * Handles the Outbox Interrupt 862 * event handler. 863 */ 864 static void dm_dmub_outbox1_low_irq(void *interrupt_params) 865 { 866 struct dmub_notification notify = {0}; 867 struct common_irq_params *irq_params = interrupt_params; 868 struct amdgpu_device *adev = irq_params->adev; 869 struct amdgpu_display_manager *dm = &adev->dm; 870 struct dmcub_trace_buf_entry entry = { 0 }; 871 u32 count = 0; 872 struct dmub_hpd_work *dmub_hpd_wrk; 873 static const char *const event_type[] = { 874 "NO_DATA", 875 "AUX_REPLY", 876 "HPD", 877 "HPD_IRQ", 878 "SET_CONFIGC_REPLY", 879 "DPIA_NOTIFICATION", 880 }; 881 882 do { 883 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { 884 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, 885 entry.param0, entry.param1); 886 887 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n", 888 entry.trace_code, entry.tick_count, entry.param0, entry.param1); 889 } else 890 break; 891 892 count++; 893 894 } while (count <= DMUB_TRACE_MAX_READ); 895 896 if (count > DMUB_TRACE_MAX_READ) 897 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ"); 898 899 if (dc_enable_dmub_notifications(adev->dm.dc) && 900 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { 901 902 do { 903 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); 904 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) { 905 DRM_ERROR("DM: notify type %d invalid!", notify.type); 906 continue; 907 } 908 if (!dm->dmub_callback[notify.type]) { 909 DRM_WARN("DMUB notification skipped due to no handler: type=%s\n", 910 event_type[notify.type]); 911 continue; 912 } 913 if (dm->dmub_thread_offload[notify.type] == true) { 914 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC); 915 if (!dmub_hpd_wrk) { 916 DRM_ERROR("Failed to allocate dmub_hpd_wrk"); 917 return; 918 } 919 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification), 920 GFP_ATOMIC); 921 if (!dmub_hpd_wrk->dmub_notify) { 922 kfree(dmub_hpd_wrk); 923 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify"); 924 return; 925 } 926 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); 927 dmub_hpd_wrk->adev = adev; 928 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); 929 } else { 930 dm->dmub_callback[notify.type](adev, ¬ify); 931 } 932 } while (notify.pending_notification); 933 } 934 } 935 936 static int dm_set_clockgating_state(void *handle, 937 enum amd_clockgating_state state) 938 { 939 return 0; 940 } 941 942 static int dm_set_powergating_state(void *handle, 943 enum amd_powergating_state state) 944 { 945 return 0; 946 } 947 948 /* Prototypes of private functions */ 949 static int dm_early_init(void *handle); 950 951 /* Allocate memory for FBC compressed data */ 952 static void amdgpu_dm_fbc_init(struct drm_connector *connector) 953 { 954 struct amdgpu_device *adev = drm_to_adev(connector->dev); 955 struct dm_compressor_info *compressor = &adev->dm.compressor; 956 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); 957 struct drm_display_mode *mode; 958 unsigned long max_size = 0; 959 960 if (adev->dm.dc->fbc_compressor == NULL) 961 return; 962 963 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) 964 return; 965 966 if (compressor->bo_ptr) 967 return; 968 969 970 list_for_each_entry(mode, &connector->modes, head) { 971 if (max_size < (unsigned long) mode->htotal * mode->vtotal) 972 max_size = (unsigned long) mode->htotal * mode->vtotal; 973 } 974 975 if (max_size) { 976 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE, 977 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr, 978 &compressor->gpu_addr, &compressor->cpu_addr); 979 980 if (r) 981 DRM_ERROR("DM: Failed to initialize FBC\n"); 982 else { 983 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; 984 DRM_INFO("DM: FBC alloc %lu\n", max_size*4); 985 } 986 987 } 988 989 } 990 991 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, 992 int pipe, bool *enabled, 993 unsigned char *buf, int max_bytes) 994 { 995 struct drm_device *dev = dev_get_drvdata(kdev); 996 struct amdgpu_device *adev = drm_to_adev(dev); 997 struct drm_connector *connector; 998 struct drm_connector_list_iter conn_iter; 999 struct amdgpu_dm_connector *aconnector; 1000 int ret = 0; 1001 1002 *enabled = false; 1003 1004 mutex_lock(&adev->dm.audio_lock); 1005 1006 drm_connector_list_iter_begin(dev, &conn_iter); 1007 drm_for_each_connector_iter(connector, &conn_iter) { 1008 1009 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1010 continue; 1011 1012 aconnector = to_amdgpu_dm_connector(connector); 1013 if (aconnector->audio_inst != port) 1014 continue; 1015 1016 *enabled = true; 1017 ret = drm_eld_size(connector->eld); 1018 memcpy(buf, connector->eld, min(max_bytes, ret)); 1019 1020 break; 1021 } 1022 drm_connector_list_iter_end(&conn_iter); 1023 1024 mutex_unlock(&adev->dm.audio_lock); 1025 1026 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); 1027 1028 return ret; 1029 } 1030 1031 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { 1032 .get_eld = amdgpu_dm_audio_component_get_eld, 1033 }; 1034 1035 static int amdgpu_dm_audio_component_bind(struct device *kdev, 1036 struct device *hda_kdev, void *data) 1037 { 1038 struct drm_device *dev = dev_get_drvdata(kdev); 1039 struct amdgpu_device *adev = drm_to_adev(dev); 1040 struct drm_audio_component *acomp = data; 1041 1042 acomp->ops = &amdgpu_dm_audio_component_ops; 1043 acomp->dev = kdev; 1044 adev->dm.audio_component = acomp; 1045 1046 return 0; 1047 } 1048 1049 static void amdgpu_dm_audio_component_unbind(struct device *kdev, 1050 struct device *hda_kdev, void *data) 1051 { 1052 struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev)); 1053 struct drm_audio_component *acomp = data; 1054 1055 acomp->ops = NULL; 1056 acomp->dev = NULL; 1057 adev->dm.audio_component = NULL; 1058 } 1059 1060 static const struct component_ops amdgpu_dm_audio_component_bind_ops = { 1061 .bind = amdgpu_dm_audio_component_bind, 1062 .unbind = amdgpu_dm_audio_component_unbind, 1063 }; 1064 1065 static int amdgpu_dm_audio_init(struct amdgpu_device *adev) 1066 { 1067 int i, ret; 1068 1069 if (!amdgpu_audio) 1070 return 0; 1071 1072 adev->mode_info.audio.enabled = true; 1073 1074 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; 1075 1076 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1077 adev->mode_info.audio.pin[i].channels = -1; 1078 adev->mode_info.audio.pin[i].rate = -1; 1079 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1080 adev->mode_info.audio.pin[i].status_bits = 0; 1081 adev->mode_info.audio.pin[i].category_code = 0; 1082 adev->mode_info.audio.pin[i].connected = false; 1083 adev->mode_info.audio.pin[i].id = 1084 adev->dm.dc->res_pool->audios[i]->inst; 1085 adev->mode_info.audio.pin[i].offset = 0; 1086 } 1087 1088 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1089 if (ret < 0) 1090 return ret; 1091 1092 adev->dm.audio_registered = true; 1093 1094 return 0; 1095 } 1096 1097 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) 1098 { 1099 if (!amdgpu_audio) 1100 return; 1101 1102 if (!adev->mode_info.audio.enabled) 1103 return; 1104 1105 if (adev->dm.audio_registered) { 1106 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); 1107 adev->dm.audio_registered = false; 1108 } 1109 1110 /* TODO: Disable audio? */ 1111 1112 adev->mode_info.audio.enabled = false; 1113 } 1114 1115 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) 1116 { 1117 struct drm_audio_component *acomp = adev->dm.audio_component; 1118 1119 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { 1120 DRM_DEBUG_KMS("Notify ELD: %d\n", pin); 1121 1122 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 1123 pin, -1); 1124 } 1125 } 1126 1127 static int dm_dmub_hw_init(struct amdgpu_device *adev) 1128 { 1129 const struct dmcub_firmware_header_v1_0 *hdr; 1130 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1131 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 1132 const struct firmware *dmub_fw = adev->dm.dmub_fw; 1133 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; 1134 struct abm *abm = adev->dm.dc->res_pool->abm; 1135 struct dc_context *ctx = adev->dm.dc->ctx; 1136 struct dmub_srv_hw_params hw_params; 1137 enum dmub_status status; 1138 const unsigned char *fw_inst_const, *fw_bss_data; 1139 u32 i, fw_inst_const_size, fw_bss_data_size; 1140 bool has_hw_support; 1141 1142 if (!dmub_srv) 1143 /* DMUB isn't supported on the ASIC. */ 1144 return 0; 1145 1146 if (!fb_info) { 1147 DRM_ERROR("No framebuffer info for DMUB service.\n"); 1148 return -EINVAL; 1149 } 1150 1151 if (!dmub_fw) { 1152 /* Firmware required for DMUB support. */ 1153 DRM_ERROR("No firmware provided for DMUB.\n"); 1154 return -EINVAL; 1155 } 1156 1157 /* initialize register offsets for ASICs with runtime initialization available */ 1158 if (dmub_srv->hw_funcs.init_reg_offsets) 1159 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx); 1160 1161 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); 1162 if (status != DMUB_STATUS_OK) { 1163 DRM_ERROR("Error checking HW support for DMUB: %d\n", status); 1164 return -EINVAL; 1165 } 1166 1167 if (!has_hw_support) { 1168 DRM_INFO("DMUB unsupported on ASIC\n"); 1169 return 0; 1170 } 1171 1172 /* Reset DMCUB if it was previously running - before we overwrite its memory. */ 1173 status = dmub_srv_hw_reset(dmub_srv); 1174 if (status != DMUB_STATUS_OK) 1175 DRM_WARN("Error resetting DMUB HW: %d\n", status); 1176 1177 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; 1178 1179 fw_inst_const = dmub_fw->data + 1180 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1181 PSP_HEADER_BYTES; 1182 1183 fw_bss_data = dmub_fw->data + 1184 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 1185 le32_to_cpu(hdr->inst_const_bytes); 1186 1187 /* Copy firmware and bios info into FB memory. */ 1188 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 1189 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 1190 1191 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 1192 1193 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, 1194 * amdgpu_ucode_init_single_fw will load dmub firmware 1195 * fw_inst_const part to cw0; otherwise, the firmware back door load 1196 * will be done by dm_dmub_hw_init 1197 */ 1198 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1199 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const, 1200 fw_inst_const_size); 1201 } 1202 1203 if (fw_bss_data_size) 1204 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr, 1205 fw_bss_data, fw_bss_data_size); 1206 1207 /* Copy firmware bios info into FB memory. */ 1208 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios, 1209 adev->bios_size); 1210 1211 /* Reset regions that need to be reset. */ 1212 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0, 1213 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size); 1214 1215 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0, 1216 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size); 1217 1218 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0, 1219 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size); 1220 1221 memset(fb_info->fb[DMUB_WINDOW_SHARED_STATE].cpu_addr, 0, 1222 fb_info->fb[DMUB_WINDOW_SHARED_STATE].size); 1223 1224 /* Initialize hardware. */ 1225 memset(&hw_params, 0, sizeof(hw_params)); 1226 hw_params.fb_base = adev->gmc.fb_start; 1227 hw_params.fb_offset = adev->vm_manager.vram_base_offset; 1228 1229 /* backdoor load firmware and trigger dmub running */ 1230 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 1231 hw_params.load_inst_const = true; 1232 1233 if (dmcu) 1234 hw_params.psp_version = dmcu->psp_version; 1235 1236 for (i = 0; i < fb_info->num_fb; ++i) 1237 hw_params.fb[i] = &fb_info->fb[i]; 1238 1239 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1240 case IP_VERSION(3, 1, 3): 1241 case IP_VERSION(3, 1, 4): 1242 case IP_VERSION(3, 5, 0): 1243 case IP_VERSION(3, 5, 1): 1244 case IP_VERSION(4, 0, 1): 1245 hw_params.dpia_supported = true; 1246 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; 1247 break; 1248 default: 1249 break; 1250 } 1251 1252 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1253 case IP_VERSION(3, 5, 0): 1254 case IP_VERSION(3, 5, 1): 1255 hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; 1256 break; 1257 default: 1258 break; 1259 } 1260 1261 status = dmub_srv_hw_init(dmub_srv, &hw_params); 1262 if (status != DMUB_STATUS_OK) { 1263 DRM_ERROR("Error initializing DMUB HW: %d\n", status); 1264 return -EINVAL; 1265 } 1266 1267 /* Wait for firmware load to finish. */ 1268 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1269 if (status != DMUB_STATUS_OK) 1270 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1271 1272 /* Init DMCU and ABM if available. */ 1273 if (dmcu && abm) { 1274 dmcu->funcs->dmcu_init(dmcu); 1275 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 1276 } 1277 1278 if (!adev->dm.dc->ctx->dmub_srv) 1279 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); 1280 if (!adev->dm.dc->ctx->dmub_srv) { 1281 DRM_ERROR("Couldn't allocate DC DMUB server!\n"); 1282 return -ENOMEM; 1283 } 1284 1285 DRM_INFO("DMUB hardware initialized: version=0x%08X\n", 1286 adev->dm.dmcub_fw_version); 1287 1288 return 0; 1289 } 1290 1291 static void dm_dmub_hw_resume(struct amdgpu_device *adev) 1292 { 1293 struct dmub_srv *dmub_srv = adev->dm.dmub_srv; 1294 enum dmub_status status; 1295 bool init; 1296 int r; 1297 1298 if (!dmub_srv) { 1299 /* DMUB isn't supported on the ASIC. */ 1300 return; 1301 } 1302 1303 status = dmub_srv_is_hw_init(dmub_srv, &init); 1304 if (status != DMUB_STATUS_OK) 1305 DRM_WARN("DMUB hardware init check failed: %d\n", status); 1306 1307 if (status == DMUB_STATUS_OK && init) { 1308 /* Wait for firmware load to finish. */ 1309 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); 1310 if (status != DMUB_STATUS_OK) 1311 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status); 1312 } else { 1313 /* Perform the full hardware initialization. */ 1314 r = dm_dmub_hw_init(adev); 1315 if (r) 1316 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1317 } 1318 } 1319 1320 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 1321 { 1322 u64 pt_base; 1323 u32 logical_addr_low; 1324 u32 logical_addr_high; 1325 u32 agp_base, agp_bot, agp_top; 1326 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 1327 1328 memset(pa_config, 0, sizeof(*pa_config)); 1329 1330 agp_base = 0; 1331 agp_bot = adev->gmc.agp_start >> 24; 1332 agp_top = adev->gmc.agp_end >> 24; 1333 1334 /* AGP aperture is disabled */ 1335 if (agp_bot > agp_top) { 1336 logical_addr_low = adev->gmc.fb_start >> 18; 1337 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1338 AMD_APU_IS_RENOIR | 1339 AMD_APU_IS_GREEN_SARDINE)) 1340 /* 1341 * Raven2 has a HW issue that it is unable to use the vram which 1342 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1343 * workaround that increase system aperture high address (add 1) 1344 * to get rid of the VM fault and hardware hang. 1345 */ 1346 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 1347 else 1348 logical_addr_high = adev->gmc.fb_end >> 18; 1349 } else { 1350 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 1351 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 1352 AMD_APU_IS_RENOIR | 1353 AMD_APU_IS_GREEN_SARDINE)) 1354 /* 1355 * Raven2 has a HW issue that it is unable to use the vram which 1356 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 1357 * workaround that increase system aperture high address (add 1) 1358 * to get rid of the VM fault and hardware hang. 1359 */ 1360 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 1361 else 1362 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 1363 } 1364 1365 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 1366 1367 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 1368 AMDGPU_GPU_PAGE_SHIFT); 1369 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 1370 AMDGPU_GPU_PAGE_SHIFT); 1371 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 1372 AMDGPU_GPU_PAGE_SHIFT); 1373 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 1374 AMDGPU_GPU_PAGE_SHIFT); 1375 page_table_base.high_part = upper_32_bits(pt_base); 1376 page_table_base.low_part = lower_32_bits(pt_base); 1377 1378 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 1379 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 1380 1381 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 1382 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 1383 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 1384 1385 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 1386 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 1387 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 1388 1389 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 1390 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 1391 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 1392 1393 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 1394 1395 } 1396 1397 static void force_connector_state( 1398 struct amdgpu_dm_connector *aconnector, 1399 enum drm_connector_force force_state) 1400 { 1401 struct drm_connector *connector = &aconnector->base; 1402 1403 mutex_lock(&connector->dev->mode_config.mutex); 1404 aconnector->base.force = force_state; 1405 mutex_unlock(&connector->dev->mode_config.mutex); 1406 1407 mutex_lock(&aconnector->hpd_lock); 1408 drm_kms_helper_connector_hotplug_event(connector); 1409 mutex_unlock(&aconnector->hpd_lock); 1410 } 1411 1412 static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 1413 { 1414 struct hpd_rx_irq_offload_work *offload_work; 1415 struct amdgpu_dm_connector *aconnector; 1416 struct dc_link *dc_link; 1417 struct amdgpu_device *adev; 1418 enum dc_connection_type new_connection_type = dc_connection_none; 1419 unsigned long flags; 1420 union test_response test_response; 1421 1422 memset(&test_response, 0, sizeof(test_response)); 1423 1424 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work); 1425 aconnector = offload_work->offload_wq->aconnector; 1426 1427 if (!aconnector) { 1428 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work"); 1429 goto skip; 1430 } 1431 1432 adev = drm_to_adev(aconnector->base.dev); 1433 dc_link = aconnector->dc_link; 1434 1435 mutex_lock(&aconnector->hpd_lock); 1436 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 1437 DRM_ERROR("KMS: Failed to detect connector\n"); 1438 mutex_unlock(&aconnector->hpd_lock); 1439 1440 if (new_connection_type == dc_connection_none) 1441 goto skip; 1442 1443 if (amdgpu_in_reset(adev)) 1444 goto skip; 1445 1446 if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 1447 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 1448 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); 1449 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1450 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false; 1451 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1452 goto skip; 1453 } 1454 1455 mutex_lock(&adev->dm.dc_lock); 1456 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 1457 dc_link_dp_handle_automated_test(dc_link); 1458 1459 if (aconnector->timing_changed) { 1460 /* force connector disconnect and reconnect */ 1461 force_connector_state(aconnector, DRM_FORCE_OFF); 1462 msleep(100); 1463 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); 1464 } 1465 1466 test_response.bits.ACK = 1; 1467 1468 core_link_write_dpcd( 1469 dc_link, 1470 DP_TEST_RESPONSE, 1471 &test_response.raw, 1472 sizeof(test_response)); 1473 } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && 1474 dc_link_check_link_loss_status(dc_link, &offload_work->data) && 1475 dc_link_dp_allow_hpd_rx_irq(dc_link)) { 1476 /* offload_work->data is from handle_hpd_rx_irq-> 1477 * schedule_hpd_rx_offload_work.this is defer handle 1478 * for hpd short pulse. upon here, link status may be 1479 * changed, need get latest link status from dpcd 1480 * registers. if link status is good, skip run link 1481 * training again. 1482 */ 1483 union hpd_irq_data irq_data; 1484 1485 memset(&irq_data, 0, sizeof(irq_data)); 1486 1487 /* before dc_link_dp_handle_link_loss, allow new link lost handle 1488 * request be added to work queue if link lost at end of dc_link_ 1489 * dp_handle_link_loss 1490 */ 1491 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags); 1492 offload_work->offload_wq->is_handling_link_loss = false; 1493 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags); 1494 1495 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && 1496 dc_link_check_link_loss_status(dc_link, &irq_data)) 1497 dc_link_dp_handle_link_loss(dc_link); 1498 } 1499 mutex_unlock(&adev->dm.dc_lock); 1500 1501 skip: 1502 kfree(offload_work); 1503 1504 } 1505 1506 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) 1507 { 1508 int max_caps = dc->caps.max_links; 1509 int i = 0; 1510 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL; 1511 1512 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL); 1513 1514 if (!hpd_rx_offload_wq) 1515 return NULL; 1516 1517 1518 for (i = 0; i < max_caps; i++) { 1519 hpd_rx_offload_wq[i].wq = 1520 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); 1521 1522 if (hpd_rx_offload_wq[i].wq == NULL) { 1523 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!"); 1524 goto out_err; 1525 } 1526 1527 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock); 1528 } 1529 1530 return hpd_rx_offload_wq; 1531 1532 out_err: 1533 for (i = 0; i < max_caps; i++) { 1534 if (hpd_rx_offload_wq[i].wq) 1535 destroy_workqueue(hpd_rx_offload_wq[i].wq); 1536 } 1537 kfree(hpd_rx_offload_wq); 1538 return NULL; 1539 } 1540 1541 struct amdgpu_stutter_quirk { 1542 u16 chip_vendor; 1543 u16 chip_device; 1544 u16 subsys_vendor; 1545 u16 subsys_device; 1546 u8 revision; 1547 }; 1548 1549 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 1550 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 1551 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1552 { 0, 0, 0, 0, 0 }, 1553 }; 1554 1555 static bool dm_should_disable_stutter(struct pci_dev *pdev) 1556 { 1557 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 1558 1559 while (p && p->chip_device != 0) { 1560 if (pdev->vendor == p->chip_vendor && 1561 pdev->device == p->chip_device && 1562 pdev->subsystem_vendor == p->subsys_vendor && 1563 pdev->subsystem_device == p->subsys_device && 1564 pdev->revision == p->revision) { 1565 return true; 1566 } 1567 ++p; 1568 } 1569 return false; 1570 } 1571 1572 static const struct dmi_system_id hpd_disconnect_quirk_table[] = { 1573 { 1574 .matches = { 1575 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1576 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), 1577 }, 1578 }, 1579 { 1580 .matches = { 1581 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1582 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), 1583 }, 1584 }, 1585 { 1586 .matches = { 1587 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1588 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), 1589 }, 1590 }, 1591 { 1592 .matches = { 1593 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1594 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"), 1595 }, 1596 }, 1597 { 1598 .matches = { 1599 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1600 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"), 1601 }, 1602 }, 1603 { 1604 .matches = { 1605 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1606 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"), 1607 }, 1608 }, 1609 { 1610 .matches = { 1611 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1612 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"), 1613 }, 1614 }, 1615 { 1616 .matches = { 1617 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1618 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"), 1619 }, 1620 }, 1621 { 1622 .matches = { 1623 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 1624 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"), 1625 }, 1626 }, 1627 {} 1628 /* TODO: refactor this from a fixed table to a dynamic option */ 1629 }; 1630 1631 static void retrieve_dmi_info(struct amdgpu_display_manager *dm) 1632 { 1633 const struct dmi_system_id *dmi_id; 1634 1635 dm->aux_hpd_discon_quirk = false; 1636 1637 dmi_id = dmi_first_match(hpd_disconnect_quirk_table); 1638 if (dmi_id) { 1639 dm->aux_hpd_discon_quirk = true; 1640 DRM_INFO("aux_hpd_discon_quirk attached\n"); 1641 } 1642 } 1643 1644 void* 1645 dm_allocate_gpu_mem( 1646 struct amdgpu_device *adev, 1647 enum dc_gpu_mem_alloc_type type, 1648 size_t size, 1649 long long *addr) 1650 { 1651 struct dal_allocation *da; 1652 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 1653 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 1654 int ret; 1655 1656 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL); 1657 if (!da) 1658 return NULL; 1659 1660 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 1661 domain, &da->bo, 1662 &da->gpu_addr, &da->cpu_ptr); 1663 1664 *addr = da->gpu_addr; 1665 1666 if (ret) { 1667 kfree(da); 1668 return NULL; 1669 } 1670 1671 /* add da to list in dm */ 1672 list_add(&da->list, &adev->dm.da_list); 1673 1674 return da->cpu_ptr; 1675 } 1676 1677 static enum dmub_status 1678 dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev, 1679 enum dmub_gpint_command command_code, 1680 uint16_t param, 1681 uint32_t timeout_us) 1682 { 1683 union dmub_gpint_data_register reg, test; 1684 uint32_t i; 1685 1686 /* Assume that VBIOS DMUB is ready to take commands */ 1687 1688 reg.bits.status = 1; 1689 reg.bits.command_code = command_code; 1690 reg.bits.param = param; 1691 1692 cgs_write_register(adev->dm.cgs_device, 0x34c0 + 0x01f8, reg.all); 1693 1694 for (i = 0; i < timeout_us; ++i) { 1695 udelay(1); 1696 1697 /* Check if our GPINT got acked */ 1698 reg.bits.status = 0; 1699 test = (union dmub_gpint_data_register) 1700 cgs_read_register(adev->dm.cgs_device, 0x34c0 + 0x01f8); 1701 1702 if (test.all == reg.all) 1703 return DMUB_STATUS_OK; 1704 } 1705 1706 return DMUB_STATUS_TIMEOUT; 1707 } 1708 1709 static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) 1710 { 1711 struct dml2_soc_bb *bb; 1712 long long addr; 1713 int i = 0; 1714 uint16_t chunk; 1715 enum dmub_gpint_command send_addrs[] = { 1716 DMUB_GPINT__SET_BB_ADDR_WORD0, 1717 DMUB_GPINT__SET_BB_ADDR_WORD1, 1718 DMUB_GPINT__SET_BB_ADDR_WORD2, 1719 DMUB_GPINT__SET_BB_ADDR_WORD3, 1720 }; 1721 enum dmub_status ret; 1722 1723 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1724 case IP_VERSION(4, 0, 1): 1725 break; 1726 default: 1727 return NULL; 1728 } 1729 1730 bb = dm_allocate_gpu_mem(adev, 1731 DC_MEM_ALLOC_TYPE_GART, 1732 sizeof(struct dml2_soc_bb), 1733 &addr); 1734 if (!bb) 1735 return NULL; 1736 1737 for (i = 0; i < 4; i++) { 1738 /* Extract 16-bit chunk */ 1739 chunk = ((uint64_t) addr >> (i * 16)) & 0xFFFF; 1740 /* Send the chunk */ 1741 ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000); 1742 if (ret != DMUB_STATUS_OK) 1743 /* No need to free bb here since it shall be done in dm_sw_fini() */ 1744 return NULL; 1745 } 1746 1747 /* Now ask DMUB to copy the bb */ 1748 ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000); 1749 if (ret != DMUB_STATUS_OK) 1750 return NULL; 1751 1752 return bb; 1753 } 1754 1755 static int amdgpu_dm_init(struct amdgpu_device *adev) 1756 { 1757 struct dc_init_data init_data; 1758 struct dc_callback_init init_params; 1759 int r; 1760 1761 adev->dm.ddev = adev_to_drm(adev); 1762 adev->dm.adev = adev; 1763 1764 /* Zero all the fields */ 1765 memset(&init_data, 0, sizeof(init_data)); 1766 memset(&init_params, 0, sizeof(init_params)); 1767 1768 mutex_init(&adev->dm.dpia_aux_lock); 1769 mutex_init(&adev->dm.dc_lock); 1770 mutex_init(&adev->dm.audio_lock); 1771 1772 if (amdgpu_dm_irq_init(adev)) { 1773 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); 1774 goto error; 1775 } 1776 1777 init_data.asic_id.chip_family = adev->family; 1778 1779 init_data.asic_id.pci_revision_id = adev->pdev->revision; 1780 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 1781 init_data.asic_id.chip_id = adev->pdev->device; 1782 1783 init_data.asic_id.vram_width = adev->gmc.vram_width; 1784 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 1785 init_data.asic_id.atombios_base_address = 1786 adev->mode_info.atom_context->bios; 1787 1788 init_data.driver = adev; 1789 1790 /* cgs_device was created in dm_sw_init() */ 1791 init_data.cgs_device = adev->dm.cgs_device; 1792 1793 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 1794 1795 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1796 case IP_VERSION(2, 1, 0): 1797 switch (adev->dm.dmcub_fw_version) { 1798 case 0: /* development */ 1799 case 0x1: /* linux-firmware.git hash 6d9f399 */ 1800 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 1801 init_data.flags.disable_dmcu = false; 1802 break; 1803 default: 1804 init_data.flags.disable_dmcu = true; 1805 } 1806 break; 1807 case IP_VERSION(2, 0, 3): 1808 init_data.flags.disable_dmcu = true; 1809 break; 1810 default: 1811 break; 1812 } 1813 1814 /* APU support S/G display by default except: 1815 * ASICs before Carrizo, 1816 * RAVEN1 (Users reported stability issue) 1817 */ 1818 1819 if (adev->asic_type < CHIP_CARRIZO) { 1820 init_data.flags.gpu_vm_support = false; 1821 } else if (adev->asic_type == CHIP_RAVEN) { 1822 if (adev->apu_flags & AMD_APU_IS_RAVEN) 1823 init_data.flags.gpu_vm_support = false; 1824 else 1825 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 1826 } else { 1827 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 1828 } 1829 1830 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 1831 1832 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 1833 init_data.flags.fbc_support = true; 1834 1835 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 1836 init_data.flags.multi_mon_pp_mclk_switch = true; 1837 1838 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 1839 init_data.flags.disable_fractional_pwm = true; 1840 1841 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 1842 init_data.flags.edp_no_power_sequencing = true; 1843 1844 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 1845 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 1846 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 1847 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 1848 1849 init_data.flags.seamless_boot_edp_requested = false; 1850 1851 if (amdgpu_device_seamless_boot_supported(adev)) { 1852 init_data.flags.seamless_boot_edp_requested = true; 1853 init_data.flags.allow_seamless_boot_optimization = true; 1854 DRM_INFO("Seamless boot condition check passed\n"); 1855 } 1856 1857 init_data.flags.enable_mipi_converter_optimization = true; 1858 1859 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 1860 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 1861 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 1862 1863 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 1864 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 1865 else 1866 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 1867 1868 init_data.flags.disable_ips_in_vpb = 0; 1869 1870 /* Enable DWB for tested platforms only */ 1871 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 1872 init_data.num_virtual_links = 1; 1873 1874 retrieve_dmi_info(&adev->dm); 1875 1876 if (adev->dm.bb_from_dmub) 1877 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 1878 else 1879 init_data.bb_from_dmub = NULL; 1880 1881 /* Display Core create. */ 1882 adev->dm.dc = dc_create(&init_data); 1883 1884 if (adev->dm.dc) { 1885 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER, 1886 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 1887 } else { 1888 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER); 1889 goto error; 1890 } 1891 1892 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 1893 adev->dm.dc->debug.force_single_disp_pipe_split = false; 1894 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 1895 } 1896 1897 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 1898 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 1899 if (dm_should_disable_stutter(adev->pdev)) 1900 adev->dm.dc->debug.disable_stutter = true; 1901 1902 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 1903 adev->dm.dc->debug.disable_stutter = true; 1904 1905 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 1906 adev->dm.dc->debug.disable_dsc = true; 1907 1908 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 1909 adev->dm.dc->debug.disable_clock_gate = true; 1910 1911 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 1912 adev->dm.dc->debug.force_subvp_mclk_switch = true; 1913 1914 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 1915 adev->dm.dc->debug.using_dml2 = true; 1916 adev->dm.dc->debug.using_dml21 = true; 1917 } 1918 1919 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 1920 1921 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 1922 adev->dm.dc->debug.ignore_cable_id = true; 1923 1924 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 1925 DRM_INFO("DP-HDMI FRL PCON supported\n"); 1926 1927 r = dm_dmub_hw_init(adev); 1928 if (r) { 1929 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 1930 goto error; 1931 } 1932 1933 dc_hardware_init(adev->dm.dc); 1934 1935 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); 1936 if (!adev->dm.hpd_rx_offload_wq) { 1937 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n"); 1938 goto error; 1939 } 1940 1941 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 1942 struct dc_phy_addr_space_config pa_config; 1943 1944 mmhub_read_system_context(adev, &pa_config); 1945 1946 // Call the DC init_memory func 1947 dc_setup_system_context(adev->dm.dc, &pa_config); 1948 } 1949 1950 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 1951 if (!adev->dm.freesync_module) { 1952 DRM_ERROR( 1953 "amdgpu: failed to initialize freesync_module.\n"); 1954 } else 1955 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", 1956 adev->dm.freesync_module); 1957 1958 amdgpu_dm_init_color_mod(); 1959 1960 if (adev->dm.dc->caps.max_links > 0) { 1961 adev->dm.vblank_control_workqueue = 1962 create_singlethread_workqueue("dm_vblank_control_workqueue"); 1963 if (!adev->dm.vblank_control_workqueue) 1964 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); 1965 } 1966 1967 if (adev->dm.dc->caps.ips_support && adev->dm.dc->config.disable_ips == DMUB_IPS_ENABLE) 1968 adev->dm.idle_workqueue = idle_create_workqueue(adev); 1969 1970 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 1971 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 1972 1973 if (!adev->dm.hdcp_workqueue) 1974 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n"); 1975 else 1976 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); 1977 1978 dc_init_callbacks(adev->dm.dc, &init_params); 1979 } 1980 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 1981 init_completion(&adev->dm.dmub_aux_transfer_done); 1982 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL); 1983 if (!adev->dm.dmub_notify) { 1984 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify"); 1985 goto error; 1986 } 1987 1988 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 1989 if (!adev->dm.delayed_hpd_wq) { 1990 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n"); 1991 goto error; 1992 } 1993 1994 amdgpu_dm_outbox_init(adev); 1995 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 1996 dmub_aux_setconfig_callback, false)) { 1997 DRM_ERROR("amdgpu: fail to register dmub aux callback"); 1998 goto error; 1999 } 2000 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 2001 * It is expected that DMUB will resend any pending notifications at this point. Note 2002 * that hpd and hpd_irq handler registration are deferred to register_hpd_handlers() to 2003 * align legacy interface initialization sequence. Connection status will be proactivly 2004 * detected once in the amdgpu_dm_initialize_drm_device. 2005 */ 2006 dc_enable_dmub_outbox(adev->dm.dc); 2007 2008 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 2009 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 2010 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 2011 } 2012 2013 if (amdgpu_dm_initialize_drm_device(adev)) { 2014 DRM_ERROR( 2015 "amdgpu: failed to initialize sw for display support.\n"); 2016 goto error; 2017 } 2018 2019 /* create fake encoders for MST */ 2020 dm_dp_create_fake_mst_encoders(adev); 2021 2022 /* TODO: Add_display_info? */ 2023 2024 /* TODO use dynamic cursor width */ 2025 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 2026 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 2027 2028 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 2029 DRM_ERROR( 2030 "amdgpu: failed to initialize sw for display support.\n"); 2031 goto error; 2032 } 2033 2034 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 2035 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev); 2036 if (!adev->dm.secure_display_ctxs) 2037 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n"); 2038 #endif 2039 2040 DRM_DEBUG_DRIVER("KMS initialized.\n"); 2041 2042 return 0; 2043 error: 2044 amdgpu_dm_fini(adev); 2045 2046 return -EINVAL; 2047 } 2048 2049 static int amdgpu_dm_early_fini(void *handle) 2050 { 2051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2052 2053 amdgpu_dm_audio_fini(adev); 2054 2055 return 0; 2056 } 2057 2058 static void amdgpu_dm_fini(struct amdgpu_device *adev) 2059 { 2060 int i; 2061 2062 if (adev->dm.vblank_control_workqueue) { 2063 destroy_workqueue(adev->dm.vblank_control_workqueue); 2064 adev->dm.vblank_control_workqueue = NULL; 2065 } 2066 2067 if (adev->dm.idle_workqueue) { 2068 if (adev->dm.idle_workqueue->running) { 2069 adev->dm.idle_workqueue->enable = false; 2070 flush_work(&adev->dm.idle_workqueue->work); 2071 } 2072 2073 kfree(adev->dm.idle_workqueue); 2074 adev->dm.idle_workqueue = NULL; 2075 } 2076 2077 amdgpu_dm_destroy_drm_device(&adev->dm); 2078 2079 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 2080 if (adev->dm.secure_display_ctxs) { 2081 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2082 if (adev->dm.secure_display_ctxs[i].crtc) { 2083 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work); 2084 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work); 2085 } 2086 } 2087 kfree(adev->dm.secure_display_ctxs); 2088 adev->dm.secure_display_ctxs = NULL; 2089 } 2090 #endif 2091 if (adev->dm.hdcp_workqueue) { 2092 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 2093 adev->dm.hdcp_workqueue = NULL; 2094 } 2095 2096 if (adev->dm.dc) { 2097 dc_deinit_callbacks(adev->dm.dc); 2098 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 2099 if (dc_enable_dmub_notifications(adev->dm.dc)) { 2100 kfree(adev->dm.dmub_notify); 2101 adev->dm.dmub_notify = NULL; 2102 destroy_workqueue(adev->dm.delayed_hpd_wq); 2103 adev->dm.delayed_hpd_wq = NULL; 2104 } 2105 } 2106 2107 if (adev->dm.dmub_bo) 2108 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 2109 &adev->dm.dmub_bo_gpu_addr, 2110 &adev->dm.dmub_bo_cpu_addr); 2111 2112 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 2113 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 2114 if (adev->dm.hpd_rx_offload_wq[i].wq) { 2115 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 2116 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 2117 } 2118 } 2119 2120 kfree(adev->dm.hpd_rx_offload_wq); 2121 adev->dm.hpd_rx_offload_wq = NULL; 2122 } 2123 2124 /* DC Destroy TODO: Replace destroy DAL */ 2125 if (adev->dm.dc) 2126 dc_destroy(&adev->dm.dc); 2127 /* 2128 * TODO: pageflip, vlank interrupt 2129 * 2130 * amdgpu_dm_irq_fini(adev); 2131 */ 2132 2133 if (adev->dm.cgs_device) { 2134 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 2135 adev->dm.cgs_device = NULL; 2136 } 2137 if (adev->dm.freesync_module) { 2138 mod_freesync_destroy(adev->dm.freesync_module); 2139 adev->dm.freesync_module = NULL; 2140 } 2141 2142 mutex_destroy(&adev->dm.audio_lock); 2143 mutex_destroy(&adev->dm.dc_lock); 2144 mutex_destroy(&adev->dm.dpia_aux_lock); 2145 } 2146 2147 static int load_dmcu_fw(struct amdgpu_device *adev) 2148 { 2149 const char *fw_name_dmcu = NULL; 2150 int r; 2151 const struct dmcu_firmware_header_v1_0 *hdr; 2152 2153 switch (adev->asic_type) { 2154 #if defined(CONFIG_DRM_AMD_DC_SI) 2155 case CHIP_TAHITI: 2156 case CHIP_PITCAIRN: 2157 case CHIP_VERDE: 2158 case CHIP_OLAND: 2159 #endif 2160 case CHIP_BONAIRE: 2161 case CHIP_HAWAII: 2162 case CHIP_KAVERI: 2163 case CHIP_KABINI: 2164 case CHIP_MULLINS: 2165 case CHIP_TONGA: 2166 case CHIP_FIJI: 2167 case CHIP_CARRIZO: 2168 case CHIP_STONEY: 2169 case CHIP_POLARIS11: 2170 case CHIP_POLARIS10: 2171 case CHIP_POLARIS12: 2172 case CHIP_VEGAM: 2173 case CHIP_VEGA10: 2174 case CHIP_VEGA12: 2175 case CHIP_VEGA20: 2176 return 0; 2177 case CHIP_NAVI12: 2178 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 2179 break; 2180 case CHIP_RAVEN: 2181 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 2182 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2183 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 2184 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 2185 else 2186 return 0; 2187 break; 2188 default: 2189 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2190 case IP_VERSION(2, 0, 2): 2191 case IP_VERSION(2, 0, 3): 2192 case IP_VERSION(2, 0, 0): 2193 case IP_VERSION(2, 1, 0): 2194 case IP_VERSION(3, 0, 0): 2195 case IP_VERSION(3, 0, 2): 2196 case IP_VERSION(3, 0, 3): 2197 case IP_VERSION(3, 0, 1): 2198 case IP_VERSION(3, 1, 2): 2199 case IP_VERSION(3, 1, 3): 2200 case IP_VERSION(3, 1, 4): 2201 case IP_VERSION(3, 1, 5): 2202 case IP_VERSION(3, 1, 6): 2203 case IP_VERSION(3, 2, 0): 2204 case IP_VERSION(3, 2, 1): 2205 case IP_VERSION(3, 5, 0): 2206 case IP_VERSION(3, 5, 1): 2207 case IP_VERSION(4, 0, 1): 2208 return 0; 2209 default: 2210 break; 2211 } 2212 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); 2213 return -EINVAL; 2214 } 2215 2216 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2217 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); 2218 return 0; 2219 } 2220 2221 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu); 2222 if (r == -ENODEV) { 2223 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 2224 DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); 2225 adev->dm.fw_dmcu = NULL; 2226 return 0; 2227 } 2228 if (r) { 2229 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n", 2230 fw_name_dmcu); 2231 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2232 return r; 2233 } 2234 2235 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 2236 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 2237 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 2238 adev->firmware.fw_size += 2239 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2240 2241 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 2242 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 2243 adev->firmware.fw_size += 2244 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 2245 2246 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 2247 2248 DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); 2249 2250 return 0; 2251 } 2252 2253 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) 2254 { 2255 struct amdgpu_device *adev = ctx; 2256 2257 return dm_read_reg(adev->dm.dc->ctx, address); 2258 } 2259 2260 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, 2261 uint32_t value) 2262 { 2263 struct amdgpu_device *adev = ctx; 2264 2265 return dm_write_reg(adev->dm.dc->ctx, address, value); 2266 } 2267 2268 static int dm_dmub_sw_init(struct amdgpu_device *adev) 2269 { 2270 struct dmub_srv_create_params create_params; 2271 struct dmub_srv_region_params region_params; 2272 struct dmub_srv_region_info region_info; 2273 struct dmub_srv_memory_params memory_params; 2274 struct dmub_srv_fb_info *fb_info; 2275 struct dmub_srv *dmub_srv; 2276 const struct dmcub_firmware_header_v1_0 *hdr; 2277 enum dmub_asic dmub_asic; 2278 enum dmub_status status; 2279 static enum dmub_window_memory_type window_memory_type[DMUB_WINDOW_TOTAL] = { 2280 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_0_INST_CONST 2281 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_1_STACK 2282 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_2_BSS_DATA 2283 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_3_VBIOS 2284 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_4_MAILBOX 2285 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_5_TRACEBUFF 2286 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_6_FW_STATE 2287 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM 2288 DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE 2289 }; 2290 int r; 2291 2292 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2293 case IP_VERSION(2, 1, 0): 2294 dmub_asic = DMUB_ASIC_DCN21; 2295 break; 2296 case IP_VERSION(3, 0, 0): 2297 dmub_asic = DMUB_ASIC_DCN30; 2298 break; 2299 case IP_VERSION(3, 0, 1): 2300 dmub_asic = DMUB_ASIC_DCN301; 2301 break; 2302 case IP_VERSION(3, 0, 2): 2303 dmub_asic = DMUB_ASIC_DCN302; 2304 break; 2305 case IP_VERSION(3, 0, 3): 2306 dmub_asic = DMUB_ASIC_DCN303; 2307 break; 2308 case IP_VERSION(3, 1, 2): 2309 case IP_VERSION(3, 1, 3): 2310 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; 2311 break; 2312 case IP_VERSION(3, 1, 4): 2313 dmub_asic = DMUB_ASIC_DCN314; 2314 break; 2315 case IP_VERSION(3, 1, 5): 2316 dmub_asic = DMUB_ASIC_DCN315; 2317 break; 2318 case IP_VERSION(3, 1, 6): 2319 dmub_asic = DMUB_ASIC_DCN316; 2320 break; 2321 case IP_VERSION(3, 2, 0): 2322 dmub_asic = DMUB_ASIC_DCN32; 2323 break; 2324 case IP_VERSION(3, 2, 1): 2325 dmub_asic = DMUB_ASIC_DCN321; 2326 break; 2327 case IP_VERSION(3, 5, 0): 2328 case IP_VERSION(3, 5, 1): 2329 dmub_asic = DMUB_ASIC_DCN35; 2330 break; 2331 case IP_VERSION(4, 0, 1): 2332 dmub_asic = DMUB_ASIC_DCN401; 2333 break; 2334 2335 default: 2336 /* ASIC doesn't support DMUB. */ 2337 return 0; 2338 } 2339 2340 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; 2341 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version); 2342 2343 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2344 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = 2345 AMDGPU_UCODE_ID_DMCUB; 2346 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = 2347 adev->dm.dmub_fw; 2348 adev->firmware.fw_size += 2349 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE); 2350 2351 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n", 2352 adev->dm.dmcub_fw_version); 2353 } 2354 2355 2356 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL); 2357 dmub_srv = adev->dm.dmub_srv; 2358 2359 if (!dmub_srv) { 2360 DRM_ERROR("Failed to allocate DMUB service!\n"); 2361 return -ENOMEM; 2362 } 2363 2364 memset(&create_params, 0, sizeof(create_params)); 2365 create_params.user_ctx = adev; 2366 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; 2367 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; 2368 create_params.asic = dmub_asic; 2369 2370 /* Create the DMUB service. */ 2371 status = dmub_srv_create(dmub_srv, &create_params); 2372 if (status != DMUB_STATUS_OK) { 2373 DRM_ERROR("Error creating DMUB service: %d\n", status); 2374 return -EINVAL; 2375 } 2376 2377 /* Calculate the size of all the regions for the DMUB service. */ 2378 memset(®ion_params, 0, sizeof(region_params)); 2379 2380 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - 2381 PSP_HEADER_BYTES - PSP_FOOTER_BYTES; 2382 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); 2383 region_params.vbios_size = adev->bios_size; 2384 region_params.fw_bss_data = region_params.bss_data_size ? 2385 adev->dm.dmub_fw->data + 2386 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2387 le32_to_cpu(hdr->inst_const_bytes) : NULL; 2388 region_params.fw_inst_const = 2389 adev->dm.dmub_fw->data + 2390 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 2391 PSP_HEADER_BYTES; 2392 region_params.window_memory_type = window_memory_type; 2393 2394 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, 2395 ®ion_info); 2396 2397 if (status != DMUB_STATUS_OK) { 2398 DRM_ERROR("Error calculating DMUB region info: %d\n", status); 2399 return -EINVAL; 2400 } 2401 2402 /* 2403 * Allocate a framebuffer based on the total size of all the regions. 2404 * TODO: Move this into GART. 2405 */ 2406 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE, 2407 AMDGPU_GEM_DOMAIN_VRAM | 2408 AMDGPU_GEM_DOMAIN_GTT, 2409 &adev->dm.dmub_bo, 2410 &adev->dm.dmub_bo_gpu_addr, 2411 &adev->dm.dmub_bo_cpu_addr); 2412 if (r) 2413 return r; 2414 2415 /* Rebase the regions on the framebuffer address. */ 2416 memset(&memory_params, 0, sizeof(memory_params)); 2417 memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; 2418 memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; 2419 memory_params.region_info = ®ion_info; 2420 memory_params.window_memory_type = window_memory_type; 2421 2422 adev->dm.dmub_fb_info = 2423 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL); 2424 fb_info = adev->dm.dmub_fb_info; 2425 2426 if (!fb_info) { 2427 DRM_ERROR( 2428 "Failed to allocate framebuffer info for DMUB service!\n"); 2429 return -ENOMEM; 2430 } 2431 2432 status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); 2433 if (status != DMUB_STATUS_OK) { 2434 DRM_ERROR("Error calculating DMUB FB info: %d\n", status); 2435 return -EINVAL; 2436 } 2437 2438 adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev); 2439 2440 return 0; 2441 } 2442 2443 static int dm_sw_init(void *handle) 2444 { 2445 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2446 int r; 2447 2448 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 2449 2450 if (!adev->dm.cgs_device) { 2451 DRM_ERROR("amdgpu: failed to create cgs device.\n"); 2452 return -EINVAL; 2453 } 2454 2455 /* Moved from dm init since we need to use allocations for storing bounding box data */ 2456 INIT_LIST_HEAD(&adev->dm.da_list); 2457 2458 r = dm_dmub_sw_init(adev); 2459 if (r) 2460 return r; 2461 2462 return load_dmcu_fw(adev); 2463 } 2464 2465 static int dm_sw_fini(void *handle) 2466 { 2467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2468 struct dal_allocation *da; 2469 2470 list_for_each_entry(da, &adev->dm.da_list, list) { 2471 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 2472 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 2473 list_del(&da->list); 2474 kfree(da); 2475 break; 2476 } 2477 } 2478 2479 adev->dm.bb_from_dmub = NULL; 2480 2481 kfree(adev->dm.dmub_fb_info); 2482 adev->dm.dmub_fb_info = NULL; 2483 2484 if (adev->dm.dmub_srv) { 2485 dmub_srv_destroy(adev->dm.dmub_srv); 2486 kfree(adev->dm.dmub_srv); 2487 adev->dm.dmub_srv = NULL; 2488 } 2489 2490 amdgpu_ucode_release(&adev->dm.dmub_fw); 2491 amdgpu_ucode_release(&adev->dm.fw_dmcu); 2492 2493 return 0; 2494 } 2495 2496 static int detect_mst_link_for_all_connectors(struct drm_device *dev) 2497 { 2498 struct amdgpu_dm_connector *aconnector; 2499 struct drm_connector *connector; 2500 struct drm_connector_list_iter iter; 2501 int ret = 0; 2502 2503 drm_connector_list_iter_begin(dev, &iter); 2504 drm_for_each_connector_iter(connector, &iter) { 2505 2506 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2507 continue; 2508 2509 aconnector = to_amdgpu_dm_connector(connector); 2510 if (aconnector->dc_link->type == dc_connection_mst_branch && 2511 aconnector->mst_mgr.aux) { 2512 drm_dbg_kms(dev, "DM_MST: starting TM on aconnector: %p [id: %d]\n", 2513 aconnector, 2514 aconnector->base.base.id); 2515 2516 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 2517 if (ret < 0) { 2518 drm_err(dev, "DM_MST: Failed to start MST\n"); 2519 aconnector->dc_link->type = 2520 dc_connection_single; 2521 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 2522 aconnector->dc_link); 2523 break; 2524 } 2525 } 2526 } 2527 drm_connector_list_iter_end(&iter); 2528 2529 return ret; 2530 } 2531 2532 static int dm_late_init(void *handle) 2533 { 2534 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2535 2536 struct dmcu_iram_parameters params; 2537 unsigned int linear_lut[16]; 2538 int i; 2539 struct dmcu *dmcu = NULL; 2540 2541 dmcu = adev->dm.dc->res_pool->dmcu; 2542 2543 for (i = 0; i < 16; i++) 2544 linear_lut[i] = 0xFFFF * i / 15; 2545 2546 params.set = 0; 2547 params.backlight_ramping_override = false; 2548 params.backlight_ramping_start = 0xCCCC; 2549 params.backlight_ramping_reduction = 0xCCCCCCCC; 2550 params.backlight_lut_array_size = 16; 2551 params.backlight_lut_array = linear_lut; 2552 2553 /* Min backlight level after ABM reduction, Don't allow below 1% 2554 * 0xFFFF x 0.01 = 0x28F 2555 */ 2556 params.min_abm_backlight = 0x28F; 2557 /* In the case where abm is implemented on dmcub, 2558 * dmcu object will be null. 2559 * ABM 2.4 and up are implemented on dmcub. 2560 */ 2561 if (dmcu) { 2562 if (!dmcu_load_iram(dmcu, params)) 2563 return -EINVAL; 2564 } else if (adev->dm.dc->ctx->dmub_srv) { 2565 struct dc_link *edp_links[MAX_NUM_EDP]; 2566 int edp_num; 2567 2568 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 2569 for (i = 0; i < edp_num; i++) { 2570 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 2571 return -EINVAL; 2572 } 2573 } 2574 2575 return detect_mst_link_for_all_connectors(adev_to_drm(adev)); 2576 } 2577 2578 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 2579 { 2580 int ret; 2581 u8 guid[16]; 2582 u64 tmp64; 2583 2584 mutex_lock(&mgr->lock); 2585 if (!mgr->mst_primary) 2586 goto out_fail; 2587 2588 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 2589 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2590 goto out_fail; 2591 } 2592 2593 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 2594 DP_MST_EN | 2595 DP_UP_REQ_EN | 2596 DP_UPSTREAM_IS_SRC); 2597 if (ret < 0) { 2598 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 2599 goto out_fail; 2600 } 2601 2602 /* Some hubs forget their guids after they resume */ 2603 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); 2604 if (ret != 16) { 2605 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 2606 goto out_fail; 2607 } 2608 2609 if (memchr_inv(guid, 0, 16) == NULL) { 2610 tmp64 = get_jiffies_64(); 2611 memcpy(&guid[0], &tmp64, sizeof(u64)); 2612 memcpy(&guid[8], &tmp64, sizeof(u64)); 2613 2614 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); 2615 2616 if (ret != 16) { 2617 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 2618 goto out_fail; 2619 } 2620 } 2621 2622 memcpy(mgr->mst_primary->guid, guid, 16); 2623 2624 out_fail: 2625 mutex_unlock(&mgr->lock); 2626 } 2627 2628 static void s3_handle_mst(struct drm_device *dev, bool suspend) 2629 { 2630 struct amdgpu_dm_connector *aconnector; 2631 struct drm_connector *connector; 2632 struct drm_connector_list_iter iter; 2633 struct drm_dp_mst_topology_mgr *mgr; 2634 2635 drm_connector_list_iter_begin(dev, &iter); 2636 drm_for_each_connector_iter(connector, &iter) { 2637 2638 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2639 continue; 2640 2641 aconnector = to_amdgpu_dm_connector(connector); 2642 if (aconnector->dc_link->type != dc_connection_mst_branch || 2643 aconnector->mst_root) 2644 continue; 2645 2646 mgr = &aconnector->mst_mgr; 2647 2648 if (suspend) { 2649 drm_dp_mst_topology_mgr_suspend(mgr); 2650 } else { 2651 /* if extended timeout is supported in hardware, 2652 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 2653 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 2654 */ 2655 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 2656 if (!dp_is_lttpr_present(aconnector->dc_link)) 2657 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 2658 2659 /* TODO: move resume_mst_branch_status() into drm mst resume again 2660 * once topology probing work is pulled out from mst resume into mst 2661 * resume 2nd step. mst resume 2nd step should be called after old 2662 * state getting restored (i.e. drm_atomic_helper_resume()). 2663 */ 2664 resume_mst_branch_status(mgr); 2665 } 2666 } 2667 drm_connector_list_iter_end(&iter); 2668 } 2669 2670 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 2671 { 2672 int ret = 0; 2673 2674 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 2675 * on window driver dc implementation. 2676 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 2677 * should be passed to smu during boot up and resume from s3. 2678 * boot up: dc calculate dcn watermark clock settings within dc_create, 2679 * dcn20_resource_construct 2680 * then call pplib functions below to pass the settings to smu: 2681 * smu_set_watermarks_for_clock_ranges 2682 * smu_set_watermarks_table 2683 * navi10_set_watermarks_table 2684 * smu_write_watermarks_table 2685 * 2686 * For Renoir, clock settings of dcn watermark are also fixed values. 2687 * dc has implemented different flow for window driver: 2688 * dc_hardware_init / dc_set_power_state 2689 * dcn10_init_hw 2690 * notify_wm_ranges 2691 * set_wm_ranges 2692 * -- Linux 2693 * smu_set_watermarks_for_clock_ranges 2694 * renoir_set_watermarks_table 2695 * smu_write_watermarks_table 2696 * 2697 * For Linux, 2698 * dc_hardware_init -> amdgpu_dm_init 2699 * dc_set_power_state --> dm_resume 2700 * 2701 * therefore, this function apply to navi10/12/14 but not Renoir 2702 * * 2703 */ 2704 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2705 case IP_VERSION(2, 0, 2): 2706 case IP_VERSION(2, 0, 0): 2707 break; 2708 default: 2709 return 0; 2710 } 2711 2712 ret = amdgpu_dpm_write_watermarks_table(adev); 2713 if (ret) { 2714 DRM_ERROR("Failed to update WMTABLE!\n"); 2715 return ret; 2716 } 2717 2718 return 0; 2719 } 2720 2721 /** 2722 * dm_hw_init() - Initialize DC device 2723 * @handle: The base driver device containing the amdgpu_dm device. 2724 * 2725 * Initialize the &struct amdgpu_display_manager device. This involves calling 2726 * the initializers of each DM component, then populating the struct with them. 2727 * 2728 * Although the function implies hardware initialization, both hardware and 2729 * software are initialized here. Splitting them out to their relevant init 2730 * hooks is a future TODO item. 2731 * 2732 * Some notable things that are initialized here: 2733 * 2734 * - Display Core, both software and hardware 2735 * - DC modules that we need (freesync and color management) 2736 * - DRM software states 2737 * - Interrupt sources and handlers 2738 * - Vblank support 2739 * - Debug FS entries, if enabled 2740 */ 2741 static int dm_hw_init(void *handle) 2742 { 2743 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2744 int r; 2745 2746 /* Create DAL display manager */ 2747 r = amdgpu_dm_init(adev); 2748 if (r) 2749 return r; 2750 amdgpu_dm_hpd_init(adev); 2751 2752 return 0; 2753 } 2754 2755 /** 2756 * dm_hw_fini() - Teardown DC device 2757 * @handle: The base driver device containing the amdgpu_dm device. 2758 * 2759 * Teardown components within &struct amdgpu_display_manager that require 2760 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 2761 * were loaded. Also flush IRQ workqueues and disable them. 2762 */ 2763 static int dm_hw_fini(void *handle) 2764 { 2765 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2766 2767 amdgpu_dm_hpd_fini(adev); 2768 2769 amdgpu_dm_irq_fini(adev); 2770 amdgpu_dm_fini(adev); 2771 return 0; 2772 } 2773 2774 2775 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 2776 struct dc_state *state, bool enable) 2777 { 2778 enum dc_irq_source irq_source; 2779 struct amdgpu_crtc *acrtc; 2780 int rc = -EBUSY; 2781 int i = 0; 2782 2783 for (i = 0; i < state->stream_count; i++) { 2784 acrtc = get_crtc_by_otg_inst( 2785 adev, state->stream_status[i].primary_otg_inst); 2786 2787 if (acrtc && state->stream_status[i].plane_count != 0) { 2788 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 2789 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 2790 if (rc) 2791 DRM_WARN("Failed to %s pflip interrupts\n", 2792 enable ? "enable" : "disable"); 2793 2794 if (enable) { 2795 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state))) 2796 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true); 2797 } else 2798 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false); 2799 2800 if (rc) 2801 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis"); 2802 2803 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 2804 /* During gpu-reset we disable and then enable vblank irq, so 2805 * don't use amdgpu_irq_get/put() to avoid refcount change. 2806 */ 2807 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 2808 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 2809 } 2810 } 2811 2812 } 2813 2814 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 2815 { 2816 struct dc_state *context = NULL; 2817 enum dc_status res = DC_ERROR_UNEXPECTED; 2818 int i; 2819 struct dc_stream_state *del_streams[MAX_PIPES]; 2820 int del_streams_count = 0; 2821 struct dc_commit_streams_params params = {}; 2822 2823 memset(del_streams, 0, sizeof(del_streams)); 2824 2825 context = dc_state_create_current_copy(dc); 2826 if (context == NULL) 2827 goto context_alloc_fail; 2828 2829 /* First remove from context all streams */ 2830 for (i = 0; i < context->stream_count; i++) { 2831 struct dc_stream_state *stream = context->streams[i]; 2832 2833 del_streams[del_streams_count++] = stream; 2834 } 2835 2836 /* Remove all planes for removed streams and then remove the streams */ 2837 for (i = 0; i < del_streams_count; i++) { 2838 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) { 2839 res = DC_FAIL_DETACH_SURFACES; 2840 goto fail; 2841 } 2842 2843 res = dc_state_remove_stream(dc, context, del_streams[i]); 2844 if (res != DC_OK) 2845 goto fail; 2846 } 2847 2848 params.streams = context->streams; 2849 params.stream_count = context->stream_count; 2850 res = dc_commit_streams(dc, ¶ms); 2851 2852 fail: 2853 dc_state_release(context); 2854 2855 context_alloc_fail: 2856 return res; 2857 } 2858 2859 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) 2860 { 2861 int i; 2862 2863 if (dm->hpd_rx_offload_wq) { 2864 for (i = 0; i < dm->dc->caps.max_links; i++) 2865 flush_workqueue(dm->hpd_rx_offload_wq[i].wq); 2866 } 2867 } 2868 2869 static int dm_suspend(void *handle) 2870 { 2871 struct amdgpu_device *adev = handle; 2872 struct amdgpu_display_manager *dm = &adev->dm; 2873 int ret = 0; 2874 2875 if (amdgpu_in_reset(adev)) { 2876 mutex_lock(&dm->dc_lock); 2877 2878 dc_allow_idle_optimizations(adev->dm.dc, false); 2879 2880 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 2881 2882 if (dm->cached_dc_state) 2883 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 2884 2885 amdgpu_dm_commit_zero_streams(dm->dc); 2886 2887 amdgpu_dm_irq_suspend(adev); 2888 2889 hpd_rx_irq_work_suspend(dm); 2890 2891 return ret; 2892 } 2893 2894 WARN_ON(adev->dm.cached_state); 2895 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 2896 if (IS_ERR(adev->dm.cached_state)) 2897 return PTR_ERR(adev->dm.cached_state); 2898 2899 s3_handle_mst(adev_to_drm(adev), true); 2900 2901 amdgpu_dm_irq_suspend(adev); 2902 2903 hpd_rx_irq_work_suspend(dm); 2904 2905 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 2906 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 2907 2908 return 0; 2909 } 2910 2911 struct drm_connector * 2912 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, 2913 struct drm_crtc *crtc) 2914 { 2915 u32 i; 2916 struct drm_connector_state *new_con_state; 2917 struct drm_connector *connector; 2918 struct drm_crtc *crtc_from_state; 2919 2920 for_each_new_connector_in_state(state, connector, new_con_state, i) { 2921 crtc_from_state = new_con_state->crtc; 2922 2923 if (crtc_from_state == crtc) 2924 return connector; 2925 } 2926 2927 return NULL; 2928 } 2929 2930 static void emulated_link_detect(struct dc_link *link) 2931 { 2932 struct dc_sink_init_data sink_init_data = { 0 }; 2933 struct display_sink_capability sink_caps = { 0 }; 2934 enum dc_edid_status edid_status; 2935 struct dc_context *dc_ctx = link->ctx; 2936 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 2937 struct dc_sink *sink = NULL; 2938 struct dc_sink *prev_sink = NULL; 2939 2940 link->type = dc_connection_none; 2941 prev_sink = link->local_sink; 2942 2943 if (prev_sink) 2944 dc_sink_release(prev_sink); 2945 2946 switch (link->connector_signal) { 2947 case SIGNAL_TYPE_HDMI_TYPE_A: { 2948 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2949 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 2950 break; 2951 } 2952 2953 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 2954 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2955 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 2956 break; 2957 } 2958 2959 case SIGNAL_TYPE_DVI_DUAL_LINK: { 2960 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2961 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 2962 break; 2963 } 2964 2965 case SIGNAL_TYPE_LVDS: { 2966 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 2967 sink_caps.signal = SIGNAL_TYPE_LVDS; 2968 break; 2969 } 2970 2971 case SIGNAL_TYPE_EDP: { 2972 sink_caps.transaction_type = 2973 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2974 sink_caps.signal = SIGNAL_TYPE_EDP; 2975 break; 2976 } 2977 2978 case SIGNAL_TYPE_DISPLAY_PORT: { 2979 sink_caps.transaction_type = 2980 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 2981 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 2982 break; 2983 } 2984 2985 default: 2986 drm_err(dev, "Invalid connector type! signal:%d\n", 2987 link->connector_signal); 2988 return; 2989 } 2990 2991 sink_init_data.link = link; 2992 sink_init_data.sink_signal = sink_caps.signal; 2993 2994 sink = dc_sink_create(&sink_init_data); 2995 if (!sink) { 2996 drm_err(dev, "Failed to create sink!\n"); 2997 return; 2998 } 2999 3000 /* dc_sink_create returns a new reference */ 3001 link->local_sink = sink; 3002 3003 edid_status = dm_helpers_read_local_edid( 3004 link->ctx, 3005 link, 3006 sink); 3007 3008 if (edid_status != EDID_OK) 3009 drm_err(dev, "Failed to read EDID\n"); 3010 3011 } 3012 3013 static void dm_gpureset_commit_state(struct dc_state *dc_state, 3014 struct amdgpu_display_manager *dm) 3015 { 3016 struct { 3017 struct dc_surface_update surface_updates[MAX_SURFACES]; 3018 struct dc_plane_info plane_infos[MAX_SURFACES]; 3019 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 3020 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 3021 struct dc_stream_update stream_update; 3022 } *bundle; 3023 int k, m; 3024 3025 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 3026 3027 if (!bundle) { 3028 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 3029 goto cleanup; 3030 } 3031 3032 for (k = 0; k < dc_state->stream_count; k++) { 3033 bundle->stream_update.stream = dc_state->streams[k]; 3034 3035 for (m = 0; m < dc_state->stream_status->plane_count; m++) { 3036 bundle->surface_updates[m].surface = 3037 dc_state->stream_status->plane_states[m]; 3038 bundle->surface_updates[m].surface->force_full_update = 3039 true; 3040 } 3041 3042 update_planes_and_stream_adapter(dm->dc, 3043 UPDATE_TYPE_FULL, 3044 dc_state->stream_status->plane_count, 3045 dc_state->streams[k], 3046 &bundle->stream_update, 3047 bundle->surface_updates); 3048 } 3049 3050 cleanup: 3051 kfree(bundle); 3052 } 3053 3054 static int dm_resume(void *handle) 3055 { 3056 struct amdgpu_device *adev = handle; 3057 struct drm_device *ddev = adev_to_drm(adev); 3058 struct amdgpu_display_manager *dm = &adev->dm; 3059 struct amdgpu_dm_connector *aconnector; 3060 struct drm_connector *connector; 3061 struct drm_connector_list_iter iter; 3062 struct drm_crtc *crtc; 3063 struct drm_crtc_state *new_crtc_state; 3064 struct dm_crtc_state *dm_new_crtc_state; 3065 struct drm_plane *plane; 3066 struct drm_plane_state *new_plane_state; 3067 struct dm_plane_state *dm_new_plane_state; 3068 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 3069 enum dc_connection_type new_connection_type = dc_connection_none; 3070 struct dc_state *dc_state; 3071 int i, r, j, ret; 3072 bool need_hotplug = false; 3073 struct dc_commit_streams_params commit_params = {}; 3074 3075 if (dm->dc->caps.ips_support) { 3076 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 3077 } 3078 3079 if (amdgpu_in_reset(adev)) { 3080 dc_state = dm->cached_dc_state; 3081 3082 /* 3083 * The dc->current_state is backed up into dm->cached_dc_state 3084 * before we commit 0 streams. 3085 * 3086 * DC will clear link encoder assignments on the real state 3087 * but the changes won't propagate over to the copy we made 3088 * before the 0 streams commit. 3089 * 3090 * DC expects that link encoder assignments are *not* valid 3091 * when committing a state, so as a workaround we can copy 3092 * off of the current state. 3093 * 3094 * We lose the previous assignments, but we had already 3095 * commit 0 streams anyway. 3096 */ 3097 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 3098 3099 r = dm_dmub_hw_init(adev); 3100 if (r) 3101 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r); 3102 3103 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3104 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3105 3106 dc_resume(dm->dc); 3107 3108 amdgpu_dm_irq_resume_early(adev); 3109 3110 for (i = 0; i < dc_state->stream_count; i++) { 3111 dc_state->streams[i]->mode_changed = true; 3112 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 3113 dc_state->stream_status[i].plane_states[j]->update_flags.raw 3114 = 0xffffffff; 3115 } 3116 } 3117 3118 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3119 amdgpu_dm_outbox_init(adev); 3120 dc_enable_dmub_outbox(adev->dm.dc); 3121 } 3122 3123 commit_params.streams = dc_state->streams; 3124 commit_params.stream_count = dc_state->stream_count; 3125 dc_exit_ips_for_hw_access(dm->dc); 3126 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 3127 3128 dm_gpureset_commit_state(dm->cached_dc_state, dm); 3129 3130 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 3131 3132 dc_state_release(dm->cached_dc_state); 3133 dm->cached_dc_state = NULL; 3134 3135 amdgpu_dm_irq_resume_late(adev); 3136 3137 mutex_unlock(&dm->dc_lock); 3138 3139 return 0; 3140 } 3141 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 3142 dc_state_release(dm_state->context); 3143 dm_state->context = dc_state_create(dm->dc, NULL); 3144 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 3145 3146 /* Before powering on DC we need to re-initialize DMUB. */ 3147 dm_dmub_hw_resume(adev); 3148 3149 /* Re-enable outbox interrupts for DPIA. */ 3150 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3151 amdgpu_dm_outbox_init(adev); 3152 dc_enable_dmub_outbox(adev->dm.dc); 3153 } 3154 3155 /* power on hardware */ 3156 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 3157 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 3158 3159 /* program HPD filter */ 3160 dc_resume(dm->dc); 3161 3162 /* 3163 * early enable HPD Rx IRQ, should be done before set mode as short 3164 * pulse interrupts are used for MST 3165 */ 3166 amdgpu_dm_irq_resume_early(adev); 3167 3168 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 3169 s3_handle_mst(ddev, false); 3170 3171 /* Do detection*/ 3172 drm_connector_list_iter_begin(ddev, &iter); 3173 drm_for_each_connector_iter(connector, &iter) { 3174 3175 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3176 continue; 3177 3178 aconnector = to_amdgpu_dm_connector(connector); 3179 3180 if (!aconnector->dc_link) 3181 continue; 3182 3183 /* 3184 * this is the case when traversing through already created end sink 3185 * MST connectors, should be skipped 3186 */ 3187 if (aconnector->mst_root) 3188 continue; 3189 3190 mutex_lock(&aconnector->hpd_lock); 3191 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3192 DRM_ERROR("KMS: Failed to detect connector\n"); 3193 3194 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3195 emulated_link_detect(aconnector->dc_link); 3196 } else { 3197 mutex_lock(&dm->dc_lock); 3198 dc_exit_ips_for_hw_access(dm->dc); 3199 dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 3200 mutex_unlock(&dm->dc_lock); 3201 } 3202 3203 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 3204 aconnector->fake_enable = false; 3205 3206 if (aconnector->dc_sink) 3207 dc_sink_release(aconnector->dc_sink); 3208 aconnector->dc_sink = NULL; 3209 amdgpu_dm_update_connector_after_detect(aconnector); 3210 mutex_unlock(&aconnector->hpd_lock); 3211 } 3212 drm_connector_list_iter_end(&iter); 3213 3214 /* Force mode set in atomic commit */ 3215 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) 3216 new_crtc_state->active_changed = true; 3217 3218 /* 3219 * atomic_check is expected to create the dc states. We need to release 3220 * them here, since they were duplicated as part of the suspend 3221 * procedure. 3222 */ 3223 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 3224 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 3225 if (dm_new_crtc_state->stream) { 3226 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 3227 dc_stream_release(dm_new_crtc_state->stream); 3228 dm_new_crtc_state->stream = NULL; 3229 } 3230 dm_new_crtc_state->base.color_mgmt_changed = true; 3231 } 3232 3233 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 3234 dm_new_plane_state = to_dm_plane_state(new_plane_state); 3235 if (dm_new_plane_state->dc_state) { 3236 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 3237 dc_plane_state_release(dm_new_plane_state->dc_state); 3238 dm_new_plane_state->dc_state = NULL; 3239 } 3240 } 3241 3242 drm_atomic_helper_resume(ddev, dm->cached_state); 3243 3244 dm->cached_state = NULL; 3245 3246 /* Do mst topology probing after resuming cached state*/ 3247 drm_connector_list_iter_begin(ddev, &iter); 3248 drm_for_each_connector_iter(connector, &iter) { 3249 3250 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3251 continue; 3252 3253 aconnector = to_amdgpu_dm_connector(connector); 3254 if (aconnector->dc_link->type != dc_connection_mst_branch || 3255 aconnector->mst_root) 3256 continue; 3257 3258 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); 3259 3260 if (ret < 0) { 3261 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, 3262 aconnector->dc_link); 3263 need_hotplug = true; 3264 } 3265 } 3266 drm_connector_list_iter_end(&iter); 3267 3268 if (need_hotplug) 3269 drm_kms_helper_hotplug_event(ddev); 3270 3271 amdgpu_dm_irq_resume_late(adev); 3272 3273 amdgpu_dm_smu_write_watermarks_table(adev); 3274 3275 return 0; 3276 } 3277 3278 /** 3279 * DOC: DM Lifecycle 3280 * 3281 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 3282 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 3283 * the base driver's device list to be initialized and torn down accordingly. 3284 * 3285 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 3286 */ 3287 3288 static const struct amd_ip_funcs amdgpu_dm_funcs = { 3289 .name = "dm", 3290 .early_init = dm_early_init, 3291 .late_init = dm_late_init, 3292 .sw_init = dm_sw_init, 3293 .sw_fini = dm_sw_fini, 3294 .early_fini = amdgpu_dm_early_fini, 3295 .hw_init = dm_hw_init, 3296 .hw_fini = dm_hw_fini, 3297 .suspend = dm_suspend, 3298 .resume = dm_resume, 3299 .is_idle = dm_is_idle, 3300 .wait_for_idle = dm_wait_for_idle, 3301 .check_soft_reset = dm_check_soft_reset, 3302 .soft_reset = dm_soft_reset, 3303 .set_clockgating_state = dm_set_clockgating_state, 3304 .set_powergating_state = dm_set_powergating_state, 3305 .dump_ip_state = NULL, 3306 .print_ip_state = NULL, 3307 }; 3308 3309 const struct amdgpu_ip_block_version dm_ip_block = { 3310 .type = AMD_IP_BLOCK_TYPE_DCE, 3311 .major = 1, 3312 .minor = 0, 3313 .rev = 0, 3314 .funcs = &amdgpu_dm_funcs, 3315 }; 3316 3317 3318 /** 3319 * DOC: atomic 3320 * 3321 * *WIP* 3322 */ 3323 3324 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 3325 .fb_create = amdgpu_display_user_framebuffer_create, 3326 .get_format_info = amdgpu_dm_plane_get_format_info, 3327 .atomic_check = amdgpu_dm_atomic_check, 3328 .atomic_commit = drm_atomic_helper_commit, 3329 }; 3330 3331 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 3332 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 3333 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 3334 }; 3335 3336 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 3337 { 3338 struct amdgpu_dm_backlight_caps *caps; 3339 struct drm_connector *conn_base; 3340 struct amdgpu_device *adev; 3341 struct drm_luminance_range_info *luminance_range; 3342 3343 if (aconnector->bl_idx == -1 || 3344 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) 3345 return; 3346 3347 conn_base = &aconnector->base; 3348 adev = drm_to_adev(conn_base->dev); 3349 3350 caps = &adev->dm.backlight_caps[aconnector->bl_idx]; 3351 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; 3352 caps->aux_support = false; 3353 3354 if (caps->ext_caps->bits.oled == 1 3355 /* 3356 * || 3357 * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || 3358 * caps->ext_caps->bits.hdr_aux_backlight_control == 1 3359 */) 3360 caps->aux_support = true; 3361 3362 if (amdgpu_backlight == 0) 3363 caps->aux_support = false; 3364 else if (amdgpu_backlight == 1) 3365 caps->aux_support = true; 3366 3367 luminance_range = &conn_base->display_info.luminance_range; 3368 3369 if (luminance_range->max_luminance) { 3370 caps->aux_min_input_signal = luminance_range->min_luminance; 3371 caps->aux_max_input_signal = luminance_range->max_luminance; 3372 } else { 3373 caps->aux_min_input_signal = 0; 3374 caps->aux_max_input_signal = 512; 3375 } 3376 } 3377 3378 void amdgpu_dm_update_connector_after_detect( 3379 struct amdgpu_dm_connector *aconnector) 3380 { 3381 struct drm_connector *connector = &aconnector->base; 3382 struct drm_device *dev = connector->dev; 3383 struct dc_sink *sink; 3384 3385 /* MST handled by drm_mst framework */ 3386 if (aconnector->mst_mgr.mst_state == true) 3387 return; 3388 3389 sink = aconnector->dc_link->local_sink; 3390 if (sink) 3391 dc_sink_retain(sink); 3392 3393 /* 3394 * Edid mgmt connector gets first update only in mode_valid hook and then 3395 * the connector sink is set to either fake or physical sink depends on link status. 3396 * Skip if already done during boot. 3397 */ 3398 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED 3399 && aconnector->dc_em_sink) { 3400 3401 /* 3402 * For S3 resume with headless use eml_sink to fake stream 3403 * because on resume connector->sink is set to NULL 3404 */ 3405 mutex_lock(&dev->mode_config.mutex); 3406 3407 if (sink) { 3408 if (aconnector->dc_sink) { 3409 amdgpu_dm_update_freesync_caps(connector, NULL); 3410 /* 3411 * retain and release below are used to 3412 * bump up refcount for sink because the link doesn't point 3413 * to it anymore after disconnect, so on next crtc to connector 3414 * reshuffle by UMD we will get into unwanted dc_sink release 3415 */ 3416 dc_sink_release(aconnector->dc_sink); 3417 } 3418 aconnector->dc_sink = sink; 3419 dc_sink_retain(aconnector->dc_sink); 3420 amdgpu_dm_update_freesync_caps(connector, 3421 aconnector->edid); 3422 } else { 3423 amdgpu_dm_update_freesync_caps(connector, NULL); 3424 if (!aconnector->dc_sink) { 3425 aconnector->dc_sink = aconnector->dc_em_sink; 3426 dc_sink_retain(aconnector->dc_sink); 3427 } 3428 } 3429 3430 mutex_unlock(&dev->mode_config.mutex); 3431 3432 if (sink) 3433 dc_sink_release(sink); 3434 return; 3435 } 3436 3437 /* 3438 * TODO: temporary guard to look for proper fix 3439 * if this sink is MST sink, we should not do anything 3440 */ 3441 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3442 dc_sink_release(sink); 3443 return; 3444 } 3445 3446 if (aconnector->dc_sink == sink) { 3447 /* 3448 * We got a DP short pulse (Link Loss, DP CTS, etc...). 3449 * Do nothing!! 3450 */ 3451 drm_dbg_kms(dev, "DCHPD: connector_id=%d: dc_sink didn't change.\n", 3452 aconnector->connector_id); 3453 if (sink) 3454 dc_sink_release(sink); 3455 return; 3456 } 3457 3458 drm_dbg_kms(dev, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", 3459 aconnector->connector_id, aconnector->dc_sink, sink); 3460 3461 mutex_lock(&dev->mode_config.mutex); 3462 3463 /* 3464 * 1. Update status of the drm connector 3465 * 2. Send an event and let userspace tell us what to do 3466 */ 3467 if (sink) { 3468 /* 3469 * TODO: check if we still need the S3 mode update workaround. 3470 * If yes, put it here. 3471 */ 3472 if (aconnector->dc_sink) { 3473 amdgpu_dm_update_freesync_caps(connector, NULL); 3474 dc_sink_release(aconnector->dc_sink); 3475 } 3476 3477 aconnector->dc_sink = sink; 3478 dc_sink_retain(aconnector->dc_sink); 3479 if (sink->dc_edid.length == 0) { 3480 aconnector->edid = NULL; 3481 if (aconnector->dc_link->aux_mode) { 3482 drm_dp_cec_unset_edid( 3483 &aconnector->dm_dp_aux.aux); 3484 } 3485 } else { 3486 aconnector->edid = 3487 (struct edid *)sink->dc_edid.raw_edid; 3488 3489 if (aconnector->dc_link->aux_mode) 3490 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, 3491 aconnector->edid); 3492 } 3493 3494 if (!aconnector->timing_requested) { 3495 aconnector->timing_requested = 3496 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL); 3497 if (!aconnector->timing_requested) 3498 drm_err(dev, 3499 "failed to create aconnector->requested_timing\n"); 3500 } 3501 3502 drm_connector_update_edid_property(connector, aconnector->edid); 3503 amdgpu_dm_update_freesync_caps(connector, aconnector->edid); 3504 update_connector_ext_caps(aconnector); 3505 } else { 3506 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); 3507 amdgpu_dm_update_freesync_caps(connector, NULL); 3508 drm_connector_update_edid_property(connector, NULL); 3509 aconnector->num_modes = 0; 3510 dc_sink_release(aconnector->dc_sink); 3511 aconnector->dc_sink = NULL; 3512 aconnector->edid = NULL; 3513 kfree(aconnector->timing_requested); 3514 aconnector->timing_requested = NULL; 3515 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ 3516 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3517 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3518 } 3519 3520 mutex_unlock(&dev->mode_config.mutex); 3521 3522 update_subconnector_property(aconnector); 3523 3524 if (sink) 3525 dc_sink_release(sink); 3526 } 3527 3528 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3529 { 3530 struct drm_connector *connector = &aconnector->base; 3531 struct drm_device *dev = connector->dev; 3532 enum dc_connection_type new_connection_type = dc_connection_none; 3533 struct amdgpu_device *adev = drm_to_adev(dev); 3534 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3535 struct dc *dc = aconnector->dc_link->ctx->dc; 3536 bool ret = false; 3537 3538 if (adev->dm.disable_hpd_irq) 3539 return; 3540 3541 /* 3542 * In case of failure or MST no need to update connector status or notify the OS 3543 * since (for MST case) MST does this in its own context. 3544 */ 3545 mutex_lock(&aconnector->hpd_lock); 3546 3547 if (adev->dm.hdcp_workqueue) { 3548 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 3549 dm_con_state->update_hdcp = true; 3550 } 3551 if (aconnector->fake_enable) 3552 aconnector->fake_enable = false; 3553 3554 aconnector->timing_changed = false; 3555 3556 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3557 DRM_ERROR("KMS: Failed to detect connector\n"); 3558 3559 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3560 emulated_link_detect(aconnector->dc_link); 3561 3562 drm_modeset_lock_all(dev); 3563 dm_restore_drm_connector_state(dev, connector); 3564 drm_modeset_unlock_all(dev); 3565 3566 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3567 drm_kms_helper_connector_hotplug_event(connector); 3568 } else { 3569 mutex_lock(&adev->dm.dc_lock); 3570 dc_exit_ips_for_hw_access(dc); 3571 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3572 mutex_unlock(&adev->dm.dc_lock); 3573 if (ret) { 3574 amdgpu_dm_update_connector_after_detect(aconnector); 3575 3576 drm_modeset_lock_all(dev); 3577 dm_restore_drm_connector_state(dev, connector); 3578 drm_modeset_unlock_all(dev); 3579 3580 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3581 drm_kms_helper_connector_hotplug_event(connector); 3582 } 3583 } 3584 mutex_unlock(&aconnector->hpd_lock); 3585 3586 } 3587 3588 static void handle_hpd_irq(void *param) 3589 { 3590 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3591 3592 handle_hpd_irq_helper(aconnector); 3593 3594 } 3595 3596 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, 3597 union hpd_irq_data hpd_irq_data) 3598 { 3599 struct hpd_rx_irq_offload_work *offload_work = 3600 kzalloc(sizeof(*offload_work), GFP_KERNEL); 3601 3602 if (!offload_work) { 3603 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n"); 3604 return; 3605 } 3606 3607 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); 3608 offload_work->data = hpd_irq_data; 3609 offload_work->offload_wq = offload_wq; 3610 3611 queue_work(offload_wq->wq, &offload_work->work); 3612 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); 3613 } 3614 3615 static void handle_hpd_rx_irq(void *param) 3616 { 3617 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; 3618 struct drm_connector *connector = &aconnector->base; 3619 struct drm_device *dev = connector->dev; 3620 struct dc_link *dc_link = aconnector->dc_link; 3621 bool is_mst_root_connector = aconnector->mst_mgr.mst_state; 3622 bool result = false; 3623 enum dc_connection_type new_connection_type = dc_connection_none; 3624 struct amdgpu_device *adev = drm_to_adev(dev); 3625 union hpd_irq_data hpd_irq_data; 3626 bool link_loss = false; 3627 bool has_left_work = false; 3628 int idx = dc_link->link_index; 3629 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; 3630 struct dc *dc = aconnector->dc_link->ctx->dc; 3631 3632 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data)); 3633 3634 if (adev->dm.disable_hpd_irq) 3635 return; 3636 3637 /* 3638 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio 3639 * conflict, after implement i2c helper, this mutex should be 3640 * retired. 3641 */ 3642 mutex_lock(&aconnector->hpd_lock); 3643 3644 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, 3645 &link_loss, true, &has_left_work); 3646 3647 if (!has_left_work) 3648 goto out; 3649 3650 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { 3651 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3652 goto out; 3653 } 3654 3655 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { 3656 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || 3657 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { 3658 bool skip = false; 3659 3660 /* 3661 * DOWN_REP_MSG_RDY is also handled by polling method 3662 * mgr->cbs->poll_hpd_irq() 3663 */ 3664 spin_lock(&offload_wq->offload_lock); 3665 skip = offload_wq->is_handling_mst_msg_rdy_event; 3666 3667 if (!skip) 3668 offload_wq->is_handling_mst_msg_rdy_event = true; 3669 3670 spin_unlock(&offload_wq->offload_lock); 3671 3672 if (!skip) 3673 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3674 3675 goto out; 3676 } 3677 3678 if (link_loss) { 3679 bool skip = false; 3680 3681 spin_lock(&offload_wq->offload_lock); 3682 skip = offload_wq->is_handling_link_loss; 3683 3684 if (!skip) 3685 offload_wq->is_handling_link_loss = true; 3686 3687 spin_unlock(&offload_wq->offload_lock); 3688 3689 if (!skip) 3690 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); 3691 3692 goto out; 3693 } 3694 } 3695 3696 out: 3697 if (result && !is_mst_root_connector) { 3698 /* Downstream Port status changed. */ 3699 if (!dc_link_detect_connection_type(dc_link, &new_connection_type)) 3700 DRM_ERROR("KMS: Failed to detect connector\n"); 3701 3702 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3703 emulated_link_detect(dc_link); 3704 3705 if (aconnector->fake_enable) 3706 aconnector->fake_enable = false; 3707 3708 amdgpu_dm_update_connector_after_detect(aconnector); 3709 3710 3711 drm_modeset_lock_all(dev); 3712 dm_restore_drm_connector_state(dev, connector); 3713 drm_modeset_unlock_all(dev); 3714 3715 drm_kms_helper_connector_hotplug_event(connector); 3716 } else { 3717 bool ret = false; 3718 3719 mutex_lock(&adev->dm.dc_lock); 3720 dc_exit_ips_for_hw_access(dc); 3721 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); 3722 mutex_unlock(&adev->dm.dc_lock); 3723 3724 if (ret) { 3725 if (aconnector->fake_enable) 3726 aconnector->fake_enable = false; 3727 3728 amdgpu_dm_update_connector_after_detect(aconnector); 3729 3730 drm_modeset_lock_all(dev); 3731 dm_restore_drm_connector_state(dev, connector); 3732 drm_modeset_unlock_all(dev); 3733 3734 drm_kms_helper_connector_hotplug_event(connector); 3735 } 3736 } 3737 } 3738 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { 3739 if (adev->dm.hdcp_workqueue) 3740 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); 3741 } 3742 3743 if (dc_link->type != dc_connection_mst_branch) 3744 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); 3745 3746 mutex_unlock(&aconnector->hpd_lock); 3747 } 3748 3749 static int register_hpd_handlers(struct amdgpu_device *adev) 3750 { 3751 struct drm_device *dev = adev_to_drm(adev); 3752 struct drm_connector *connector; 3753 struct amdgpu_dm_connector *aconnector; 3754 const struct dc_link *dc_link; 3755 struct dc_interrupt_params int_params = {0}; 3756 3757 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3758 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3759 3760 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 3761 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, 3762 dmub_hpd_callback, true)) { 3763 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3764 return -EINVAL; 3765 } 3766 3767 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, 3768 dmub_hpd_callback, true)) { 3769 DRM_ERROR("amdgpu: fail to register dmub hpd callback"); 3770 return -EINVAL; 3771 } 3772 } 3773 3774 list_for_each_entry(connector, 3775 &dev->mode_config.connector_list, head) { 3776 3777 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3778 continue; 3779 3780 aconnector = to_amdgpu_dm_connector(connector); 3781 dc_link = aconnector->dc_link; 3782 3783 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { 3784 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3785 int_params.irq_source = dc_link->irq_source_hpd; 3786 3787 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3788 int_params.irq_source < DC_IRQ_SOURCE_HPD1 || 3789 int_params.irq_source > DC_IRQ_SOURCE_HPD6) { 3790 DRM_ERROR("Failed to register hpd irq!\n"); 3791 return -EINVAL; 3792 } 3793 3794 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3795 handle_hpd_irq, (void *) aconnector)) 3796 return -ENOMEM; 3797 } 3798 3799 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { 3800 3801 /* Also register for DP short pulse (hpd_rx). */ 3802 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 3803 int_params.irq_source = dc_link->irq_source_hpd_rx; 3804 3805 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3806 int_params.irq_source < DC_IRQ_SOURCE_HPD1RX || 3807 int_params.irq_source > DC_IRQ_SOURCE_HPD6RX) { 3808 DRM_ERROR("Failed to register hpd rx irq!\n"); 3809 return -EINVAL; 3810 } 3811 3812 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3813 handle_hpd_rx_irq, (void *) aconnector)) 3814 return -ENOMEM; 3815 } 3816 } 3817 return 0; 3818 } 3819 3820 #if defined(CONFIG_DRM_AMD_DC_SI) 3821 /* Register IRQ sources and initialize IRQ callbacks */ 3822 static int dce60_register_irq_handlers(struct amdgpu_device *adev) 3823 { 3824 struct dc *dc = adev->dm.dc; 3825 struct common_irq_params *c_irq_params; 3826 struct dc_interrupt_params int_params = {0}; 3827 int r; 3828 int i; 3829 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3830 3831 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3832 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3833 3834 /* 3835 * Actions of amdgpu_irq_add_id(): 3836 * 1. Register a set() function with base driver. 3837 * Base driver will call set() function to enable/disable an 3838 * interrupt in DC hardware. 3839 * 2. Register amdgpu_dm_irq_handler(). 3840 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3841 * coming from DC hardware. 3842 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3843 * for acknowledging and handling. 3844 */ 3845 3846 /* Use VBLANK interrupt */ 3847 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3848 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); 3849 if (r) { 3850 DRM_ERROR("Failed to add crtc irq id!\n"); 3851 return r; 3852 } 3853 3854 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3855 int_params.irq_source = 3856 dc_interrupt_to_irq_source(dc, i + 1, 0); 3857 3858 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3859 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3860 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3861 DRM_ERROR("Failed to register vblank irq!\n"); 3862 return -EINVAL; 3863 } 3864 3865 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3866 3867 c_irq_params->adev = adev; 3868 c_irq_params->irq_src = int_params.irq_source; 3869 3870 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3871 dm_crtc_high_irq, c_irq_params)) 3872 return -ENOMEM; 3873 } 3874 3875 /* Use GRPH_PFLIP interrupt */ 3876 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 3877 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 3878 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 3879 if (r) { 3880 DRM_ERROR("Failed to add page flip irq id!\n"); 3881 return r; 3882 } 3883 3884 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3885 int_params.irq_source = 3886 dc_interrupt_to_irq_source(dc, i, 0); 3887 3888 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3889 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 3890 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 3891 DRM_ERROR("Failed to register pflip irq!\n"); 3892 return -EINVAL; 3893 } 3894 3895 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 3896 3897 c_irq_params->adev = adev; 3898 c_irq_params->irq_src = int_params.irq_source; 3899 3900 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3901 dm_pflip_high_irq, c_irq_params)) 3902 return -ENOMEM; 3903 } 3904 3905 /* HPD */ 3906 r = amdgpu_irq_add_id(adev, client_id, 3907 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 3908 if (r) { 3909 DRM_ERROR("Failed to add hpd irq id!\n"); 3910 return r; 3911 } 3912 3913 r = register_hpd_handlers(adev); 3914 3915 return r; 3916 } 3917 #endif 3918 3919 /* Register IRQ sources and initialize IRQ callbacks */ 3920 static int dce110_register_irq_handlers(struct amdgpu_device *adev) 3921 { 3922 struct dc *dc = adev->dm.dc; 3923 struct common_irq_params *c_irq_params; 3924 struct dc_interrupt_params int_params = {0}; 3925 int r; 3926 int i; 3927 unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 3928 3929 if (adev->family >= AMDGPU_FAMILY_AI) 3930 client_id = SOC15_IH_CLIENTID_DCE; 3931 3932 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 3933 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 3934 3935 /* 3936 * Actions of amdgpu_irq_add_id(): 3937 * 1. Register a set() function with base driver. 3938 * Base driver will call set() function to enable/disable an 3939 * interrupt in DC hardware. 3940 * 2. Register amdgpu_dm_irq_handler(). 3941 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 3942 * coming from DC hardware. 3943 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 3944 * for acknowledging and handling. 3945 */ 3946 3947 /* Use VBLANK interrupt */ 3948 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { 3949 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); 3950 if (r) { 3951 DRM_ERROR("Failed to add crtc irq id!\n"); 3952 return r; 3953 } 3954 3955 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3956 int_params.irq_source = 3957 dc_interrupt_to_irq_source(dc, i, 0); 3958 3959 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3960 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 3961 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 3962 DRM_ERROR("Failed to register vblank irq!\n"); 3963 return -EINVAL; 3964 } 3965 3966 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 3967 3968 c_irq_params->adev = adev; 3969 c_irq_params->irq_src = int_params.irq_source; 3970 3971 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 3972 dm_crtc_high_irq, c_irq_params)) 3973 return -ENOMEM; 3974 } 3975 3976 /* Use VUPDATE interrupt */ 3977 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { 3978 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); 3979 if (r) { 3980 DRM_ERROR("Failed to add vupdate irq id!\n"); 3981 return r; 3982 } 3983 3984 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 3985 int_params.irq_source = 3986 dc_interrupt_to_irq_source(dc, i, 0); 3987 3988 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 3989 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 3990 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 3991 DRM_ERROR("Failed to register vupdate irq!\n"); 3992 return -EINVAL; 3993 } 3994 3995 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 3996 3997 c_irq_params->adev = adev; 3998 c_irq_params->irq_src = int_params.irq_source; 3999 4000 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4001 dm_vupdate_high_irq, c_irq_params)) 4002 return -ENOMEM; 4003 } 4004 4005 /* Use GRPH_PFLIP interrupt */ 4006 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; 4007 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { 4008 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); 4009 if (r) { 4010 DRM_ERROR("Failed to add page flip irq id!\n"); 4011 return r; 4012 } 4013 4014 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4015 int_params.irq_source = 4016 dc_interrupt_to_irq_source(dc, i, 0); 4017 4018 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4019 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4020 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4021 DRM_ERROR("Failed to register pflip irq!\n"); 4022 return -EINVAL; 4023 } 4024 4025 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4026 4027 c_irq_params->adev = adev; 4028 c_irq_params->irq_src = int_params.irq_source; 4029 4030 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4031 dm_pflip_high_irq, c_irq_params)) 4032 return -ENOMEM; 4033 } 4034 4035 /* HPD */ 4036 r = amdgpu_irq_add_id(adev, client_id, 4037 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 4038 if (r) { 4039 DRM_ERROR("Failed to add hpd irq id!\n"); 4040 return r; 4041 } 4042 4043 r = register_hpd_handlers(adev); 4044 4045 return r; 4046 } 4047 4048 /* Register IRQ sources and initialize IRQ callbacks */ 4049 static int dcn10_register_irq_handlers(struct amdgpu_device *adev) 4050 { 4051 struct dc *dc = adev->dm.dc; 4052 struct common_irq_params *c_irq_params; 4053 struct dc_interrupt_params int_params = {0}; 4054 int r; 4055 int i; 4056 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 4057 static const unsigned int vrtl_int_srcid[] = { 4058 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL, 4059 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL, 4060 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL, 4061 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL, 4062 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL, 4063 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 4064 }; 4065 #endif 4066 4067 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4068 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4069 4070 /* 4071 * Actions of amdgpu_irq_add_id(): 4072 * 1. Register a set() function with base driver. 4073 * Base driver will call set() function to enable/disable an 4074 * interrupt in DC hardware. 4075 * 2. Register amdgpu_dm_irq_handler(). 4076 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts 4077 * coming from DC hardware. 4078 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC 4079 * for acknowledging and handling. 4080 */ 4081 4082 /* Use VSTARTUP interrupt */ 4083 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; 4084 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; 4085 i++) { 4086 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); 4087 4088 if (r) { 4089 DRM_ERROR("Failed to add crtc irq id!\n"); 4090 return r; 4091 } 4092 4093 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4094 int_params.irq_source = 4095 dc_interrupt_to_irq_source(dc, i, 0); 4096 4097 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4098 int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || 4099 int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { 4100 DRM_ERROR("Failed to register vblank irq!\n"); 4101 return -EINVAL; 4102 } 4103 4104 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; 4105 4106 c_irq_params->adev = adev; 4107 c_irq_params->irq_src = int_params.irq_source; 4108 4109 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4110 dm_crtc_high_irq, c_irq_params)) 4111 return -ENOMEM; 4112 } 4113 4114 /* Use otg vertical line interrupt */ 4115 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 4116 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { 4117 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, 4118 vrtl_int_srcid[i], &adev->vline0_irq); 4119 4120 if (r) { 4121 DRM_ERROR("Failed to add vline0 irq id!\n"); 4122 return r; 4123 } 4124 4125 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4126 int_params.irq_source = 4127 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); 4128 4129 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4130 int_params.irq_source < DC_IRQ_SOURCE_DC1_VLINE0 || 4131 int_params.irq_source > DC_IRQ_SOURCE_DC6_VLINE0) { 4132 DRM_ERROR("Failed to register vline0 irq!\n"); 4133 return -EINVAL; 4134 } 4135 4136 c_irq_params = &adev->dm.vline0_params[int_params.irq_source 4137 - DC_IRQ_SOURCE_DC1_VLINE0]; 4138 4139 c_irq_params->adev = adev; 4140 c_irq_params->irq_src = int_params.irq_source; 4141 4142 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4143 dm_dcn_vertical_interrupt0_high_irq, 4144 c_irq_params)) 4145 return -ENOMEM; 4146 } 4147 #endif 4148 4149 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to 4150 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx 4151 * to trigger at end of each vblank, regardless of state of the lock, 4152 * matching DCE behaviour. 4153 */ 4154 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT; 4155 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1; 4156 i++) { 4157 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); 4158 4159 if (r) { 4160 DRM_ERROR("Failed to add vupdate irq id!\n"); 4161 return r; 4162 } 4163 4164 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4165 int_params.irq_source = 4166 dc_interrupt_to_irq_source(dc, i, 0); 4167 4168 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4169 int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || 4170 int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { 4171 DRM_ERROR("Failed to register vupdate irq!\n"); 4172 return -EINVAL; 4173 } 4174 4175 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; 4176 4177 c_irq_params->adev = adev; 4178 c_irq_params->irq_src = int_params.irq_source; 4179 4180 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4181 dm_vupdate_high_irq, c_irq_params)) 4182 return -ENOMEM; 4183 } 4184 4185 /* Use GRPH_PFLIP interrupt */ 4186 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; 4187 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1; 4188 i++) { 4189 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); 4190 if (r) { 4191 DRM_ERROR("Failed to add page flip irq id!\n"); 4192 return r; 4193 } 4194 4195 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; 4196 int_params.irq_source = 4197 dc_interrupt_to_irq_source(dc, i, 0); 4198 4199 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || 4200 int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || 4201 int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { 4202 DRM_ERROR("Failed to register pflip irq!\n"); 4203 return -EINVAL; 4204 } 4205 4206 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; 4207 4208 c_irq_params->adev = adev; 4209 c_irq_params->irq_src = int_params.irq_source; 4210 4211 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4212 dm_pflip_high_irq, c_irq_params)) 4213 return -ENOMEM; 4214 } 4215 4216 /* HPD */ 4217 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, 4218 &adev->hpd_irq); 4219 if (r) { 4220 DRM_ERROR("Failed to add hpd irq id!\n"); 4221 return r; 4222 } 4223 4224 r = register_hpd_handlers(adev); 4225 4226 return r; 4227 } 4228 /* Register Outbox IRQ sources and initialize IRQ callbacks */ 4229 static int register_outbox_irq_handlers(struct amdgpu_device *adev) 4230 { 4231 struct dc *dc = adev->dm.dc; 4232 struct common_irq_params *c_irq_params; 4233 struct dc_interrupt_params int_params = {0}; 4234 int r, i; 4235 4236 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; 4237 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; 4238 4239 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT, 4240 &adev->dmub_outbox_irq); 4241 if (r) { 4242 DRM_ERROR("Failed to add outbox irq id!\n"); 4243 return r; 4244 } 4245 4246 if (dc->ctx->dmub_srv) { 4247 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT; 4248 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; 4249 int_params.irq_source = 4250 dc_interrupt_to_irq_source(dc, i, 0); 4251 4252 c_irq_params = &adev->dm.dmub_outbox_params[0]; 4253 4254 c_irq_params->adev = adev; 4255 c_irq_params->irq_src = int_params.irq_source; 4256 4257 if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, 4258 dm_dmub_outbox1_low_irq, c_irq_params)) 4259 return -ENOMEM; 4260 } 4261 4262 return 0; 4263 } 4264 4265 /* 4266 * Acquires the lock for the atomic state object and returns 4267 * the new atomic state. 4268 * 4269 * This should only be called during atomic check. 4270 */ 4271 int dm_atomic_get_state(struct drm_atomic_state *state, 4272 struct dm_atomic_state **dm_state) 4273 { 4274 struct drm_device *dev = state->dev; 4275 struct amdgpu_device *adev = drm_to_adev(dev); 4276 struct amdgpu_display_manager *dm = &adev->dm; 4277 struct drm_private_state *priv_state; 4278 4279 if (*dm_state) 4280 return 0; 4281 4282 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 4283 if (IS_ERR(priv_state)) 4284 return PTR_ERR(priv_state); 4285 4286 *dm_state = to_dm_atomic_state(priv_state); 4287 4288 return 0; 4289 } 4290 4291 static struct dm_atomic_state * 4292 dm_atomic_get_new_state(struct drm_atomic_state *state) 4293 { 4294 struct drm_device *dev = state->dev; 4295 struct amdgpu_device *adev = drm_to_adev(dev); 4296 struct amdgpu_display_manager *dm = &adev->dm; 4297 struct drm_private_obj *obj; 4298 struct drm_private_state *new_obj_state; 4299 int i; 4300 4301 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 4302 if (obj->funcs == dm->atomic_obj.funcs) 4303 return to_dm_atomic_state(new_obj_state); 4304 } 4305 4306 return NULL; 4307 } 4308 4309 static struct drm_private_state * 4310 dm_atomic_duplicate_state(struct drm_private_obj *obj) 4311 { 4312 struct dm_atomic_state *old_state, *new_state; 4313 4314 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 4315 if (!new_state) 4316 return NULL; 4317 4318 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 4319 4320 old_state = to_dm_atomic_state(obj->state); 4321 4322 if (old_state && old_state->context) 4323 new_state->context = dc_state_create_copy(old_state->context); 4324 4325 if (!new_state->context) { 4326 kfree(new_state); 4327 return NULL; 4328 } 4329 4330 return &new_state->base; 4331 } 4332 4333 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 4334 struct drm_private_state *state) 4335 { 4336 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 4337 4338 if (dm_state && dm_state->context) 4339 dc_state_release(dm_state->context); 4340 4341 kfree(dm_state); 4342 } 4343 4344 static struct drm_private_state_funcs dm_atomic_state_funcs = { 4345 .atomic_duplicate_state = dm_atomic_duplicate_state, 4346 .atomic_destroy_state = dm_atomic_destroy_state, 4347 }; 4348 4349 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 4350 { 4351 struct dm_atomic_state *state; 4352 int r; 4353 4354 adev->mode_info.mode_config_initialized = true; 4355 4356 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 4357 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 4358 4359 adev_to_drm(adev)->mode_config.max_width = 16384; 4360 adev_to_drm(adev)->mode_config.max_height = 16384; 4361 4362 adev_to_drm(adev)->mode_config.preferred_depth = 24; 4363 if (adev->asic_type == CHIP_HAWAII) 4364 /* disable prefer shadow for now due to hibernation issues */ 4365 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 4366 else 4367 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 4368 /* indicates support for immediate flip */ 4369 adev_to_drm(adev)->mode_config.async_page_flip = true; 4370 4371 state = kzalloc(sizeof(*state), GFP_KERNEL); 4372 if (!state) 4373 return -ENOMEM; 4374 4375 state->context = dc_state_create_current_copy(adev->dm.dc); 4376 if (!state->context) { 4377 kfree(state); 4378 return -ENOMEM; 4379 } 4380 4381 drm_atomic_private_obj_init(adev_to_drm(adev), 4382 &adev->dm.atomic_obj, 4383 &state->base, 4384 &dm_atomic_state_funcs); 4385 4386 r = amdgpu_display_modeset_create_props(adev); 4387 if (r) { 4388 dc_state_release(state->context); 4389 kfree(state); 4390 return r; 4391 } 4392 4393 #ifdef AMD_PRIVATE_COLOR 4394 if (amdgpu_dm_create_color_properties(adev)) { 4395 dc_state_release(state->context); 4396 kfree(state); 4397 return -ENOMEM; 4398 } 4399 #endif 4400 4401 r = amdgpu_dm_audio_init(adev); 4402 if (r) { 4403 dc_state_release(state->context); 4404 kfree(state); 4405 return r; 4406 } 4407 4408 return 0; 4409 } 4410 4411 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 4412 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 4413 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 4414 4415 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 4416 int bl_idx) 4417 { 4418 #if defined(CONFIG_ACPI) 4419 struct amdgpu_dm_backlight_caps caps; 4420 4421 memset(&caps, 0, sizeof(caps)); 4422 4423 if (dm->backlight_caps[bl_idx].caps_valid) 4424 return; 4425 4426 amdgpu_acpi_get_backlight_caps(&caps); 4427 if (caps.caps_valid) { 4428 dm->backlight_caps[bl_idx].caps_valid = true; 4429 if (caps.aux_support) 4430 return; 4431 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; 4432 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; 4433 } else { 4434 dm->backlight_caps[bl_idx].min_input_signal = 4435 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4436 dm->backlight_caps[bl_idx].max_input_signal = 4437 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4438 } 4439 #else 4440 if (dm->backlight_caps[bl_idx].aux_support) 4441 return; 4442 4443 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; 4444 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; 4445 #endif 4446 } 4447 4448 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 4449 unsigned int *min, unsigned int *max) 4450 { 4451 if (!caps) 4452 return 0; 4453 4454 if (caps->aux_support) { 4455 // Firmware limits are in nits, DC API wants millinits. 4456 *max = 1000 * caps->aux_max_input_signal; 4457 *min = 1000 * caps->aux_min_input_signal; 4458 } else { 4459 // Firmware limits are 8-bit, PWM control is 16-bit. 4460 *max = 0x101 * caps->max_input_signal; 4461 *min = 0x101 * caps->min_input_signal; 4462 } 4463 return 1; 4464 } 4465 4466 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, 4467 uint32_t brightness) 4468 { 4469 unsigned int min, max; 4470 4471 if (!get_brightness_range(caps, &min, &max)) 4472 return brightness; 4473 4474 // Rescale 0..255 to min..max 4475 return min + DIV_ROUND_CLOSEST((max - min) * brightness, 4476 AMDGPU_MAX_BL_LEVEL); 4477 } 4478 4479 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, 4480 uint32_t brightness) 4481 { 4482 unsigned int min, max; 4483 4484 if (!get_brightness_range(caps, &min, &max)) 4485 return brightness; 4486 4487 if (brightness < min) 4488 return 0; 4489 // Rescale min..max to 0..255 4490 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), 4491 max - min); 4492 } 4493 4494 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, 4495 int bl_idx, 4496 u32 user_brightness) 4497 { 4498 struct amdgpu_dm_backlight_caps caps; 4499 struct dc_link *link; 4500 u32 brightness; 4501 bool rc; 4502 4503 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4504 caps = dm->backlight_caps[bl_idx]; 4505 4506 dm->brightness[bl_idx] = user_brightness; 4507 /* update scratch register */ 4508 if (bl_idx == 0) 4509 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); 4510 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); 4511 link = (struct dc_link *)dm->backlight_link[bl_idx]; 4512 4513 /* Change brightness based on AUX property */ 4514 if (caps.aux_support) { 4515 rc = dc_link_set_backlight_level_nits(link, true, brightness, 4516 AUX_BL_DEFAULT_TRANSITION_TIME_MS); 4517 if (!rc) 4518 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx); 4519 } else { 4520 rc = dc_link_set_backlight_level(link, brightness, 0); 4521 if (!rc) 4522 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); 4523 } 4524 4525 if (rc) 4526 dm->actual_brightness[bl_idx] = user_brightness; 4527 } 4528 4529 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) 4530 { 4531 struct amdgpu_display_manager *dm = bl_get_data(bd); 4532 int i; 4533 4534 for (i = 0; i < dm->num_of_edps; i++) { 4535 if (bd == dm->backlight_dev[i]) 4536 break; 4537 } 4538 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4539 i = 0; 4540 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); 4541 4542 return 0; 4543 } 4544 4545 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, 4546 int bl_idx) 4547 { 4548 int ret; 4549 struct amdgpu_dm_backlight_caps caps; 4550 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; 4551 4552 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4553 caps = dm->backlight_caps[bl_idx]; 4554 4555 if (caps.aux_support) { 4556 u32 avg, peak; 4557 bool rc; 4558 4559 rc = dc_link_get_backlight_level_nits(link, &avg, &peak); 4560 if (!rc) 4561 return dm->brightness[bl_idx]; 4562 return convert_brightness_to_user(&caps, avg); 4563 } 4564 4565 ret = dc_link_get_backlight_level(link); 4566 4567 if (ret == DC_ERROR_UNEXPECTED) 4568 return dm->brightness[bl_idx]; 4569 4570 return convert_brightness_to_user(&caps, ret); 4571 } 4572 4573 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) 4574 { 4575 struct amdgpu_display_manager *dm = bl_get_data(bd); 4576 int i; 4577 4578 for (i = 0; i < dm->num_of_edps; i++) { 4579 if (bd == dm->backlight_dev[i]) 4580 break; 4581 } 4582 if (i >= AMDGPU_DM_MAX_NUM_EDP) 4583 i = 0; 4584 return amdgpu_dm_backlight_get_level(dm, i); 4585 } 4586 4587 static const struct backlight_ops amdgpu_dm_backlight_ops = { 4588 .options = BL_CORE_SUSPENDRESUME, 4589 .get_brightness = amdgpu_dm_backlight_get_brightness, 4590 .update_status = amdgpu_dm_backlight_update_status, 4591 }; 4592 4593 static void 4594 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) 4595 { 4596 struct drm_device *drm = aconnector->base.dev; 4597 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 4598 struct backlight_properties props = { 0 }; 4599 struct amdgpu_dm_backlight_caps caps = { 0 }; 4600 char bl_name[16]; 4601 4602 if (aconnector->bl_idx == -1) 4603 return; 4604 4605 if (!acpi_video_backlight_use_native()) { 4606 drm_info(drm, "Skipping amdgpu DM backlight registration\n"); 4607 /* Try registering an ACPI video backlight device instead. */ 4608 acpi_video_register_backlight(); 4609 return; 4610 } 4611 4612 amdgpu_acpi_get_backlight_caps(&caps); 4613 if (caps.caps_valid) { 4614 if (power_supply_is_system_supplied() > 0) 4615 props.brightness = caps.ac_level; 4616 else 4617 props.brightness = caps.dc_level; 4618 } else 4619 props.brightness = AMDGPU_MAX_BL_LEVEL; 4620 4621 props.max_brightness = AMDGPU_MAX_BL_LEVEL; 4622 props.type = BACKLIGHT_RAW; 4623 4624 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", 4625 drm->primary->index + aconnector->bl_idx); 4626 4627 dm->backlight_dev[aconnector->bl_idx] = 4628 backlight_device_register(bl_name, aconnector->base.kdev, dm, 4629 &amdgpu_dm_backlight_ops, &props); 4630 4631 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) { 4632 DRM_ERROR("DM: Backlight registration failed!\n"); 4633 dm->backlight_dev[aconnector->bl_idx] = NULL; 4634 } else 4635 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); 4636 } 4637 4638 static int initialize_plane(struct amdgpu_display_manager *dm, 4639 struct amdgpu_mode_info *mode_info, int plane_id, 4640 enum drm_plane_type plane_type, 4641 const struct dc_plane_cap *plane_cap) 4642 { 4643 struct drm_plane *plane; 4644 unsigned long possible_crtcs; 4645 int ret = 0; 4646 4647 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL); 4648 if (!plane) { 4649 DRM_ERROR("KMS: Failed to allocate plane\n"); 4650 return -ENOMEM; 4651 } 4652 plane->type = plane_type; 4653 4654 /* 4655 * HACK: IGT tests expect that the primary plane for a CRTC 4656 * can only have one possible CRTC. Only expose support for 4657 * any CRTC if they're not going to be used as a primary plane 4658 * for a CRTC - like overlay or underlay planes. 4659 */ 4660 possible_crtcs = 1 << plane_id; 4661 if (plane_id >= dm->dc->caps.max_streams) 4662 possible_crtcs = 0xff; 4663 4664 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 4665 4666 if (ret) { 4667 DRM_ERROR("KMS: Failed to initialize plane\n"); 4668 kfree(plane); 4669 return ret; 4670 } 4671 4672 if (mode_info) 4673 mode_info->planes[plane_id] = plane; 4674 4675 return ret; 4676 } 4677 4678 4679 static void setup_backlight_device(struct amdgpu_display_manager *dm, 4680 struct amdgpu_dm_connector *aconnector) 4681 { 4682 struct dc_link *link = aconnector->dc_link; 4683 int bl_idx = dm->num_of_edps; 4684 4685 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) || 4686 link->type == dc_connection_none) 4687 return; 4688 4689 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) { 4690 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n"); 4691 return; 4692 } 4693 4694 aconnector->bl_idx = bl_idx; 4695 4696 amdgpu_dm_update_backlight_caps(dm, bl_idx); 4697 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; 4698 dm->backlight_link[bl_idx] = link; 4699 dm->num_of_edps++; 4700 4701 update_connector_ext_caps(aconnector); 4702 } 4703 4704 static void amdgpu_set_panel_orientation(struct drm_connector *connector); 4705 4706 /* 4707 * In this architecture, the association 4708 * connector -> encoder -> crtc 4709 * id not really requried. The crtc and connector will hold the 4710 * display_index as an abstraction to use with DAL component 4711 * 4712 * Returns 0 on success 4713 */ 4714 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 4715 { 4716 struct amdgpu_display_manager *dm = &adev->dm; 4717 s32 i; 4718 struct amdgpu_dm_connector *aconnector = NULL; 4719 struct amdgpu_encoder *aencoder = NULL; 4720 struct amdgpu_mode_info *mode_info = &adev->mode_info; 4721 u32 link_cnt; 4722 s32 primary_planes; 4723 enum dc_connection_type new_connection_type = dc_connection_none; 4724 const struct dc_plane_cap *plane; 4725 bool psr_feature_enabled = false; 4726 bool replay_feature_enabled = false; 4727 int max_overlay = dm->dc->caps.max_slave_planes; 4728 4729 dm->display_indexes_num = dm->dc->caps.max_streams; 4730 /* Update the actual used number of crtc */ 4731 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 4732 4733 amdgpu_dm_set_irq_funcs(adev); 4734 4735 link_cnt = dm->dc->caps.max_links; 4736 if (amdgpu_dm_mode_config_init(dm->adev)) { 4737 DRM_ERROR("DM: Failed to initialize mode config\n"); 4738 return -EINVAL; 4739 } 4740 4741 /* There is one primary plane per CRTC */ 4742 primary_planes = dm->dc->caps.max_streams; 4743 if (primary_planes > AMDGPU_MAX_PLANES) { 4744 DRM_ERROR("DM: Plane nums out of 6 planes\n"); 4745 return -EINVAL; 4746 } 4747 4748 /* 4749 * Initialize primary planes, implicit planes for legacy IOCTLS. 4750 * Order is reversed to match iteration order in atomic check. 4751 */ 4752 for (i = (primary_planes - 1); i >= 0; i--) { 4753 plane = &dm->dc->caps.planes[i]; 4754 4755 if (initialize_plane(dm, mode_info, i, 4756 DRM_PLANE_TYPE_PRIMARY, plane)) { 4757 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 4758 goto fail; 4759 } 4760 } 4761 4762 /* 4763 * Initialize overlay planes, index starting after primary planes. 4764 * These planes have a higher DRM index than the primary planes since 4765 * they should be considered as having a higher z-order. 4766 * Order is reversed to match iteration order in atomic check. 4767 * 4768 * Only support DCN for now, and only expose one so we don't encourage 4769 * userspace to use up all the pipes. 4770 */ 4771 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 4772 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 4773 4774 /* Do not create overlay if MPO disabled */ 4775 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 4776 break; 4777 4778 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 4779 continue; 4780 4781 if (!plane->pixel_format_support.argb8888) 4782 continue; 4783 4784 if (max_overlay-- == 0) 4785 break; 4786 4787 if (initialize_plane(dm, NULL, primary_planes + i, 4788 DRM_PLANE_TYPE_OVERLAY, plane)) { 4789 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 4790 goto fail; 4791 } 4792 } 4793 4794 for (i = 0; i < dm->dc->caps.max_streams; i++) 4795 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 4796 DRM_ERROR("KMS: Failed to initialize crtc\n"); 4797 goto fail; 4798 } 4799 4800 /* Use Outbox interrupt */ 4801 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4802 case IP_VERSION(3, 0, 0): 4803 case IP_VERSION(3, 1, 2): 4804 case IP_VERSION(3, 1, 3): 4805 case IP_VERSION(3, 1, 4): 4806 case IP_VERSION(3, 1, 5): 4807 case IP_VERSION(3, 1, 6): 4808 case IP_VERSION(3, 2, 0): 4809 case IP_VERSION(3, 2, 1): 4810 case IP_VERSION(2, 1, 0): 4811 case IP_VERSION(3, 5, 0): 4812 case IP_VERSION(3, 5, 1): 4813 case IP_VERSION(4, 0, 1): 4814 if (register_outbox_irq_handlers(dm->adev)) { 4815 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4816 goto fail; 4817 } 4818 break; 4819 default: 4820 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", 4821 amdgpu_ip_version(adev, DCE_HWIP, 0)); 4822 } 4823 4824 /* Determine whether to enable PSR support by default. */ 4825 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 4826 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4827 case IP_VERSION(3, 1, 2): 4828 case IP_VERSION(3, 1, 3): 4829 case IP_VERSION(3, 1, 4): 4830 case IP_VERSION(3, 1, 5): 4831 case IP_VERSION(3, 1, 6): 4832 case IP_VERSION(3, 2, 0): 4833 case IP_VERSION(3, 2, 1): 4834 case IP_VERSION(3, 5, 0): 4835 case IP_VERSION(3, 5, 1): 4836 case IP_VERSION(4, 0, 1): 4837 psr_feature_enabled = true; 4838 break; 4839 default: 4840 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 4841 break; 4842 } 4843 } 4844 4845 /* Determine whether to enable Replay support by default. */ 4846 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 4847 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4848 /* 4849 * Disabled by default due to https://gitlab.freedesktop.org/drm/amd/-/issues/3344 4850 * case IP_VERSION(3, 1, 4): 4851 * case IP_VERSION(3, 1, 5): 4852 * case IP_VERSION(3, 1, 6): 4853 * case IP_VERSION(3, 2, 0): 4854 * case IP_VERSION(3, 2, 1): 4855 * case IP_VERSION(3, 5, 0): 4856 * case IP_VERSION(3, 5, 1): 4857 * replay_feature_enabled = true; 4858 * break; 4859 */ 4860 default: 4861 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 4862 break; 4863 } 4864 } 4865 4866 if (link_cnt > MAX_LINKS) { 4867 DRM_ERROR( 4868 "KMS: Cannot support more than %d display indexes\n", 4869 MAX_LINKS); 4870 goto fail; 4871 } 4872 4873 /* loops over all connectors on the board */ 4874 for (i = 0; i < link_cnt; i++) { 4875 struct dc_link *link = NULL; 4876 4877 link = dc_get_link_at_index(dm->dc, i); 4878 4879 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 4880 struct amdgpu_dm_wb_connector *wbcon = kzalloc(sizeof(*wbcon), GFP_KERNEL); 4881 4882 if (!wbcon) { 4883 DRM_ERROR("KMS: Failed to allocate writeback connector\n"); 4884 continue; 4885 } 4886 4887 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 4888 DRM_ERROR("KMS: Failed to initialize writeback connector\n"); 4889 kfree(wbcon); 4890 continue; 4891 } 4892 4893 link->psr_settings.psr_feature_enabled = false; 4894 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 4895 4896 continue; 4897 } 4898 4899 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); 4900 if (!aconnector) 4901 goto fail; 4902 4903 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); 4904 if (!aencoder) 4905 goto fail; 4906 4907 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 4908 DRM_ERROR("KMS: Failed to initialize encoder\n"); 4909 goto fail; 4910 } 4911 4912 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 4913 DRM_ERROR("KMS: Failed to initialize connector\n"); 4914 goto fail; 4915 } 4916 4917 if (dm->hpd_rx_offload_wq) 4918 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 4919 aconnector; 4920 4921 if (!dc_link_detect_connection_type(link, &new_connection_type)) 4922 DRM_ERROR("KMS: Failed to detect connector\n"); 4923 4924 if (aconnector->base.force && new_connection_type == dc_connection_none) { 4925 emulated_link_detect(link); 4926 amdgpu_dm_update_connector_after_detect(aconnector); 4927 } else { 4928 bool ret = false; 4929 4930 mutex_lock(&dm->dc_lock); 4931 dc_exit_ips_for_hw_access(dm->dc); 4932 ret = dc_link_detect(link, DETECT_REASON_BOOT); 4933 mutex_unlock(&dm->dc_lock); 4934 4935 if (ret) { 4936 amdgpu_dm_update_connector_after_detect(aconnector); 4937 setup_backlight_device(dm, aconnector); 4938 4939 /* Disable PSR if Replay can be enabled */ 4940 if (replay_feature_enabled) 4941 if (amdgpu_dm_set_replay_caps(link, aconnector)) 4942 psr_feature_enabled = false; 4943 4944 if (psr_feature_enabled) 4945 amdgpu_dm_set_psr_caps(link); 4946 4947 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when 4948 * PSR is also supported. 4949 */ 4950 if (link->psr_settings.psr_feature_enabled) 4951 adev_to_drm(adev)->vblank_disable_immediate = false; 4952 } 4953 } 4954 amdgpu_set_panel_orientation(&aconnector->base); 4955 } 4956 4957 /* Software is initialized. Now we can register interrupt handlers. */ 4958 switch (adev->asic_type) { 4959 #if defined(CONFIG_DRM_AMD_DC_SI) 4960 case CHIP_TAHITI: 4961 case CHIP_PITCAIRN: 4962 case CHIP_VERDE: 4963 case CHIP_OLAND: 4964 if (dce60_register_irq_handlers(dm->adev)) { 4965 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4966 goto fail; 4967 } 4968 break; 4969 #endif 4970 case CHIP_BONAIRE: 4971 case CHIP_HAWAII: 4972 case CHIP_KAVERI: 4973 case CHIP_KABINI: 4974 case CHIP_MULLINS: 4975 case CHIP_TONGA: 4976 case CHIP_FIJI: 4977 case CHIP_CARRIZO: 4978 case CHIP_STONEY: 4979 case CHIP_POLARIS11: 4980 case CHIP_POLARIS10: 4981 case CHIP_POLARIS12: 4982 case CHIP_VEGAM: 4983 case CHIP_VEGA10: 4984 case CHIP_VEGA12: 4985 case CHIP_VEGA20: 4986 if (dce110_register_irq_handlers(dm->adev)) { 4987 DRM_ERROR("DM: Failed to initialize IRQ\n"); 4988 goto fail; 4989 } 4990 break; 4991 default: 4992 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 4993 case IP_VERSION(1, 0, 0): 4994 case IP_VERSION(1, 0, 1): 4995 case IP_VERSION(2, 0, 2): 4996 case IP_VERSION(2, 0, 3): 4997 case IP_VERSION(2, 0, 0): 4998 case IP_VERSION(2, 1, 0): 4999 case IP_VERSION(3, 0, 0): 5000 case IP_VERSION(3, 0, 2): 5001 case IP_VERSION(3, 0, 3): 5002 case IP_VERSION(3, 0, 1): 5003 case IP_VERSION(3, 1, 2): 5004 case IP_VERSION(3, 1, 3): 5005 case IP_VERSION(3, 1, 4): 5006 case IP_VERSION(3, 1, 5): 5007 case IP_VERSION(3, 1, 6): 5008 case IP_VERSION(3, 2, 0): 5009 case IP_VERSION(3, 2, 1): 5010 case IP_VERSION(3, 5, 0): 5011 case IP_VERSION(3, 5, 1): 5012 case IP_VERSION(4, 0, 1): 5013 if (dcn10_register_irq_handlers(dm->adev)) { 5014 DRM_ERROR("DM: Failed to initialize IRQ\n"); 5015 goto fail; 5016 } 5017 break; 5018 default: 5019 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n", 5020 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5021 goto fail; 5022 } 5023 break; 5024 } 5025 5026 return 0; 5027 fail: 5028 kfree(aencoder); 5029 kfree(aconnector); 5030 5031 return -EINVAL; 5032 } 5033 5034 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 5035 { 5036 drm_atomic_private_obj_fini(&dm->atomic_obj); 5037 } 5038 5039 /****************************************************************************** 5040 * amdgpu_display_funcs functions 5041 *****************************************************************************/ 5042 5043 /* 5044 * dm_bandwidth_update - program display watermarks 5045 * 5046 * @adev: amdgpu_device pointer 5047 * 5048 * Calculate and program the display watermarks and line buffer allocation. 5049 */ 5050 static void dm_bandwidth_update(struct amdgpu_device *adev) 5051 { 5052 /* TODO: implement later */ 5053 } 5054 5055 static const struct amdgpu_display_funcs dm_display_funcs = { 5056 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 5057 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 5058 .backlight_set_level = NULL, /* never called for DC */ 5059 .backlight_get_level = NULL, /* never called for DC */ 5060 .hpd_sense = NULL,/* called unconditionally */ 5061 .hpd_set_polarity = NULL, /* called unconditionally */ 5062 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 5063 .page_flip_get_scanoutpos = 5064 dm_crtc_get_scanoutpos,/* called unconditionally */ 5065 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 5066 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 5067 }; 5068 5069 #if defined(CONFIG_DEBUG_KERNEL_DC) 5070 5071 static ssize_t s3_debug_store(struct device *device, 5072 struct device_attribute *attr, 5073 const char *buf, 5074 size_t count) 5075 { 5076 int ret; 5077 int s3_state; 5078 struct drm_device *drm_dev = dev_get_drvdata(device); 5079 struct amdgpu_device *adev = drm_to_adev(drm_dev); 5080 5081 ret = kstrtoint(buf, 0, &s3_state); 5082 5083 if (ret == 0) { 5084 if (s3_state) { 5085 dm_resume(adev); 5086 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 5087 } else 5088 dm_suspend(adev); 5089 } 5090 5091 return ret == 0 ? count : 0; 5092 } 5093 5094 DEVICE_ATTR_WO(s3_debug); 5095 5096 #endif 5097 5098 static int dm_init_microcode(struct amdgpu_device *adev) 5099 { 5100 char *fw_name_dmub; 5101 int r; 5102 5103 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5104 case IP_VERSION(2, 1, 0): 5105 fw_name_dmub = FIRMWARE_RENOIR_DMUB; 5106 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) 5107 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB; 5108 break; 5109 case IP_VERSION(3, 0, 0): 5110 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0)) 5111 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB; 5112 else 5113 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB; 5114 break; 5115 case IP_VERSION(3, 0, 1): 5116 fw_name_dmub = FIRMWARE_VANGOGH_DMUB; 5117 break; 5118 case IP_VERSION(3, 0, 2): 5119 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB; 5120 break; 5121 case IP_VERSION(3, 0, 3): 5122 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB; 5123 break; 5124 case IP_VERSION(3, 1, 2): 5125 case IP_VERSION(3, 1, 3): 5126 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB; 5127 break; 5128 case IP_VERSION(3, 1, 4): 5129 fw_name_dmub = FIRMWARE_DCN_314_DMUB; 5130 break; 5131 case IP_VERSION(3, 1, 5): 5132 fw_name_dmub = FIRMWARE_DCN_315_DMUB; 5133 break; 5134 case IP_VERSION(3, 1, 6): 5135 fw_name_dmub = FIRMWARE_DCN316_DMUB; 5136 break; 5137 case IP_VERSION(3, 2, 0): 5138 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB; 5139 break; 5140 case IP_VERSION(3, 2, 1): 5141 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB; 5142 break; 5143 case IP_VERSION(3, 5, 0): 5144 fw_name_dmub = FIRMWARE_DCN_35_DMUB; 5145 break; 5146 case IP_VERSION(3, 5, 1): 5147 fw_name_dmub = FIRMWARE_DCN_351_DMUB; 5148 break; 5149 case IP_VERSION(4, 0, 1): 5150 fw_name_dmub = FIRMWARE_DCN_401_DMUB; 5151 break; 5152 default: 5153 /* ASIC doesn't support DMUB. */ 5154 return 0; 5155 } 5156 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub); 5157 return r; 5158 } 5159 5160 static int dm_early_init(void *handle) 5161 { 5162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5163 struct amdgpu_mode_info *mode_info = &adev->mode_info; 5164 struct atom_context *ctx = mode_info->atom_context; 5165 int index = GetIndexIntoMasterTable(DATA, Object_Header); 5166 u16 data_offset; 5167 5168 /* if there is no object header, skip DM */ 5169 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 5170 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 5171 dev_info(adev->dev, "No object header, skipping DM\n"); 5172 return -ENOENT; 5173 } 5174 5175 switch (adev->asic_type) { 5176 #if defined(CONFIG_DRM_AMD_DC_SI) 5177 case CHIP_TAHITI: 5178 case CHIP_PITCAIRN: 5179 case CHIP_VERDE: 5180 adev->mode_info.num_crtc = 6; 5181 adev->mode_info.num_hpd = 6; 5182 adev->mode_info.num_dig = 6; 5183 break; 5184 case CHIP_OLAND: 5185 adev->mode_info.num_crtc = 2; 5186 adev->mode_info.num_hpd = 2; 5187 adev->mode_info.num_dig = 2; 5188 break; 5189 #endif 5190 case CHIP_BONAIRE: 5191 case CHIP_HAWAII: 5192 adev->mode_info.num_crtc = 6; 5193 adev->mode_info.num_hpd = 6; 5194 adev->mode_info.num_dig = 6; 5195 break; 5196 case CHIP_KAVERI: 5197 adev->mode_info.num_crtc = 4; 5198 adev->mode_info.num_hpd = 6; 5199 adev->mode_info.num_dig = 7; 5200 break; 5201 case CHIP_KABINI: 5202 case CHIP_MULLINS: 5203 adev->mode_info.num_crtc = 2; 5204 adev->mode_info.num_hpd = 6; 5205 adev->mode_info.num_dig = 6; 5206 break; 5207 case CHIP_FIJI: 5208 case CHIP_TONGA: 5209 adev->mode_info.num_crtc = 6; 5210 adev->mode_info.num_hpd = 6; 5211 adev->mode_info.num_dig = 7; 5212 break; 5213 case CHIP_CARRIZO: 5214 adev->mode_info.num_crtc = 3; 5215 adev->mode_info.num_hpd = 6; 5216 adev->mode_info.num_dig = 9; 5217 break; 5218 case CHIP_STONEY: 5219 adev->mode_info.num_crtc = 2; 5220 adev->mode_info.num_hpd = 6; 5221 adev->mode_info.num_dig = 9; 5222 break; 5223 case CHIP_POLARIS11: 5224 case CHIP_POLARIS12: 5225 adev->mode_info.num_crtc = 5; 5226 adev->mode_info.num_hpd = 5; 5227 adev->mode_info.num_dig = 5; 5228 break; 5229 case CHIP_POLARIS10: 5230 case CHIP_VEGAM: 5231 adev->mode_info.num_crtc = 6; 5232 adev->mode_info.num_hpd = 6; 5233 adev->mode_info.num_dig = 6; 5234 break; 5235 case CHIP_VEGA10: 5236 case CHIP_VEGA12: 5237 case CHIP_VEGA20: 5238 adev->mode_info.num_crtc = 6; 5239 adev->mode_info.num_hpd = 6; 5240 adev->mode_info.num_dig = 6; 5241 break; 5242 default: 5243 5244 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 5245 case IP_VERSION(2, 0, 2): 5246 case IP_VERSION(3, 0, 0): 5247 adev->mode_info.num_crtc = 6; 5248 adev->mode_info.num_hpd = 6; 5249 adev->mode_info.num_dig = 6; 5250 break; 5251 case IP_VERSION(2, 0, 0): 5252 case IP_VERSION(3, 0, 2): 5253 adev->mode_info.num_crtc = 5; 5254 adev->mode_info.num_hpd = 5; 5255 adev->mode_info.num_dig = 5; 5256 break; 5257 case IP_VERSION(2, 0, 3): 5258 case IP_VERSION(3, 0, 3): 5259 adev->mode_info.num_crtc = 2; 5260 adev->mode_info.num_hpd = 2; 5261 adev->mode_info.num_dig = 2; 5262 break; 5263 case IP_VERSION(1, 0, 0): 5264 case IP_VERSION(1, 0, 1): 5265 case IP_VERSION(3, 0, 1): 5266 case IP_VERSION(2, 1, 0): 5267 case IP_VERSION(3, 1, 2): 5268 case IP_VERSION(3, 1, 3): 5269 case IP_VERSION(3, 1, 4): 5270 case IP_VERSION(3, 1, 5): 5271 case IP_VERSION(3, 1, 6): 5272 case IP_VERSION(3, 2, 0): 5273 case IP_VERSION(3, 2, 1): 5274 case IP_VERSION(3, 5, 0): 5275 case IP_VERSION(3, 5, 1): 5276 case IP_VERSION(4, 0, 1): 5277 adev->mode_info.num_crtc = 4; 5278 adev->mode_info.num_hpd = 4; 5279 adev->mode_info.num_dig = 4; 5280 break; 5281 default: 5282 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n", 5283 amdgpu_ip_version(adev, DCE_HWIP, 0)); 5284 return -EINVAL; 5285 } 5286 break; 5287 } 5288 5289 if (adev->mode_info.funcs == NULL) 5290 adev->mode_info.funcs = &dm_display_funcs; 5291 5292 /* 5293 * Note: Do NOT change adev->audio_endpt_rreg and 5294 * adev->audio_endpt_wreg because they are initialised in 5295 * amdgpu_device_init() 5296 */ 5297 #if defined(CONFIG_DEBUG_KERNEL_DC) 5298 device_create_file( 5299 adev_to_drm(adev)->dev, 5300 &dev_attr_s3_debug); 5301 #endif 5302 adev->dc_enabled = true; 5303 5304 return dm_init_microcode(adev); 5305 } 5306 5307 static bool modereset_required(struct drm_crtc_state *crtc_state) 5308 { 5309 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 5310 } 5311 5312 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) 5313 { 5314 drm_encoder_cleanup(encoder); 5315 kfree(encoder); 5316 } 5317 5318 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { 5319 .destroy = amdgpu_dm_encoder_destroy, 5320 }; 5321 5322 static int 5323 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 5324 const enum surface_pixel_format format, 5325 enum dc_color_space *color_space) 5326 { 5327 bool full_range; 5328 5329 *color_space = COLOR_SPACE_SRGB; 5330 5331 /* DRM color properties only affect non-RGB formats. */ 5332 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 5333 return 0; 5334 5335 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 5336 5337 switch (plane_state->color_encoding) { 5338 case DRM_COLOR_YCBCR_BT601: 5339 if (full_range) 5340 *color_space = COLOR_SPACE_YCBCR601; 5341 else 5342 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 5343 break; 5344 5345 case DRM_COLOR_YCBCR_BT709: 5346 if (full_range) 5347 *color_space = COLOR_SPACE_YCBCR709; 5348 else 5349 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 5350 break; 5351 5352 case DRM_COLOR_YCBCR_BT2020: 5353 if (full_range) 5354 *color_space = COLOR_SPACE_2020_YCBCR; 5355 else 5356 return -EINVAL; 5357 break; 5358 5359 default: 5360 return -EINVAL; 5361 } 5362 5363 return 0; 5364 } 5365 5366 static int 5367 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 5368 const struct drm_plane_state *plane_state, 5369 const u64 tiling_flags, 5370 struct dc_plane_info *plane_info, 5371 struct dc_plane_address *address, 5372 bool tmz_surface, 5373 bool force_disable_dcc) 5374 { 5375 const struct drm_framebuffer *fb = plane_state->fb; 5376 const struct amdgpu_framebuffer *afb = 5377 to_amdgpu_framebuffer(plane_state->fb); 5378 int ret; 5379 5380 memset(plane_info, 0, sizeof(*plane_info)); 5381 5382 switch (fb->format->format) { 5383 case DRM_FORMAT_C8: 5384 plane_info->format = 5385 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 5386 break; 5387 case DRM_FORMAT_RGB565: 5388 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 5389 break; 5390 case DRM_FORMAT_XRGB8888: 5391 case DRM_FORMAT_ARGB8888: 5392 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 5393 break; 5394 case DRM_FORMAT_XRGB2101010: 5395 case DRM_FORMAT_ARGB2101010: 5396 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 5397 break; 5398 case DRM_FORMAT_XBGR2101010: 5399 case DRM_FORMAT_ABGR2101010: 5400 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 5401 break; 5402 case DRM_FORMAT_XBGR8888: 5403 case DRM_FORMAT_ABGR8888: 5404 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 5405 break; 5406 case DRM_FORMAT_NV21: 5407 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 5408 break; 5409 case DRM_FORMAT_NV12: 5410 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 5411 break; 5412 case DRM_FORMAT_P010: 5413 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 5414 break; 5415 case DRM_FORMAT_XRGB16161616F: 5416 case DRM_FORMAT_ARGB16161616F: 5417 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 5418 break; 5419 case DRM_FORMAT_XBGR16161616F: 5420 case DRM_FORMAT_ABGR16161616F: 5421 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 5422 break; 5423 case DRM_FORMAT_XRGB16161616: 5424 case DRM_FORMAT_ARGB16161616: 5425 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 5426 break; 5427 case DRM_FORMAT_XBGR16161616: 5428 case DRM_FORMAT_ABGR16161616: 5429 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 5430 break; 5431 default: 5432 DRM_ERROR( 5433 "Unsupported screen format %p4cc\n", 5434 &fb->format->format); 5435 return -EINVAL; 5436 } 5437 5438 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 5439 case DRM_MODE_ROTATE_0: 5440 plane_info->rotation = ROTATION_ANGLE_0; 5441 break; 5442 case DRM_MODE_ROTATE_90: 5443 plane_info->rotation = ROTATION_ANGLE_90; 5444 break; 5445 case DRM_MODE_ROTATE_180: 5446 plane_info->rotation = ROTATION_ANGLE_180; 5447 break; 5448 case DRM_MODE_ROTATE_270: 5449 plane_info->rotation = ROTATION_ANGLE_270; 5450 break; 5451 default: 5452 plane_info->rotation = ROTATION_ANGLE_0; 5453 break; 5454 } 5455 5456 5457 plane_info->visible = true; 5458 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 5459 5460 plane_info->layer_index = plane_state->normalized_zpos; 5461 5462 ret = fill_plane_color_attributes(plane_state, plane_info->format, 5463 &plane_info->color_space); 5464 if (ret) 5465 return ret; 5466 5467 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 5468 plane_info->rotation, tiling_flags, 5469 &plane_info->tiling_info, 5470 &plane_info->plane_size, 5471 &plane_info->dcc, address, 5472 tmz_surface, force_disable_dcc); 5473 if (ret) 5474 return ret; 5475 5476 amdgpu_dm_plane_fill_blending_from_plane_state( 5477 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 5478 &plane_info->global_alpha, &plane_info->global_alpha_value); 5479 5480 return 0; 5481 } 5482 5483 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 5484 struct dc_plane_state *dc_plane_state, 5485 struct drm_plane_state *plane_state, 5486 struct drm_crtc_state *crtc_state) 5487 { 5488 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5489 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 5490 struct dc_scaling_info scaling_info; 5491 struct dc_plane_info plane_info; 5492 int ret; 5493 bool force_disable_dcc = false; 5494 5495 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 5496 if (ret) 5497 return ret; 5498 5499 dc_plane_state->src_rect = scaling_info.src_rect; 5500 dc_plane_state->dst_rect = scaling_info.dst_rect; 5501 dc_plane_state->clip_rect = scaling_info.clip_rect; 5502 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 5503 5504 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; 5505 ret = fill_dc_plane_info_and_addr(adev, plane_state, 5506 afb->tiling_flags, 5507 &plane_info, 5508 &dc_plane_state->address, 5509 afb->tmz_surface, 5510 force_disable_dcc); 5511 if (ret) 5512 return ret; 5513 5514 dc_plane_state->format = plane_info.format; 5515 dc_plane_state->color_space = plane_info.color_space; 5516 dc_plane_state->format = plane_info.format; 5517 dc_plane_state->plane_size = plane_info.plane_size; 5518 dc_plane_state->rotation = plane_info.rotation; 5519 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 5520 dc_plane_state->stereo_format = plane_info.stereo_format; 5521 dc_plane_state->tiling_info = plane_info.tiling_info; 5522 dc_plane_state->visible = plane_info.visible; 5523 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 5524 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 5525 dc_plane_state->global_alpha = plane_info.global_alpha; 5526 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 5527 dc_plane_state->dcc = plane_info.dcc; 5528 dc_plane_state->layer_index = plane_info.layer_index; 5529 dc_plane_state->flip_int_enabled = true; 5530 5531 /* 5532 * Always set input transfer function, since plane state is refreshed 5533 * every time. 5534 */ 5535 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 5536 plane_state, 5537 dc_plane_state); 5538 if (ret) 5539 return ret; 5540 5541 return 0; 5542 } 5543 5544 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 5545 struct rect *dirty_rect, int32_t x, 5546 s32 y, s32 width, s32 height, 5547 int *i, bool ffu) 5548 { 5549 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 5550 5551 dirty_rect->x = x; 5552 dirty_rect->y = y; 5553 dirty_rect->width = width; 5554 dirty_rect->height = height; 5555 5556 if (ffu) 5557 drm_dbg(plane->dev, 5558 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 5559 plane->base.id, width, height); 5560 else 5561 drm_dbg(plane->dev, 5562 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 5563 plane->base.id, x, y, width, height); 5564 5565 (*i)++; 5566 } 5567 5568 /** 5569 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 5570 * 5571 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 5572 * remote fb 5573 * @old_plane_state: Old state of @plane 5574 * @new_plane_state: New state of @plane 5575 * @crtc_state: New state of CRTC connected to the @plane 5576 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 5577 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 5578 * If PSR SU is enabled and damage clips are available, only the regions of the screen 5579 * that have changed will be updated. If PSR SU is not enabled, 5580 * or if damage clips are not available, the entire screen will be updated. 5581 * @dirty_regions_changed: dirty regions changed 5582 * 5583 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 5584 * (referred to as "damage clips" in DRM nomenclature) that require updating on 5585 * the eDP remote buffer. The responsibility of specifying the dirty regions is 5586 * amdgpu_dm's. 5587 * 5588 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 5589 * plane with regions that require flushing to the eDP remote buffer. In 5590 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 5591 * implicitly provide damage clips without any client support via the plane 5592 * bounds. 5593 */ 5594 static void fill_dc_dirty_rects(struct drm_plane *plane, 5595 struct drm_plane_state *old_plane_state, 5596 struct drm_plane_state *new_plane_state, 5597 struct drm_crtc_state *crtc_state, 5598 struct dc_flip_addrs *flip_addrs, 5599 bool is_psr_su, 5600 bool *dirty_regions_changed) 5601 { 5602 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 5603 struct rect *dirty_rects = flip_addrs->dirty_rects; 5604 u32 num_clips; 5605 struct drm_mode_rect *clips; 5606 bool bb_changed; 5607 bool fb_changed; 5608 u32 i = 0; 5609 *dirty_regions_changed = false; 5610 5611 /* 5612 * Cursor plane has it's own dirty rect update interface. See 5613 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 5614 */ 5615 if (plane->type == DRM_PLANE_TYPE_CURSOR) 5616 return; 5617 5618 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 5619 goto ffu; 5620 5621 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 5622 clips = drm_plane_get_damage_clips(new_plane_state); 5623 5624 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 5625 is_psr_su))) 5626 goto ffu; 5627 5628 if (!dm_crtc_state->mpo_requested) { 5629 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 5630 goto ffu; 5631 5632 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 5633 fill_dc_dirty_rect(new_plane_state->plane, 5634 &dirty_rects[flip_addrs->dirty_rect_count], 5635 clips->x1, clips->y1, 5636 clips->x2 - clips->x1, clips->y2 - clips->y1, 5637 &flip_addrs->dirty_rect_count, 5638 false); 5639 return; 5640 } 5641 5642 /* 5643 * MPO is requested. Add entire plane bounding box to dirty rects if 5644 * flipped to or damaged. 5645 * 5646 * If plane is moved or resized, also add old bounding box to dirty 5647 * rects. 5648 */ 5649 fb_changed = old_plane_state->fb->base.id != 5650 new_plane_state->fb->base.id; 5651 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 5652 old_plane_state->crtc_y != new_plane_state->crtc_y || 5653 old_plane_state->crtc_w != new_plane_state->crtc_w || 5654 old_plane_state->crtc_h != new_plane_state->crtc_h); 5655 5656 drm_dbg(plane->dev, 5657 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 5658 new_plane_state->plane->base.id, 5659 bb_changed, fb_changed, num_clips); 5660 5661 *dirty_regions_changed = bb_changed; 5662 5663 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 5664 goto ffu; 5665 5666 if (bb_changed) { 5667 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5668 new_plane_state->crtc_x, 5669 new_plane_state->crtc_y, 5670 new_plane_state->crtc_w, 5671 new_plane_state->crtc_h, &i, false); 5672 5673 /* Add old plane bounding-box if plane is moved or resized */ 5674 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5675 old_plane_state->crtc_x, 5676 old_plane_state->crtc_y, 5677 old_plane_state->crtc_w, 5678 old_plane_state->crtc_h, &i, false); 5679 } 5680 5681 if (num_clips) { 5682 for (; i < num_clips; clips++) 5683 fill_dc_dirty_rect(new_plane_state->plane, 5684 &dirty_rects[i], clips->x1, 5685 clips->y1, clips->x2 - clips->x1, 5686 clips->y2 - clips->y1, &i, false); 5687 } else if (fb_changed && !bb_changed) { 5688 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 5689 new_plane_state->crtc_x, 5690 new_plane_state->crtc_y, 5691 new_plane_state->crtc_w, 5692 new_plane_state->crtc_h, &i, false); 5693 } 5694 5695 flip_addrs->dirty_rect_count = i; 5696 return; 5697 5698 ffu: 5699 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 5700 dm_crtc_state->base.mode.crtc_hdisplay, 5701 dm_crtc_state->base.mode.crtc_vdisplay, 5702 &flip_addrs->dirty_rect_count, true); 5703 } 5704 5705 static void update_stream_scaling_settings(const struct drm_display_mode *mode, 5706 const struct dm_connector_state *dm_state, 5707 struct dc_stream_state *stream) 5708 { 5709 enum amdgpu_rmx_type rmx_type; 5710 5711 struct rect src = { 0 }; /* viewport in composition space*/ 5712 struct rect dst = { 0 }; /* stream addressable area */ 5713 5714 /* no mode. nothing to be done */ 5715 if (!mode) 5716 return; 5717 5718 /* Full screen scaling by default */ 5719 src.width = mode->hdisplay; 5720 src.height = mode->vdisplay; 5721 dst.width = stream->timing.h_addressable; 5722 dst.height = stream->timing.v_addressable; 5723 5724 if (dm_state) { 5725 rmx_type = dm_state->scaling; 5726 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 5727 if (src.width * dst.height < 5728 src.height * dst.width) { 5729 /* height needs less upscaling/more downscaling */ 5730 dst.width = src.width * 5731 dst.height / src.height; 5732 } else { 5733 /* width needs less upscaling/more downscaling */ 5734 dst.height = src.height * 5735 dst.width / src.width; 5736 } 5737 } else if (rmx_type == RMX_CENTER) { 5738 dst = src; 5739 } 5740 5741 dst.x = (stream->timing.h_addressable - dst.width) / 2; 5742 dst.y = (stream->timing.v_addressable - dst.height) / 2; 5743 5744 if (dm_state->underscan_enable) { 5745 dst.x += dm_state->underscan_hborder / 2; 5746 dst.y += dm_state->underscan_vborder / 2; 5747 dst.width -= dm_state->underscan_hborder; 5748 dst.height -= dm_state->underscan_vborder; 5749 } 5750 } 5751 5752 stream->src = src; 5753 stream->dst = dst; 5754 5755 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", 5756 dst.x, dst.y, dst.width, dst.height); 5757 5758 } 5759 5760 static enum dc_color_depth 5761 convert_color_depth_from_display_info(const struct drm_connector *connector, 5762 bool is_y420, int requested_bpc) 5763 { 5764 u8 bpc; 5765 5766 if (is_y420) { 5767 bpc = 8; 5768 5769 /* Cap display bpc based on HDMI 2.0 HF-VSDB */ 5770 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48) 5771 bpc = 16; 5772 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36) 5773 bpc = 12; 5774 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 5775 bpc = 10; 5776 } else { 5777 bpc = (uint8_t)connector->display_info.bpc; 5778 /* Assume 8 bpc by default if no bpc is specified. */ 5779 bpc = bpc ? bpc : 8; 5780 } 5781 5782 if (requested_bpc > 0) { 5783 /* 5784 * Cap display bpc based on the user requested value. 5785 * 5786 * The value for state->max_bpc may not correctly updated 5787 * depending on when the connector gets added to the state 5788 * or if this was called outside of atomic check, so it 5789 * can't be used directly. 5790 */ 5791 bpc = min_t(u8, bpc, requested_bpc); 5792 5793 /* Round down to the nearest even number. */ 5794 bpc = bpc - (bpc & 1); 5795 } 5796 5797 switch (bpc) { 5798 case 0: 5799 /* 5800 * Temporary Work around, DRM doesn't parse color depth for 5801 * EDID revision before 1.4 5802 * TODO: Fix edid parsing 5803 */ 5804 return COLOR_DEPTH_888; 5805 case 6: 5806 return COLOR_DEPTH_666; 5807 case 8: 5808 return COLOR_DEPTH_888; 5809 case 10: 5810 return COLOR_DEPTH_101010; 5811 case 12: 5812 return COLOR_DEPTH_121212; 5813 case 14: 5814 return COLOR_DEPTH_141414; 5815 case 16: 5816 return COLOR_DEPTH_161616; 5817 default: 5818 return COLOR_DEPTH_UNDEFINED; 5819 } 5820 } 5821 5822 static enum dc_aspect_ratio 5823 get_aspect_ratio(const struct drm_display_mode *mode_in) 5824 { 5825 /* 1-1 mapping, since both enums follow the HDMI spec. */ 5826 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; 5827 } 5828 5829 static enum dc_color_space 5830 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, 5831 const struct drm_connector_state *connector_state) 5832 { 5833 enum dc_color_space color_space = COLOR_SPACE_SRGB; 5834 5835 switch (connector_state->colorspace) { 5836 case DRM_MODE_COLORIMETRY_BT601_YCC: 5837 if (dc_crtc_timing->flags.Y_ONLY) 5838 color_space = COLOR_SPACE_YCBCR601_LIMITED; 5839 else 5840 color_space = COLOR_SPACE_YCBCR601; 5841 break; 5842 case DRM_MODE_COLORIMETRY_BT709_YCC: 5843 if (dc_crtc_timing->flags.Y_ONLY) 5844 color_space = COLOR_SPACE_YCBCR709_LIMITED; 5845 else 5846 color_space = COLOR_SPACE_YCBCR709; 5847 break; 5848 case DRM_MODE_COLORIMETRY_OPRGB: 5849 color_space = COLOR_SPACE_ADOBERGB; 5850 break; 5851 case DRM_MODE_COLORIMETRY_BT2020_RGB: 5852 case DRM_MODE_COLORIMETRY_BT2020_YCC: 5853 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) 5854 color_space = COLOR_SPACE_2020_RGB_FULLRANGE; 5855 else 5856 color_space = COLOR_SPACE_2020_YCBCR; 5857 break; 5858 case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601 5859 default: 5860 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { 5861 color_space = COLOR_SPACE_SRGB; 5862 /* 5863 * 27030khz is the separation point between HDTV and SDTV 5864 * according to HDMI spec, we use YCbCr709 and YCbCr601 5865 * respectively 5866 */ 5867 } else if (dc_crtc_timing->pix_clk_100hz > 270300) { 5868 if (dc_crtc_timing->flags.Y_ONLY) 5869 color_space = 5870 COLOR_SPACE_YCBCR709_LIMITED; 5871 else 5872 color_space = COLOR_SPACE_YCBCR709; 5873 } else { 5874 if (dc_crtc_timing->flags.Y_ONLY) 5875 color_space = 5876 COLOR_SPACE_YCBCR601_LIMITED; 5877 else 5878 color_space = COLOR_SPACE_YCBCR601; 5879 } 5880 break; 5881 } 5882 5883 return color_space; 5884 } 5885 5886 static enum display_content_type 5887 get_output_content_type(const struct drm_connector_state *connector_state) 5888 { 5889 switch (connector_state->content_type) { 5890 default: 5891 case DRM_MODE_CONTENT_TYPE_NO_DATA: 5892 return DISPLAY_CONTENT_TYPE_NO_DATA; 5893 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 5894 return DISPLAY_CONTENT_TYPE_GRAPHICS; 5895 case DRM_MODE_CONTENT_TYPE_PHOTO: 5896 return DISPLAY_CONTENT_TYPE_PHOTO; 5897 case DRM_MODE_CONTENT_TYPE_CINEMA: 5898 return DISPLAY_CONTENT_TYPE_CINEMA; 5899 case DRM_MODE_CONTENT_TYPE_GAME: 5900 return DISPLAY_CONTENT_TYPE_GAME; 5901 } 5902 } 5903 5904 static bool adjust_colour_depth_from_display_info( 5905 struct dc_crtc_timing *timing_out, 5906 const struct drm_display_info *info) 5907 { 5908 enum dc_color_depth depth = timing_out->display_color_depth; 5909 int normalized_clk; 5910 5911 do { 5912 normalized_clk = timing_out->pix_clk_100hz / 10; 5913 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 5914 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 5915 normalized_clk /= 2; 5916 /* Adjusting pix clock following on HDMI spec based on colour depth */ 5917 switch (depth) { 5918 case COLOR_DEPTH_888: 5919 break; 5920 case COLOR_DEPTH_101010: 5921 normalized_clk = (normalized_clk * 30) / 24; 5922 break; 5923 case COLOR_DEPTH_121212: 5924 normalized_clk = (normalized_clk * 36) / 24; 5925 break; 5926 case COLOR_DEPTH_161616: 5927 normalized_clk = (normalized_clk * 48) / 24; 5928 break; 5929 default: 5930 /* The above depths are the only ones valid for HDMI. */ 5931 return false; 5932 } 5933 if (normalized_clk <= info->max_tmds_clock) { 5934 timing_out->display_color_depth = depth; 5935 return true; 5936 } 5937 } while (--depth > COLOR_DEPTH_666); 5938 return false; 5939 } 5940 5941 static void fill_stream_properties_from_drm_display_mode( 5942 struct dc_stream_state *stream, 5943 const struct drm_display_mode *mode_in, 5944 const struct drm_connector *connector, 5945 const struct drm_connector_state *connector_state, 5946 const struct dc_stream_state *old_stream, 5947 int requested_bpc) 5948 { 5949 struct dc_crtc_timing *timing_out = &stream->timing; 5950 const struct drm_display_info *info = &connector->display_info; 5951 struct amdgpu_dm_connector *aconnector = NULL; 5952 struct hdmi_vendor_infoframe hv_frame; 5953 struct hdmi_avi_infoframe avi_frame; 5954 5955 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5956 aconnector = to_amdgpu_dm_connector(connector); 5957 5958 memset(&hv_frame, 0, sizeof(hv_frame)); 5959 memset(&avi_frame, 0, sizeof(avi_frame)); 5960 5961 timing_out->h_border_left = 0; 5962 timing_out->h_border_right = 0; 5963 timing_out->v_border_top = 0; 5964 timing_out->v_border_bottom = 0; 5965 /* TODO: un-hardcode */ 5966 if (drm_mode_is_420_only(info, mode_in) 5967 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5968 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5969 else if (drm_mode_is_420_also(info, mode_in) 5970 && aconnector 5971 && aconnector->force_yuv420_output) 5972 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 5973 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444) 5974 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 5975 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; 5976 else 5977 timing_out->pixel_encoding = PIXEL_ENCODING_RGB; 5978 5979 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; 5980 timing_out->display_color_depth = convert_color_depth_from_display_info( 5981 connector, 5982 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), 5983 requested_bpc); 5984 timing_out->scan_type = SCANNING_TYPE_NODATA; 5985 timing_out->hdmi_vic = 0; 5986 5987 if (old_stream) { 5988 timing_out->vic = old_stream->timing.vic; 5989 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; 5990 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; 5991 } else { 5992 timing_out->vic = drm_match_cea_mode(mode_in); 5993 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) 5994 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; 5995 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) 5996 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; 5997 } 5998 5999 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 6000 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); 6001 timing_out->vic = avi_frame.video_code; 6002 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); 6003 timing_out->hdmi_vic = hv_frame.vic; 6004 } 6005 6006 if (aconnector && is_freesync_video_mode(mode_in, aconnector)) { 6007 timing_out->h_addressable = mode_in->hdisplay; 6008 timing_out->h_total = mode_in->htotal; 6009 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; 6010 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; 6011 timing_out->v_total = mode_in->vtotal; 6012 timing_out->v_addressable = mode_in->vdisplay; 6013 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; 6014 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; 6015 timing_out->pix_clk_100hz = mode_in->clock * 10; 6016 } else { 6017 timing_out->h_addressable = mode_in->crtc_hdisplay; 6018 timing_out->h_total = mode_in->crtc_htotal; 6019 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; 6020 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; 6021 timing_out->v_total = mode_in->crtc_vtotal; 6022 timing_out->v_addressable = mode_in->crtc_vdisplay; 6023 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; 6024 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; 6025 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; 6026 } 6027 6028 timing_out->aspect_ratio = get_aspect_ratio(mode_in); 6029 6030 stream->out_transfer_func.type = TF_TYPE_PREDEFINED; 6031 stream->out_transfer_func.tf = TRANSFER_FUNCTION_SRGB; 6032 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 6033 if (!adjust_colour_depth_from_display_info(timing_out, info) && 6034 drm_mode_is_420_also(info, mode_in) && 6035 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 6036 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 6037 adjust_colour_depth_from_display_info(timing_out, info); 6038 } 6039 } 6040 6041 stream->output_color_space = get_output_color_space(timing_out, connector_state); 6042 stream->content_type = get_output_content_type(connector_state); 6043 } 6044 6045 static void fill_audio_info(struct audio_info *audio_info, 6046 const struct drm_connector *drm_connector, 6047 const struct dc_sink *dc_sink) 6048 { 6049 int i = 0; 6050 int cea_revision = 0; 6051 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; 6052 6053 audio_info->manufacture_id = edid_caps->manufacturer_id; 6054 audio_info->product_id = edid_caps->product_id; 6055 6056 cea_revision = drm_connector->display_info.cea_rev; 6057 6058 strscpy(audio_info->display_name, 6059 edid_caps->display_name, 6060 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 6061 6062 if (cea_revision >= 3) { 6063 audio_info->mode_count = edid_caps->audio_mode_count; 6064 6065 for (i = 0; i < audio_info->mode_count; ++i) { 6066 audio_info->modes[i].format_code = 6067 (enum audio_format_code) 6068 (edid_caps->audio_modes[i].format_code); 6069 audio_info->modes[i].channel_count = 6070 edid_caps->audio_modes[i].channel_count; 6071 audio_info->modes[i].sample_rates.all = 6072 edid_caps->audio_modes[i].sample_rate; 6073 audio_info->modes[i].sample_size = 6074 edid_caps->audio_modes[i].sample_size; 6075 } 6076 } 6077 6078 audio_info->flags.all = edid_caps->speaker_flags; 6079 6080 /* TODO: We only check for the progressive mode, check for interlace mode too */ 6081 if (drm_connector->latency_present[0]) { 6082 audio_info->video_latency = drm_connector->video_latency[0]; 6083 audio_info->audio_latency = drm_connector->audio_latency[0]; 6084 } 6085 6086 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ 6087 6088 } 6089 6090 static void 6091 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, 6092 struct drm_display_mode *dst_mode) 6093 { 6094 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; 6095 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; 6096 dst_mode->crtc_clock = src_mode->crtc_clock; 6097 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; 6098 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; 6099 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; 6100 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; 6101 dst_mode->crtc_htotal = src_mode->crtc_htotal; 6102 dst_mode->crtc_hskew = src_mode->crtc_hskew; 6103 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; 6104 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; 6105 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; 6106 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; 6107 dst_mode->crtc_vtotal = src_mode->crtc_vtotal; 6108 } 6109 6110 static void 6111 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, 6112 const struct drm_display_mode *native_mode, 6113 bool scale_enabled) 6114 { 6115 if (scale_enabled) { 6116 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6117 } else if (native_mode->clock == drm_mode->clock && 6118 native_mode->htotal == drm_mode->htotal && 6119 native_mode->vtotal == drm_mode->vtotal) { 6120 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); 6121 } else { 6122 /* no scaling nor amdgpu inserted, no need to patch */ 6123 } 6124 } 6125 6126 static struct dc_sink * 6127 create_fake_sink(struct dc_link *link) 6128 { 6129 struct dc_sink_init_data sink_init_data = { 0 }; 6130 struct dc_sink *sink = NULL; 6131 6132 sink_init_data.link = link; 6133 sink_init_data.sink_signal = link->connector_signal; 6134 6135 sink = dc_sink_create(&sink_init_data); 6136 if (!sink) { 6137 DRM_ERROR("Failed to create sink!\n"); 6138 return NULL; 6139 } 6140 sink->sink_signal = SIGNAL_TYPE_VIRTUAL; 6141 6142 return sink; 6143 } 6144 6145 static void set_multisync_trigger_params( 6146 struct dc_stream_state *stream) 6147 { 6148 struct dc_stream_state *master = NULL; 6149 6150 if (stream->triggered_crtc_reset.enabled) { 6151 master = stream->triggered_crtc_reset.event_source; 6152 stream->triggered_crtc_reset.event = 6153 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 6154 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 6155 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 6156 } 6157 } 6158 6159 static void set_master_stream(struct dc_stream_state *stream_set[], 6160 int stream_count) 6161 { 6162 int j, highest_rfr = 0, master_stream = 0; 6163 6164 for (j = 0; j < stream_count; j++) { 6165 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 6166 int refresh_rate = 0; 6167 6168 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 6169 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 6170 if (refresh_rate > highest_rfr) { 6171 highest_rfr = refresh_rate; 6172 master_stream = j; 6173 } 6174 } 6175 } 6176 for (j = 0; j < stream_count; j++) { 6177 if (stream_set[j]) 6178 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 6179 } 6180 } 6181 6182 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 6183 { 6184 int i = 0; 6185 struct dc_stream_state *stream; 6186 6187 if (context->stream_count < 2) 6188 return; 6189 for (i = 0; i < context->stream_count ; i++) { 6190 if (!context->streams[i]) 6191 continue; 6192 /* 6193 * TODO: add a function to read AMD VSDB bits and set 6194 * crtc_sync_master.multi_sync_enabled flag 6195 * For now it's set to false 6196 */ 6197 } 6198 6199 set_master_stream(context->streams, context->stream_count); 6200 6201 for (i = 0; i < context->stream_count ; i++) { 6202 stream = context->streams[i]; 6203 6204 if (!stream) 6205 continue; 6206 6207 set_multisync_trigger_params(stream); 6208 } 6209 } 6210 6211 /** 6212 * DOC: FreeSync Video 6213 * 6214 * When a userspace application wants to play a video, the content follows a 6215 * standard format definition that usually specifies the FPS for that format. 6216 * The below list illustrates some video format and the expected FPS, 6217 * respectively: 6218 * 6219 * - TV/NTSC (23.976 FPS) 6220 * - Cinema (24 FPS) 6221 * - TV/PAL (25 FPS) 6222 * - TV/NTSC (29.97 FPS) 6223 * - TV/NTSC (30 FPS) 6224 * - Cinema HFR (48 FPS) 6225 * - TV/PAL (50 FPS) 6226 * - Commonly used (60 FPS) 6227 * - Multiples of 24 (48,72,96 FPS) 6228 * 6229 * The list of standards video format is not huge and can be added to the 6230 * connector modeset list beforehand. With that, userspace can leverage 6231 * FreeSync to extends the front porch in order to attain the target refresh 6232 * rate. Such a switch will happen seamlessly, without screen blanking or 6233 * reprogramming of the output in any other way. If the userspace requests a 6234 * modesetting change compatible with FreeSync modes that only differ in the 6235 * refresh rate, DC will skip the full update and avoid blink during the 6236 * transition. For example, the video player can change the modesetting from 6237 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without 6238 * causing any display blink. This same concept can be applied to a mode 6239 * setting change. 6240 */ 6241 static struct drm_display_mode * 6242 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, 6243 bool use_probed_modes) 6244 { 6245 struct drm_display_mode *m, *m_pref = NULL; 6246 u16 current_refresh, highest_refresh; 6247 struct list_head *list_head = use_probed_modes ? 6248 &aconnector->base.probed_modes : 6249 &aconnector->base.modes; 6250 6251 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6252 return NULL; 6253 6254 if (aconnector->freesync_vid_base.clock != 0) 6255 return &aconnector->freesync_vid_base; 6256 6257 /* Find the preferred mode */ 6258 list_for_each_entry(m, list_head, head) { 6259 if (m->type & DRM_MODE_TYPE_PREFERRED) { 6260 m_pref = m; 6261 break; 6262 } 6263 } 6264 6265 if (!m_pref) { 6266 /* Probably an EDID with no preferred mode. Fallback to first entry */ 6267 m_pref = list_first_entry_or_null( 6268 &aconnector->base.modes, struct drm_display_mode, head); 6269 if (!m_pref) { 6270 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n"); 6271 return NULL; 6272 } 6273 } 6274 6275 highest_refresh = drm_mode_vrefresh(m_pref); 6276 6277 /* 6278 * Find the mode with highest refresh rate with same resolution. 6279 * For some monitors, preferred mode is not the mode with highest 6280 * supported refresh rate. 6281 */ 6282 list_for_each_entry(m, list_head, head) { 6283 current_refresh = drm_mode_vrefresh(m); 6284 6285 if (m->hdisplay == m_pref->hdisplay && 6286 m->vdisplay == m_pref->vdisplay && 6287 highest_refresh < current_refresh) { 6288 highest_refresh = current_refresh; 6289 m_pref = m; 6290 } 6291 } 6292 6293 drm_mode_copy(&aconnector->freesync_vid_base, m_pref); 6294 return m_pref; 6295 } 6296 6297 static bool is_freesync_video_mode(const struct drm_display_mode *mode, 6298 struct amdgpu_dm_connector *aconnector) 6299 { 6300 struct drm_display_mode *high_mode; 6301 int timing_diff; 6302 6303 high_mode = get_highest_refresh_rate_mode(aconnector, false); 6304 if (!high_mode || !mode) 6305 return false; 6306 6307 timing_diff = high_mode->vtotal - mode->vtotal; 6308 6309 if (high_mode->clock == 0 || high_mode->clock != mode->clock || 6310 high_mode->hdisplay != mode->hdisplay || 6311 high_mode->vdisplay != mode->vdisplay || 6312 high_mode->hsync_start != mode->hsync_start || 6313 high_mode->hsync_end != mode->hsync_end || 6314 high_mode->htotal != mode->htotal || 6315 high_mode->hskew != mode->hskew || 6316 high_mode->vscan != mode->vscan || 6317 high_mode->vsync_start - mode->vsync_start != timing_diff || 6318 high_mode->vsync_end - mode->vsync_end != timing_diff) 6319 return false; 6320 else 6321 return true; 6322 } 6323 6324 #if defined(CONFIG_DRM_AMD_DC_FP) 6325 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, 6326 struct dc_sink *sink, struct dc_stream_state *stream, 6327 struct dsc_dec_dpcd_caps *dsc_caps) 6328 { 6329 stream->timing.flags.DSC = 0; 6330 dsc_caps->is_dsc_supported = false; 6331 6332 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 6333 sink->sink_signal == SIGNAL_TYPE_EDP)) { 6334 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || 6335 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) 6336 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, 6337 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, 6338 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, 6339 dsc_caps); 6340 } 6341 } 6342 6343 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, 6344 struct dc_sink *sink, struct dc_stream_state *stream, 6345 struct dsc_dec_dpcd_caps *dsc_caps, 6346 uint32_t max_dsc_target_bpp_limit_override) 6347 { 6348 const struct dc_link_settings *verified_link_cap = NULL; 6349 u32 link_bw_in_kbps; 6350 u32 edp_min_bpp_x16, edp_max_bpp_x16; 6351 struct dc *dc = sink->ctx->dc; 6352 struct dc_dsc_bw_range bw_range = {0}; 6353 struct dc_dsc_config dsc_cfg = {0}; 6354 struct dc_dsc_config_options dsc_options = {0}; 6355 6356 dc_dsc_get_default_config_option(dc, &dsc_options); 6357 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6358 6359 verified_link_cap = dc_link_get_link_cap(stream->link); 6360 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); 6361 edp_min_bpp_x16 = 8 * 16; 6362 edp_max_bpp_x16 = 8 * 16; 6363 6364 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) 6365 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; 6366 6367 if (edp_max_bpp_x16 < edp_min_bpp_x16) 6368 edp_min_bpp_x16 = edp_max_bpp_x16; 6369 6370 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], 6371 dc->debug.dsc_min_slice_height_override, 6372 edp_min_bpp_x16, edp_max_bpp_x16, 6373 dsc_caps, 6374 &stream->timing, 6375 dc_link_get_highest_encoding_format(aconnector->dc_link), 6376 &bw_range)) { 6377 6378 if (bw_range.max_kbps < link_bw_in_kbps) { 6379 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6380 dsc_caps, 6381 &dsc_options, 6382 0, 6383 &stream->timing, 6384 dc_link_get_highest_encoding_format(aconnector->dc_link), 6385 &dsc_cfg)) { 6386 stream->timing.dsc_cfg = dsc_cfg; 6387 stream->timing.flags.DSC = 1; 6388 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; 6389 } 6390 return; 6391 } 6392 } 6393 6394 if (dc_dsc_compute_config(dc->res_pool->dscs[0], 6395 dsc_caps, 6396 &dsc_options, 6397 link_bw_in_kbps, 6398 &stream->timing, 6399 dc_link_get_highest_encoding_format(aconnector->dc_link), 6400 &dsc_cfg)) { 6401 stream->timing.dsc_cfg = dsc_cfg; 6402 stream->timing.flags.DSC = 1; 6403 } 6404 } 6405 6406 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, 6407 struct dc_sink *sink, struct dc_stream_state *stream, 6408 struct dsc_dec_dpcd_caps *dsc_caps) 6409 { 6410 struct drm_connector *drm_connector = &aconnector->base; 6411 u32 link_bandwidth_kbps; 6412 struct dc *dc = sink->ctx->dc; 6413 u32 max_supported_bw_in_kbps, timing_bw_in_kbps; 6414 u32 dsc_max_supported_bw_in_kbps; 6415 u32 max_dsc_target_bpp_limit_override = 6416 drm_connector->display_info.max_dsc_bpp; 6417 struct dc_dsc_config_options dsc_options = {0}; 6418 6419 dc_dsc_get_default_config_option(dc, &dsc_options); 6420 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16; 6421 6422 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, 6423 dc_link_get_link_cap(aconnector->dc_link)); 6424 6425 /* Set DSC policy according to dsc_clock_en */ 6426 dc_dsc_policy_set_enable_dsc_when_not_needed( 6427 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); 6428 6429 if (sink->sink_signal == SIGNAL_TYPE_EDP && 6430 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && 6431 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { 6432 6433 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); 6434 6435 } else if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { 6436 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { 6437 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6438 dsc_caps, 6439 &dsc_options, 6440 link_bandwidth_kbps, 6441 &stream->timing, 6442 dc_link_get_highest_encoding_format(aconnector->dc_link), 6443 &stream->timing.dsc_cfg)) { 6444 stream->timing.flags.DSC = 1; 6445 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); 6446 } 6447 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { 6448 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, 6449 dc_link_get_highest_encoding_format(aconnector->dc_link)); 6450 max_supported_bw_in_kbps = link_bandwidth_kbps; 6451 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; 6452 6453 if (timing_bw_in_kbps > max_supported_bw_in_kbps && 6454 max_supported_bw_in_kbps > 0 && 6455 dsc_max_supported_bw_in_kbps > 0) 6456 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], 6457 dsc_caps, 6458 &dsc_options, 6459 dsc_max_supported_bw_in_kbps, 6460 &stream->timing, 6461 dc_link_get_highest_encoding_format(aconnector->dc_link), 6462 &stream->timing.dsc_cfg)) { 6463 stream->timing.flags.DSC = 1; 6464 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", 6465 __func__, drm_connector->name); 6466 } 6467 } 6468 } 6469 6470 /* Overwrite the stream flag if DSC is enabled through debugfs */ 6471 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) 6472 stream->timing.flags.DSC = 1; 6473 6474 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) 6475 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; 6476 6477 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) 6478 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; 6479 6480 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) 6481 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; 6482 } 6483 #endif 6484 6485 static struct dc_stream_state * 6486 create_stream_for_sink(struct drm_connector *connector, 6487 const struct drm_display_mode *drm_mode, 6488 const struct dm_connector_state *dm_state, 6489 const struct dc_stream_state *old_stream, 6490 int requested_bpc) 6491 { 6492 struct amdgpu_dm_connector *aconnector = NULL; 6493 struct drm_display_mode *preferred_mode = NULL; 6494 const struct drm_connector_state *con_state = &dm_state->base; 6495 struct dc_stream_state *stream = NULL; 6496 struct drm_display_mode mode; 6497 struct drm_display_mode saved_mode; 6498 struct drm_display_mode *freesync_mode = NULL; 6499 bool native_mode_found = false; 6500 bool recalculate_timing = false; 6501 bool scale = dm_state->scaling != RMX_OFF; 6502 int mode_refresh; 6503 int preferred_refresh = 0; 6504 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN; 6505 #if defined(CONFIG_DRM_AMD_DC_FP) 6506 struct dsc_dec_dpcd_caps dsc_caps; 6507 #endif 6508 struct dc_link *link = NULL; 6509 struct dc_sink *sink = NULL; 6510 6511 drm_mode_init(&mode, drm_mode); 6512 memset(&saved_mode, 0, sizeof(saved_mode)); 6513 6514 if (connector == NULL) { 6515 DRM_ERROR("connector is NULL!\n"); 6516 return stream; 6517 } 6518 6519 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) { 6520 aconnector = NULL; 6521 aconnector = to_amdgpu_dm_connector(connector); 6522 link = aconnector->dc_link; 6523 } else { 6524 struct drm_writeback_connector *wbcon = NULL; 6525 struct amdgpu_dm_wb_connector *dm_wbcon = NULL; 6526 6527 wbcon = drm_connector_to_writeback(connector); 6528 dm_wbcon = to_amdgpu_dm_wb_connector(wbcon); 6529 link = dm_wbcon->link; 6530 } 6531 6532 if (!aconnector || !aconnector->dc_sink) { 6533 sink = create_fake_sink(link); 6534 if (!sink) 6535 return stream; 6536 6537 } else { 6538 sink = aconnector->dc_sink; 6539 dc_sink_retain(sink); 6540 } 6541 6542 stream = dc_create_stream_for_sink(sink); 6543 6544 if (stream == NULL) { 6545 DRM_ERROR("Failed to create stream for sink!\n"); 6546 goto finish; 6547 } 6548 6549 /* We leave this NULL for writeback connectors */ 6550 stream->dm_stream_context = aconnector; 6551 6552 stream->timing.flags.LTE_340MCSC_SCRAMBLE = 6553 connector->display_info.hdmi.scdc.scrambling.low_rates; 6554 6555 list_for_each_entry(preferred_mode, &connector->modes, head) { 6556 /* Search for preferred mode */ 6557 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { 6558 native_mode_found = true; 6559 break; 6560 } 6561 } 6562 if (!native_mode_found) 6563 preferred_mode = list_first_entry_or_null( 6564 &connector->modes, 6565 struct drm_display_mode, 6566 head); 6567 6568 mode_refresh = drm_mode_vrefresh(&mode); 6569 6570 if (preferred_mode == NULL) { 6571 /* 6572 * This may not be an error, the use case is when we have no 6573 * usermode calls to reset and set mode upon hotplug. In this 6574 * case, we call set mode ourselves to restore the previous mode 6575 * and the modelist may not be filled in time. 6576 */ 6577 DRM_DEBUG_DRIVER("No preferred mode found\n"); 6578 } else if (aconnector) { 6579 recalculate_timing = amdgpu_freesync_vid_mode && 6580 is_freesync_video_mode(&mode, aconnector); 6581 if (recalculate_timing) { 6582 freesync_mode = get_highest_refresh_rate_mode(aconnector, false); 6583 drm_mode_copy(&saved_mode, &mode); 6584 saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio; 6585 drm_mode_copy(&mode, freesync_mode); 6586 mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio; 6587 } else { 6588 decide_crtc_timing_for_drm_display_mode( 6589 &mode, preferred_mode, scale); 6590 6591 preferred_refresh = drm_mode_vrefresh(preferred_mode); 6592 } 6593 } 6594 6595 if (recalculate_timing) 6596 drm_mode_set_crtcinfo(&saved_mode, 0); 6597 6598 /* 6599 * If scaling is enabled and refresh rate didn't change 6600 * we copy the vic and polarities of the old timings 6601 */ 6602 if (!scale || mode_refresh != preferred_refresh) 6603 fill_stream_properties_from_drm_display_mode( 6604 stream, &mode, connector, con_state, NULL, 6605 requested_bpc); 6606 else 6607 fill_stream_properties_from_drm_display_mode( 6608 stream, &mode, connector, con_state, old_stream, 6609 requested_bpc); 6610 6611 /* The rest isn't needed for writeback connectors */ 6612 if (!aconnector) 6613 goto finish; 6614 6615 if (aconnector->timing_changed) { 6616 drm_dbg(aconnector->base.dev, 6617 "overriding timing for automated test, bpc %d, changing to %d\n", 6618 stream->timing.display_color_depth, 6619 aconnector->timing_requested->display_color_depth); 6620 stream->timing = *aconnector->timing_requested; 6621 } 6622 6623 #if defined(CONFIG_DRM_AMD_DC_FP) 6624 /* SST DSC determination policy */ 6625 update_dsc_caps(aconnector, sink, stream, &dsc_caps); 6626 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) 6627 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); 6628 #endif 6629 6630 update_stream_scaling_settings(&mode, dm_state, stream); 6631 6632 fill_audio_info( 6633 &stream->audio_info, 6634 connector, 6635 sink); 6636 6637 update_stream_signal(stream, sink); 6638 6639 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 6640 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); 6641 6642 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 6643 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 6644 stream->signal == SIGNAL_TYPE_EDP) { 6645 // 6646 // should decide stream support vsc sdp colorimetry capability 6647 // before building vsc info packet 6648 // 6649 stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && 6650 stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED; 6651 6652 if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) 6653 tf = TRANSFER_FUNC_GAMMA_22; 6654 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); 6655 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY; 6656 6657 } 6658 finish: 6659 dc_sink_release(sink); 6660 6661 return stream; 6662 } 6663 6664 static enum drm_connector_status 6665 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) 6666 { 6667 bool connected; 6668 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6669 6670 /* 6671 * Notes: 6672 * 1. This interface is NOT called in context of HPD irq. 6673 * 2. This interface *is called* in context of user-mode ioctl. Which 6674 * makes it a bad place for *any* MST-related activity. 6675 */ 6676 6677 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && 6678 !aconnector->fake_enable) 6679 connected = (aconnector->dc_sink != NULL); 6680 else 6681 connected = (aconnector->base.force == DRM_FORCE_ON || 6682 aconnector->base.force == DRM_FORCE_ON_DIGITAL); 6683 6684 update_subconnector_property(aconnector); 6685 6686 return (connected ? connector_status_connected : 6687 connector_status_disconnected); 6688 } 6689 6690 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 6691 struct drm_connector_state *connector_state, 6692 struct drm_property *property, 6693 uint64_t val) 6694 { 6695 struct drm_device *dev = connector->dev; 6696 struct amdgpu_device *adev = drm_to_adev(dev); 6697 struct dm_connector_state *dm_old_state = 6698 to_dm_connector_state(connector->state); 6699 struct dm_connector_state *dm_new_state = 6700 to_dm_connector_state(connector_state); 6701 6702 int ret = -EINVAL; 6703 6704 if (property == dev->mode_config.scaling_mode_property) { 6705 enum amdgpu_rmx_type rmx_type; 6706 6707 switch (val) { 6708 case DRM_MODE_SCALE_CENTER: 6709 rmx_type = RMX_CENTER; 6710 break; 6711 case DRM_MODE_SCALE_ASPECT: 6712 rmx_type = RMX_ASPECT; 6713 break; 6714 case DRM_MODE_SCALE_FULLSCREEN: 6715 rmx_type = RMX_FULL; 6716 break; 6717 case DRM_MODE_SCALE_NONE: 6718 default: 6719 rmx_type = RMX_OFF; 6720 break; 6721 } 6722 6723 if (dm_old_state->scaling == rmx_type) 6724 return 0; 6725 6726 dm_new_state->scaling = rmx_type; 6727 ret = 0; 6728 } else if (property == adev->mode_info.underscan_hborder_property) { 6729 dm_new_state->underscan_hborder = val; 6730 ret = 0; 6731 } else if (property == adev->mode_info.underscan_vborder_property) { 6732 dm_new_state->underscan_vborder = val; 6733 ret = 0; 6734 } else if (property == adev->mode_info.underscan_property) { 6735 dm_new_state->underscan_enable = val; 6736 ret = 0; 6737 } 6738 6739 return ret; 6740 } 6741 6742 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 6743 const struct drm_connector_state *state, 6744 struct drm_property *property, 6745 uint64_t *val) 6746 { 6747 struct drm_device *dev = connector->dev; 6748 struct amdgpu_device *adev = drm_to_adev(dev); 6749 struct dm_connector_state *dm_state = 6750 to_dm_connector_state(state); 6751 int ret = -EINVAL; 6752 6753 if (property == dev->mode_config.scaling_mode_property) { 6754 switch (dm_state->scaling) { 6755 case RMX_CENTER: 6756 *val = DRM_MODE_SCALE_CENTER; 6757 break; 6758 case RMX_ASPECT: 6759 *val = DRM_MODE_SCALE_ASPECT; 6760 break; 6761 case RMX_FULL: 6762 *val = DRM_MODE_SCALE_FULLSCREEN; 6763 break; 6764 case RMX_OFF: 6765 default: 6766 *val = DRM_MODE_SCALE_NONE; 6767 break; 6768 } 6769 ret = 0; 6770 } else if (property == adev->mode_info.underscan_hborder_property) { 6771 *val = dm_state->underscan_hborder; 6772 ret = 0; 6773 } else if (property == adev->mode_info.underscan_vborder_property) { 6774 *val = dm_state->underscan_vborder; 6775 ret = 0; 6776 } else if (property == adev->mode_info.underscan_property) { 6777 *val = dm_state->underscan_enable; 6778 ret = 0; 6779 } 6780 6781 return ret; 6782 } 6783 6784 /** 6785 * DOC: panel power savings 6786 * 6787 * The display manager allows you to set your desired **panel power savings** 6788 * level (between 0-4, with 0 representing off), e.g. using the following:: 6789 * 6790 * # echo 3 > /sys/class/drm/card0-eDP-1/amdgpu/panel_power_savings 6791 * 6792 * Modifying this value can have implications on color accuracy, so tread 6793 * carefully. 6794 */ 6795 6796 static ssize_t panel_power_savings_show(struct device *device, 6797 struct device_attribute *attr, 6798 char *buf) 6799 { 6800 struct drm_connector *connector = dev_get_drvdata(device); 6801 struct drm_device *dev = connector->dev; 6802 u8 val; 6803 6804 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6805 val = to_dm_connector_state(connector->state)->abm_level == 6806 ABM_LEVEL_IMMEDIATE_DISABLE ? 0 : 6807 to_dm_connector_state(connector->state)->abm_level; 6808 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6809 6810 return sysfs_emit(buf, "%u\n", val); 6811 } 6812 6813 static ssize_t panel_power_savings_store(struct device *device, 6814 struct device_attribute *attr, 6815 const char *buf, size_t count) 6816 { 6817 struct drm_connector *connector = dev_get_drvdata(device); 6818 struct drm_device *dev = connector->dev; 6819 long val; 6820 int ret; 6821 6822 ret = kstrtol(buf, 0, &val); 6823 6824 if (ret) 6825 return ret; 6826 6827 if (val < 0 || val > 4) 6828 return -EINVAL; 6829 6830 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 6831 to_dm_connector_state(connector->state)->abm_level = val ?: 6832 ABM_LEVEL_IMMEDIATE_DISABLE; 6833 drm_modeset_unlock(&dev->mode_config.connection_mutex); 6834 6835 drm_kms_helper_hotplug_event(dev); 6836 6837 return count; 6838 } 6839 6840 static DEVICE_ATTR_RW(panel_power_savings); 6841 6842 static struct attribute *amdgpu_attrs[] = { 6843 &dev_attr_panel_power_savings.attr, 6844 NULL 6845 }; 6846 6847 static const struct attribute_group amdgpu_group = { 6848 .name = "amdgpu", 6849 .attrs = amdgpu_attrs 6850 }; 6851 6852 static bool 6853 amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) 6854 { 6855 if (amdgpu_dm_abm_level >= 0) 6856 return false; 6857 6858 if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 6859 return false; 6860 6861 /* check for OLED panels */ 6862 if (amdgpu_dm_connector->bl_idx >= 0) { 6863 struct drm_device *drm = amdgpu_dm_connector->base.dev; 6864 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm; 6865 struct amdgpu_dm_backlight_caps *caps; 6866 6867 caps = &dm->backlight_caps[amdgpu_dm_connector->bl_idx]; 6868 if (caps->aux_support) 6869 return false; 6870 } 6871 6872 return true; 6873 } 6874 6875 static void amdgpu_dm_connector_unregister(struct drm_connector *connector) 6876 { 6877 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); 6878 6879 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) 6880 sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); 6881 6882 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); 6883 } 6884 6885 static void amdgpu_dm_connector_destroy(struct drm_connector *connector) 6886 { 6887 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 6888 struct amdgpu_device *adev = drm_to_adev(connector->dev); 6889 struct amdgpu_display_manager *dm = &adev->dm; 6890 6891 /* 6892 * Call only if mst_mgr was initialized before since it's not done 6893 * for all connector types. 6894 */ 6895 if (aconnector->mst_mgr.dev) 6896 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 6897 6898 if (aconnector->bl_idx != -1) { 6899 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 6900 dm->backlight_dev[aconnector->bl_idx] = NULL; 6901 } 6902 6903 if (aconnector->dc_em_sink) 6904 dc_sink_release(aconnector->dc_em_sink); 6905 aconnector->dc_em_sink = NULL; 6906 if (aconnector->dc_sink) 6907 dc_sink_release(aconnector->dc_sink); 6908 aconnector->dc_sink = NULL; 6909 6910 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); 6911 drm_connector_unregister(connector); 6912 drm_connector_cleanup(connector); 6913 if (aconnector->i2c) { 6914 i2c_del_adapter(&aconnector->i2c->base); 6915 kfree(aconnector->i2c); 6916 } 6917 kfree(aconnector->dm_dp_aux.aux.name); 6918 6919 kfree(connector); 6920 } 6921 6922 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) 6923 { 6924 struct dm_connector_state *state = 6925 to_dm_connector_state(connector->state); 6926 6927 if (connector->state) 6928 __drm_atomic_helper_connector_destroy_state(connector->state); 6929 6930 kfree(state); 6931 6932 state = kzalloc(sizeof(*state), GFP_KERNEL); 6933 6934 if (state) { 6935 state->scaling = RMX_OFF; 6936 state->underscan_enable = false; 6937 state->underscan_hborder = 0; 6938 state->underscan_vborder = 0; 6939 state->base.max_requested_bpc = 8; 6940 state->vcpi_slots = 0; 6941 state->pbn = 0; 6942 6943 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 6944 if (amdgpu_dm_abm_level <= 0) 6945 state->abm_level = ABM_LEVEL_IMMEDIATE_DISABLE; 6946 else 6947 state->abm_level = amdgpu_dm_abm_level; 6948 } 6949 6950 __drm_atomic_helper_connector_reset(connector, &state->base); 6951 } 6952 } 6953 6954 struct drm_connector_state * 6955 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) 6956 { 6957 struct dm_connector_state *state = 6958 to_dm_connector_state(connector->state); 6959 6960 struct dm_connector_state *new_state = 6961 kmemdup(state, sizeof(*state), GFP_KERNEL); 6962 6963 if (!new_state) 6964 return NULL; 6965 6966 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 6967 6968 new_state->freesync_capable = state->freesync_capable; 6969 new_state->abm_level = state->abm_level; 6970 new_state->scaling = state->scaling; 6971 new_state->underscan_enable = state->underscan_enable; 6972 new_state->underscan_hborder = state->underscan_hborder; 6973 new_state->underscan_vborder = state->underscan_vborder; 6974 new_state->vcpi_slots = state->vcpi_slots; 6975 new_state->pbn = state->pbn; 6976 return &new_state->base; 6977 } 6978 6979 static int 6980 amdgpu_dm_connector_late_register(struct drm_connector *connector) 6981 { 6982 struct amdgpu_dm_connector *amdgpu_dm_connector = 6983 to_amdgpu_dm_connector(connector); 6984 int r; 6985 6986 if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) { 6987 r = sysfs_create_group(&connector->kdev->kobj, 6988 &amdgpu_group); 6989 if (r) 6990 return r; 6991 } 6992 6993 amdgpu_dm_register_backlight_device(amdgpu_dm_connector); 6994 6995 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 6996 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 6997 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; 6998 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); 6999 if (r) 7000 return r; 7001 } 7002 7003 #if defined(CONFIG_DEBUG_FS) 7004 connector_debugfs_init(amdgpu_dm_connector); 7005 #endif 7006 7007 return 0; 7008 } 7009 7010 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) 7011 { 7012 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7013 struct dc_link *dc_link = aconnector->dc_link; 7014 struct dc_sink *dc_em_sink = aconnector->dc_em_sink; 7015 struct edid *edid; 7016 struct i2c_adapter *ddc; 7017 7018 if (dc_link && dc_link->aux_mode) 7019 ddc = &aconnector->dm_dp_aux.aux.ddc; 7020 else 7021 ddc = &aconnector->i2c->base; 7022 7023 /* 7024 * Note: drm_get_edid gets edid in the following order: 7025 * 1) override EDID if set via edid_override debugfs, 7026 * 2) firmware EDID if set via edid_firmware module parameter 7027 * 3) regular DDC read. 7028 */ 7029 edid = drm_get_edid(connector, ddc); 7030 if (!edid) { 7031 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 7032 return; 7033 } 7034 7035 aconnector->edid = edid; 7036 7037 /* Update emulated (virtual) sink's EDID */ 7038 if (dc_em_sink && dc_link) { 7039 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); 7040 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH); 7041 dm_helpers_parse_edid_caps( 7042 dc_link, 7043 &dc_em_sink->dc_edid, 7044 &dc_em_sink->edid_caps); 7045 } 7046 } 7047 7048 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { 7049 .reset = amdgpu_dm_connector_funcs_reset, 7050 .detect = amdgpu_dm_connector_detect, 7051 .fill_modes = drm_helper_probe_single_connector_modes, 7052 .destroy = amdgpu_dm_connector_destroy, 7053 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, 7054 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 7055 .atomic_set_property = amdgpu_dm_connector_atomic_set_property, 7056 .atomic_get_property = amdgpu_dm_connector_atomic_get_property, 7057 .late_register = amdgpu_dm_connector_late_register, 7058 .early_unregister = amdgpu_dm_connector_unregister, 7059 .force = amdgpu_dm_connector_funcs_force 7060 }; 7061 7062 static int get_modes(struct drm_connector *connector) 7063 { 7064 return amdgpu_dm_connector_get_modes(connector); 7065 } 7066 7067 static void create_eml_sink(struct amdgpu_dm_connector *aconnector) 7068 { 7069 struct drm_connector *connector = &aconnector->base; 7070 struct dc_link *dc_link = aconnector->dc_link; 7071 struct dc_sink_init_data init_params = { 7072 .link = aconnector->dc_link, 7073 .sink_signal = SIGNAL_TYPE_VIRTUAL 7074 }; 7075 struct edid *edid; 7076 struct i2c_adapter *ddc; 7077 7078 if (dc_link->aux_mode) 7079 ddc = &aconnector->dm_dp_aux.aux.ddc; 7080 else 7081 ddc = &aconnector->i2c->base; 7082 7083 /* 7084 * Note: drm_get_edid gets edid in the following order: 7085 * 1) override EDID if set via edid_override debugfs, 7086 * 2) firmware EDID if set via edid_firmware module parameter 7087 * 3) regular DDC read. 7088 */ 7089 edid = drm_get_edid(connector, ddc); 7090 if (!edid) { 7091 DRM_ERROR("No EDID found on connector: %s.\n", connector->name); 7092 return; 7093 } 7094 7095 if (drm_detect_hdmi_monitor(edid)) 7096 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 7097 7098 aconnector->edid = edid; 7099 7100 aconnector->dc_em_sink = dc_link_add_remote_sink( 7101 aconnector->dc_link, 7102 (uint8_t *)edid, 7103 (edid->extensions + 1) * EDID_LENGTH, 7104 &init_params); 7105 7106 if (aconnector->base.force == DRM_FORCE_ON) { 7107 aconnector->dc_sink = aconnector->dc_link->local_sink ? 7108 aconnector->dc_link->local_sink : 7109 aconnector->dc_em_sink; 7110 if (aconnector->dc_sink) 7111 dc_sink_retain(aconnector->dc_sink); 7112 } 7113 } 7114 7115 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) 7116 { 7117 struct dc_link *link = (struct dc_link *)aconnector->dc_link; 7118 7119 /* 7120 * In case of headless boot with force on for DP managed connector 7121 * Those settings have to be != 0 to get initial modeset 7122 */ 7123 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { 7124 link->verified_link_cap.lane_count = LANE_COUNT_FOUR; 7125 link->verified_link_cap.link_rate = LINK_RATE_HIGH2; 7126 } 7127 7128 create_eml_sink(aconnector); 7129 } 7130 7131 static enum dc_status dm_validate_stream_and_context(struct dc *dc, 7132 struct dc_stream_state *stream) 7133 { 7134 enum dc_status dc_result = DC_ERROR_UNEXPECTED; 7135 struct dc_plane_state *dc_plane_state = NULL; 7136 struct dc_state *dc_state = NULL; 7137 7138 if (!stream) 7139 goto cleanup; 7140 7141 dc_plane_state = dc_create_plane_state(dc); 7142 if (!dc_plane_state) 7143 goto cleanup; 7144 7145 dc_state = dc_state_create(dc, NULL); 7146 if (!dc_state) 7147 goto cleanup; 7148 7149 /* populate stream to plane */ 7150 dc_plane_state->src_rect.height = stream->src.height; 7151 dc_plane_state->src_rect.width = stream->src.width; 7152 dc_plane_state->dst_rect.height = stream->src.height; 7153 dc_plane_state->dst_rect.width = stream->src.width; 7154 dc_plane_state->clip_rect.height = stream->src.height; 7155 dc_plane_state->clip_rect.width = stream->src.width; 7156 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256; 7157 dc_plane_state->plane_size.surface_size.height = stream->src.height; 7158 dc_plane_state->plane_size.surface_size.width = stream->src.width; 7159 dc_plane_state->plane_size.chroma_size.height = stream->src.height; 7160 dc_plane_state->plane_size.chroma_size.width = stream->src.width; 7161 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 7162 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; 7163 dc_plane_state->rotation = ROTATION_ANGLE_0; 7164 dc_plane_state->is_tiling_rotated = false; 7165 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL; 7166 7167 dc_result = dc_validate_stream(dc, stream); 7168 if (dc_result == DC_OK) 7169 dc_result = dc_validate_plane(dc, dc_plane_state); 7170 7171 if (dc_result == DC_OK) 7172 dc_result = dc_state_add_stream(dc, dc_state, stream); 7173 7174 if (dc_result == DC_OK && !dc_state_add_plane( 7175 dc, 7176 stream, 7177 dc_plane_state, 7178 dc_state)) 7179 dc_result = DC_FAIL_ATTACH_SURFACES; 7180 7181 if (dc_result == DC_OK) 7182 dc_result = dc_validate_global_state(dc, dc_state, true); 7183 7184 cleanup: 7185 if (dc_state) 7186 dc_state_release(dc_state); 7187 7188 if (dc_plane_state) 7189 dc_plane_state_release(dc_plane_state); 7190 7191 return dc_result; 7192 } 7193 7194 struct dc_stream_state * 7195 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, 7196 const struct drm_display_mode *drm_mode, 7197 const struct dm_connector_state *dm_state, 7198 const struct dc_stream_state *old_stream) 7199 { 7200 struct drm_connector *connector = &aconnector->base; 7201 struct amdgpu_device *adev = drm_to_adev(connector->dev); 7202 struct dc_stream_state *stream; 7203 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL; 7204 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8; 7205 enum dc_status dc_result = DC_OK; 7206 7207 if (!dm_state) 7208 return NULL; 7209 7210 do { 7211 stream = create_stream_for_sink(connector, drm_mode, 7212 dm_state, old_stream, 7213 requested_bpc); 7214 if (stream == NULL) { 7215 DRM_ERROR("Failed to create stream for sink!\n"); 7216 break; 7217 } 7218 7219 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7220 return stream; 7221 7222 dc_result = dc_validate_stream(adev->dm.dc, stream); 7223 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 7224 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); 7225 7226 if (dc_result == DC_OK) 7227 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); 7228 7229 if (dc_result != DC_OK) { 7230 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n", 7231 drm_mode->hdisplay, 7232 drm_mode->vdisplay, 7233 drm_mode->clock, 7234 dc_result, 7235 dc_status_to_str(dc_result)); 7236 7237 dc_stream_release(stream); 7238 stream = NULL; 7239 requested_bpc -= 2; /* lower bpc to retry validation */ 7240 } 7241 7242 } while (stream == NULL && requested_bpc >= 6); 7243 7244 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) { 7245 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n"); 7246 7247 aconnector->force_yuv420_output = true; 7248 stream = create_validate_stream_for_sink(aconnector, drm_mode, 7249 dm_state, old_stream); 7250 aconnector->force_yuv420_output = false; 7251 } 7252 7253 return stream; 7254 } 7255 7256 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 7257 struct drm_display_mode *mode) 7258 { 7259 int result = MODE_ERROR; 7260 struct dc_sink *dc_sink; 7261 /* TODO: Unhardcode stream count */ 7262 struct dc_stream_state *stream; 7263 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7264 7265 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || 7266 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) 7267 return result; 7268 7269 /* 7270 * Only run this the first time mode_valid is called to initilialize 7271 * EDID mgmt 7272 */ 7273 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && 7274 !aconnector->dc_em_sink) 7275 handle_edid_mgmt(aconnector); 7276 7277 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; 7278 7279 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL && 7280 aconnector->base.force != DRM_FORCE_ON) { 7281 DRM_ERROR("dc_sink is NULL!\n"); 7282 goto fail; 7283 } 7284 7285 drm_mode_set_crtcinfo(mode, 0); 7286 7287 stream = create_validate_stream_for_sink(aconnector, mode, 7288 to_dm_connector_state(connector->state), 7289 NULL); 7290 if (stream) { 7291 dc_stream_release(stream); 7292 result = MODE_OK; 7293 } 7294 7295 fail: 7296 /* TODO: error handling*/ 7297 return result; 7298 } 7299 7300 static int fill_hdr_info_packet(const struct drm_connector_state *state, 7301 struct dc_info_packet *out) 7302 { 7303 struct hdmi_drm_infoframe frame; 7304 unsigned char buf[30]; /* 26 + 4 */ 7305 ssize_t len; 7306 int ret, i; 7307 7308 memset(out, 0, sizeof(*out)); 7309 7310 if (!state->hdr_output_metadata) 7311 return 0; 7312 7313 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); 7314 if (ret) 7315 return ret; 7316 7317 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); 7318 if (len < 0) 7319 return (int)len; 7320 7321 /* Static metadata is a fixed 26 bytes + 4 byte header. */ 7322 if (len != 30) 7323 return -EINVAL; 7324 7325 /* Prepare the infopacket for DC. */ 7326 switch (state->connector->connector_type) { 7327 case DRM_MODE_CONNECTOR_HDMIA: 7328 out->hb0 = 0x87; /* type */ 7329 out->hb1 = 0x01; /* version */ 7330 out->hb2 = 0x1A; /* length */ 7331 out->sb[0] = buf[3]; /* checksum */ 7332 i = 1; 7333 break; 7334 7335 case DRM_MODE_CONNECTOR_DisplayPort: 7336 case DRM_MODE_CONNECTOR_eDP: 7337 out->hb0 = 0x00; /* sdp id, zero */ 7338 out->hb1 = 0x87; /* type */ 7339 out->hb2 = 0x1D; /* payload len - 1 */ 7340 out->hb3 = (0x13 << 2); /* sdp version */ 7341 out->sb[0] = 0x01; /* version */ 7342 out->sb[1] = 0x1A; /* length */ 7343 i = 2; 7344 break; 7345 7346 default: 7347 return -EINVAL; 7348 } 7349 7350 memcpy(&out->sb[i], &buf[4], 26); 7351 out->valid = true; 7352 7353 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, 7354 sizeof(out->sb), false); 7355 7356 return 0; 7357 } 7358 7359 static int 7360 amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 7361 struct drm_atomic_state *state) 7362 { 7363 struct drm_connector_state *new_con_state = 7364 drm_atomic_get_new_connector_state(state, conn); 7365 struct drm_connector_state *old_con_state = 7366 drm_atomic_get_old_connector_state(state, conn); 7367 struct drm_crtc *crtc = new_con_state->crtc; 7368 struct drm_crtc_state *new_crtc_state; 7369 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); 7370 int ret; 7371 7372 trace_amdgpu_dm_connector_atomic_check(new_con_state); 7373 7374 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 7375 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); 7376 if (ret < 0) 7377 return ret; 7378 } 7379 7380 if (!crtc) 7381 return 0; 7382 7383 if (new_con_state->colorspace != old_con_state->colorspace) { 7384 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7385 if (IS_ERR(new_crtc_state)) 7386 return PTR_ERR(new_crtc_state); 7387 7388 new_crtc_state->mode_changed = true; 7389 } 7390 7391 if (new_con_state->content_type != old_con_state->content_type) { 7392 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7393 if (IS_ERR(new_crtc_state)) 7394 return PTR_ERR(new_crtc_state); 7395 7396 new_crtc_state->mode_changed = true; 7397 } 7398 7399 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { 7400 struct dc_info_packet hdr_infopacket; 7401 7402 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); 7403 if (ret) 7404 return ret; 7405 7406 new_crtc_state = drm_atomic_get_crtc_state(state, crtc); 7407 if (IS_ERR(new_crtc_state)) 7408 return PTR_ERR(new_crtc_state); 7409 7410 /* 7411 * DC considers the stream backends changed if the 7412 * static metadata changes. Forcing the modeset also 7413 * gives a simple way for userspace to switch from 7414 * 8bpc to 10bpc when setting the metadata to enter 7415 * or exit HDR. 7416 * 7417 * Changing the static metadata after it's been 7418 * set is permissible, however. So only force a 7419 * modeset if we're entering or exiting HDR. 7420 */ 7421 new_crtc_state->mode_changed = new_crtc_state->mode_changed || 7422 !old_con_state->hdr_output_metadata || 7423 !new_con_state->hdr_output_metadata; 7424 } 7425 7426 return 0; 7427 } 7428 7429 static const struct drm_connector_helper_funcs 7430 amdgpu_dm_connector_helper_funcs = { 7431 /* 7432 * If hotplugging a second bigger display in FB Con mode, bigger resolution 7433 * modes will be filtered by drm_mode_validate_size(), and those modes 7434 * are missing after user start lightdm. So we need to renew modes list. 7435 * in get_modes call back, not just return the modes count 7436 */ 7437 .get_modes = get_modes, 7438 .mode_valid = amdgpu_dm_connector_mode_valid, 7439 .atomic_check = amdgpu_dm_connector_atomic_check, 7440 }; 7441 7442 static void dm_encoder_helper_disable(struct drm_encoder *encoder) 7443 { 7444 7445 } 7446 7447 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) 7448 { 7449 switch (display_color_depth) { 7450 case COLOR_DEPTH_666: 7451 return 6; 7452 case COLOR_DEPTH_888: 7453 return 8; 7454 case COLOR_DEPTH_101010: 7455 return 10; 7456 case COLOR_DEPTH_121212: 7457 return 12; 7458 case COLOR_DEPTH_141414: 7459 return 14; 7460 case COLOR_DEPTH_161616: 7461 return 16; 7462 default: 7463 break; 7464 } 7465 return 0; 7466 } 7467 7468 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 7469 struct drm_crtc_state *crtc_state, 7470 struct drm_connector_state *conn_state) 7471 { 7472 struct drm_atomic_state *state = crtc_state->state; 7473 struct drm_connector *connector = conn_state->connector; 7474 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 7475 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); 7476 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 7477 struct drm_dp_mst_topology_mgr *mst_mgr; 7478 struct drm_dp_mst_port *mst_port; 7479 struct drm_dp_mst_topology_state *mst_state; 7480 enum dc_color_depth color_depth; 7481 int clock, bpp = 0; 7482 bool is_y420 = false; 7483 7484 if (!aconnector->mst_output_port) 7485 return 0; 7486 7487 mst_port = aconnector->mst_output_port; 7488 mst_mgr = &aconnector->mst_root->mst_mgr; 7489 7490 if (!crtc_state->connectors_changed && !crtc_state->mode_changed) 7491 return 0; 7492 7493 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); 7494 if (IS_ERR(mst_state)) 7495 return PTR_ERR(mst_state); 7496 7497 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); 7498 7499 if (!state->duplicated) { 7500 int max_bpc = conn_state->max_requested_bpc; 7501 7502 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) && 7503 aconnector->force_yuv420_output; 7504 color_depth = convert_color_depth_from_display_info(connector, 7505 is_y420, 7506 max_bpc); 7507 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; 7508 clock = adjusted_mode->clock; 7509 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); 7510 } 7511 7512 dm_new_connector_state->vcpi_slots = 7513 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, 7514 dm_new_connector_state->pbn); 7515 if (dm_new_connector_state->vcpi_slots < 0) { 7516 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); 7517 return dm_new_connector_state->vcpi_slots; 7518 } 7519 return 0; 7520 } 7521 7522 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { 7523 .disable = dm_encoder_helper_disable, 7524 .atomic_check = dm_encoder_helper_atomic_check 7525 }; 7526 7527 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, 7528 struct dc_state *dc_state, 7529 struct dsc_mst_fairness_vars *vars) 7530 { 7531 struct dc_stream_state *stream = NULL; 7532 struct drm_connector *connector; 7533 struct drm_connector_state *new_con_state; 7534 struct amdgpu_dm_connector *aconnector; 7535 struct dm_connector_state *dm_conn_state; 7536 int i, j, ret; 7537 int vcpi, pbn_div, pbn = 0, slot_num = 0; 7538 7539 for_each_new_connector_in_state(state, connector, new_con_state, i) { 7540 7541 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 7542 continue; 7543 7544 aconnector = to_amdgpu_dm_connector(connector); 7545 7546 if (!aconnector->mst_output_port) 7547 continue; 7548 7549 if (!new_con_state || !new_con_state->crtc) 7550 continue; 7551 7552 dm_conn_state = to_dm_connector_state(new_con_state); 7553 7554 for (j = 0; j < dc_state->stream_count; j++) { 7555 stream = dc_state->streams[j]; 7556 if (!stream) 7557 continue; 7558 7559 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 7560 break; 7561 7562 stream = NULL; 7563 } 7564 7565 if (!stream) 7566 continue; 7567 7568 pbn_div = dm_mst_get_pbn_divider(stream->link); 7569 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 7570 for (j = 0; j < dc_state->stream_count; j++) { 7571 if (vars[j].aconnector == aconnector) { 7572 pbn = vars[j].pbn; 7573 break; 7574 } 7575 } 7576 7577 if (j == dc_state->stream_count || pbn_div == 0) 7578 continue; 7579 7580 slot_num = DIV_ROUND_UP(pbn, pbn_div); 7581 7582 if (stream->timing.flags.DSC != 1) { 7583 dm_conn_state->pbn = pbn; 7584 dm_conn_state->vcpi_slots = slot_num; 7585 7586 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 7587 dm_conn_state->pbn, false); 7588 if (ret < 0) 7589 return ret; 7590 7591 continue; 7592 } 7593 7594 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 7595 if (vcpi < 0) 7596 return vcpi; 7597 7598 dm_conn_state->pbn = pbn; 7599 dm_conn_state->vcpi_slots = vcpi; 7600 } 7601 return 0; 7602 } 7603 7604 static int to_drm_connector_type(enum signal_type st) 7605 { 7606 switch (st) { 7607 case SIGNAL_TYPE_HDMI_TYPE_A: 7608 return DRM_MODE_CONNECTOR_HDMIA; 7609 case SIGNAL_TYPE_EDP: 7610 return DRM_MODE_CONNECTOR_eDP; 7611 case SIGNAL_TYPE_LVDS: 7612 return DRM_MODE_CONNECTOR_LVDS; 7613 case SIGNAL_TYPE_RGB: 7614 return DRM_MODE_CONNECTOR_VGA; 7615 case SIGNAL_TYPE_DISPLAY_PORT: 7616 case SIGNAL_TYPE_DISPLAY_PORT_MST: 7617 return DRM_MODE_CONNECTOR_DisplayPort; 7618 case SIGNAL_TYPE_DVI_DUAL_LINK: 7619 case SIGNAL_TYPE_DVI_SINGLE_LINK: 7620 return DRM_MODE_CONNECTOR_DVID; 7621 case SIGNAL_TYPE_VIRTUAL: 7622 return DRM_MODE_CONNECTOR_VIRTUAL; 7623 7624 default: 7625 return DRM_MODE_CONNECTOR_Unknown; 7626 } 7627 } 7628 7629 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) 7630 { 7631 struct drm_encoder *encoder; 7632 7633 /* There is only one encoder per connector */ 7634 drm_connector_for_each_possible_encoder(connector, encoder) 7635 return encoder; 7636 7637 return NULL; 7638 } 7639 7640 static void amdgpu_dm_get_native_mode(struct drm_connector *connector) 7641 { 7642 struct drm_encoder *encoder; 7643 struct amdgpu_encoder *amdgpu_encoder; 7644 7645 encoder = amdgpu_dm_connector_to_encoder(connector); 7646 7647 if (encoder == NULL) 7648 return; 7649 7650 amdgpu_encoder = to_amdgpu_encoder(encoder); 7651 7652 amdgpu_encoder->native_mode.clock = 0; 7653 7654 if (!list_empty(&connector->probed_modes)) { 7655 struct drm_display_mode *preferred_mode = NULL; 7656 7657 list_for_each_entry(preferred_mode, 7658 &connector->probed_modes, 7659 head) { 7660 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) 7661 amdgpu_encoder->native_mode = *preferred_mode; 7662 7663 break; 7664 } 7665 7666 } 7667 } 7668 7669 static struct drm_display_mode * 7670 amdgpu_dm_create_common_mode(struct drm_encoder *encoder, 7671 char *name, 7672 int hdisplay, int vdisplay) 7673 { 7674 struct drm_device *dev = encoder->dev; 7675 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7676 struct drm_display_mode *mode = NULL; 7677 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7678 7679 mode = drm_mode_duplicate(dev, native_mode); 7680 7681 if (mode == NULL) 7682 return NULL; 7683 7684 mode->hdisplay = hdisplay; 7685 mode->vdisplay = vdisplay; 7686 mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7687 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); 7688 7689 return mode; 7690 7691 } 7692 7693 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, 7694 struct drm_connector *connector) 7695 { 7696 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 7697 struct drm_display_mode *mode = NULL; 7698 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 7699 struct amdgpu_dm_connector *amdgpu_dm_connector = 7700 to_amdgpu_dm_connector(connector); 7701 int i; 7702 int n; 7703 struct mode_size { 7704 char name[DRM_DISPLAY_MODE_LEN]; 7705 int w; 7706 int h; 7707 } common_modes[] = { 7708 { "640x480", 640, 480}, 7709 { "800x600", 800, 600}, 7710 { "1024x768", 1024, 768}, 7711 { "1280x720", 1280, 720}, 7712 { "1280x800", 1280, 800}, 7713 {"1280x1024", 1280, 1024}, 7714 { "1440x900", 1440, 900}, 7715 {"1680x1050", 1680, 1050}, 7716 {"1600x1200", 1600, 1200}, 7717 {"1920x1080", 1920, 1080}, 7718 {"1920x1200", 1920, 1200} 7719 }; 7720 7721 n = ARRAY_SIZE(common_modes); 7722 7723 for (i = 0; i < n; i++) { 7724 struct drm_display_mode *curmode = NULL; 7725 bool mode_existed = false; 7726 7727 if (common_modes[i].w > native_mode->hdisplay || 7728 common_modes[i].h > native_mode->vdisplay || 7729 (common_modes[i].w == native_mode->hdisplay && 7730 common_modes[i].h == native_mode->vdisplay)) 7731 continue; 7732 7733 list_for_each_entry(curmode, &connector->probed_modes, head) { 7734 if (common_modes[i].w == curmode->hdisplay && 7735 common_modes[i].h == curmode->vdisplay) { 7736 mode_existed = true; 7737 break; 7738 } 7739 } 7740 7741 if (mode_existed) 7742 continue; 7743 7744 mode = amdgpu_dm_create_common_mode(encoder, 7745 common_modes[i].name, common_modes[i].w, 7746 common_modes[i].h); 7747 if (!mode) 7748 continue; 7749 7750 drm_mode_probed_add(connector, mode); 7751 amdgpu_dm_connector->num_modes++; 7752 } 7753 } 7754 7755 static void amdgpu_set_panel_orientation(struct drm_connector *connector) 7756 { 7757 struct drm_encoder *encoder; 7758 struct amdgpu_encoder *amdgpu_encoder; 7759 const struct drm_display_mode *native_mode; 7760 7761 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP && 7762 connector->connector_type != DRM_MODE_CONNECTOR_LVDS) 7763 return; 7764 7765 mutex_lock(&connector->dev->mode_config.mutex); 7766 amdgpu_dm_connector_get_modes(connector); 7767 mutex_unlock(&connector->dev->mode_config.mutex); 7768 7769 encoder = amdgpu_dm_connector_to_encoder(connector); 7770 if (!encoder) 7771 return; 7772 7773 amdgpu_encoder = to_amdgpu_encoder(encoder); 7774 7775 native_mode = &amdgpu_encoder->native_mode; 7776 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0) 7777 return; 7778 7779 drm_connector_set_panel_orientation_with_quirk(connector, 7780 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 7781 native_mode->hdisplay, 7782 native_mode->vdisplay); 7783 } 7784 7785 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, 7786 struct edid *edid) 7787 { 7788 struct amdgpu_dm_connector *amdgpu_dm_connector = 7789 to_amdgpu_dm_connector(connector); 7790 7791 if (edid) { 7792 /* empty probed_modes */ 7793 INIT_LIST_HEAD(&connector->probed_modes); 7794 amdgpu_dm_connector->num_modes = 7795 drm_add_edid_modes(connector, edid); 7796 7797 /* sorting the probed modes before calling function 7798 * amdgpu_dm_get_native_mode() since EDID can have 7799 * more than one preferred mode. The modes that are 7800 * later in the probed mode list could be of higher 7801 * and preferred resolution. For example, 3840x2160 7802 * resolution in base EDID preferred timing and 4096x2160 7803 * preferred resolution in DID extension block later. 7804 */ 7805 drm_mode_sort(&connector->probed_modes); 7806 amdgpu_dm_get_native_mode(connector); 7807 7808 /* Freesync capabilities are reset by calling 7809 * drm_add_edid_modes() and need to be 7810 * restored here. 7811 */ 7812 amdgpu_dm_update_freesync_caps(connector, edid); 7813 } else { 7814 amdgpu_dm_connector->num_modes = 0; 7815 } 7816 } 7817 7818 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector, 7819 struct drm_display_mode *mode) 7820 { 7821 struct drm_display_mode *m; 7822 7823 list_for_each_entry(m, &aconnector->base.probed_modes, head) { 7824 if (drm_mode_equal(m, mode)) 7825 return true; 7826 } 7827 7828 return false; 7829 } 7830 7831 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) 7832 { 7833 const struct drm_display_mode *m; 7834 struct drm_display_mode *new_mode; 7835 uint i; 7836 u32 new_modes_count = 0; 7837 7838 /* Standard FPS values 7839 * 7840 * 23.976 - TV/NTSC 7841 * 24 - Cinema 7842 * 25 - TV/PAL 7843 * 29.97 - TV/NTSC 7844 * 30 - TV/NTSC 7845 * 48 - Cinema HFR 7846 * 50 - TV/PAL 7847 * 60 - Commonly used 7848 * 48,72,96,120 - Multiples of 24 7849 */ 7850 static const u32 common_rates[] = { 7851 23976, 24000, 25000, 29970, 30000, 7852 48000, 50000, 60000, 72000, 96000, 120000 7853 }; 7854 7855 /* 7856 * Find mode with highest refresh rate with the same resolution 7857 * as the preferred mode. Some monitors report a preferred mode 7858 * with lower resolution than the highest refresh rate supported. 7859 */ 7860 7861 m = get_highest_refresh_rate_mode(aconnector, true); 7862 if (!m) 7863 return 0; 7864 7865 for (i = 0; i < ARRAY_SIZE(common_rates); i++) { 7866 u64 target_vtotal, target_vtotal_diff; 7867 u64 num, den; 7868 7869 if (drm_mode_vrefresh(m) * 1000 < common_rates[i]) 7870 continue; 7871 7872 if (common_rates[i] < aconnector->min_vfreq * 1000 || 7873 common_rates[i] > aconnector->max_vfreq * 1000) 7874 continue; 7875 7876 num = (unsigned long long)m->clock * 1000 * 1000; 7877 den = common_rates[i] * (unsigned long long)m->htotal; 7878 target_vtotal = div_u64(num, den); 7879 target_vtotal_diff = target_vtotal - m->vtotal; 7880 7881 /* Check for illegal modes */ 7882 if (m->vsync_start + target_vtotal_diff < m->vdisplay || 7883 m->vsync_end + target_vtotal_diff < m->vsync_start || 7884 m->vtotal + target_vtotal_diff < m->vsync_end) 7885 continue; 7886 7887 new_mode = drm_mode_duplicate(aconnector->base.dev, m); 7888 if (!new_mode) 7889 goto out; 7890 7891 new_mode->vtotal += (u16)target_vtotal_diff; 7892 new_mode->vsync_start += (u16)target_vtotal_diff; 7893 new_mode->vsync_end += (u16)target_vtotal_diff; 7894 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 7895 new_mode->type |= DRM_MODE_TYPE_DRIVER; 7896 7897 if (!is_duplicate_mode(aconnector, new_mode)) { 7898 drm_mode_probed_add(&aconnector->base, new_mode); 7899 new_modes_count += 1; 7900 } else 7901 drm_mode_destroy(aconnector->base.dev, new_mode); 7902 } 7903 out: 7904 return new_modes_count; 7905 } 7906 7907 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, 7908 struct edid *edid) 7909 { 7910 struct amdgpu_dm_connector *amdgpu_dm_connector = 7911 to_amdgpu_dm_connector(connector); 7912 7913 if (!(amdgpu_freesync_vid_mode && edid)) 7914 return; 7915 7916 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 7917 amdgpu_dm_connector->num_modes += 7918 add_fs_modes(amdgpu_dm_connector); 7919 } 7920 7921 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) 7922 { 7923 struct amdgpu_dm_connector *amdgpu_dm_connector = 7924 to_amdgpu_dm_connector(connector); 7925 struct drm_encoder *encoder; 7926 struct edid *edid = amdgpu_dm_connector->edid; 7927 struct dc_link_settings *verified_link_cap = 7928 &amdgpu_dm_connector->dc_link->verified_link_cap; 7929 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; 7930 7931 encoder = amdgpu_dm_connector_to_encoder(connector); 7932 7933 if (!drm_edid_is_valid(edid)) { 7934 amdgpu_dm_connector->num_modes = 7935 drm_add_modes_noedid(connector, 640, 480); 7936 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) 7937 amdgpu_dm_connector->num_modes += 7938 drm_add_modes_noedid(connector, 1920, 1080); 7939 } else { 7940 amdgpu_dm_connector_ddc_get_modes(connector, edid); 7941 if (encoder) 7942 amdgpu_dm_connector_add_common_modes(encoder, connector); 7943 amdgpu_dm_connector_add_freesync_modes(connector, edid); 7944 } 7945 amdgpu_dm_fbc_init(connector); 7946 7947 return amdgpu_dm_connector->num_modes; 7948 } 7949 7950 static const u32 supported_colorspaces = 7951 BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | 7952 BIT(DRM_MODE_COLORIMETRY_OPRGB) | 7953 BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | 7954 BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); 7955 7956 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 7957 struct amdgpu_dm_connector *aconnector, 7958 int connector_type, 7959 struct dc_link *link, 7960 int link_index) 7961 { 7962 struct amdgpu_device *adev = drm_to_adev(dm->ddev); 7963 7964 /* 7965 * Some of the properties below require access to state, like bpc. 7966 * Allocate some default initial connector state with our reset helper. 7967 */ 7968 if (aconnector->base.funcs->reset) 7969 aconnector->base.funcs->reset(&aconnector->base); 7970 7971 aconnector->connector_id = link_index; 7972 aconnector->bl_idx = -1; 7973 aconnector->dc_link = link; 7974 aconnector->base.interlace_allowed = false; 7975 aconnector->base.doublescan_allowed = false; 7976 aconnector->base.stereo_allowed = false; 7977 aconnector->base.dpms = DRM_MODE_DPMS_OFF; 7978 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ 7979 aconnector->audio_inst = -1; 7980 aconnector->pack_sdp_v1_3 = false; 7981 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; 7982 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 7983 mutex_init(&aconnector->hpd_lock); 7984 mutex_init(&aconnector->handle_mst_msg_ready); 7985 7986 /* 7987 * configure support HPD hot plug connector_>polled default value is 0 7988 * which means HPD hot plug not supported 7989 */ 7990 switch (connector_type) { 7991 case DRM_MODE_CONNECTOR_HDMIA: 7992 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7993 aconnector->base.ycbcr_420_allowed = 7994 link->link_enc->features.hdmi_ycbcr420_supported ? true : false; 7995 break; 7996 case DRM_MODE_CONNECTOR_DisplayPort: 7997 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 7998 link->link_enc = link_enc_cfg_get_link_enc(link); 7999 ASSERT(link->link_enc); 8000 if (link->link_enc) 8001 aconnector->base.ycbcr_420_allowed = 8002 link->link_enc->features.dp_ycbcr420_supported ? true : false; 8003 break; 8004 case DRM_MODE_CONNECTOR_DVID: 8005 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; 8006 break; 8007 default: 8008 break; 8009 } 8010 8011 drm_object_attach_property(&aconnector->base.base, 8012 dm->ddev->mode_config.scaling_mode_property, 8013 DRM_MODE_SCALE_NONE); 8014 8015 drm_object_attach_property(&aconnector->base.base, 8016 adev->mode_info.underscan_property, 8017 UNDERSCAN_OFF); 8018 drm_object_attach_property(&aconnector->base.base, 8019 adev->mode_info.underscan_hborder_property, 8020 0); 8021 drm_object_attach_property(&aconnector->base.base, 8022 adev->mode_info.underscan_vborder_property, 8023 0); 8024 8025 if (!aconnector->mst_root) 8026 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); 8027 8028 aconnector->base.state->max_bpc = 16; 8029 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc; 8030 8031 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 8032 /* Content Type is currently only implemented for HDMI. */ 8033 drm_connector_attach_content_type_property(&aconnector->base); 8034 } 8035 8036 if (connector_type == DRM_MODE_CONNECTOR_HDMIA) { 8037 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces)) 8038 drm_connector_attach_colorspace_property(&aconnector->base); 8039 } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) || 8040 connector_type == DRM_MODE_CONNECTOR_eDP) { 8041 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces)) 8042 drm_connector_attach_colorspace_property(&aconnector->base); 8043 } 8044 8045 if (connector_type == DRM_MODE_CONNECTOR_HDMIA || 8046 connector_type == DRM_MODE_CONNECTOR_DisplayPort || 8047 connector_type == DRM_MODE_CONNECTOR_eDP) { 8048 drm_connector_attach_hdr_output_metadata_property(&aconnector->base); 8049 8050 if (!aconnector->mst_root) 8051 drm_connector_attach_vrr_capable_property(&aconnector->base); 8052 8053 if (adev->dm.hdcp_workqueue) 8054 drm_connector_attach_content_protection_property(&aconnector->base, true); 8055 } 8056 } 8057 8058 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, 8059 struct i2c_msg *msgs, int num) 8060 { 8061 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); 8062 struct ddc_service *ddc_service = i2c->ddc_service; 8063 struct i2c_command cmd; 8064 int i; 8065 int result = -EIO; 8066 8067 if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported) 8068 return result; 8069 8070 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); 8071 8072 if (!cmd.payloads) 8073 return result; 8074 8075 cmd.number_of_payloads = num; 8076 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 8077 cmd.speed = 100; 8078 8079 for (i = 0; i < num; i++) { 8080 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); 8081 cmd.payloads[i].address = msgs[i].addr; 8082 cmd.payloads[i].length = msgs[i].len; 8083 cmd.payloads[i].data = msgs[i].buf; 8084 } 8085 8086 if (dc_submit_i2c( 8087 ddc_service->ctx->dc, 8088 ddc_service->link->link_index, 8089 &cmd)) 8090 result = num; 8091 8092 kfree(cmd.payloads); 8093 return result; 8094 } 8095 8096 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) 8097 { 8098 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 8099 } 8100 8101 static const struct i2c_algorithm amdgpu_dm_i2c_algo = { 8102 .master_xfer = amdgpu_dm_i2c_xfer, 8103 .functionality = amdgpu_dm_i2c_func, 8104 }; 8105 8106 static struct amdgpu_i2c_adapter * 8107 create_i2c(struct ddc_service *ddc_service, 8108 int link_index, 8109 int *res) 8110 { 8111 struct amdgpu_device *adev = ddc_service->ctx->driver_context; 8112 struct amdgpu_i2c_adapter *i2c; 8113 8114 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); 8115 if (!i2c) 8116 return NULL; 8117 i2c->base.owner = THIS_MODULE; 8118 i2c->base.dev.parent = &adev->pdev->dev; 8119 i2c->base.algo = &amdgpu_dm_i2c_algo; 8120 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); 8121 i2c_set_adapdata(&i2c->base, i2c); 8122 i2c->ddc_service = ddc_service; 8123 8124 return i2c; 8125 } 8126 8127 8128 /* 8129 * Note: this function assumes that dc_link_detect() was called for the 8130 * dc_link which will be represented by this aconnector. 8131 */ 8132 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 8133 struct amdgpu_dm_connector *aconnector, 8134 u32 link_index, 8135 struct amdgpu_encoder *aencoder) 8136 { 8137 int res = 0; 8138 int connector_type; 8139 struct dc *dc = dm->dc; 8140 struct dc_link *link = dc_get_link_at_index(dc, link_index); 8141 struct amdgpu_i2c_adapter *i2c; 8142 8143 /* Not needed for writeback connector */ 8144 link->priv = aconnector; 8145 8146 8147 i2c = create_i2c(link->ddc, link->link_index, &res); 8148 if (!i2c) { 8149 DRM_ERROR("Failed to create i2c adapter data\n"); 8150 return -ENOMEM; 8151 } 8152 8153 aconnector->i2c = i2c; 8154 res = i2c_add_adapter(&i2c->base); 8155 8156 if (res) { 8157 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); 8158 goto out_free; 8159 } 8160 8161 connector_type = to_drm_connector_type(link->connector_signal); 8162 8163 res = drm_connector_init_with_ddc( 8164 dm->ddev, 8165 &aconnector->base, 8166 &amdgpu_dm_connector_funcs, 8167 connector_type, 8168 &i2c->base); 8169 8170 if (res) { 8171 DRM_ERROR("connector_init failed\n"); 8172 aconnector->connector_id = -1; 8173 goto out_free; 8174 } 8175 8176 drm_connector_helper_add( 8177 &aconnector->base, 8178 &amdgpu_dm_connector_helper_funcs); 8179 8180 amdgpu_dm_connector_init_helper( 8181 dm, 8182 aconnector, 8183 connector_type, 8184 link, 8185 link_index); 8186 8187 drm_connector_attach_encoder( 8188 &aconnector->base, &aencoder->base); 8189 8190 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort 8191 || connector_type == DRM_MODE_CONNECTOR_eDP) 8192 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); 8193 8194 out_free: 8195 if (res) { 8196 kfree(i2c); 8197 aconnector->i2c = NULL; 8198 } 8199 return res; 8200 } 8201 8202 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) 8203 { 8204 switch (adev->mode_info.num_crtc) { 8205 case 1: 8206 return 0x1; 8207 case 2: 8208 return 0x3; 8209 case 3: 8210 return 0x7; 8211 case 4: 8212 return 0xf; 8213 case 5: 8214 return 0x1f; 8215 case 6: 8216 default: 8217 return 0x3f; 8218 } 8219 } 8220 8221 static int amdgpu_dm_encoder_init(struct drm_device *dev, 8222 struct amdgpu_encoder *aencoder, 8223 uint32_t link_index) 8224 { 8225 struct amdgpu_device *adev = drm_to_adev(dev); 8226 8227 int res = drm_encoder_init(dev, 8228 &aencoder->base, 8229 &amdgpu_dm_encoder_funcs, 8230 DRM_MODE_ENCODER_TMDS, 8231 NULL); 8232 8233 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); 8234 8235 if (!res) 8236 aencoder->encoder_id = link_index; 8237 else 8238 aencoder->encoder_id = -1; 8239 8240 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); 8241 8242 return res; 8243 } 8244 8245 static void manage_dm_interrupts(struct amdgpu_device *adev, 8246 struct amdgpu_crtc *acrtc, 8247 bool enable) 8248 { 8249 if (enable) 8250 drm_crtc_vblank_on(&acrtc->base); 8251 else 8252 drm_crtc_vblank_off(&acrtc->base); 8253 } 8254 8255 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 8256 struct amdgpu_crtc *acrtc) 8257 { 8258 int irq_type = 8259 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 8260 8261 /** 8262 * This reads the current state for the IRQ and force reapplies 8263 * the setting to hardware. 8264 */ 8265 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 8266 } 8267 8268 static bool 8269 is_scaling_state_different(const struct dm_connector_state *dm_state, 8270 const struct dm_connector_state *old_dm_state) 8271 { 8272 if (dm_state->scaling != old_dm_state->scaling) 8273 return true; 8274 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 8275 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 8276 return true; 8277 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 8278 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 8279 return true; 8280 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 8281 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 8282 return true; 8283 return false; 8284 } 8285 8286 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 8287 struct drm_crtc_state *old_crtc_state, 8288 struct drm_connector_state *new_conn_state, 8289 struct drm_connector_state *old_conn_state, 8290 const struct drm_connector *connector, 8291 struct hdcp_workqueue *hdcp_w) 8292 { 8293 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 8294 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 8295 8296 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 8297 connector->index, connector->status, connector->dpms); 8298 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 8299 old_conn_state->content_protection, new_conn_state->content_protection); 8300 8301 if (old_crtc_state) 8302 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8303 old_crtc_state->enable, 8304 old_crtc_state->active, 8305 old_crtc_state->mode_changed, 8306 old_crtc_state->active_changed, 8307 old_crtc_state->connectors_changed); 8308 8309 if (new_crtc_state) 8310 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 8311 new_crtc_state->enable, 8312 new_crtc_state->active, 8313 new_crtc_state->mode_changed, 8314 new_crtc_state->active_changed, 8315 new_crtc_state->connectors_changed); 8316 8317 /* hdcp content type change */ 8318 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 8319 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 8320 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8321 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 8322 return true; 8323 } 8324 8325 /* CP is being re enabled, ignore this */ 8326 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 8327 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8328 if (new_crtc_state && new_crtc_state->mode_changed) { 8329 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8330 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 8331 return true; 8332 } 8333 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 8334 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 8335 return false; 8336 } 8337 8338 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 8339 * 8340 * Handles: UNDESIRED -> ENABLED 8341 */ 8342 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 8343 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 8344 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 8345 8346 /* Stream removed and re-enabled 8347 * 8348 * Can sometimes overlap with the HPD case, 8349 * thus set update_hdcp to false to avoid 8350 * setting HDCP multiple times. 8351 * 8352 * Handles: DESIRED -> DESIRED (Special case) 8353 */ 8354 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 8355 new_conn_state->crtc && new_conn_state->crtc->enabled && 8356 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8357 dm_con_state->update_hdcp = false; 8358 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 8359 __func__); 8360 return true; 8361 } 8362 8363 /* Hot-plug, headless s3, dpms 8364 * 8365 * Only start HDCP if the display is connected/enabled. 8366 * update_hdcp flag will be set to false until the next 8367 * HPD comes in. 8368 * 8369 * Handles: DESIRED -> DESIRED (Special case) 8370 */ 8371 if (dm_con_state->update_hdcp && 8372 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 8373 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 8374 dm_con_state->update_hdcp = false; 8375 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 8376 __func__); 8377 return true; 8378 } 8379 8380 if (old_conn_state->content_protection == new_conn_state->content_protection) { 8381 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 8382 if (new_crtc_state && new_crtc_state->mode_changed) { 8383 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 8384 __func__); 8385 return true; 8386 } 8387 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 8388 __func__); 8389 return false; 8390 } 8391 8392 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 8393 return false; 8394 } 8395 8396 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 8397 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 8398 __func__); 8399 return true; 8400 } 8401 8402 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 8403 return false; 8404 } 8405 8406 static void remove_stream(struct amdgpu_device *adev, 8407 struct amdgpu_crtc *acrtc, 8408 struct dc_stream_state *stream) 8409 { 8410 /* this is the update mode case */ 8411 8412 acrtc->otg_inst = -1; 8413 acrtc->enabled = false; 8414 } 8415 8416 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 8417 { 8418 8419 assert_spin_locked(&acrtc->base.dev->event_lock); 8420 WARN_ON(acrtc->event); 8421 8422 acrtc->event = acrtc->base.state->event; 8423 8424 /* Set the flip status */ 8425 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 8426 8427 /* Mark this event as consumed */ 8428 acrtc->base.state->event = NULL; 8429 8430 drm_dbg_state(acrtc->base.dev, 8431 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 8432 acrtc->crtc_id); 8433 } 8434 8435 static void update_freesync_state_on_stream( 8436 struct amdgpu_display_manager *dm, 8437 struct dm_crtc_state *new_crtc_state, 8438 struct dc_stream_state *new_stream, 8439 struct dc_plane_state *surface, 8440 u32 flip_timestamp_in_us) 8441 { 8442 struct mod_vrr_params vrr_params; 8443 struct dc_info_packet vrr_infopacket = {0}; 8444 struct amdgpu_device *adev = dm->adev; 8445 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8446 unsigned long flags; 8447 bool pack_sdp_v1_3 = false; 8448 struct amdgpu_dm_connector *aconn; 8449 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 8450 8451 if (!new_stream) 8452 return; 8453 8454 /* 8455 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8456 * For now it's sufficient to just guard against these conditions. 8457 */ 8458 8459 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8460 return; 8461 8462 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8463 vrr_params = acrtc->dm_irq_params.vrr_params; 8464 8465 if (surface) { 8466 mod_freesync_handle_preflip( 8467 dm->freesync_module, 8468 surface, 8469 new_stream, 8470 flip_timestamp_in_us, 8471 &vrr_params); 8472 8473 if (adev->family < AMDGPU_FAMILY_AI && 8474 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 8475 mod_freesync_handle_v_update(dm->freesync_module, 8476 new_stream, &vrr_params); 8477 8478 /* Need to call this before the frame ends. */ 8479 dc_stream_adjust_vmin_vmax(dm->dc, 8480 new_crtc_state->stream, 8481 &vrr_params.adjust); 8482 } 8483 } 8484 8485 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 8486 8487 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 8488 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 8489 8490 if (aconn->vsdb_info.amd_vsdb_version == 1) 8491 packet_type = PACKET_TYPE_FS_V1; 8492 else if (aconn->vsdb_info.amd_vsdb_version == 2) 8493 packet_type = PACKET_TYPE_FS_V2; 8494 else if (aconn->vsdb_info.amd_vsdb_version == 3) 8495 packet_type = PACKET_TYPE_FS_V3; 8496 8497 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 8498 &new_stream->adaptive_sync_infopacket); 8499 } 8500 8501 mod_freesync_build_vrr_infopacket( 8502 dm->freesync_module, 8503 new_stream, 8504 &vrr_params, 8505 packet_type, 8506 TRANSFER_FUNC_UNKNOWN, 8507 &vrr_infopacket, 8508 pack_sdp_v1_3); 8509 8510 new_crtc_state->freesync_vrr_info_changed |= 8511 (memcmp(&new_crtc_state->vrr_infopacket, 8512 &vrr_infopacket, 8513 sizeof(vrr_infopacket)) != 0); 8514 8515 acrtc->dm_irq_params.vrr_params = vrr_params; 8516 new_crtc_state->vrr_infopacket = vrr_infopacket; 8517 8518 new_stream->vrr_infopacket = vrr_infopacket; 8519 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 8520 8521 if (new_crtc_state->freesync_vrr_info_changed) 8522 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", 8523 new_crtc_state->base.crtc->base.id, 8524 (int)new_crtc_state->base.vrr_enabled, 8525 (int)vrr_params.state); 8526 8527 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8528 } 8529 8530 static void update_stream_irq_parameters( 8531 struct amdgpu_display_manager *dm, 8532 struct dm_crtc_state *new_crtc_state) 8533 { 8534 struct dc_stream_state *new_stream = new_crtc_state->stream; 8535 struct mod_vrr_params vrr_params; 8536 struct mod_freesync_config config = new_crtc_state->freesync_config; 8537 struct amdgpu_device *adev = dm->adev; 8538 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 8539 unsigned long flags; 8540 8541 if (!new_stream) 8542 return; 8543 8544 /* 8545 * TODO: Determine why min/max totals and vrefresh can be 0 here. 8546 * For now it's sufficient to just guard against these conditions. 8547 */ 8548 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 8549 return; 8550 8551 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 8552 vrr_params = acrtc->dm_irq_params.vrr_params; 8553 8554 if (new_crtc_state->vrr_supported && 8555 config.min_refresh_in_uhz && 8556 config.max_refresh_in_uhz) { 8557 /* 8558 * if freesync compatible mode was set, config.state will be set 8559 * in atomic check 8560 */ 8561 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 8562 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 8563 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 8564 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 8565 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 8566 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 8567 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 8568 } else { 8569 config.state = new_crtc_state->base.vrr_enabled ? 8570 VRR_STATE_ACTIVE_VARIABLE : 8571 VRR_STATE_INACTIVE; 8572 } 8573 } else { 8574 config.state = VRR_STATE_UNSUPPORTED; 8575 } 8576 8577 mod_freesync_build_vrr_params(dm->freesync_module, 8578 new_stream, 8579 &config, &vrr_params); 8580 8581 new_crtc_state->freesync_config = config; 8582 /* Copy state for access from DM IRQ handler */ 8583 acrtc->dm_irq_params.freesync_config = config; 8584 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 8585 acrtc->dm_irq_params.vrr_params = vrr_params; 8586 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 8587 } 8588 8589 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state, 8590 struct dm_crtc_state *new_state) 8591 { 8592 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 8593 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 8594 8595 if (!old_vrr_active && new_vrr_active) { 8596 /* Transition VRR inactive -> active: 8597 * While VRR is active, we must not disable vblank irq, as a 8598 * reenable after disable would compute bogus vblank/pflip 8599 * timestamps if it likely happened inside display front-porch. 8600 * 8601 * We also need vupdate irq for the actual core vblank handling 8602 * at end of vblank. 8603 */ 8604 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 8605 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 8606 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n", 8607 __func__, new_state->base.crtc->base.id); 8608 } else if (old_vrr_active && !new_vrr_active) { 8609 /* Transition VRR active -> inactive: 8610 * Allow vblank irq disable again for fixed refresh rate. 8611 */ 8612 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 8613 drm_crtc_vblank_put(new_state->base.crtc); 8614 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n", 8615 __func__, new_state->base.crtc->base.id); 8616 } 8617 } 8618 8619 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state) 8620 { 8621 struct drm_plane *plane; 8622 struct drm_plane_state *old_plane_state; 8623 int i; 8624 8625 /* 8626 * TODO: Make this per-stream so we don't issue redundant updates for 8627 * commits with multiple streams. 8628 */ 8629 for_each_old_plane_in_state(state, plane, old_plane_state, i) 8630 if (plane->type == DRM_PLANE_TYPE_CURSOR) 8631 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 8632 } 8633 8634 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 8635 { 8636 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 8637 8638 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 8639 } 8640 8641 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 8642 struct drm_plane_state *old_plane_state, 8643 struct dc_stream_update *update) 8644 { 8645 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8646 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8647 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 8648 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8649 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8650 uint64_t address = afb ? afb->address : 0; 8651 struct dc_cursor_position position = {0}; 8652 struct dc_cursor_attributes attributes; 8653 int ret; 8654 8655 if (!plane->state->fb && !old_plane_state->fb) 8656 return; 8657 8658 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 8659 amdgpu_crtc->crtc_id, plane->state->crtc_w, 8660 plane->state->crtc_h); 8661 8662 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 8663 if (ret) 8664 return; 8665 8666 if (!position.enable) { 8667 /* turn off cursor */ 8668 if (crtc_state && crtc_state->stream) { 8669 dc_stream_set_cursor_position(crtc_state->stream, 8670 &position); 8671 update->cursor_position = &crtc_state->stream->cursor_position; 8672 } 8673 return; 8674 } 8675 8676 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8677 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8678 8679 memset(&attributes, 0, sizeof(attributes)); 8680 attributes.address.high_part = upper_32_bits(address); 8681 attributes.address.low_part = lower_32_bits(address); 8682 attributes.width = plane->state->crtc_w; 8683 attributes.height = plane->state->crtc_h; 8684 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8685 attributes.rotation_angle = 0; 8686 attributes.attribute_flags.value = 0; 8687 8688 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 8689 * legacy gamma setup. 8690 */ 8691 if (crtc_state->cm_is_degamma_srgb && 8692 adev->dm.dc->caps.color.dpp.gamma_corr) 8693 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 8694 8695 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 8696 8697 if (crtc_state->stream) { 8698 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8699 &attributes)) 8700 DRM_ERROR("DC failed to set cursor attributes\n"); 8701 8702 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 8703 8704 if (!dc_stream_set_cursor_position(crtc_state->stream, 8705 &position)) 8706 DRM_ERROR("DC failed to set cursor position\n"); 8707 8708 update->cursor_position = &crtc_state->stream->cursor_position; 8709 } 8710 } 8711 8712 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 8713 struct drm_device *dev, 8714 struct amdgpu_display_manager *dm, 8715 struct drm_crtc *pcrtc, 8716 bool wait_for_vblank) 8717 { 8718 u32 i; 8719 u64 timestamp_ns = ktime_get_ns(); 8720 struct drm_plane *plane; 8721 struct drm_plane_state *old_plane_state, *new_plane_state; 8722 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 8723 struct drm_crtc_state *new_pcrtc_state = 8724 drm_atomic_get_new_crtc_state(state, pcrtc); 8725 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 8726 struct dm_crtc_state *dm_old_crtc_state = 8727 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 8728 int planes_count = 0, vpos, hpos; 8729 unsigned long flags; 8730 u32 target_vblank, last_flip_vblank; 8731 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 8732 bool cursor_update = false; 8733 bool pflip_present = false; 8734 bool dirty_rects_changed = false; 8735 bool updated_planes_and_streams = false; 8736 struct { 8737 struct dc_surface_update surface_updates[MAX_SURFACES]; 8738 struct dc_plane_info plane_infos[MAX_SURFACES]; 8739 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 8740 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 8741 struct dc_stream_update stream_update; 8742 } *bundle; 8743 8744 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); 8745 8746 if (!bundle) { 8747 drm_err(dev, "Failed to allocate update bundle\n"); 8748 goto cleanup; 8749 } 8750 8751 /* 8752 * Disable the cursor first if we're disabling all the planes. 8753 * It'll remain on the screen after the planes are re-enabled 8754 * if we don't. 8755 * 8756 * If the cursor is transitioning from native to overlay mode, the 8757 * native cursor needs to be disabled first. 8758 */ 8759 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 8760 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 8761 struct dc_cursor_position cursor_position = {0}; 8762 8763 if (!dc_stream_set_cursor_position(acrtc_state->stream, 8764 &cursor_position)) 8765 drm_err(dev, "DC failed to disable native cursor\n"); 8766 8767 bundle->stream_update.cursor_position = 8768 &acrtc_state->stream->cursor_position; 8769 } 8770 8771 if (acrtc_state->active_planes == 0 && 8772 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 8773 amdgpu_dm_commit_cursors(state); 8774 8775 /* update planes when needed */ 8776 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 8777 struct drm_crtc *crtc = new_plane_state->crtc; 8778 struct drm_crtc_state *new_crtc_state; 8779 struct drm_framebuffer *fb = new_plane_state->fb; 8780 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 8781 bool plane_needs_flip; 8782 struct dc_plane_state *dc_plane; 8783 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 8784 8785 /* Cursor plane is handled after stream updates */ 8786 if (plane->type == DRM_PLANE_TYPE_CURSOR && 8787 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 8788 if ((fb && crtc == pcrtc) || 8789 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 8790 cursor_update = true; 8791 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 8792 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 8793 } 8794 8795 continue; 8796 } 8797 8798 if (!fb || !crtc || pcrtc != crtc) 8799 continue; 8800 8801 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 8802 if (!new_crtc_state->active) 8803 continue; 8804 8805 dc_plane = dm_new_plane_state->dc_state; 8806 if (!dc_plane) 8807 continue; 8808 8809 bundle->surface_updates[planes_count].surface = dc_plane; 8810 if (new_pcrtc_state->color_mgmt_changed) { 8811 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 8812 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 8813 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 8814 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 8815 bundle->surface_updates[planes_count].func_shaper = &dc_plane->in_shaper_func; 8816 bundle->surface_updates[planes_count].lut3d_func = &dc_plane->lut3d_func; 8817 bundle->surface_updates[planes_count].blend_tf = &dc_plane->blend_tf; 8818 } 8819 8820 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 8821 &bundle->scaling_infos[planes_count]); 8822 8823 bundle->surface_updates[planes_count].scaling_info = 8824 &bundle->scaling_infos[planes_count]; 8825 8826 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 8827 8828 pflip_present = pflip_present || plane_needs_flip; 8829 8830 if (!plane_needs_flip) { 8831 planes_count += 1; 8832 continue; 8833 } 8834 8835 fill_dc_plane_info_and_addr( 8836 dm->adev, new_plane_state, 8837 afb->tiling_flags, 8838 &bundle->plane_infos[planes_count], 8839 &bundle->flip_addrs[planes_count].address, 8840 afb->tmz_surface, false); 8841 8842 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 8843 new_plane_state->plane->index, 8844 bundle->plane_infos[planes_count].dcc.enable); 8845 8846 bundle->surface_updates[planes_count].plane_info = 8847 &bundle->plane_infos[planes_count]; 8848 8849 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 8850 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 8851 fill_dc_dirty_rects(plane, old_plane_state, 8852 new_plane_state, new_crtc_state, 8853 &bundle->flip_addrs[planes_count], 8854 acrtc_state->stream->link->psr_settings.psr_version == 8855 DC_PSR_VERSION_SU_1, 8856 &dirty_rects_changed); 8857 8858 /* 8859 * If the dirty regions changed, PSR-SU need to be disabled temporarily 8860 * and enabled it again after dirty regions are stable to avoid video glitch. 8861 * PSR-SU will be enabled in vblank_control_worker() if user pause the video 8862 * during the PSR-SU was disabled. 8863 */ 8864 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 8865 acrtc_attach->dm_irq_params.allow_psr_entry && 8866 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 8867 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 8868 #endif 8869 dirty_rects_changed) { 8870 mutex_lock(&dm->dc_lock); 8871 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 8872 timestamp_ns; 8873 if (acrtc_state->stream->link->psr_settings.psr_allow_active) 8874 amdgpu_dm_psr_disable(acrtc_state->stream); 8875 mutex_unlock(&dm->dc_lock); 8876 } 8877 } 8878 8879 /* 8880 * Only allow immediate flips for fast updates that don't 8881 * change memory domain, FB pitch, DCC state, rotation or 8882 * mirroring. 8883 * 8884 * dm_crtc_helper_atomic_check() only accepts async flips with 8885 * fast updates. 8886 */ 8887 if (crtc->state->async_flip && 8888 (acrtc_state->update_type != UPDATE_TYPE_FAST || 8889 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 8890 drm_warn_once(state->dev, 8891 "[PLANE:%d:%s] async flip with non-fast update\n", 8892 plane->base.id, plane->name); 8893 8894 bundle->flip_addrs[planes_count].flip_immediate = 8895 crtc->state->async_flip && 8896 acrtc_state->update_type == UPDATE_TYPE_FAST && 8897 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 8898 8899 timestamp_ns = ktime_get_ns(); 8900 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 8901 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 8902 bundle->surface_updates[planes_count].surface = dc_plane; 8903 8904 if (!bundle->surface_updates[planes_count].surface) { 8905 DRM_ERROR("No surface for CRTC: id=%d\n", 8906 acrtc_attach->crtc_id); 8907 continue; 8908 } 8909 8910 if (plane == pcrtc->primary) 8911 update_freesync_state_on_stream( 8912 dm, 8913 acrtc_state, 8914 acrtc_state->stream, 8915 dc_plane, 8916 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 8917 8918 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 8919 __func__, 8920 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 8921 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 8922 8923 planes_count += 1; 8924 8925 } 8926 8927 if (pflip_present) { 8928 if (!vrr_active) { 8929 /* Use old throttling in non-vrr fixed refresh rate mode 8930 * to keep flip scheduling based on target vblank counts 8931 * working in a backwards compatible way, e.g., for 8932 * clients using the GLX_OML_sync_control extension or 8933 * DRI3/Present extension with defined target_msc. 8934 */ 8935 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 8936 } else { 8937 /* For variable refresh rate mode only: 8938 * Get vblank of last completed flip to avoid > 1 vrr 8939 * flips per video frame by use of throttling, but allow 8940 * flip programming anywhere in the possibly large 8941 * variable vrr vblank interval for fine-grained flip 8942 * timing control and more opportunity to avoid stutter 8943 * on late submission of flips. 8944 */ 8945 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8946 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 8947 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8948 } 8949 8950 target_vblank = last_flip_vblank + wait_for_vblank; 8951 8952 /* 8953 * Wait until we're out of the vertical blank period before the one 8954 * targeted by the flip 8955 */ 8956 while ((acrtc_attach->enabled && 8957 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 8958 0, &vpos, &hpos, NULL, 8959 NULL, &pcrtc->hwmode) 8960 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 8961 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 8962 (int)(target_vblank - 8963 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 8964 usleep_range(1000, 1100); 8965 } 8966 8967 /** 8968 * Prepare the flip event for the pageflip interrupt to handle. 8969 * 8970 * This only works in the case where we've already turned on the 8971 * appropriate hardware blocks (eg. HUBP) so in the transition case 8972 * from 0 -> n planes we have to skip a hardware generated event 8973 * and rely on sending it from software. 8974 */ 8975 if (acrtc_attach->base.state->event && 8976 acrtc_state->active_planes > 0) { 8977 drm_crtc_vblank_get(pcrtc); 8978 8979 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8980 8981 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 8982 prepare_flip_isr(acrtc_attach); 8983 8984 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 8985 } 8986 8987 if (acrtc_state->stream) { 8988 if (acrtc_state->freesync_vrr_info_changed) 8989 bundle->stream_update.vrr_infopacket = 8990 &acrtc_state->stream->vrr_infopacket; 8991 } 8992 } else if (cursor_update && acrtc_state->active_planes > 0) { 8993 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 8994 if (acrtc_attach->base.state->event) { 8995 drm_crtc_vblank_get(pcrtc); 8996 acrtc_attach->event = acrtc_attach->base.state->event; 8997 acrtc_attach->base.state->event = NULL; 8998 } 8999 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9000 } 9001 9002 /* Update the planes if changed or disable if we don't have any. */ 9003 if ((planes_count || acrtc_state->active_planes == 0) && 9004 acrtc_state->stream) { 9005 /* 9006 * If PSR or idle optimizations are enabled then flush out 9007 * any pending work before hardware programming. 9008 */ 9009 if (dm->vblank_control_workqueue) 9010 flush_workqueue(dm->vblank_control_workqueue); 9011 9012 bundle->stream_update.stream = acrtc_state->stream; 9013 if (new_pcrtc_state->mode_changed) { 9014 bundle->stream_update.src = acrtc_state->stream->src; 9015 bundle->stream_update.dst = acrtc_state->stream->dst; 9016 } 9017 9018 if (new_pcrtc_state->color_mgmt_changed) { 9019 /* 9020 * TODO: This isn't fully correct since we've actually 9021 * already modified the stream in place. 9022 */ 9023 bundle->stream_update.gamut_remap = 9024 &acrtc_state->stream->gamut_remap_matrix; 9025 bundle->stream_update.output_csc_transform = 9026 &acrtc_state->stream->csc_color_matrix; 9027 bundle->stream_update.out_transfer_func = 9028 &acrtc_state->stream->out_transfer_func; 9029 bundle->stream_update.lut3d_func = 9030 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 9031 bundle->stream_update.func_shaper = 9032 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 9033 } 9034 9035 acrtc_state->stream->abm_level = acrtc_state->abm_level; 9036 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 9037 bundle->stream_update.abm_level = &acrtc_state->abm_level; 9038 9039 mutex_lock(&dm->dc_lock); 9040 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) && 9041 acrtc_state->stream->link->psr_settings.psr_allow_active) 9042 amdgpu_dm_psr_disable(acrtc_state->stream); 9043 mutex_unlock(&dm->dc_lock); 9044 9045 /* 9046 * If FreeSync state on the stream has changed then we need to 9047 * re-adjust the min/max bounds now that DC doesn't handle this 9048 * as part of commit. 9049 */ 9050 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 9051 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 9052 dc_stream_adjust_vmin_vmax( 9053 dm->dc, acrtc_state->stream, 9054 &acrtc_attach->dm_irq_params.vrr_params.adjust); 9055 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 9056 } 9057 mutex_lock(&dm->dc_lock); 9058 update_planes_and_stream_adapter(dm->dc, 9059 acrtc_state->update_type, 9060 planes_count, 9061 acrtc_state->stream, 9062 &bundle->stream_update, 9063 bundle->surface_updates); 9064 updated_planes_and_streams = true; 9065 9066 /** 9067 * Enable or disable the interrupts on the backend. 9068 * 9069 * Most pipes are put into power gating when unused. 9070 * 9071 * When power gating is enabled on a pipe we lose the 9072 * interrupt enablement state when power gating is disabled. 9073 * 9074 * So we need to update the IRQ control state in hardware 9075 * whenever the pipe turns on (since it could be previously 9076 * power gated) or off (since some pipes can't be power gated 9077 * on some ASICs). 9078 */ 9079 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 9080 dm_update_pflip_irq_state(drm_to_adev(dev), 9081 acrtc_attach); 9082 9083 if (acrtc_state->update_type > UPDATE_TYPE_FAST) { 9084 if (acrtc_state->stream->link->replay_settings.config.replay_supported && 9085 !acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 9086 struct amdgpu_dm_connector *aconn = 9087 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 9088 amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn); 9089 } else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED && 9090 !acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 9091 9092 struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *) 9093 acrtc_state->stream->dm_stream_context; 9094 9095 if (!aconn->disallow_edp_enter_psr) 9096 amdgpu_dm_link_setup_psr(acrtc_state->stream); 9097 } 9098 } 9099 9100 /* Decrement skip count when PSR is enabled and we're doing fast updates. */ 9101 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 9102 acrtc_state->stream->link->psr_settings.psr_feature_enabled) { 9103 struct amdgpu_dm_connector *aconn = 9104 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 9105 9106 if (aconn->psr_skip_count > 0) 9107 aconn->psr_skip_count--; 9108 9109 /* Allow PSR when skip count is 0. */ 9110 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count; 9111 9112 /* 9113 * If sink supports PSR SU, there is no need to rely on 9114 * a vblank event disable request to enable PSR. PSR SU 9115 * can be enabled immediately once OS demonstrates an 9116 * adequate number of fast atomic commits to notify KMD 9117 * of update events. See `vblank_control_worker()`. 9118 */ 9119 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 9120 acrtc_attach->dm_irq_params.allow_psr_entry && 9121 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 9122 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) && 9123 #endif 9124 !acrtc_state->stream->link->psr_settings.psr_allow_active && 9125 !aconn->disallow_edp_enter_psr && 9126 (timestamp_ns - 9127 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) > 9128 500000000) 9129 amdgpu_dm_psr_enable(acrtc_state->stream); 9130 } else { 9131 acrtc_attach->dm_irq_params.allow_psr_entry = false; 9132 } 9133 9134 mutex_unlock(&dm->dc_lock); 9135 } 9136 9137 /* 9138 * Update cursor state *after* programming all the planes. 9139 * This avoids redundant programming in the case where we're going 9140 * to be disabling a single plane - those pipes are being disabled. 9141 */ 9142 if (acrtc_state->active_planes && 9143 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 9144 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 9145 amdgpu_dm_commit_cursors(state); 9146 9147 cleanup: 9148 kfree(bundle); 9149 } 9150 9151 static void amdgpu_dm_commit_audio(struct drm_device *dev, 9152 struct drm_atomic_state *state) 9153 { 9154 struct amdgpu_device *adev = drm_to_adev(dev); 9155 struct amdgpu_dm_connector *aconnector; 9156 struct drm_connector *connector; 9157 struct drm_connector_state *old_con_state, *new_con_state; 9158 struct drm_crtc_state *new_crtc_state; 9159 struct dm_crtc_state *new_dm_crtc_state; 9160 const struct dc_stream_status *status; 9161 int i, inst; 9162 9163 /* Notify device removals. */ 9164 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9165 if (old_con_state->crtc != new_con_state->crtc) { 9166 /* CRTC changes require notification. */ 9167 goto notify; 9168 } 9169 9170 if (!new_con_state->crtc) 9171 continue; 9172 9173 new_crtc_state = drm_atomic_get_new_crtc_state( 9174 state, new_con_state->crtc); 9175 9176 if (!new_crtc_state) 9177 continue; 9178 9179 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9180 continue; 9181 9182 notify: 9183 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9184 continue; 9185 9186 aconnector = to_amdgpu_dm_connector(connector); 9187 9188 mutex_lock(&adev->dm.audio_lock); 9189 inst = aconnector->audio_inst; 9190 aconnector->audio_inst = -1; 9191 mutex_unlock(&adev->dm.audio_lock); 9192 9193 amdgpu_dm_audio_eld_notify(adev, inst); 9194 } 9195 9196 /* Notify audio device additions. */ 9197 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9198 if (!new_con_state->crtc) 9199 continue; 9200 9201 new_crtc_state = drm_atomic_get_new_crtc_state( 9202 state, new_con_state->crtc); 9203 9204 if (!new_crtc_state) 9205 continue; 9206 9207 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 9208 continue; 9209 9210 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 9211 if (!new_dm_crtc_state->stream) 9212 continue; 9213 9214 status = dc_stream_get_status(new_dm_crtc_state->stream); 9215 if (!status) 9216 continue; 9217 9218 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9219 continue; 9220 9221 aconnector = to_amdgpu_dm_connector(connector); 9222 9223 mutex_lock(&adev->dm.audio_lock); 9224 inst = status->audio_inst; 9225 aconnector->audio_inst = inst; 9226 mutex_unlock(&adev->dm.audio_lock); 9227 9228 amdgpu_dm_audio_eld_notify(adev, inst); 9229 } 9230 } 9231 9232 /* 9233 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 9234 * @crtc_state: the DRM CRTC state 9235 * @stream_state: the DC stream state. 9236 * 9237 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 9238 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 9239 */ 9240 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 9241 struct dc_stream_state *stream_state) 9242 { 9243 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 9244 } 9245 9246 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 9247 struct dm_crtc_state *crtc_state) 9248 { 9249 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 9250 } 9251 9252 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, 9253 struct dc_state *dc_state) 9254 { 9255 struct drm_device *dev = state->dev; 9256 struct amdgpu_device *adev = drm_to_adev(dev); 9257 struct amdgpu_display_manager *dm = &adev->dm; 9258 struct drm_crtc *crtc; 9259 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9260 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9261 struct drm_connector_state *old_con_state; 9262 struct drm_connector *connector; 9263 bool mode_set_reset_required = false; 9264 u32 i; 9265 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 9266 9267 /* Disable writeback */ 9268 for_each_old_connector_in_state(state, connector, old_con_state, i) { 9269 struct dm_connector_state *dm_old_con_state; 9270 struct amdgpu_crtc *acrtc; 9271 9272 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9273 continue; 9274 9275 old_crtc_state = NULL; 9276 9277 dm_old_con_state = to_dm_connector_state(old_con_state); 9278 if (!dm_old_con_state->base.crtc) 9279 continue; 9280 9281 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 9282 if (acrtc) 9283 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9284 9285 if (!acrtc || !acrtc->wb_enabled) 9286 continue; 9287 9288 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9289 9290 dm_clear_writeback(dm, dm_old_crtc_state); 9291 acrtc->wb_enabled = false; 9292 } 9293 9294 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 9295 new_crtc_state, i) { 9296 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9297 9298 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9299 9300 if (old_crtc_state->active && 9301 (!new_crtc_state->active || 9302 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9303 manage_dm_interrupts(adev, acrtc, false); 9304 dc_stream_release(dm_old_crtc_state->stream); 9305 } 9306 } 9307 9308 drm_atomic_helper_calc_timestamping_constants(state); 9309 9310 /* update changed items */ 9311 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9312 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9313 9314 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9315 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9316 9317 drm_dbg_state(state->dev, 9318 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 9319 acrtc->crtc_id, 9320 new_crtc_state->enable, 9321 new_crtc_state->active, 9322 new_crtc_state->planes_changed, 9323 new_crtc_state->mode_changed, 9324 new_crtc_state->active_changed, 9325 new_crtc_state->connectors_changed); 9326 9327 /* Disable cursor if disabling crtc */ 9328 if (old_crtc_state->active && !new_crtc_state->active) { 9329 struct dc_cursor_position position; 9330 9331 memset(&position, 0, sizeof(position)); 9332 mutex_lock(&dm->dc_lock); 9333 dc_exit_ips_for_hw_access(dm->dc); 9334 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 9335 mutex_unlock(&dm->dc_lock); 9336 } 9337 9338 /* Copy all transient state flags into dc state */ 9339 if (dm_new_crtc_state->stream) { 9340 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 9341 dm_new_crtc_state->stream); 9342 } 9343 9344 /* handles headless hotplug case, updating new_state and 9345 * aconnector as needed 9346 */ 9347 9348 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 9349 9350 drm_dbg_atomic(dev, 9351 "Atomic commit: SET crtc id %d: [%p]\n", 9352 acrtc->crtc_id, acrtc); 9353 9354 if (!dm_new_crtc_state->stream) { 9355 /* 9356 * this could happen because of issues with 9357 * userspace notifications delivery. 9358 * In this case userspace tries to set mode on 9359 * display which is disconnected in fact. 9360 * dc_sink is NULL in this case on aconnector. 9361 * We expect reset mode will come soon. 9362 * 9363 * This can also happen when unplug is done 9364 * during resume sequence ended 9365 * 9366 * In this case, we want to pretend we still 9367 * have a sink to keep the pipe running so that 9368 * hw state is consistent with the sw state 9369 */ 9370 drm_dbg_atomic(dev, 9371 "Failed to create new stream for crtc %d\n", 9372 acrtc->base.base.id); 9373 continue; 9374 } 9375 9376 if (dm_old_crtc_state->stream) 9377 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9378 9379 pm_runtime_get_noresume(dev->dev); 9380 9381 acrtc->enabled = true; 9382 acrtc->hw_mode = new_crtc_state->mode; 9383 crtc->hwmode = new_crtc_state->mode; 9384 mode_set_reset_required = true; 9385 } else if (modereset_required(new_crtc_state)) { 9386 drm_dbg_atomic(dev, 9387 "Atomic commit: RESET. crtc id %d:[%p]\n", 9388 acrtc->crtc_id, acrtc); 9389 /* i.e. reset mode */ 9390 if (dm_old_crtc_state->stream) 9391 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 9392 9393 mode_set_reset_required = true; 9394 } 9395 } /* for_each_crtc_in_state() */ 9396 9397 /* if there mode set or reset, disable eDP PSR, Replay */ 9398 if (mode_set_reset_required) { 9399 if (dm->vblank_control_workqueue) 9400 flush_workqueue(dm->vblank_control_workqueue); 9401 9402 amdgpu_dm_replay_disable_all(dm); 9403 amdgpu_dm_psr_disable_all(dm); 9404 } 9405 9406 dm_enable_per_frame_crtc_master_sync(dc_state); 9407 mutex_lock(&dm->dc_lock); 9408 dc_exit_ips_for_hw_access(dm->dc); 9409 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 9410 9411 /* Allow idle optimization when vblank count is 0 for display off */ 9412 if (dm->active_vblank_irq_count == 0) 9413 dc_allow_idle_optimizations(dm->dc, true); 9414 mutex_unlock(&dm->dc_lock); 9415 9416 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9417 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9418 9419 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9420 9421 if (dm_new_crtc_state->stream != NULL) { 9422 const struct dc_stream_status *status = 9423 dc_stream_get_status(dm_new_crtc_state->stream); 9424 9425 if (!status) 9426 status = dc_state_get_stream_status(dc_state, 9427 dm_new_crtc_state->stream); 9428 if (!status) 9429 drm_err(dev, 9430 "got no status for stream %p on acrtc%p\n", 9431 dm_new_crtc_state->stream, acrtc); 9432 else 9433 acrtc->otg_inst = status->primary_otg_inst; 9434 } 9435 } 9436 } 9437 9438 static void dm_set_writeback(struct amdgpu_display_manager *dm, 9439 struct dm_crtc_state *crtc_state, 9440 struct drm_connector *connector, 9441 struct drm_connector_state *new_con_state) 9442 { 9443 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 9444 struct amdgpu_device *adev = dm->adev; 9445 struct amdgpu_crtc *acrtc; 9446 struct dc_writeback_info *wb_info; 9447 struct pipe_ctx *pipe = NULL; 9448 struct amdgpu_framebuffer *afb; 9449 int i = 0; 9450 9451 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 9452 if (!wb_info) { 9453 DRM_ERROR("Failed to allocate wb_info\n"); 9454 return; 9455 } 9456 9457 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 9458 if (!acrtc) { 9459 DRM_ERROR("no amdgpu_crtc found\n"); 9460 kfree(wb_info); 9461 return; 9462 } 9463 9464 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 9465 if (!afb) { 9466 DRM_ERROR("No amdgpu_framebuffer found\n"); 9467 kfree(wb_info); 9468 return; 9469 } 9470 9471 for (i = 0; i < MAX_PIPES; i++) { 9472 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 9473 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 9474 break; 9475 } 9476 } 9477 9478 /* fill in wb_info */ 9479 wb_info->wb_enabled = true; 9480 9481 wb_info->dwb_pipe_inst = 0; 9482 wb_info->dwb_params.dwbscl_black_color = 0; 9483 wb_info->dwb_params.hdr_mult = 0x1F000; 9484 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 9485 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 9486 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 9487 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 9488 9489 /* width & height from crtc */ 9490 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 9491 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 9492 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 9493 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 9494 9495 wb_info->dwb_params.cnv_params.crop_en = false; 9496 wb_info->dwb_params.stereo_params.stereo_enabled = false; 9497 9498 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 9499 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 9500 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 9501 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 9502 9503 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 9504 9505 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 9506 9507 wb_info->dwb_params.scaler_taps.h_taps = 4; 9508 wb_info->dwb_params.scaler_taps.v_taps = 4; 9509 wb_info->dwb_params.scaler_taps.h_taps_c = 2; 9510 wb_info->dwb_params.scaler_taps.v_taps_c = 2; 9511 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 9512 9513 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 9514 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 9515 9516 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 9517 wb_info->mcif_buf_params.luma_address[i] = afb->address; 9518 wb_info->mcif_buf_params.chroma_address[i] = 0; 9519 } 9520 9521 wb_info->mcif_buf_params.p_vmid = 1; 9522 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 9523 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 9524 wb_info->mcif_warmup_params.region_size = 9525 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 9526 } 9527 wb_info->mcif_warmup_params.p_vmid = 1; 9528 wb_info->writeback_source_plane = pipe->plane_state; 9529 9530 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 9531 9532 acrtc->wb_pending = true; 9533 acrtc->wb_conn = wb_conn; 9534 drm_writeback_queue_job(wb_conn, new_con_state); 9535 } 9536 9537 /** 9538 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 9539 * @state: The atomic state to commit 9540 * 9541 * This will tell DC to commit the constructed DC state from atomic_check, 9542 * programming the hardware. Any failures here implies a hardware failure, since 9543 * atomic check should have filtered anything non-kosher. 9544 */ 9545 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 9546 { 9547 struct drm_device *dev = state->dev; 9548 struct amdgpu_device *adev = drm_to_adev(dev); 9549 struct amdgpu_display_manager *dm = &adev->dm; 9550 struct dm_atomic_state *dm_state; 9551 struct dc_state *dc_state = NULL; 9552 u32 i, j; 9553 struct drm_crtc *crtc; 9554 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 9555 unsigned long flags; 9556 bool wait_for_vblank = true; 9557 struct drm_connector *connector; 9558 struct drm_connector_state *old_con_state, *new_con_state; 9559 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 9560 int crtc_disable_count = 0; 9561 9562 trace_amdgpu_dm_atomic_commit_tail_begin(state); 9563 9564 drm_atomic_helper_update_legacy_modeset_state(dev, state); 9565 drm_dp_mst_atomic_wait_for_dependencies(state); 9566 9567 dm_state = dm_atomic_get_new_state(state); 9568 if (dm_state && dm_state->context) { 9569 dc_state = dm_state->context; 9570 amdgpu_dm_commit_streams(state, dc_state); 9571 } 9572 9573 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9574 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9575 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9576 struct amdgpu_dm_connector *aconnector; 9577 9578 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 9579 continue; 9580 9581 aconnector = to_amdgpu_dm_connector(connector); 9582 9583 if (!adev->dm.hdcp_workqueue) 9584 continue; 9585 9586 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i); 9587 9588 if (!connector) 9589 continue; 9590 9591 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 9592 connector->index, connector->status, connector->dpms); 9593 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 9594 old_con_state->content_protection, new_con_state->content_protection); 9595 9596 if (aconnector->dc_sink) { 9597 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 9598 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 9599 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n", 9600 aconnector->dc_sink->edid_caps.display_name); 9601 } 9602 } 9603 9604 new_crtc_state = NULL; 9605 old_crtc_state = NULL; 9606 9607 if (acrtc) { 9608 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9609 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9610 } 9611 9612 if (old_crtc_state) 9613 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9614 old_crtc_state->enable, 9615 old_crtc_state->active, 9616 old_crtc_state->mode_changed, 9617 old_crtc_state->active_changed, 9618 old_crtc_state->connectors_changed); 9619 9620 if (new_crtc_state) 9621 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 9622 new_crtc_state->enable, 9623 new_crtc_state->active, 9624 new_crtc_state->mode_changed, 9625 new_crtc_state->active_changed, 9626 new_crtc_state->connectors_changed); 9627 } 9628 9629 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9630 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9631 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9632 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 9633 9634 if (!adev->dm.hdcp_workqueue) 9635 continue; 9636 9637 new_crtc_state = NULL; 9638 old_crtc_state = NULL; 9639 9640 if (acrtc) { 9641 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9642 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9643 } 9644 9645 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9646 9647 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 9648 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 9649 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 9650 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 9651 dm_new_con_state->update_hdcp = true; 9652 continue; 9653 } 9654 9655 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 9656 old_con_state, connector, adev->dm.hdcp_workqueue)) { 9657 /* when display is unplugged from mst hub, connctor will 9658 * be destroyed within dm_dp_mst_connector_destroy. connector 9659 * hdcp perperties, like type, undesired, desired, enabled, 9660 * will be lost. So, save hdcp properties into hdcp_work within 9661 * amdgpu_dm_atomic_commit_tail. if the same display is 9662 * plugged back with same display index, its hdcp properties 9663 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 9664 */ 9665 9666 bool enable_encryption = false; 9667 9668 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 9669 enable_encryption = true; 9670 9671 if (aconnector->dc_link && aconnector->dc_sink && 9672 aconnector->dc_link->type == dc_connection_mst_branch) { 9673 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 9674 struct hdcp_workqueue *hdcp_w = 9675 &hdcp_work[aconnector->dc_link->link_index]; 9676 9677 hdcp_w->hdcp_content_type[connector->index] = 9678 new_con_state->hdcp_content_type; 9679 hdcp_w->content_protection[connector->index] = 9680 new_con_state->content_protection; 9681 } 9682 9683 if (new_crtc_state && new_crtc_state->mode_changed && 9684 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 9685 enable_encryption = true; 9686 9687 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 9688 9689 if (aconnector->dc_link) 9690 hdcp_update_display( 9691 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 9692 new_con_state->hdcp_content_type, enable_encryption); 9693 } 9694 } 9695 9696 /* Handle connector state changes */ 9697 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 9698 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9699 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 9700 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9701 struct dc_surface_update *dummy_updates; 9702 struct dc_stream_update stream_update; 9703 struct dc_info_packet hdr_packet; 9704 struct dc_stream_status *status = NULL; 9705 bool abm_changed, hdr_changed, scaling_changed; 9706 9707 memset(&stream_update, 0, sizeof(stream_update)); 9708 9709 if (acrtc) { 9710 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9711 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 9712 } 9713 9714 /* Skip any modesets/resets */ 9715 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 9716 continue; 9717 9718 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9719 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9720 9721 scaling_changed = is_scaling_state_different(dm_new_con_state, 9722 dm_old_con_state); 9723 9724 abm_changed = dm_new_crtc_state->abm_level != 9725 dm_old_crtc_state->abm_level; 9726 9727 hdr_changed = 9728 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 9729 9730 if (!scaling_changed && !abm_changed && !hdr_changed) 9731 continue; 9732 9733 stream_update.stream = dm_new_crtc_state->stream; 9734 if (scaling_changed) { 9735 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, 9736 dm_new_con_state, dm_new_crtc_state->stream); 9737 9738 stream_update.src = dm_new_crtc_state->stream->src; 9739 stream_update.dst = dm_new_crtc_state->stream->dst; 9740 } 9741 9742 if (abm_changed) { 9743 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 9744 9745 stream_update.abm_level = &dm_new_crtc_state->abm_level; 9746 } 9747 9748 if (hdr_changed) { 9749 fill_hdr_info_packet(new_con_state, &hdr_packet); 9750 stream_update.hdr_static_metadata = &hdr_packet; 9751 } 9752 9753 status = dc_stream_get_status(dm_new_crtc_state->stream); 9754 9755 if (WARN_ON(!status)) 9756 continue; 9757 9758 WARN_ON(!status->plane_count); 9759 9760 /* 9761 * TODO: DC refuses to perform stream updates without a dc_surface_update. 9762 * Here we create an empty update on each plane. 9763 * To fix this, DC should permit updating only stream properties. 9764 */ 9765 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 9766 if (!dummy_updates) { 9767 DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); 9768 continue; 9769 } 9770 for (j = 0; j < status->plane_count; j++) 9771 dummy_updates[j].surface = status->plane_states[0]; 9772 9773 sort(dummy_updates, status->plane_count, 9774 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 9775 9776 mutex_lock(&dm->dc_lock); 9777 dc_exit_ips_for_hw_access(dm->dc); 9778 dc_update_planes_and_stream(dm->dc, 9779 dummy_updates, 9780 status->plane_count, 9781 dm_new_crtc_state->stream, 9782 &stream_update); 9783 mutex_unlock(&dm->dc_lock); 9784 kfree(dummy_updates); 9785 } 9786 9787 /** 9788 * Enable interrupts for CRTCs that are newly enabled or went through 9789 * a modeset. It was intentionally deferred until after the front end 9790 * state was modified to wait until the OTG was on and so the IRQ 9791 * handlers didn't access stale or invalid state. 9792 */ 9793 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 9794 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 9795 #ifdef CONFIG_DEBUG_FS 9796 enum amdgpu_dm_pipe_crc_source cur_crc_src; 9797 #endif 9798 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 9799 if (old_crtc_state->active && !new_crtc_state->active) 9800 crtc_disable_count++; 9801 9802 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9803 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 9804 9805 /* For freesync config update on crtc state and params for irq */ 9806 update_stream_irq_parameters(dm, dm_new_crtc_state); 9807 9808 #ifdef CONFIG_DEBUG_FS 9809 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9810 cur_crc_src = acrtc->dm_irq_params.crc_src; 9811 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9812 #endif 9813 9814 if (new_crtc_state->active && 9815 (!old_crtc_state->active || 9816 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9817 dc_stream_retain(dm_new_crtc_state->stream); 9818 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 9819 manage_dm_interrupts(adev, acrtc, true); 9820 } 9821 /* Handle vrr on->off / off->on transitions */ 9822 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); 9823 9824 #ifdef CONFIG_DEBUG_FS 9825 if (new_crtc_state->active && 9826 (!old_crtc_state->active || 9827 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 9828 /** 9829 * Frontend may have changed so reapply the CRC capture 9830 * settings for the stream. 9831 */ 9832 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 9833 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 9834 if (amdgpu_dm_crc_window_is_activated(crtc)) { 9835 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9836 acrtc->dm_irq_params.window_param.update_win = true; 9837 9838 /** 9839 * It takes 2 frames for HW to stably generate CRC when 9840 * resuming from suspend, so we set skip_frame_cnt 2. 9841 */ 9842 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2; 9843 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9844 } 9845 #endif 9846 if (amdgpu_dm_crtc_configure_crc_source( 9847 crtc, dm_new_crtc_state, cur_crc_src)) 9848 drm_dbg_atomic(dev, "Failed to configure crc source"); 9849 } 9850 } 9851 #endif 9852 } 9853 9854 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 9855 if (new_crtc_state->async_flip) 9856 wait_for_vblank = false; 9857 9858 /* update planes when needed per crtc*/ 9859 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 9860 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9861 9862 if (dm_new_crtc_state->stream) 9863 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 9864 } 9865 9866 /* Enable writeback */ 9867 for_each_new_connector_in_state(state, connector, new_con_state, i) { 9868 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 9869 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 9870 9871 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 9872 continue; 9873 9874 if (!new_con_state->writeback_job) 9875 continue; 9876 9877 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 9878 9879 if (!new_crtc_state) 9880 continue; 9881 9882 if (acrtc->wb_enabled) 9883 continue; 9884 9885 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 9886 9887 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 9888 acrtc->wb_enabled = true; 9889 } 9890 9891 /* Update audio instances for each connector. */ 9892 amdgpu_dm_commit_audio(dev, state); 9893 9894 /* restore the backlight level */ 9895 for (i = 0; i < dm->num_of_edps; i++) { 9896 if (dm->backlight_dev[i] && 9897 (dm->actual_brightness[i] != dm->brightness[i])) 9898 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 9899 } 9900 9901 /* 9902 * send vblank event on all events not handled in flip and 9903 * mark consumed event for drm_atomic_helper_commit_hw_done 9904 */ 9905 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 9906 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 9907 9908 if (new_crtc_state->event) 9909 drm_send_event_locked(dev, &new_crtc_state->event->base); 9910 9911 new_crtc_state->event = NULL; 9912 } 9913 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 9914 9915 /* Signal HW programming completion */ 9916 drm_atomic_helper_commit_hw_done(state); 9917 9918 if (wait_for_vblank) 9919 drm_atomic_helper_wait_for_flip_done(dev, state); 9920 9921 drm_atomic_helper_cleanup_planes(dev, state); 9922 9923 /* Don't free the memory if we are hitting this as part of suspend. 9924 * This way we don't free any memory during suspend; see 9925 * amdgpu_bo_free_kernel(). The memory will be freed in the first 9926 * non-suspend modeset or when the driver is torn down. 9927 */ 9928 if (!adev->in_suspend) { 9929 /* return the stolen vga memory back to VRAM */ 9930 if (!adev->mman.keep_stolen_vga_memory) 9931 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 9932 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 9933 } 9934 9935 /* 9936 * Finally, drop a runtime PM reference for each newly disabled CRTC, 9937 * so we can put the GPU into runtime suspend if we're not driving any 9938 * displays anymore 9939 */ 9940 for (i = 0; i < crtc_disable_count; i++) 9941 pm_runtime_put_autosuspend(dev->dev); 9942 pm_runtime_mark_last_busy(dev->dev); 9943 } 9944 9945 static int dm_force_atomic_commit(struct drm_connector *connector) 9946 { 9947 int ret = 0; 9948 struct drm_device *ddev = connector->dev; 9949 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); 9950 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 9951 struct drm_plane *plane = disconnected_acrtc->base.primary; 9952 struct drm_connector_state *conn_state; 9953 struct drm_crtc_state *crtc_state; 9954 struct drm_plane_state *plane_state; 9955 9956 if (!state) 9957 return -ENOMEM; 9958 9959 state->acquire_ctx = ddev->mode_config.acquire_ctx; 9960 9961 /* Construct an atomic state to restore previous display setting */ 9962 9963 /* 9964 * Attach connectors to drm_atomic_state 9965 */ 9966 conn_state = drm_atomic_get_connector_state(state, connector); 9967 9968 ret = PTR_ERR_OR_ZERO(conn_state); 9969 if (ret) 9970 goto out; 9971 9972 /* Attach crtc to drm_atomic_state*/ 9973 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); 9974 9975 ret = PTR_ERR_OR_ZERO(crtc_state); 9976 if (ret) 9977 goto out; 9978 9979 /* force a restore */ 9980 crtc_state->mode_changed = true; 9981 9982 /* Attach plane to drm_atomic_state */ 9983 plane_state = drm_atomic_get_plane_state(state, plane); 9984 9985 ret = PTR_ERR_OR_ZERO(plane_state); 9986 if (ret) 9987 goto out; 9988 9989 /* Call commit internally with the state we just constructed */ 9990 ret = drm_atomic_commit(state); 9991 9992 out: 9993 drm_atomic_state_put(state); 9994 if (ret) 9995 DRM_ERROR("Restoring old state failed with %i\n", ret); 9996 9997 return ret; 9998 } 9999 10000 /* 10001 * This function handles all cases when set mode does not come upon hotplug. 10002 * This includes when a display is unplugged then plugged back into the 10003 * same port and when running without usermode desktop manager supprot 10004 */ 10005 void dm_restore_drm_connector_state(struct drm_device *dev, 10006 struct drm_connector *connector) 10007 { 10008 struct amdgpu_dm_connector *aconnector; 10009 struct amdgpu_crtc *disconnected_acrtc; 10010 struct dm_crtc_state *acrtc_state; 10011 10012 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10013 return; 10014 10015 aconnector = to_amdgpu_dm_connector(connector); 10016 10017 if (!aconnector->dc_sink || !connector->state || !connector->encoder) 10018 return; 10019 10020 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); 10021 if (!disconnected_acrtc) 10022 return; 10023 10024 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); 10025 if (!acrtc_state->stream) 10026 return; 10027 10028 /* 10029 * If the previous sink is not released and different from the current, 10030 * we deduce we are in a state where we can not rely on usermode call 10031 * to turn on the display, so we do it here 10032 */ 10033 if (acrtc_state->stream->sink != aconnector->dc_sink) 10034 dm_force_atomic_commit(&aconnector->base); 10035 } 10036 10037 /* 10038 * Grabs all modesetting locks to serialize against any blocking commits, 10039 * Waits for completion of all non blocking commits. 10040 */ 10041 static int do_aquire_global_lock(struct drm_device *dev, 10042 struct drm_atomic_state *state) 10043 { 10044 struct drm_crtc *crtc; 10045 struct drm_crtc_commit *commit; 10046 long ret; 10047 10048 /* 10049 * Adding all modeset locks to aquire_ctx will 10050 * ensure that when the framework release it the 10051 * extra locks we are locking here will get released to 10052 */ 10053 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 10054 if (ret) 10055 return ret; 10056 10057 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 10058 spin_lock(&crtc->commit_lock); 10059 commit = list_first_entry_or_null(&crtc->commit_list, 10060 struct drm_crtc_commit, commit_entry); 10061 if (commit) 10062 drm_crtc_commit_get(commit); 10063 spin_unlock(&crtc->commit_lock); 10064 10065 if (!commit) 10066 continue; 10067 10068 /* 10069 * Make sure all pending HW programming completed and 10070 * page flips done 10071 */ 10072 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 10073 10074 if (ret > 0) 10075 ret = wait_for_completion_interruptible_timeout( 10076 &commit->flip_done, 10*HZ); 10077 10078 if (ret == 0) 10079 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n", 10080 crtc->base.id, crtc->name); 10081 10082 drm_crtc_commit_put(commit); 10083 } 10084 10085 return ret < 0 ? ret : 0; 10086 } 10087 10088 static void get_freesync_config_for_crtc( 10089 struct dm_crtc_state *new_crtc_state, 10090 struct dm_connector_state *new_con_state) 10091 { 10092 struct mod_freesync_config config = {0}; 10093 struct amdgpu_dm_connector *aconnector; 10094 struct drm_display_mode *mode = &new_crtc_state->base.mode; 10095 int vrefresh = drm_mode_vrefresh(mode); 10096 bool fs_vid_mode = false; 10097 10098 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 10099 return; 10100 10101 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 10102 10103 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 10104 vrefresh >= aconnector->min_vfreq && 10105 vrefresh <= aconnector->max_vfreq; 10106 10107 if (new_crtc_state->vrr_supported) { 10108 new_crtc_state->stream->ignore_msa_timing_param = true; 10109 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 10110 10111 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 10112 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 10113 config.vsif_supported = true; 10114 config.btr = true; 10115 10116 if (fs_vid_mode) { 10117 config.state = VRR_STATE_ACTIVE_FIXED; 10118 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 10119 goto out; 10120 } else if (new_crtc_state->base.vrr_enabled) { 10121 config.state = VRR_STATE_ACTIVE_VARIABLE; 10122 } else { 10123 config.state = VRR_STATE_INACTIVE; 10124 } 10125 } 10126 out: 10127 new_crtc_state->freesync_config = config; 10128 } 10129 10130 static void reset_freesync_config_for_crtc( 10131 struct dm_crtc_state *new_crtc_state) 10132 { 10133 new_crtc_state->vrr_supported = false; 10134 10135 memset(&new_crtc_state->vrr_infopacket, 0, 10136 sizeof(new_crtc_state->vrr_infopacket)); 10137 } 10138 10139 static bool 10140 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 10141 struct drm_crtc_state *new_crtc_state) 10142 { 10143 const struct drm_display_mode *old_mode, *new_mode; 10144 10145 if (!old_crtc_state || !new_crtc_state) 10146 return false; 10147 10148 old_mode = &old_crtc_state->mode; 10149 new_mode = &new_crtc_state->mode; 10150 10151 if (old_mode->clock == new_mode->clock && 10152 old_mode->hdisplay == new_mode->hdisplay && 10153 old_mode->vdisplay == new_mode->vdisplay && 10154 old_mode->htotal == new_mode->htotal && 10155 old_mode->vtotal != new_mode->vtotal && 10156 old_mode->hsync_start == new_mode->hsync_start && 10157 old_mode->vsync_start != new_mode->vsync_start && 10158 old_mode->hsync_end == new_mode->hsync_end && 10159 old_mode->vsync_end != new_mode->vsync_end && 10160 old_mode->hskew == new_mode->hskew && 10161 old_mode->vscan == new_mode->vscan && 10162 (old_mode->vsync_end - old_mode->vsync_start) == 10163 (new_mode->vsync_end - new_mode->vsync_start)) 10164 return true; 10165 10166 return false; 10167 } 10168 10169 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 10170 { 10171 u64 num, den, res; 10172 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 10173 10174 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 10175 10176 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 10177 den = (unsigned long long)new_crtc_state->mode.htotal * 10178 (unsigned long long)new_crtc_state->mode.vtotal; 10179 10180 res = div_u64(num, den); 10181 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 10182 } 10183 10184 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 10185 struct drm_atomic_state *state, 10186 struct drm_crtc *crtc, 10187 struct drm_crtc_state *old_crtc_state, 10188 struct drm_crtc_state *new_crtc_state, 10189 bool enable, 10190 bool *lock_and_validation_needed) 10191 { 10192 struct dm_atomic_state *dm_state = NULL; 10193 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10194 struct dc_stream_state *new_stream; 10195 int ret = 0; 10196 10197 /* 10198 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 10199 * update changed items 10200 */ 10201 struct amdgpu_crtc *acrtc = NULL; 10202 struct drm_connector *connector = NULL; 10203 struct amdgpu_dm_connector *aconnector = NULL; 10204 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 10205 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 10206 10207 new_stream = NULL; 10208 10209 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10210 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10211 acrtc = to_amdgpu_crtc(crtc); 10212 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 10213 if (connector) 10214 aconnector = to_amdgpu_dm_connector(connector); 10215 10216 /* TODO This hack should go away */ 10217 if (connector && enable) { 10218 /* Make sure fake sink is created in plug-in scenario */ 10219 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 10220 connector); 10221 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 10222 connector); 10223 10224 if (IS_ERR(drm_new_conn_state)) { 10225 ret = PTR_ERR_OR_ZERO(drm_new_conn_state); 10226 goto fail; 10227 } 10228 10229 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 10230 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 10231 10232 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10233 goto skip_modeset; 10234 10235 new_stream = create_validate_stream_for_sink(aconnector, 10236 &new_crtc_state->mode, 10237 dm_new_conn_state, 10238 dm_old_crtc_state->stream); 10239 10240 /* 10241 * we can have no stream on ACTION_SET if a display 10242 * was disconnected during S3, in this case it is not an 10243 * error, the OS will be updated after detection, and 10244 * will do the right thing on next atomic commit 10245 */ 10246 10247 if (!new_stream) { 10248 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", 10249 __func__, acrtc->base.base.id); 10250 ret = -ENOMEM; 10251 goto fail; 10252 } 10253 10254 /* 10255 * TODO: Check VSDB bits to decide whether this should 10256 * be enabled or not. 10257 */ 10258 new_stream->triggered_crtc_reset.enabled = 10259 dm->force_timing_sync; 10260 10261 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10262 10263 ret = fill_hdr_info_packet(drm_new_conn_state, 10264 &new_stream->hdr_static_metadata); 10265 if (ret) 10266 goto fail; 10267 10268 /* 10269 * If we already removed the old stream from the context 10270 * (and set the new stream to NULL) then we can't reuse 10271 * the old stream even if the stream and scaling are unchanged. 10272 * We'll hit the BUG_ON and black screen. 10273 * 10274 * TODO: Refactor this function to allow this check to work 10275 * in all conditions. 10276 */ 10277 if (amdgpu_freesync_vid_mode && 10278 dm_new_crtc_state->stream && 10279 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 10280 goto skip_modeset; 10281 10282 if (dm_new_crtc_state->stream && 10283 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10284 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 10285 new_crtc_state->mode_changed = false; 10286 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", 10287 new_crtc_state->mode_changed); 10288 } 10289 } 10290 10291 /* mode_changed flag may get updated above, need to check again */ 10292 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 10293 goto skip_modeset; 10294 10295 drm_dbg_state(state->dev, 10296 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 10297 acrtc->crtc_id, 10298 new_crtc_state->enable, 10299 new_crtc_state->active, 10300 new_crtc_state->planes_changed, 10301 new_crtc_state->mode_changed, 10302 new_crtc_state->active_changed, 10303 new_crtc_state->connectors_changed); 10304 10305 /* Remove stream for any changed/disabled CRTC */ 10306 if (!enable) { 10307 10308 if (!dm_old_crtc_state->stream) 10309 goto skip_modeset; 10310 10311 /* Unset freesync video if it was active before */ 10312 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 10313 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 10314 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 10315 } 10316 10317 /* Now check if we should set freesync video mode */ 10318 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 10319 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 10320 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 10321 is_timing_unchanged_for_freesync(new_crtc_state, 10322 old_crtc_state)) { 10323 new_crtc_state->mode_changed = false; 10324 DRM_DEBUG_DRIVER( 10325 "Mode change not required for front porch change, setting mode_changed to %d", 10326 new_crtc_state->mode_changed); 10327 10328 set_freesync_fixed_config(dm_new_crtc_state); 10329 10330 goto skip_modeset; 10331 } else if (amdgpu_freesync_vid_mode && aconnector && 10332 is_freesync_video_mode(&new_crtc_state->mode, 10333 aconnector)) { 10334 struct drm_display_mode *high_mode; 10335 10336 high_mode = get_highest_refresh_rate_mode(aconnector, false); 10337 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 10338 set_freesync_fixed_config(dm_new_crtc_state); 10339 } 10340 10341 ret = dm_atomic_get_state(state, &dm_state); 10342 if (ret) 10343 goto fail; 10344 10345 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", 10346 crtc->base.id); 10347 10348 /* i.e. reset mode */ 10349 if (dc_state_remove_stream( 10350 dm->dc, 10351 dm_state->context, 10352 dm_old_crtc_state->stream) != DC_OK) { 10353 ret = -EINVAL; 10354 goto fail; 10355 } 10356 10357 dc_stream_release(dm_old_crtc_state->stream); 10358 dm_new_crtc_state->stream = NULL; 10359 10360 reset_freesync_config_for_crtc(dm_new_crtc_state); 10361 10362 *lock_and_validation_needed = true; 10363 10364 } else {/* Add stream for any updated/enabled CRTC */ 10365 /* 10366 * Quick fix to prevent NULL pointer on new_stream when 10367 * added MST connectors not found in existing crtc_state in the chained mode 10368 * TODO: need to dig out the root cause of that 10369 */ 10370 if (!connector) 10371 goto skip_modeset; 10372 10373 if (modereset_required(new_crtc_state)) 10374 goto skip_modeset; 10375 10376 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 10377 dm_old_crtc_state->stream)) { 10378 10379 WARN_ON(dm_new_crtc_state->stream); 10380 10381 ret = dm_atomic_get_state(state, &dm_state); 10382 if (ret) 10383 goto fail; 10384 10385 dm_new_crtc_state->stream = new_stream; 10386 10387 dc_stream_retain(new_stream); 10388 10389 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", 10390 crtc->base.id); 10391 10392 if (dc_state_add_stream( 10393 dm->dc, 10394 dm_state->context, 10395 dm_new_crtc_state->stream) != DC_OK) { 10396 ret = -EINVAL; 10397 goto fail; 10398 } 10399 10400 *lock_and_validation_needed = true; 10401 } 10402 } 10403 10404 skip_modeset: 10405 /* Release extra reference */ 10406 if (new_stream) 10407 dc_stream_release(new_stream); 10408 10409 /* 10410 * We want to do dc stream updates that do not require a 10411 * full modeset below. 10412 */ 10413 if (!(enable && connector && new_crtc_state->active)) 10414 return 0; 10415 /* 10416 * Given above conditions, the dc state cannot be NULL because: 10417 * 1. We're in the process of enabling CRTCs (just been added 10418 * to the dc context, or already is on the context) 10419 * 2. Has a valid connector attached, and 10420 * 3. Is currently active and enabled. 10421 * => The dc stream state currently exists. 10422 */ 10423 BUG_ON(dm_new_crtc_state->stream == NULL); 10424 10425 /* Scaling or underscan settings */ 10426 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 10427 drm_atomic_crtc_needs_modeset(new_crtc_state)) 10428 update_stream_scaling_settings( 10429 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 10430 10431 /* ABM settings */ 10432 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 10433 10434 /* 10435 * Color management settings. We also update color properties 10436 * when a modeset is needed, to ensure it gets reprogrammed. 10437 */ 10438 if (dm_new_crtc_state->base.color_mgmt_changed || 10439 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 10440 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 10441 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 10442 if (ret) 10443 goto fail; 10444 } 10445 10446 /* Update Freesync settings. */ 10447 get_freesync_config_for_crtc(dm_new_crtc_state, 10448 dm_new_conn_state); 10449 10450 return ret; 10451 10452 fail: 10453 if (new_stream) 10454 dc_stream_release(new_stream); 10455 return ret; 10456 } 10457 10458 static bool should_reset_plane(struct drm_atomic_state *state, 10459 struct drm_plane *plane, 10460 struct drm_plane_state *old_plane_state, 10461 struct drm_plane_state *new_plane_state) 10462 { 10463 struct drm_plane *other; 10464 struct drm_plane_state *old_other_state, *new_other_state; 10465 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10466 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 10467 struct amdgpu_device *adev = drm_to_adev(plane->dev); 10468 int i; 10469 10470 /* 10471 * TODO: Remove this hack for all asics once it proves that the 10472 * fast updates works fine on DCN3.2+. 10473 */ 10474 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 10475 state->allow_modeset) 10476 return true; 10477 10478 /* Exit early if we know that we're adding or removing the plane. */ 10479 if (old_plane_state->crtc != new_plane_state->crtc) 10480 return true; 10481 10482 /* old crtc == new_crtc == NULL, plane not in context. */ 10483 if (!new_plane_state->crtc) 10484 return false; 10485 10486 new_crtc_state = 10487 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 10488 old_crtc_state = 10489 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 10490 10491 if (!new_crtc_state) 10492 return true; 10493 10494 /* 10495 * A change in cursor mode means a new dc pipe needs to be acquired or 10496 * released from the state 10497 */ 10498 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 10499 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 10500 if (plane->type == DRM_PLANE_TYPE_CURSOR && 10501 old_dm_crtc_state != NULL && 10502 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 10503 return true; 10504 } 10505 10506 /* CRTC Degamma changes currently require us to recreate planes. */ 10507 if (new_crtc_state->color_mgmt_changed) 10508 return true; 10509 10510 /* 10511 * On zpos change, planes need to be reordered by removing and re-adding 10512 * them one by one to the dc state, in order of descending zpos. 10513 * 10514 * TODO: We can likely skip bandwidth validation if the only thing that 10515 * changed about the plane was it'z z-ordering. 10516 */ 10517 if (new_crtc_state->zpos_changed) 10518 return true; 10519 10520 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 10521 return true; 10522 10523 /* 10524 * If there are any new primary or overlay planes being added or 10525 * removed then the z-order can potentially change. To ensure 10526 * correct z-order and pipe acquisition the current DC architecture 10527 * requires us to remove and recreate all existing planes. 10528 * 10529 * TODO: Come up with a more elegant solution for this. 10530 */ 10531 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 10532 struct amdgpu_framebuffer *old_afb, *new_afb; 10533 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 10534 10535 dm_new_other_state = to_dm_plane_state(new_other_state); 10536 dm_old_other_state = to_dm_plane_state(old_other_state); 10537 10538 if (other->type == DRM_PLANE_TYPE_CURSOR) 10539 continue; 10540 10541 if (old_other_state->crtc != new_plane_state->crtc && 10542 new_other_state->crtc != new_plane_state->crtc) 10543 continue; 10544 10545 if (old_other_state->crtc != new_other_state->crtc) 10546 return true; 10547 10548 /* Src/dst size and scaling updates. */ 10549 if (old_other_state->src_w != new_other_state->src_w || 10550 old_other_state->src_h != new_other_state->src_h || 10551 old_other_state->crtc_w != new_other_state->crtc_w || 10552 old_other_state->crtc_h != new_other_state->crtc_h) 10553 return true; 10554 10555 /* Rotation / mirroring updates. */ 10556 if (old_other_state->rotation != new_other_state->rotation) 10557 return true; 10558 10559 /* Blending updates. */ 10560 if (old_other_state->pixel_blend_mode != 10561 new_other_state->pixel_blend_mode) 10562 return true; 10563 10564 /* Alpha updates. */ 10565 if (old_other_state->alpha != new_other_state->alpha) 10566 return true; 10567 10568 /* Colorspace changes. */ 10569 if (old_other_state->color_range != new_other_state->color_range || 10570 old_other_state->color_encoding != new_other_state->color_encoding) 10571 return true; 10572 10573 /* HDR/Transfer Function changes. */ 10574 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 10575 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 10576 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 10577 dm_old_other_state->ctm != dm_new_other_state->ctm || 10578 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 10579 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 10580 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 10581 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 10582 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 10583 return true; 10584 10585 /* Framebuffer checks fall at the end. */ 10586 if (!old_other_state->fb || !new_other_state->fb) 10587 continue; 10588 10589 /* Pixel format changes can require bandwidth updates. */ 10590 if (old_other_state->fb->format != new_other_state->fb->format) 10591 return true; 10592 10593 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 10594 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 10595 10596 /* Tiling and DCC changes also require bandwidth updates. */ 10597 if (old_afb->tiling_flags != new_afb->tiling_flags || 10598 old_afb->base.modifier != new_afb->base.modifier) 10599 return true; 10600 } 10601 10602 return false; 10603 } 10604 10605 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 10606 struct drm_plane_state *new_plane_state, 10607 struct drm_framebuffer *fb) 10608 { 10609 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 10610 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 10611 unsigned int pitch; 10612 bool linear; 10613 10614 if (fb->width > new_acrtc->max_cursor_width || 10615 fb->height > new_acrtc->max_cursor_height) { 10616 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", 10617 new_plane_state->fb->width, 10618 new_plane_state->fb->height); 10619 return -EINVAL; 10620 } 10621 if (new_plane_state->src_w != fb->width << 16 || 10622 new_plane_state->src_h != fb->height << 16) { 10623 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10624 return -EINVAL; 10625 } 10626 10627 /* Pitch in pixels */ 10628 pitch = fb->pitches[0] / fb->format->cpp[0]; 10629 10630 if (fb->width != pitch) { 10631 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", 10632 fb->width, pitch); 10633 return -EINVAL; 10634 } 10635 10636 switch (pitch) { 10637 case 64: 10638 case 128: 10639 case 256: 10640 /* FB pitch is supported by cursor plane */ 10641 break; 10642 default: 10643 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); 10644 return -EINVAL; 10645 } 10646 10647 /* Core DRM takes care of checking FB modifiers, so we only need to 10648 * check tiling flags when the FB doesn't have a modifier. 10649 */ 10650 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 10651 if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { 10652 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 10653 } else if (adev->family >= AMDGPU_FAMILY_AI) { 10654 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 10655 } else { 10656 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 10657 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 10658 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 10659 } 10660 if (!linear) { 10661 DRM_DEBUG_ATOMIC("Cursor FB not linear"); 10662 return -EINVAL; 10663 } 10664 } 10665 10666 return 0; 10667 } 10668 10669 /* 10670 * Helper function for checking the cursor in native mode 10671 */ 10672 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 10673 struct drm_plane *plane, 10674 struct drm_plane_state *new_plane_state, 10675 bool enable) 10676 { 10677 10678 struct amdgpu_crtc *new_acrtc; 10679 int ret; 10680 10681 if (!enable || !new_plane_crtc || 10682 drm_atomic_plane_disabling(plane->state, new_plane_state)) 10683 return 0; 10684 10685 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 10686 10687 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 10688 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); 10689 return -EINVAL; 10690 } 10691 10692 if (new_plane_state->fb) { 10693 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 10694 new_plane_state->fb); 10695 if (ret) 10696 return ret; 10697 } 10698 10699 return 0; 10700 } 10701 10702 static bool dm_should_update_native_cursor(struct drm_atomic_state *state, 10703 struct drm_crtc *old_plane_crtc, 10704 struct drm_crtc *new_plane_crtc, 10705 bool enable) 10706 { 10707 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10708 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 10709 10710 if (!enable) { 10711 if (old_plane_crtc == NULL) 10712 return true; 10713 10714 old_crtc_state = drm_atomic_get_old_crtc_state( 10715 state, old_plane_crtc); 10716 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10717 10718 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 10719 } else { 10720 if (new_plane_crtc == NULL) 10721 return true; 10722 10723 new_crtc_state = drm_atomic_get_new_crtc_state( 10724 state, new_plane_crtc); 10725 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10726 10727 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 10728 } 10729 } 10730 10731 static int dm_update_plane_state(struct dc *dc, 10732 struct drm_atomic_state *state, 10733 struct drm_plane *plane, 10734 struct drm_plane_state *old_plane_state, 10735 struct drm_plane_state *new_plane_state, 10736 bool enable, 10737 bool *lock_and_validation_needed, 10738 bool *is_top_most_overlay) 10739 { 10740 10741 struct dm_atomic_state *dm_state = NULL; 10742 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 10743 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 10744 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 10745 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 10746 bool needs_reset, update_native_cursor; 10747 int ret = 0; 10748 10749 10750 new_plane_crtc = new_plane_state->crtc; 10751 old_plane_crtc = old_plane_state->crtc; 10752 dm_new_plane_state = to_dm_plane_state(new_plane_state); 10753 dm_old_plane_state = to_dm_plane_state(old_plane_state); 10754 10755 update_native_cursor = dm_should_update_native_cursor(state, 10756 old_plane_crtc, 10757 new_plane_crtc, 10758 enable); 10759 10760 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 10761 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 10762 new_plane_state, enable); 10763 if (ret) 10764 return ret; 10765 10766 return 0; 10767 } 10768 10769 needs_reset = should_reset_plane(state, plane, old_plane_state, 10770 new_plane_state); 10771 10772 /* Remove any changed/removed planes */ 10773 if (!enable) { 10774 if (!needs_reset) 10775 return 0; 10776 10777 if (!old_plane_crtc) 10778 return 0; 10779 10780 old_crtc_state = drm_atomic_get_old_crtc_state( 10781 state, old_plane_crtc); 10782 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 10783 10784 if (!dm_old_crtc_state->stream) 10785 return 0; 10786 10787 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", 10788 plane->base.id, old_plane_crtc->base.id); 10789 10790 ret = dm_atomic_get_state(state, &dm_state); 10791 if (ret) 10792 return ret; 10793 10794 if (!dc_state_remove_plane( 10795 dc, 10796 dm_old_crtc_state->stream, 10797 dm_old_plane_state->dc_state, 10798 dm_state->context)) { 10799 10800 return -EINVAL; 10801 } 10802 10803 if (dm_old_plane_state->dc_state) 10804 dc_plane_state_release(dm_old_plane_state->dc_state); 10805 10806 dm_new_plane_state->dc_state = NULL; 10807 10808 *lock_and_validation_needed = true; 10809 10810 } else { /* Add new planes */ 10811 struct dc_plane_state *dc_new_plane_state; 10812 10813 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 10814 return 0; 10815 10816 if (!new_plane_crtc) 10817 return 0; 10818 10819 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 10820 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 10821 10822 if (!dm_new_crtc_state->stream) 10823 return 0; 10824 10825 if (!needs_reset) 10826 return 0; 10827 10828 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 10829 if (ret) 10830 goto out; 10831 10832 WARN_ON(dm_new_plane_state->dc_state); 10833 10834 dc_new_plane_state = dc_create_plane_state(dc); 10835 if (!dc_new_plane_state) { 10836 ret = -ENOMEM; 10837 goto out; 10838 } 10839 10840 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", 10841 plane->base.id, new_plane_crtc->base.id); 10842 10843 ret = fill_dc_plane_attributes( 10844 drm_to_adev(new_plane_crtc->dev), 10845 dc_new_plane_state, 10846 new_plane_state, 10847 new_crtc_state); 10848 if (ret) { 10849 dc_plane_state_release(dc_new_plane_state); 10850 goto out; 10851 } 10852 10853 ret = dm_atomic_get_state(state, &dm_state); 10854 if (ret) { 10855 dc_plane_state_release(dc_new_plane_state); 10856 goto out; 10857 } 10858 10859 /* 10860 * Any atomic check errors that occur after this will 10861 * not need a release. The plane state will be attached 10862 * to the stream, and therefore part of the atomic 10863 * state. It'll be released when the atomic state is 10864 * cleaned. 10865 */ 10866 if (!dc_state_add_plane( 10867 dc, 10868 dm_new_crtc_state->stream, 10869 dc_new_plane_state, 10870 dm_state->context)) { 10871 10872 dc_plane_state_release(dc_new_plane_state); 10873 ret = -EINVAL; 10874 goto out; 10875 } 10876 10877 dm_new_plane_state->dc_state = dc_new_plane_state; 10878 10879 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 10880 10881 /* Tell DC to do a full surface update every time there 10882 * is a plane change. Inefficient, but works for now. 10883 */ 10884 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; 10885 10886 *lock_and_validation_needed = true; 10887 } 10888 10889 out: 10890 /* If enabling cursor overlay failed, attempt fallback to native mode */ 10891 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 10892 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 10893 new_plane_state, enable); 10894 if (ret) 10895 return ret; 10896 10897 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 10898 } 10899 10900 return ret; 10901 } 10902 10903 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 10904 int *src_w, int *src_h) 10905 { 10906 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 10907 case DRM_MODE_ROTATE_90: 10908 case DRM_MODE_ROTATE_270: 10909 *src_w = plane_state->src_h >> 16; 10910 *src_h = plane_state->src_w >> 16; 10911 break; 10912 case DRM_MODE_ROTATE_0: 10913 case DRM_MODE_ROTATE_180: 10914 default: 10915 *src_w = plane_state->src_w >> 16; 10916 *src_h = plane_state->src_h >> 16; 10917 break; 10918 } 10919 } 10920 10921 static void 10922 dm_get_plane_scale(struct drm_plane_state *plane_state, 10923 int *out_plane_scale_w, int *out_plane_scale_h) 10924 { 10925 int plane_src_w, plane_src_h; 10926 10927 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 10928 *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w; 10929 *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h; 10930 } 10931 10932 /* 10933 * The normalized_zpos value cannot be used by this iterator directly. It's only 10934 * calculated for enabled planes, potentially causing normalized_zpos collisions 10935 * between enabled/disabled planes in the atomic state. We need a unique value 10936 * so that the iterator will not generate the same object twice, or loop 10937 * indefinitely. 10938 */ 10939 static inline struct __drm_planes_state *__get_next_zpos( 10940 struct drm_atomic_state *state, 10941 struct __drm_planes_state *prev) 10942 { 10943 unsigned int highest_zpos = 0, prev_zpos = 256; 10944 uint32_t highest_id = 0, prev_id = UINT_MAX; 10945 struct drm_plane_state *new_plane_state; 10946 struct drm_plane *plane; 10947 int i, highest_i = -1; 10948 10949 if (prev != NULL) { 10950 prev_zpos = prev->new_state->zpos; 10951 prev_id = prev->ptr->base.id; 10952 } 10953 10954 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 10955 /* Skip planes with higher zpos than the previously returned */ 10956 if (new_plane_state->zpos > prev_zpos || 10957 (new_plane_state->zpos == prev_zpos && 10958 plane->base.id >= prev_id)) 10959 continue; 10960 10961 /* Save the index of the plane with highest zpos */ 10962 if (new_plane_state->zpos > highest_zpos || 10963 (new_plane_state->zpos == highest_zpos && 10964 plane->base.id > highest_id)) { 10965 highest_zpos = new_plane_state->zpos; 10966 highest_id = plane->base.id; 10967 highest_i = i; 10968 } 10969 } 10970 10971 if (highest_i < 0) 10972 return NULL; 10973 10974 return &state->planes[highest_i]; 10975 } 10976 10977 /* 10978 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 10979 * by descending zpos, as read from the new plane state. This is the same 10980 * ordering as defined by drm_atomic_normalize_zpos(). 10981 */ 10982 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 10983 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 10984 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 10985 for_each_if(((plane) = __i->ptr, \ 10986 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 10987 (old_plane_state) = __i->old_state, \ 10988 (new_plane_state) = __i->new_state, 1)) 10989 10990 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) 10991 { 10992 struct drm_connector *connector; 10993 struct drm_connector_state *conn_state, *old_conn_state; 10994 struct amdgpu_dm_connector *aconnector = NULL; 10995 int i; 10996 10997 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 10998 if (!conn_state->crtc) 10999 conn_state = old_conn_state; 11000 11001 if (conn_state->crtc != crtc) 11002 continue; 11003 11004 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 11005 continue; 11006 11007 aconnector = to_amdgpu_dm_connector(connector); 11008 if (!aconnector->mst_output_port || !aconnector->mst_root) 11009 aconnector = NULL; 11010 else 11011 break; 11012 } 11013 11014 if (!aconnector) 11015 return 0; 11016 11017 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 11018 } 11019 11020 /** 11021 * DOC: Cursor Modes - Native vs Overlay 11022 * 11023 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 11024 * plane. It does not require a dedicated hw plane to enable, but it is 11025 * subjected to the same z-order and scaling as the hw plane. It also has format 11026 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 11027 * hw plane. 11028 * 11029 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 11030 * own scaling and z-pos. It also has no blending restrictions. It lends to a 11031 * cursor behavior more akin to a DRM client's expectations. However, it does 11032 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 11033 * available. 11034 */ 11035 11036 /** 11037 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 11038 * @adev: amdgpu device 11039 * @state: DRM atomic state 11040 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 11041 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 11042 * 11043 * Get whether the cursor should be enabled in native mode, or overlay mode, on 11044 * the dm_crtc_state. 11045 * 11046 * The cursor should be enabled in overlay mode if there exists an underlying 11047 * plane - on which the cursor may be blended - that is either YUV formatted, or 11048 * scaled differently from the cursor. 11049 * 11050 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 11051 * calling this function. 11052 * 11053 * Return: 0 on success, or an error code if getting the cursor plane state 11054 * failed. 11055 */ 11056 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 11057 struct drm_atomic_state *state, 11058 struct dm_crtc_state *dm_crtc_state, 11059 enum amdgpu_dm_cursor_mode *cursor_mode) 11060 { 11061 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 11062 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 11063 struct drm_plane *plane; 11064 bool consider_mode_change = false; 11065 bool entire_crtc_covered = false; 11066 bool cursor_changed = false; 11067 int underlying_scale_w, underlying_scale_h; 11068 int cursor_scale_w, cursor_scale_h; 11069 int i; 11070 11071 /* Overlay cursor not supported on HW before DCN 11072 * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 11073 * as previous DCN generations, so enable native mode on DCN401 in addition to DCE 11074 */ 11075 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 || 11076 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 11077 *cursor_mode = DM_CURSOR_NATIVE_MODE; 11078 return 0; 11079 } 11080 11081 /* Init cursor_mode to be the same as current */ 11082 *cursor_mode = dm_crtc_state->cursor_mode; 11083 11084 /* 11085 * Cursor mode can change if a plane's format changes, scale changes, is 11086 * enabled/disabled, or z-order changes. 11087 */ 11088 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 11089 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 11090 11091 /* Only care about planes on this CRTC */ 11092 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 11093 continue; 11094 11095 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11096 cursor_changed = true; 11097 11098 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 11099 drm_atomic_plane_disabling(old_plane_state, plane_state) || 11100 old_plane_state->fb->format != plane_state->fb->format) { 11101 consider_mode_change = true; 11102 break; 11103 } 11104 11105 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 11106 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 11107 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 11108 consider_mode_change = true; 11109 break; 11110 } 11111 } 11112 11113 if (!consider_mode_change && !crtc_state->zpos_changed) 11114 return 0; 11115 11116 /* 11117 * If no cursor change on this CRTC, and not enabled on this CRTC, then 11118 * no need to set cursor mode. This avoids needlessly locking the cursor 11119 * state. 11120 */ 11121 if (!cursor_changed && 11122 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 11123 return 0; 11124 } 11125 11126 cursor_state = drm_atomic_get_plane_state(state, 11127 crtc_state->crtc->cursor); 11128 if (IS_ERR(cursor_state)) 11129 return PTR_ERR(cursor_state); 11130 11131 /* Cursor is disabled */ 11132 if (!cursor_state->fb) 11133 return 0; 11134 11135 /* For all planes in descending z-order (all of which are below cursor 11136 * as per zpos definitions), check their scaling and format 11137 */ 11138 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 11139 11140 /* Only care about non-cursor planes on this CRTC */ 11141 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 11142 plane->type == DRM_PLANE_TYPE_CURSOR) 11143 continue; 11144 11145 /* Underlying plane is YUV format - use overlay cursor */ 11146 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 11147 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 11148 return 0; 11149 } 11150 11151 dm_get_plane_scale(plane_state, 11152 &underlying_scale_w, &underlying_scale_h); 11153 dm_get_plane_scale(cursor_state, 11154 &cursor_scale_w, &cursor_scale_h); 11155 11156 /* Underlying plane has different scale - use overlay cursor */ 11157 if (cursor_scale_w != underlying_scale_w && 11158 cursor_scale_h != underlying_scale_h) { 11159 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 11160 return 0; 11161 } 11162 11163 /* If this plane covers the whole CRTC, no need to check planes underneath */ 11164 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 11165 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 11166 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 11167 entire_crtc_covered = true; 11168 break; 11169 } 11170 } 11171 11172 /* If planes do not cover the entire CRTC, use overlay mode to enable 11173 * cursor over holes 11174 */ 11175 if (entire_crtc_covered) 11176 *cursor_mode = DM_CURSOR_NATIVE_MODE; 11177 else 11178 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 11179 11180 return 0; 11181 } 11182 11183 /** 11184 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 11185 * 11186 * @dev: The DRM device 11187 * @state: The atomic state to commit 11188 * 11189 * Validate that the given atomic state is programmable by DC into hardware. 11190 * This involves constructing a &struct dc_state reflecting the new hardware 11191 * state we wish to commit, then querying DC to see if it is programmable. It's 11192 * important not to modify the existing DC state. Otherwise, atomic_check 11193 * may unexpectedly commit hardware changes. 11194 * 11195 * When validating the DC state, it's important that the right locks are 11196 * acquired. For full updates case which removes/adds/updates streams on one 11197 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 11198 * that any such full update commit will wait for completion of any outstanding 11199 * flip using DRMs synchronization events. 11200 * 11201 * Note that DM adds the affected connectors for all CRTCs in state, when that 11202 * might not seem necessary. This is because DC stream creation requires the 11203 * DC sink, which is tied to the DRM connector state. Cleaning this up should 11204 * be possible but non-trivial - a possible TODO item. 11205 * 11206 * Return: -Error code if validation failed. 11207 */ 11208 static int amdgpu_dm_atomic_check(struct drm_device *dev, 11209 struct drm_atomic_state *state) 11210 { 11211 struct amdgpu_device *adev = drm_to_adev(dev); 11212 struct dm_atomic_state *dm_state = NULL; 11213 struct dc *dc = adev->dm.dc; 11214 struct drm_connector *connector; 11215 struct drm_connector_state *old_con_state, *new_con_state; 11216 struct drm_crtc *crtc; 11217 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 11218 struct drm_plane *plane; 11219 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 11220 enum dc_status status; 11221 int ret, i; 11222 bool lock_and_validation_needed = false; 11223 bool is_top_most_overlay = true; 11224 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 11225 struct drm_dp_mst_topology_mgr *mgr; 11226 struct drm_dp_mst_topology_state *mst_state; 11227 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 11228 11229 trace_amdgpu_dm_atomic_check_begin(state); 11230 11231 ret = drm_atomic_helper_check_modeset(dev, state); 11232 if (ret) { 11233 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n"); 11234 goto fail; 11235 } 11236 11237 /* Check connector changes */ 11238 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 11239 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 11240 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11241 11242 /* Skip connectors that are disabled or part of modeset already. */ 11243 if (!new_con_state->crtc) 11244 continue; 11245 11246 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 11247 if (IS_ERR(new_crtc_state)) { 11248 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n"); 11249 ret = PTR_ERR(new_crtc_state); 11250 goto fail; 11251 } 11252 11253 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 11254 dm_old_con_state->scaling != dm_new_con_state->scaling) 11255 new_crtc_state->connectors_changed = true; 11256 } 11257 11258 if (dc_resource_is_dsc_encoding_supported(dc)) { 11259 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11260 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 11261 ret = add_affected_mst_dsc_crtcs(state, crtc); 11262 if (ret) { 11263 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n"); 11264 goto fail; 11265 } 11266 } 11267 } 11268 } 11269 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11270 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 11271 11272 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 11273 !new_crtc_state->color_mgmt_changed && 11274 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 11275 dm_old_crtc_state->dsc_force_changed == false) 11276 continue; 11277 11278 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 11279 if (ret) { 11280 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n"); 11281 goto fail; 11282 } 11283 11284 if (!new_crtc_state->enable) 11285 continue; 11286 11287 ret = drm_atomic_add_affected_connectors(state, crtc); 11288 if (ret) { 11289 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n"); 11290 goto fail; 11291 } 11292 11293 ret = drm_atomic_add_affected_planes(state, crtc); 11294 if (ret) { 11295 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n"); 11296 goto fail; 11297 } 11298 11299 if (dm_old_crtc_state->dsc_force_changed) 11300 new_crtc_state->mode_changed = true; 11301 } 11302 11303 /* 11304 * Add all primary and overlay planes on the CRTC to the state 11305 * whenever a plane is enabled to maintain correct z-ordering 11306 * and to enable fast surface updates. 11307 */ 11308 drm_for_each_crtc(crtc, dev) { 11309 bool modified = false; 11310 11311 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 11312 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11313 continue; 11314 11315 if (new_plane_state->crtc == crtc || 11316 old_plane_state->crtc == crtc) { 11317 modified = true; 11318 break; 11319 } 11320 } 11321 11322 if (!modified) 11323 continue; 11324 11325 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 11326 if (plane->type == DRM_PLANE_TYPE_CURSOR) 11327 continue; 11328 11329 new_plane_state = 11330 drm_atomic_get_plane_state(state, plane); 11331 11332 if (IS_ERR(new_plane_state)) { 11333 ret = PTR_ERR(new_plane_state); 11334 drm_dbg_atomic(dev, "new_plane_state is BAD\n"); 11335 goto fail; 11336 } 11337 } 11338 } 11339 11340 /* 11341 * DC consults the zpos (layer_index in DC terminology) to determine the 11342 * hw plane on which to enable the hw cursor (see 11343 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 11344 * atomic state, so call drm helper to normalize zpos. 11345 */ 11346 ret = drm_atomic_normalize_zpos(dev, state); 11347 if (ret) { 11348 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 11349 goto fail; 11350 } 11351 11352 /* 11353 * Determine whether cursors on each CRTC should be enabled in native or 11354 * overlay mode. 11355 */ 11356 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11357 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11358 11359 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 11360 &dm_new_crtc_state->cursor_mode); 11361 if (ret) { 11362 drm_dbg(dev, "Failed to determine cursor mode\n"); 11363 goto fail; 11364 } 11365 } 11366 11367 /* Remove exiting planes if they are modified */ 11368 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 11369 if (old_plane_state->fb && new_plane_state->fb && 11370 get_mem_type(old_plane_state->fb) != 11371 get_mem_type(new_plane_state->fb)) 11372 lock_and_validation_needed = true; 11373 11374 ret = dm_update_plane_state(dc, state, plane, 11375 old_plane_state, 11376 new_plane_state, 11377 false, 11378 &lock_and_validation_needed, 11379 &is_top_most_overlay); 11380 if (ret) { 11381 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 11382 goto fail; 11383 } 11384 } 11385 11386 /* Disable all crtcs which require disable */ 11387 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11388 ret = dm_update_crtc_state(&adev->dm, state, crtc, 11389 old_crtc_state, 11390 new_crtc_state, 11391 false, 11392 &lock_and_validation_needed); 11393 if (ret) { 11394 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n"); 11395 goto fail; 11396 } 11397 } 11398 11399 /* Enable all crtcs which require enable */ 11400 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 11401 ret = dm_update_crtc_state(&adev->dm, state, crtc, 11402 old_crtc_state, 11403 new_crtc_state, 11404 true, 11405 &lock_and_validation_needed); 11406 if (ret) { 11407 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n"); 11408 goto fail; 11409 } 11410 } 11411 11412 /* Add new/modified planes */ 11413 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 11414 ret = dm_update_plane_state(dc, state, plane, 11415 old_plane_state, 11416 new_plane_state, 11417 true, 11418 &lock_and_validation_needed, 11419 &is_top_most_overlay); 11420 if (ret) { 11421 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 11422 goto fail; 11423 } 11424 } 11425 11426 #if defined(CONFIG_DRM_AMD_DC_FP) 11427 if (dc_resource_is_dsc_encoding_supported(dc)) { 11428 ret = pre_validate_dsc(state, &dm_state, vars); 11429 if (ret != 0) 11430 goto fail; 11431 } 11432 #endif 11433 11434 /* Run this here since we want to validate the streams we created */ 11435 ret = drm_atomic_helper_check_planes(dev, state); 11436 if (ret) { 11437 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n"); 11438 goto fail; 11439 } 11440 11441 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11442 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11443 if (dm_new_crtc_state->mpo_requested) 11444 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 11445 } 11446 11447 /* Check cursor restrictions */ 11448 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11449 enum amdgpu_dm_cursor_mode required_cursor_mode; 11450 int is_rotated, is_scaled; 11451 11452 /* Overlay cusor not subject to native cursor restrictions */ 11453 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 11454 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 11455 continue; 11456 11457 /* Check if rotation or scaling is enabled on DCN401 */ 11458 if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && 11459 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { 11460 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 11461 11462 is_rotated = new_cursor_state && 11463 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 11464 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 11465 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 11466 11467 if (is_rotated || is_scaled) { 11468 drm_dbg_driver( 11469 crtc->dev, 11470 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 11471 crtc->base.id, crtc->name); 11472 ret = -EINVAL; 11473 goto fail; 11474 } 11475 } 11476 11477 /* If HW can only do native cursor, check restrictions again */ 11478 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 11479 &required_cursor_mode); 11480 if (ret) { 11481 drm_dbg_driver(crtc->dev, 11482 "[CRTC:%d:%s] Checking cursor mode failed\n", 11483 crtc->base.id, crtc->name); 11484 goto fail; 11485 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 11486 drm_dbg_driver(crtc->dev, 11487 "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n", 11488 crtc->base.id, crtc->name); 11489 ret = -EINVAL; 11490 goto fail; 11491 } 11492 } 11493 11494 if (state->legacy_cursor_update) { 11495 /* 11496 * This is a fast cursor update coming from the plane update 11497 * helper, check if it can be done asynchronously for better 11498 * performance. 11499 */ 11500 state->async_update = 11501 !drm_atomic_helper_async_check(dev, state); 11502 11503 /* 11504 * Skip the remaining global validation if this is an async 11505 * update. Cursor updates can be done without affecting 11506 * state or bandwidth calcs and this avoids the performance 11507 * penalty of locking the private state object and 11508 * allocating a new dc_state. 11509 */ 11510 if (state->async_update) 11511 return 0; 11512 } 11513 11514 /* Check scaling and underscan changes*/ 11515 /* TODO Removed scaling changes validation due to inability to commit 11516 * new stream into context w\o causing full reset. Need to 11517 * decide how to handle. 11518 */ 11519 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 11520 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 11521 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 11522 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 11523 11524 /* Skip any modesets/resets */ 11525 if (!acrtc || drm_atomic_crtc_needs_modeset( 11526 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 11527 continue; 11528 11529 /* Skip any thing not scale or underscan changes */ 11530 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 11531 continue; 11532 11533 lock_and_validation_needed = true; 11534 } 11535 11536 /* set the slot info for each mst_state based on the link encoding format */ 11537 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 11538 struct amdgpu_dm_connector *aconnector; 11539 struct drm_connector *connector; 11540 struct drm_connector_list_iter iter; 11541 u8 link_coding_cap; 11542 11543 drm_connector_list_iter_begin(dev, &iter); 11544 drm_for_each_connector_iter(connector, &iter) { 11545 if (connector->index == mst_state->mgr->conn_base_id) { 11546 aconnector = to_amdgpu_dm_connector(connector); 11547 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 11548 drm_dp_mst_update_slots(mst_state, link_coding_cap); 11549 11550 break; 11551 } 11552 } 11553 drm_connector_list_iter_end(&iter); 11554 } 11555 11556 /** 11557 * Streams and planes are reset when there are changes that affect 11558 * bandwidth. Anything that affects bandwidth needs to go through 11559 * DC global validation to ensure that the configuration can be applied 11560 * to hardware. 11561 * 11562 * We have to currently stall out here in atomic_check for outstanding 11563 * commits to finish in this case because our IRQ handlers reference 11564 * DRM state directly - we can end up disabling interrupts too early 11565 * if we don't. 11566 * 11567 * TODO: Remove this stall and drop DM state private objects. 11568 */ 11569 if (lock_and_validation_needed) { 11570 ret = dm_atomic_get_state(state, &dm_state); 11571 if (ret) { 11572 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); 11573 goto fail; 11574 } 11575 11576 ret = do_aquire_global_lock(dev, state); 11577 if (ret) { 11578 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n"); 11579 goto fail; 11580 } 11581 11582 #if defined(CONFIG_DRM_AMD_DC_FP) 11583 if (dc_resource_is_dsc_encoding_supported(dc)) { 11584 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 11585 if (ret) { 11586 drm_dbg_atomic(dev, "compute_mst_dsc_configs_for_state() failed\n"); 11587 ret = -EINVAL; 11588 goto fail; 11589 } 11590 } 11591 #endif 11592 11593 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 11594 if (ret) { 11595 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); 11596 goto fail; 11597 } 11598 11599 /* 11600 * Perform validation of MST topology in the state: 11601 * We need to perform MST atomic check before calling 11602 * dc_validate_global_state(), or there is a chance 11603 * to get stuck in an infinite loop and hang eventually. 11604 */ 11605 ret = drm_dp_mst_atomic_check(state); 11606 if (ret) { 11607 drm_dbg_atomic(dev, "drm_dp_mst_atomic_check() failed\n"); 11608 goto fail; 11609 } 11610 status = dc_validate_global_state(dc, dm_state->context, true); 11611 if (status != DC_OK) { 11612 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 11613 dc_status_to_str(status), status); 11614 ret = -EINVAL; 11615 goto fail; 11616 } 11617 } else { 11618 /* 11619 * The commit is a fast update. Fast updates shouldn't change 11620 * the DC context, affect global validation, and can have their 11621 * commit work done in parallel with other commits not touching 11622 * the same resource. If we have a new DC context as part of 11623 * the DM atomic state from validation we need to free it and 11624 * retain the existing one instead. 11625 * 11626 * Furthermore, since the DM atomic state only contains the DC 11627 * context and can safely be annulled, we can free the state 11628 * and clear the associated private object now to free 11629 * some memory and avoid a possible use-after-free later. 11630 */ 11631 11632 for (i = 0; i < state->num_private_objs; i++) { 11633 struct drm_private_obj *obj = state->private_objs[i].ptr; 11634 11635 if (obj->funcs == adev->dm.atomic_obj.funcs) { 11636 int j = state->num_private_objs-1; 11637 11638 dm_atomic_destroy_state(obj, 11639 state->private_objs[i].state); 11640 11641 /* If i is not at the end of the array then the 11642 * last element needs to be moved to where i was 11643 * before the array can safely be truncated. 11644 */ 11645 if (i != j) 11646 state->private_objs[i] = 11647 state->private_objs[j]; 11648 11649 state->private_objs[j].ptr = NULL; 11650 state->private_objs[j].state = NULL; 11651 state->private_objs[j].old_state = NULL; 11652 state->private_objs[j].new_state = NULL; 11653 11654 state->num_private_objs = j; 11655 break; 11656 } 11657 } 11658 } 11659 11660 /* Store the overall update type for use later in atomic check. */ 11661 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 11662 struct dm_crtc_state *dm_new_crtc_state = 11663 to_dm_crtc_state(new_crtc_state); 11664 11665 /* 11666 * Only allow async flips for fast updates that don't change 11667 * the FB pitch, the DCC state, rotation, etc. 11668 */ 11669 if (new_crtc_state->async_flip && lock_and_validation_needed) { 11670 drm_dbg_atomic(crtc->dev, 11671 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 11672 crtc->base.id, crtc->name); 11673 ret = -EINVAL; 11674 goto fail; 11675 } 11676 11677 dm_new_crtc_state->update_type = lock_and_validation_needed ? 11678 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 11679 } 11680 11681 /* Must be success */ 11682 WARN_ON(ret); 11683 11684 trace_amdgpu_dm_atomic_check_finish(state, ret); 11685 11686 return ret; 11687 11688 fail: 11689 if (ret == -EDEADLK) 11690 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 11691 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 11692 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 11693 else 11694 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret); 11695 11696 trace_amdgpu_dm_atomic_check_finish(state, ret); 11697 11698 return ret; 11699 } 11700 11701 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm, 11702 unsigned int offset, 11703 unsigned int total_length, 11704 u8 *data, 11705 unsigned int length, 11706 struct amdgpu_hdmi_vsdb_info *vsdb) 11707 { 11708 bool res; 11709 union dmub_rb_cmd cmd; 11710 struct dmub_cmd_send_edid_cea *input; 11711 struct dmub_cmd_edid_cea_output *output; 11712 11713 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES) 11714 return false; 11715 11716 memset(&cmd, 0, sizeof(cmd)); 11717 11718 input = &cmd.edid_cea.data.input; 11719 11720 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA; 11721 cmd.edid_cea.header.sub_type = 0; 11722 cmd.edid_cea.header.payload_bytes = 11723 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header); 11724 input->offset = offset; 11725 input->length = length; 11726 input->cea_total_length = total_length; 11727 memcpy(input->payload, data, length); 11728 11729 res = dc_wake_and_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY); 11730 if (!res) { 11731 DRM_ERROR("EDID CEA parser failed\n"); 11732 return false; 11733 } 11734 11735 output = &cmd.edid_cea.data.output; 11736 11737 if (output->type == DMUB_CMD__EDID_CEA_ACK) { 11738 if (!output->ack.success) { 11739 DRM_ERROR("EDID CEA ack failed at offset %d\n", 11740 output->ack.offset); 11741 } 11742 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) { 11743 if (!output->amd_vsdb.vsdb_found) 11744 return false; 11745 11746 vsdb->freesync_supported = output->amd_vsdb.freesync_supported; 11747 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version; 11748 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate; 11749 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate; 11750 } else { 11751 DRM_WARN("Unknown EDID CEA parser results\n"); 11752 return false; 11753 } 11754 11755 return true; 11756 } 11757 11758 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm, 11759 u8 *edid_ext, int len, 11760 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11761 { 11762 int i; 11763 11764 /* send extension block to DMCU for parsing */ 11765 for (i = 0; i < len; i += 8) { 11766 bool res; 11767 int offset; 11768 11769 /* send 8 bytes a time */ 11770 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8)) 11771 return false; 11772 11773 if (i+8 == len) { 11774 /* EDID block sent completed, expect result */ 11775 int version, min_rate, max_rate; 11776 11777 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate); 11778 if (res) { 11779 /* amd vsdb found */ 11780 vsdb_info->freesync_supported = 1; 11781 vsdb_info->amd_vsdb_version = version; 11782 vsdb_info->min_refresh_rate_hz = min_rate; 11783 vsdb_info->max_refresh_rate_hz = max_rate; 11784 return true; 11785 } 11786 /* not amd vsdb */ 11787 return false; 11788 } 11789 11790 /* check for ack*/ 11791 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset); 11792 if (!res) 11793 return false; 11794 } 11795 11796 return false; 11797 } 11798 11799 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm, 11800 u8 *edid_ext, int len, 11801 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11802 { 11803 int i; 11804 11805 /* send extension block to DMCU for parsing */ 11806 for (i = 0; i < len; i += 8) { 11807 /* send 8 bytes a time */ 11808 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info)) 11809 return false; 11810 } 11811 11812 return vsdb_info->freesync_supported; 11813 } 11814 11815 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, 11816 u8 *edid_ext, int len, 11817 struct amdgpu_hdmi_vsdb_info *vsdb_info) 11818 { 11819 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 11820 bool ret; 11821 11822 mutex_lock(&adev->dm.dc_lock); 11823 if (adev->dm.dmub_srv) 11824 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info); 11825 else 11826 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info); 11827 mutex_unlock(&adev->dm.dc_lock); 11828 return ret; 11829 } 11830 11831 static void parse_edid_displayid_vrr(struct drm_connector *connector, 11832 struct edid *edid) 11833 { 11834 u8 *edid_ext = NULL; 11835 int i; 11836 int j = 0; 11837 u16 min_vfreq; 11838 u16 max_vfreq; 11839 11840 if (edid == NULL || edid->extensions == 0) 11841 return; 11842 11843 /* Find DisplayID extension */ 11844 for (i = 0; i < edid->extensions; i++) { 11845 edid_ext = (void *)(edid + (i + 1)); 11846 if (edid_ext[0] == DISPLAYID_EXT) 11847 break; 11848 } 11849 11850 if (edid_ext == NULL) 11851 return; 11852 11853 while (j < EDID_LENGTH) { 11854 /* Get dynamic video timing range from DisplayID if available */ 11855 if (EDID_LENGTH - j > 13 && edid_ext[j] == 0x25 && 11856 (edid_ext[j+1] & 0xFE) == 0 && (edid_ext[j+2] == 9)) { 11857 min_vfreq = edid_ext[j+9]; 11858 if (edid_ext[j+1] & 7) 11859 max_vfreq = edid_ext[j+10] + ((edid_ext[j+11] & 3) << 8); 11860 else 11861 max_vfreq = edid_ext[j+10]; 11862 11863 if (max_vfreq && min_vfreq) { 11864 connector->display_info.monitor_range.max_vfreq = max_vfreq; 11865 connector->display_info.monitor_range.min_vfreq = min_vfreq; 11866 11867 return; 11868 } 11869 } 11870 j++; 11871 } 11872 } 11873 11874 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11875 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11876 { 11877 u8 *edid_ext = NULL; 11878 int i; 11879 int j = 0; 11880 11881 if (edid == NULL || edid->extensions == 0) 11882 return -ENODEV; 11883 11884 /* Find DisplayID extension */ 11885 for (i = 0; i < edid->extensions; i++) { 11886 edid_ext = (void *)(edid + (i + 1)); 11887 if (edid_ext[0] == DISPLAYID_EXT) 11888 break; 11889 } 11890 11891 while (j < EDID_LENGTH) { 11892 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; 11893 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); 11894 11895 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && 11896 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { 11897 vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; 11898 vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; 11899 DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); 11900 11901 return true; 11902 } 11903 j++; 11904 } 11905 11906 return false; 11907 } 11908 11909 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, 11910 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) 11911 { 11912 u8 *edid_ext = NULL; 11913 int i; 11914 bool valid_vsdb_found = false; 11915 11916 /*----- drm_find_cea_extension() -----*/ 11917 /* No EDID or EDID extensions */ 11918 if (edid == NULL || edid->extensions == 0) 11919 return -ENODEV; 11920 11921 /* Find CEA extension */ 11922 for (i = 0; i < edid->extensions; i++) { 11923 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1); 11924 if (edid_ext[0] == CEA_EXT) 11925 break; 11926 } 11927 11928 if (i == edid->extensions) 11929 return -ENODEV; 11930 11931 /*----- cea_db_offsets() -----*/ 11932 if (edid_ext[0] != CEA_EXT) 11933 return -ENODEV; 11934 11935 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info); 11936 11937 return valid_vsdb_found ? i : -ENODEV; 11938 } 11939 11940 /** 11941 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities 11942 * 11943 * @connector: Connector to query. 11944 * @edid: EDID from monitor 11945 * 11946 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep 11947 * track of some of the display information in the internal data struct used by 11948 * amdgpu_dm. This function checks which type of connector we need to set the 11949 * FreeSync parameters. 11950 */ 11951 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 11952 struct edid *edid) 11953 { 11954 int i = 0; 11955 struct detailed_timing *timing; 11956 struct detailed_non_pixel *data; 11957 struct detailed_data_monitor_range *range; 11958 struct amdgpu_dm_connector *amdgpu_dm_connector = 11959 to_amdgpu_dm_connector(connector); 11960 struct dm_connector_state *dm_con_state = NULL; 11961 struct dc_sink *sink; 11962 11963 struct amdgpu_device *adev = drm_to_adev(connector->dev); 11964 struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; 11965 bool freesync_capable = false; 11966 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; 11967 11968 if (!connector->state) { 11969 DRM_ERROR("%s - Connector has no state", __func__); 11970 goto update; 11971 } 11972 11973 sink = amdgpu_dm_connector->dc_sink ? 11974 amdgpu_dm_connector->dc_sink : 11975 amdgpu_dm_connector->dc_em_sink; 11976 11977 if (!edid || !sink) { 11978 dm_con_state = to_dm_connector_state(connector->state); 11979 11980 amdgpu_dm_connector->min_vfreq = 0; 11981 amdgpu_dm_connector->max_vfreq = 0; 11982 connector->display_info.monitor_range.min_vfreq = 0; 11983 connector->display_info.monitor_range.max_vfreq = 0; 11984 freesync_capable = false; 11985 11986 goto update; 11987 } 11988 11989 dm_con_state = to_dm_connector_state(connector->state); 11990 11991 if (!adev->dm.freesync_module) 11992 goto update; 11993 11994 /* Some eDP panels only have the refresh rate range info in DisplayID */ 11995 if ((connector->display_info.monitor_range.min_vfreq == 0 || 11996 connector->display_info.monitor_range.max_vfreq == 0)) 11997 parse_edid_displayid_vrr(connector, edid); 11998 11999 if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || 12000 sink->sink_signal == SIGNAL_TYPE_EDP)) { 12001 bool edid_check_required = false; 12002 12003 if (amdgpu_dm_connector->dc_link && 12004 amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { 12005 if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { 12006 amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; 12007 amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; 12008 if (amdgpu_dm_connector->max_vfreq - 12009 amdgpu_dm_connector->min_vfreq > 10) 12010 freesync_capable = true; 12011 } else { 12012 edid_check_required = edid->version > 1 || 12013 (edid->version == 1 && 12014 edid->revision > 1); 12015 } 12016 } 12017 12018 if (edid_check_required) { 12019 for (i = 0; i < 4; i++) { 12020 12021 timing = &edid->detailed_timings[i]; 12022 data = &timing->data.other_data; 12023 range = &data->data.range; 12024 /* 12025 * Check if monitor has continuous frequency mode 12026 */ 12027 if (data->type != EDID_DETAIL_MONITOR_RANGE) 12028 continue; 12029 /* 12030 * Check for flag range limits only. If flag == 1 then 12031 * no additional timing information provided. 12032 * Default GTF, GTF Secondary curve and CVT are not 12033 * supported 12034 */ 12035 if (range->flags != 1) 12036 continue; 12037 12038 connector->display_info.monitor_range.min_vfreq = range->min_vfreq; 12039 connector->display_info.monitor_range.max_vfreq = range->max_vfreq; 12040 12041 if (edid->revision >= 4) { 12042 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 12043 connector->display_info.monitor_range.min_vfreq += 255; 12044 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 12045 connector->display_info.monitor_range.max_vfreq += 255; 12046 } 12047 12048 amdgpu_dm_connector->min_vfreq = 12049 connector->display_info.monitor_range.min_vfreq; 12050 amdgpu_dm_connector->max_vfreq = 12051 connector->display_info.monitor_range.max_vfreq; 12052 12053 break; 12054 } 12055 12056 if (amdgpu_dm_connector->max_vfreq - 12057 amdgpu_dm_connector->min_vfreq > 10) { 12058 12059 freesync_capable = true; 12060 } 12061 } 12062 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 12063 12064 if (vsdb_info.replay_mode) { 12065 amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode; 12066 amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version; 12067 amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; 12068 } 12069 12070 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { 12071 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 12072 if (i >= 0 && vsdb_info.freesync_supported) { 12073 timing = &edid->detailed_timings[i]; 12074 data = &timing->data.other_data; 12075 12076 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 12077 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 12078 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 12079 freesync_capable = true; 12080 12081 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 12082 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 12083 } 12084 } 12085 12086 if (amdgpu_dm_connector->dc_link) 12087 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link); 12088 12089 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) { 12090 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); 12091 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) { 12092 12093 amdgpu_dm_connector->pack_sdp_v1_3 = true; 12094 amdgpu_dm_connector->as_type = as_type; 12095 amdgpu_dm_connector->vsdb_info = vsdb_info; 12096 12097 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; 12098 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; 12099 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) 12100 freesync_capable = true; 12101 12102 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; 12103 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; 12104 } 12105 } 12106 12107 update: 12108 if (dm_con_state) 12109 dm_con_state->freesync_capable = freesync_capable; 12110 12111 if (connector->state && amdgpu_dm_connector->dc_link && !freesync_capable && 12112 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported) { 12113 amdgpu_dm_connector->dc_link->replay_settings.config.replay_supported = false; 12114 amdgpu_dm_connector->dc_link->replay_settings.replay_feature_enabled = false; 12115 } 12116 12117 if (connector->vrr_capable_property) 12118 drm_connector_set_vrr_capable_property(connector, 12119 freesync_capable); 12120 } 12121 12122 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 12123 { 12124 struct amdgpu_device *adev = drm_to_adev(dev); 12125 struct dc *dc = adev->dm.dc; 12126 int i; 12127 12128 mutex_lock(&adev->dm.dc_lock); 12129 if (dc->current_state) { 12130 for (i = 0; i < dc->current_state->stream_count; ++i) 12131 dc->current_state->streams[i] 12132 ->triggered_crtc_reset.enabled = 12133 adev->dm.force_timing_sync; 12134 12135 dm_enable_per_frame_crtc_master_sync(dc->current_state); 12136 dc_trigger_sync(dc, dc->current_state); 12137 } 12138 mutex_unlock(&adev->dm.dc_lock); 12139 } 12140 12141 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 12142 { 12143 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 12144 dc_exit_ips_for_hw_access(dc); 12145 } 12146 12147 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 12148 u32 value, const char *func_name) 12149 { 12150 #ifdef DM_CHECK_ADDR_0 12151 if (address == 0) { 12152 drm_err(adev_to_drm(ctx->driver_context), 12153 "invalid register write. address = 0"); 12154 return; 12155 } 12156 #endif 12157 12158 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 12159 cgs_write_register(ctx->cgs_device, address, value); 12160 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 12161 } 12162 12163 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 12164 const char *func_name) 12165 { 12166 u32 value; 12167 #ifdef DM_CHECK_ADDR_0 12168 if (address == 0) { 12169 drm_err(adev_to_drm(ctx->driver_context), 12170 "invalid register read; address = 0\n"); 12171 return 0; 12172 } 12173 #endif 12174 12175 if (ctx->dmub_srv && 12176 ctx->dmub_srv->reg_helper_offload.gather_in_progress && 12177 !ctx->dmub_srv->reg_helper_offload.should_burst_write) { 12178 ASSERT(false); 12179 return 0; 12180 } 12181 12182 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 12183 12184 value = cgs_read_register(ctx->cgs_device, address); 12185 12186 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 12187 12188 return value; 12189 } 12190 12191 int amdgpu_dm_process_dmub_aux_transfer_sync( 12192 struct dc_context *ctx, 12193 unsigned int link_index, 12194 struct aux_payload *payload, 12195 enum aux_return_code_type *operation_result) 12196 { 12197 struct amdgpu_device *adev = ctx->driver_context; 12198 struct dmub_notification *p_notify = adev->dm.dmub_notify; 12199 int ret = -1; 12200 12201 mutex_lock(&adev->dm.dpia_aux_lock); 12202 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) { 12203 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE; 12204 goto out; 12205 } 12206 12207 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 12208 DRM_ERROR("wait_for_completion_timeout timeout!"); 12209 *operation_result = AUX_RET_ERROR_TIMEOUT; 12210 goto out; 12211 } 12212 12213 if (p_notify->result != AUX_RET_SUCCESS) { 12214 /* 12215 * Transient states before tunneling is enabled could 12216 * lead to this error. We can ignore this for now. 12217 */ 12218 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) { 12219 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n", 12220 payload->address, payload->length, 12221 p_notify->result); 12222 } 12223 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 12224 goto out; 12225 } 12226 12227 12228 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command; 12229 if (!payload->write && p_notify->aux_reply.length && 12230 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) { 12231 12232 if (payload->length != p_notify->aux_reply.length) { 12233 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n", 12234 p_notify->aux_reply.length, 12235 payload->address, payload->length); 12236 *operation_result = AUX_RET_ERROR_INVALID_REPLY; 12237 goto out; 12238 } 12239 12240 memcpy(payload->data, p_notify->aux_reply.data, 12241 p_notify->aux_reply.length); 12242 } 12243 12244 /* success */ 12245 ret = p_notify->aux_reply.length; 12246 *operation_result = p_notify->result; 12247 out: 12248 reinit_completion(&adev->dm.dmub_aux_transfer_done); 12249 mutex_unlock(&adev->dm.dpia_aux_lock); 12250 return ret; 12251 } 12252 12253 int amdgpu_dm_process_dmub_set_config_sync( 12254 struct dc_context *ctx, 12255 unsigned int link_index, 12256 struct set_config_cmd_payload *payload, 12257 enum set_config_status *operation_result) 12258 { 12259 struct amdgpu_device *adev = ctx->driver_context; 12260 bool is_cmd_complete; 12261 int ret; 12262 12263 mutex_lock(&adev->dm.dpia_aux_lock); 12264 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc, 12265 link_index, payload, adev->dm.dmub_notify); 12266 12267 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) { 12268 ret = 0; 12269 *operation_result = adev->dm.dmub_notify->sc_status; 12270 } else { 12271 DRM_ERROR("wait_for_completion_timeout timeout!"); 12272 ret = -1; 12273 *operation_result = SET_CONFIG_UNKNOWN_ERROR; 12274 } 12275 12276 if (!is_cmd_complete) 12277 reinit_completion(&adev->dm.dmub_aux_transfer_done); 12278 mutex_unlock(&adev->dm.dpia_aux_lock); 12279 return ret; 12280 } 12281 12282 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 12283 { 12284 return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type); 12285 } 12286 12287 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type) 12288 { 12289 return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type); 12290 } 12291