1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "dc/dc_state.h" 42 #include "amdgpu_dm_trace.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_dm_wb.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 #include "amdgpu_dm_replay.h" 69 #include "amdgpu_dm_backlight.h" 70 #include "amdgpu_dm_audio.h" 71 #include "amdgpu_dm_dmub.h" 72 #include "amdgpu_dm_connector.h" 73 #include "amdgpu_dm_kunit_helpers.h" 74 75 #include "ivsrcid/ivsrcid_vislands30.h" 76 77 #include <linux/backlight.h> 78 #include <linux/module.h> 79 #include <linux/moduleparam.h> 80 #include <linux/types.h> 81 #include <linux/pm_runtime.h> 82 #include <linux/pci.h> 83 #include <linux/power_supply.h> 84 #include <linux/firmware.h> 85 #include <linux/component.h> 86 #include <linux/sort.h> 87 88 #include <drm/drm_privacy_screen_consumer.h> 89 #include <drm/display/drm_dp_mst_helper.h> 90 #include <drm/display/drm_hdmi_helper.h> 91 #include <drm/drm_atomic.h> 92 #include <drm/drm_atomic_uapi.h> 93 #include <drm/drm_atomic_helper.h> 94 #include <drm/drm_blend.h> 95 #include <drm/drm_fixed.h> 96 #include <drm/drm_fourcc.h> 97 #include <drm/drm_edid.h> 98 #include <drm/drm_eld.h> 99 #include <drm/drm_mode.h> 100 #include <drm/drm_utils.h> 101 #include <drm/drm_vblank.h> 102 #include <drm/drm_colorop.h> 103 #include <drm/drm_gem_atomic_helper.h> 104 105 #include <media/cec-notifier.h> 106 #include <acpi/video.h> 107 108 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 109 110 #include "modules/inc/mod_freesync.h" 111 #include "modules/inc/mod_power.h" 112 #include "modules/power/power_helpers.h" 113 114 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 115 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 116 117 /** 118 * DOC: overview 119 * 120 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 121 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 122 * requests into DC requests, and DC responses into DRM responses. 123 * 124 * The root control structure is &struct amdgpu_display_manager. 125 */ 126 127 /* basic init/fini API */ 128 static int amdgpu_dm_init(struct amdgpu_device *adev); 129 static void amdgpu_dm_fini(struct amdgpu_device *adev); 130 static void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state); 131 132 /* 133 * initializes drm_device display related structures, based on the information 134 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 135 * drm_encoder, drm_mode_config 136 * 137 * Returns 0 on success 138 */ 139 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 140 /* removes and deallocates the drm structures, created by the above function */ 141 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 142 143 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 144 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 145 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 146 147 static int amdgpu_dm_atomic_check(struct drm_device *dev, 148 struct drm_atomic_commit *state); 149 150 STATIC_IFN_KUNIT bool 151 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 152 struct drm_crtc_state *new_crtc_state); 153 154 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 155 { 156 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 157 dc_exit_ips_for_hw_access(dc); 158 } 159 160 /* 161 * dm_vblank_get_counter 162 * 163 * @brief 164 * Get counter for number of vertical blanks 165 * 166 * @param 167 * struct amdgpu_device *adev - [in] desired amdgpu device 168 * int disp_idx - [in] which CRTC to get the counter from 169 * 170 * @return 171 * Counter for vertical blanks 172 */ 173 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 174 { 175 struct amdgpu_crtc *acrtc = NULL; 176 177 if (crtc >= adev->mode_info.num_crtc) 178 return 0; 179 180 acrtc = adev->mode_info.crtcs[crtc]; 181 182 if (!acrtc->dm_irq_params.stream) { 183 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 184 crtc); 185 return 0; 186 } 187 188 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 189 } 190 191 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 192 u32 *vbl, u32 *position) 193 { 194 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 195 struct amdgpu_crtc *acrtc = NULL; 196 struct dc *dc = adev->dm.dc; 197 198 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 199 return -EINVAL; 200 201 acrtc = adev->mode_info.crtcs[crtc]; 202 203 if (!acrtc->dm_irq_params.stream) { 204 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 205 crtc); 206 return 0; 207 } 208 209 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 210 dc_allow_idle_optimizations(dc, false); 211 212 /* 213 * TODO rework base driver to use values directly. 214 * for now parse it back into reg-format 215 */ 216 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 217 &v_blank_start, 218 &v_blank_end, 219 &h_position, 220 &v_position); 221 222 *position = v_position | (h_position << 16); 223 *vbl = v_blank_start | (v_blank_end << 16); 224 225 return 0; 226 } 227 228 static bool dm_is_idle(struct amdgpu_ip_block *ip_block) 229 { 230 /* XXX todo */ 231 return true; 232 } 233 234 static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 235 { 236 /* XXX todo */ 237 return 0; 238 } 239 240 static int dm_soft_reset(struct amdgpu_ip_block *ip_block) 241 { 242 /* XXX todo */ 243 return 0; 244 } 245 246 STATIC_IFN_KUNIT bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 247 struct dm_crtc_state *new_state) 248 { 249 if (new_state->stream->adjust.timing_adjust_pending) 250 return true; 251 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 252 return true; 253 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 254 return true; 255 else 256 return false; 257 } 258 EXPORT_IF_KUNIT(is_dc_timing_adjust_needed); 259 260 /* 261 * DC will program planes with their z-order determined by their ordering 262 * in the dc_surface_updates array. This comparator is used to sort them 263 * by descending zpos. 264 */ 265 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 266 { 267 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 268 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 269 270 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 271 return sb->surface->layer_index - sa->surface->layer_index; 272 } 273 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 274 275 /** 276 * update_planes_and_stream_adapter() - Send planes to be updated in DC 277 * 278 * DC has a generic way to update planes and stream via 279 * dc_update_planes_and_stream function; however, DM might need some 280 * adjustments and preparation before calling it. This function is a wrapper 281 * for the dc_update_planes_and_stream that does any required configuration 282 * before passing control to DC. 283 * 284 * @dc: Display Core control structure 285 * @update_type: specify whether it is FULL/MEDIUM/FAST update 286 * @planes_count: planes count to update 287 * @stream: stream state 288 * @stream_update: stream update 289 * @array_of_surface_update: dc surface update pointer 290 * 291 */ 292 static inline bool update_planes_and_stream_adapter(struct dc *dc, 293 int update_type, 294 int planes_count, 295 struct dc_stream_state *stream, 296 struct dc_stream_update *stream_update, 297 struct dc_surface_update *array_of_surface_update) 298 { 299 sort(array_of_surface_update, planes_count, 300 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 301 302 /* 303 * Previous frame finished and HW is ready for optimization. 304 */ 305 dc_post_update_surfaces_to_stream(dc); 306 307 return dc_update_planes_and_stream(dc, 308 array_of_surface_update, 309 planes_count, 310 stream, 311 stream_update); 312 } 313 314 static int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 315 enum amd_clockgating_state state) 316 { 317 return 0; 318 } 319 320 static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 321 enum amd_powergating_state state) 322 { 323 return 0; 324 } 325 326 /* Prototypes of private functions */ 327 static int dm_early_init(struct amdgpu_ip_block *ip_block); 328 329 /* Allocate memory for FBC compressed data */ 330 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 331 { 332 u64 pt_base; 333 u32 logical_addr_low; 334 u32 logical_addr_high; 335 u32 agp_base, agp_bot, agp_top; 336 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 337 338 memset(pa_config, 0, sizeof(*pa_config)); 339 340 agp_base = 0; 341 agp_bot = adev->gmc.agp_start >> 24; 342 agp_top = adev->gmc.agp_end >> 24; 343 344 /* AGP aperture is disabled */ 345 if (agp_bot > agp_top) { 346 logical_addr_low = adev->gmc.fb_start >> 18; 347 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 348 AMD_APU_IS_RENOIR | 349 AMD_APU_IS_GREEN_SARDINE)) 350 /* 351 * Raven2 has a HW issue that it is unable to use the vram which 352 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 353 * workaround that increase system aperture high address (add 1) 354 * to get rid of the VM fault and hardware hang. 355 */ 356 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 357 else 358 logical_addr_high = adev->gmc.fb_end >> 18; 359 } else { 360 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 361 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 362 AMD_APU_IS_RENOIR | 363 AMD_APU_IS_GREEN_SARDINE)) 364 /* 365 * Raven2 has a HW issue that it is unable to use the vram which 366 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 367 * workaround that increase system aperture high address (add 1) 368 * to get rid of the VM fault and hardware hang. 369 */ 370 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 371 else 372 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 373 } 374 375 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 376 377 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 378 AMDGPU_GPU_PAGE_SHIFT); 379 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 380 AMDGPU_GPU_PAGE_SHIFT); 381 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 382 AMDGPU_GPU_PAGE_SHIFT); 383 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 384 AMDGPU_GPU_PAGE_SHIFT); 385 page_table_base.high_part = upper_32_bits(pt_base); 386 page_table_base.low_part = lower_32_bits(pt_base); 387 388 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 389 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 390 391 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 392 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 393 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 394 395 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 396 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 397 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 398 399 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 400 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 401 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 402 403 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 404 405 } 406 407 struct amdgpu_stutter_quirk { 408 u16 chip_vendor; 409 u16 chip_device; 410 u16 subsys_vendor; 411 u16 subsys_device; 412 u8 revision; 413 }; 414 415 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 416 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 417 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 418 { 0, 0, 0, 0, 0 }, 419 }; 420 421 static bool dm_should_disable_stutter(struct pci_dev *pdev) 422 { 423 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 424 425 while (p && p->chip_device != 0) { 426 if (pdev->vendor == p->chip_vendor && 427 pdev->device == p->chip_device && 428 pdev->subsystem_vendor == p->subsys_vendor && 429 pdev->subsystem_device == p->subsys_device && 430 pdev->revision == p->revision) { 431 return true; 432 } 433 ++p; 434 } 435 return false; 436 } 437 438 439 void* 440 dm_allocate_gpu_mem( 441 struct amdgpu_device *adev, 442 enum dc_gpu_mem_alloc_type type, 443 size_t size, 444 long long *addr) 445 { 446 struct dal_allocation *da; 447 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 448 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 449 int ret; 450 451 da = kzalloc_obj(struct dal_allocation); 452 if (!da) 453 return NULL; 454 455 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 456 domain, &da->bo, 457 &da->gpu_addr, &da->cpu_ptr); 458 459 *addr = da->gpu_addr; 460 461 if (ret) { 462 kfree(da); 463 return NULL; 464 } 465 466 /* add da to list in dm */ 467 list_add(&da->list, &adev->dm.da_list); 468 469 return da->cpu_ptr; 470 } 471 472 void 473 dm_free_gpu_mem( 474 struct amdgpu_device *adev, 475 enum dc_gpu_mem_alloc_type type, 476 void *pvMem) 477 { 478 struct dal_allocation *da; 479 480 /* walk the da list in DM */ 481 list_for_each_entry(da, &adev->dm.da_list, list) { 482 if (pvMem == da->cpu_ptr) { 483 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 484 list_del(&da->list); 485 kfree(da); 486 break; 487 } 488 } 489 490 } 491 492 static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 493 { 494 struct mod_power_init_params init_data[MAX_NUM_EDP]; 495 496 if (dm->num_of_edps == 0) { 497 drm_dbg_driver( 498 dm->ddev, 499 "amdgpu: No eDP detected, skip initializing power module\n"); 500 return 0; 501 } 502 503 /* Initialize all the power module parameters */ 504 for (int i = 0; i < dm->num_of_edps; i++) { 505 init_data[i].allow_psr_smu_optimizations = 506 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 507 init_data[i].allow_psr_multi_disp_optimizations = 508 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 509 /* See dm_late_init */ 510 init_data[i].backlight_ramping_override = false; 511 init_data[i].backlight_ramping_start = 0xCCCC; 512 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 513 init_data[i].def_varibright_level = 0; 514 init_data[i].abm_config_setting = 0; 515 init_data[i].num_backlight_levels = 101; 516 init_data[i].use_nits_based_brightness = false; 517 init_data[i].panel_max_millinits = 0; 518 init_data[i].panel_min_millinits = 0; 519 init_data[i].disable_fractional_pwm = 520 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 521 init_data[i].use_custom_backlight_caps = false; 522 init_data[i].custom_backlight_caps_config_no = 0; 523 init_data[i].use_linear_backlight_curve = false; 524 init_data[i].def_varibright_enable = 0; 525 init_data[i].varibright_level = 0; 526 /* 527 * Power module uses 16-bit backlight levels (0xFFFF max) rather 528 * than 8-bit(0XFF max) 529 */ 530 init_data[i].min_backlight_pwm = 531 dm->backlight_caps[i].min_input_signal * 0x101; 532 init_data[i].max_backlight_pwm = 533 dm->backlight_caps[i].max_input_signal * 0x101; 534 init_data[i].min_abm_backlight = 535 dm->backlight_caps[i].min_input_signal * 0x101; 536 537 /* Min backlight level after ABM reduction, Don't allow below 1% 538 * 0xFFFF x 0.01 = 0x28F 539 */ 540 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 541 0x28F : init_data[i].min_abm_backlight; 542 } 543 544 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 545 if (!dm->power_module) { 546 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 547 return -ENOMEM; 548 } 549 550 mod_power_hw_init(dm->power_module); 551 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 552 553 return 0; 554 } 555 556 static int amdgpu_dm_init(struct amdgpu_device *adev) 557 { 558 struct dc_init_data init_data; 559 struct dc_callback_init init_params; 560 int r; 561 562 adev->dm.ddev = adev_to_drm(adev); 563 adev->dm.adev = adev; 564 565 /* Zero all the fields */ 566 memset(&init_data, 0, sizeof(init_data)); 567 memset(&init_params, 0, sizeof(init_params)); 568 569 mutex_init(&adev->dm.dpia_aux_lock); 570 mutex_init(&adev->dm.dc_lock); 571 mutex_init(&adev->dm.audio_lock); 572 573 spin_lock_init(&adev->dm.dmub_lock); 574 575 if (amdgpu_dm_irq_init(adev)) { 576 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 577 goto error; 578 } 579 580 /* special handling for early revisions of GC 11.5.4 */ 581 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 582 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 583 else 584 init_data.asic_id.chip_family = adev->family; 585 586 init_data.asic_id.pci_revision_id = adev->pdev->revision; 587 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 588 init_data.asic_id.chip_id = adev->pdev->device; 589 590 init_data.asic_id.vram_width = adev->gmc.vram_width; 591 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 592 init_data.asic_id.atombios_base_address = 593 adev->mode_info.atom_context->bios; 594 595 init_data.driver = adev; 596 597 /* cgs_device was created in dm_sw_init() */ 598 init_data.cgs_device = adev->dm.cgs_device; 599 600 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 601 602 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 603 case IP_VERSION(2, 1, 0): 604 switch (adev->dm.dmcub_fw_version) { 605 case 0: /* development */ 606 case 0x1: /* linux-firmware.git hash 6d9f399 */ 607 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 608 init_data.flags.disable_dmcu = false; 609 break; 610 default: 611 init_data.flags.disable_dmcu = true; 612 } 613 break; 614 case IP_VERSION(2, 0, 3): 615 init_data.flags.disable_dmcu = true; 616 break; 617 default: 618 break; 619 } 620 621 /* APU support S/G display by default except: 622 * ASICs before Carrizo, 623 * RAVEN1 (Users reported stability issue) 624 */ 625 626 if (adev->asic_type < CHIP_CARRIZO) { 627 init_data.flags.gpu_vm_support = false; 628 } else if (adev->asic_type == CHIP_RAVEN) { 629 if (adev->apu_flags & AMD_APU_IS_RAVEN) 630 init_data.flags.gpu_vm_support = false; 631 else 632 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 633 } else { 634 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 635 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 636 else 637 init_data.flags.gpu_vm_support = 638 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 639 } 640 641 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 642 643 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 644 init_data.flags.fbc_support = true; 645 646 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 647 init_data.flags.multi_mon_pp_mclk_switch = true; 648 649 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 650 init_data.flags.disable_fractional_pwm = true; 651 652 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 653 init_data.flags.edp_no_power_sequencing = true; 654 655 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 656 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 657 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 658 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 659 660 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 661 init_data.flags.enable_frl = true; 662 663 init_data.flags.seamless_boot_edp_requested = false; 664 665 if (amdgpu_device_seamless_boot_supported(adev)) { 666 init_data.flags.seamless_boot_edp_requested = true; 667 init_data.flags.allow_seamless_boot_optimization = true; 668 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 669 } 670 671 init_data.flags.enable_mipi_converter_optimization = true; 672 673 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 674 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 675 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 676 677 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 678 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 679 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 680 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 681 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 682 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 683 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 684 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 685 else 686 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 687 688 init_data.flags.disable_ips_in_vpb = 0; 689 690 /* DCN35 and above supports dynamic DTBCLK switch */ 691 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 692 init_data.flags.allow_0_dtb_clk = true; 693 694 /* Enable DWB for tested platforms only */ 695 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 696 init_data.num_virtual_links = 1; 697 698 /* DCN42 and above dpia switch to unified link training path */ 699 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 700 init_data.flags.consolidated_dpia_dp_lt = true; 701 init_data.flags.enable_dpia_pre_training = true; 702 init_data.flags.unify_link_enc_assignment = true; 703 init_data.flags.usb4_bw_alloc_support = true; 704 } 705 retrieve_dmi_info(&adev->dm); 706 if (adev->dm.edp0_on_dp1_quirk) 707 init_data.flags.support_edp0_on_dp1 = true; 708 709 if (adev->dm.bb_from_dmub) 710 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 711 else 712 init_data.bb_from_dmub = NULL; 713 714 /* Display Core create. */ 715 adev->dm.dc = dc_create(&init_data); 716 717 if (adev->dm.dc) { 718 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 719 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 720 } else { 721 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 722 goto error; 723 } 724 725 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 726 adev->dm.dc->debug.force_single_disp_pipe_split = false; 727 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 728 } 729 730 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 731 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 732 if (dm_should_disable_stutter(adev->pdev)) 733 adev->dm.dc->debug.disable_stutter = true; 734 735 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 736 adev->dm.dc->debug.disable_stutter = true; 737 738 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 739 adev->dm.dc->debug.disable_dsc = true; 740 741 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 742 adev->dm.dc->debug.disable_clock_gate = true; 743 744 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 745 adev->dm.dc->debug.force_subvp_mclk_switch = true; 746 747 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 748 adev->dm.dc->debug.force_disable_subvp = true; 749 adev->dm.dc->debug.fams2_config.bits.enable = false; 750 } 751 752 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 753 adev->dm.dc->debug.using_dml2 = true; 754 adev->dm.dc->debug.using_dml21 = true; 755 } 756 757 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 758 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 759 760 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 761 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 762 763 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 764 adev->dm.dc->debug.skip_detection_link_training = true; 765 766 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 767 768 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 769 adev->dm.dc->debug.ignore_cable_id = true; 770 771 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 772 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 773 774 r = dm_dmub_hw_init(adev); 775 if (r) { 776 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 777 goto error; 778 } 779 780 dc_hardware_init(adev->dm.dc); 781 782 /* GOP/vBIOS may leave an OPTC enabled for a display present at power-on 783 * but no longer driven (e.g. an external DP unplugged at boot). Such a 784 * dangling pipe keeps DCN out of idle and blocks s0i3. Power it down 785 * here when nothing needs to be preserved. 786 */ 787 if (adev->flags & AMD_IS_APU) 788 dc_disable_dangling_timing_generators(adev->dm.dc); 789 790 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 791 if (!adev->dm.hpd_rx_offload_wq) { 792 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 793 goto error; 794 } 795 796 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 797 struct dc_phy_addr_space_config pa_config; 798 799 mmhub_read_system_context(adev, &pa_config); 800 801 // Call the DC init_memory func 802 dc_setup_system_context(adev->dm.dc, &pa_config); 803 } 804 805 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 806 if (!adev->dm.freesync_module) { 807 drm_err(adev_to_drm(adev), 808 "failed to initialize freesync_module.\n"); 809 } else 810 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 811 adev->dm.freesync_module); 812 813 amdgpu_dm_init_color_mod(); 814 815 if (adev->dm.dc->caps.max_links > 0) { 816 adev->dm.vblank_control_workqueue = 817 create_singlethread_workqueue("dm_vblank_control_workqueue"); 818 if (!adev->dm.vblank_control_workqueue) 819 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 820 } 821 822 if (adev->dm.dc->caps.ips_support && 823 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 824 adev->dm.idle_workqueue = idle_create_workqueue(adev); 825 826 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 827 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 828 829 if (!adev->dm.hdcp_workqueue) 830 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 831 else 832 drm_dbg_driver(adev_to_drm(adev), 833 "hdcp_workqueue init done %p.\n", 834 adev->dm.hdcp_workqueue); 835 836 dc_init_callbacks(adev->dm.dc, &init_params); 837 } 838 if (adev->dm.dc->caps.max_links > 0) { 839 adev->dm.hdmi_frl_status_polling_wq = 840 create_singlethread_workqueue("hdmi_frl_status_polling_workqueue"); 841 if (!adev->dm.hdmi_frl_status_polling_wq) 842 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_workqueue\n"); 843 } 844 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 845 init_completion(&adev->dm.dmub_aux_transfer_done); 846 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 847 if (!adev->dm.dmub_notify) { 848 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 849 goto error; 850 } 851 852 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 853 if (!adev->dm.delayed_hpd_wq) { 854 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 855 goto error; 856 } 857 858 amdgpu_dm_outbox_init(adev); 859 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 860 dm_dmub_aux_setconfig_callback, false)) { 861 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 862 goto error; 863 } 864 865 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 866 init_completion(&adev->dm.fused_io[i].replied); 867 868 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 869 dm_dmub_aux_fused_io_callback, false)) { 870 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 871 goto error; 872 } 873 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 874 * It is expected that DMUB will resend any pending notifications at this point. Note 875 * that hpd and hpd_irq handler registration are deferred to 876 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 877 * sequence. Connection status will be proactivly detected once in the 878 * amdgpu_dm_initialize_drm_device. 879 */ 880 dc_enable_dmub_outbox(adev->dm.dc); 881 882 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 883 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 884 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 885 } 886 887 if (amdgpu_dm_initialize_drm_device(adev)) { 888 drm_err(adev_to_drm(adev), 889 "failed to initialize sw for display support.\n"); 890 goto error; 891 } 892 893 if (amdgpu_dm_init_power_module(&adev->dm)) 894 goto error; 895 896 /* create fake encoders for MST */ 897 dm_dp_create_fake_mst_encoders(adev); 898 899 /* TODO: Add_display_info? */ 900 901 /* TODO use dynamic cursor width */ 902 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 903 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 904 905 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 906 drm_err(adev_to_drm(adev), 907 "failed to initialize vblank for display support.\n"); 908 goto error; 909 } 910 911 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 912 amdgpu_dm_crtc_secure_display_create_contexts(adev); 913 if (!adev->dm.secure_display_ctx.crtc_ctx) 914 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 915 916 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 917 adev->dm.secure_display_ctx.support_mul_roi = true; 918 919 #endif 920 921 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 922 923 return 0; 924 error: 925 amdgpu_dm_fini(adev); 926 927 return -EINVAL; 928 } 929 930 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 931 { 932 struct amdgpu_device *adev = ip_block->adev; 933 934 amdgpu_dm_audio_fini(adev); 935 936 return 0; 937 } 938 939 static void amdgpu_dm_fini(struct amdgpu_device *adev) 940 { 941 int i; 942 943 if (adev->dm.vblank_control_workqueue) { 944 destroy_workqueue(adev->dm.vblank_control_workqueue); 945 adev->dm.vblank_control_workqueue = NULL; 946 } 947 948 if (adev->dm.idle_workqueue) { 949 if (adev->dm.idle_workqueue->running) { 950 adev->dm.idle_workqueue->enable = false; 951 flush_work(&adev->dm.idle_workqueue->work); 952 } 953 954 kfree(adev->dm.idle_workqueue); 955 adev->dm.idle_workqueue = NULL; 956 } 957 958 /* 959 * Disable ISM before dc_destroy() invalidates dm->dc. 960 * 961 * Quiesce workers first without dc_lock (they take dc_lock 962 * themselves, so syncing under it would deadlock), then drive the 963 * FSM back to FULL_POWER_RUNNING under dc_lock. 964 */ 965 amdgpu_dm_ism_disable(&adev->dm); 966 scoped_guard(mutex, &adev->dm.dc_lock) 967 amdgpu_dm_ism_force_full_power(&adev->dm); 968 969 amdgpu_dm_destroy_drm_device(&adev->dm); 970 971 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 972 if (adev->dm.secure_display_ctx.crtc_ctx) { 973 for (i = 0; i < adev->mode_info.num_crtc; i++) { 974 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 975 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 976 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 977 } 978 } 979 kfree(adev->dm.secure_display_ctx.crtc_ctx); 980 adev->dm.secure_display_ctx.crtc_ctx = NULL; 981 } 982 #endif 983 if (adev->dm.hdcp_workqueue) { 984 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 985 adev->dm.hdcp_workqueue = NULL; 986 } 987 988 if (adev->dm.dc) { 989 dc_deinit_callbacks(adev->dm.dc); 990 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 991 if (dc_enable_dmub_notifications(adev->dm.dc)) { 992 kfree(adev->dm.dmub_notify); 993 adev->dm.dmub_notify = NULL; 994 destroy_workqueue(adev->dm.delayed_hpd_wq); 995 adev->dm.delayed_hpd_wq = NULL; 996 } 997 } 998 999 if (adev->dm.dmub_bo) 1000 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1001 &adev->dm.dmub_bo_gpu_addr, 1002 &adev->dm.dmub_bo_cpu_addr); 1003 1004 if (adev->dm.boot_time_crc_info.bo_ptr) 1005 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 1006 &adev->dm.boot_time_crc_info.gpu_addr, 1007 &adev->dm.boot_time_crc_info.cpu_addr); 1008 1009 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 1010 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1011 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1012 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1013 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1014 } 1015 } 1016 1017 kfree(adev->dm.hpd_rx_offload_wq); 1018 adev->dm.hpd_rx_offload_wq = NULL; 1019 } 1020 1021 /* DC Destroy TODO: Replace destroy DAL */ 1022 if (adev->dm.dc) 1023 dc_destroy(&adev->dm.dc); 1024 /* 1025 * TODO: pageflip, vlank interrupt 1026 * 1027 * amdgpu_dm_irq_fini(adev); 1028 */ 1029 1030 if (adev->dm.cgs_device) { 1031 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1032 adev->dm.cgs_device = NULL; 1033 } 1034 if (adev->dm.freesync_module) { 1035 mod_freesync_destroy(adev->dm.freesync_module); 1036 adev->dm.freesync_module = NULL; 1037 } 1038 1039 if (adev->dm.power_module) { 1040 mod_power_destroy(adev->dm.power_module); 1041 adev->dm.power_module = NULL; 1042 } 1043 mutex_destroy(&adev->dm.audio_lock); 1044 mutex_destroy(&adev->dm.dc_lock); 1045 mutex_destroy(&adev->dm.dpia_aux_lock); 1046 } 1047 1048 static int load_dmcu_fw(struct amdgpu_device *adev) 1049 { 1050 const char *fw_name_dmcu = NULL; 1051 int r; 1052 const struct dmcu_firmware_header_v1_0 *hdr; 1053 1054 switch (adev->asic_type) { 1055 #if defined(CONFIG_DRM_AMD_DC_SI) 1056 case CHIP_TAHITI: 1057 case CHIP_PITCAIRN: 1058 case CHIP_VERDE: 1059 case CHIP_OLAND: 1060 #endif 1061 case CHIP_BONAIRE: 1062 case CHIP_HAWAII: 1063 case CHIP_KAVERI: 1064 case CHIP_KABINI: 1065 case CHIP_MULLINS: 1066 case CHIP_TONGA: 1067 case CHIP_FIJI: 1068 case CHIP_CARRIZO: 1069 case CHIP_STONEY: 1070 case CHIP_POLARIS11: 1071 case CHIP_POLARIS10: 1072 case CHIP_POLARIS12: 1073 case CHIP_VEGAM: 1074 case CHIP_VEGA10: 1075 case CHIP_VEGA12: 1076 case CHIP_VEGA20: 1077 return 0; 1078 case CHIP_NAVI12: 1079 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1080 break; 1081 case CHIP_RAVEN: 1082 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1083 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1084 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1085 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1086 else 1087 return 0; 1088 break; 1089 default: 1090 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1091 case IP_VERSION(2, 0, 2): 1092 case IP_VERSION(2, 0, 3): 1093 case IP_VERSION(2, 0, 0): 1094 case IP_VERSION(2, 1, 0): 1095 case IP_VERSION(3, 0, 0): 1096 case IP_VERSION(3, 0, 2): 1097 case IP_VERSION(3, 0, 3): 1098 case IP_VERSION(3, 0, 1): 1099 case IP_VERSION(3, 1, 2): 1100 case IP_VERSION(3, 1, 3): 1101 case IP_VERSION(3, 1, 4): 1102 case IP_VERSION(3, 1, 5): 1103 case IP_VERSION(3, 1, 6): 1104 case IP_VERSION(3, 2, 0): 1105 case IP_VERSION(3, 2, 1): 1106 case IP_VERSION(3, 5, 0): 1107 case IP_VERSION(3, 5, 1): 1108 case IP_VERSION(3, 6, 0): 1109 case IP_VERSION(4, 0, 1): 1110 case IP_VERSION(4, 2, 0): 1111 case IP_VERSION(4, 2, 1): 1112 return 0; 1113 default: 1114 break; 1115 } 1116 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1117 return -EINVAL; 1118 } 1119 1120 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1121 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1122 return 0; 1123 } 1124 1125 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1126 "%s", fw_name_dmcu); 1127 if (r == -ENODEV) { 1128 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1129 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1130 adev->dm.fw_dmcu = NULL; 1131 return 0; 1132 } 1133 if (r) { 1134 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1135 fw_name_dmcu); 1136 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1137 return r; 1138 } 1139 1140 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1141 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1142 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1143 adev->firmware.fw_size += 1144 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1145 1146 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1147 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1148 adev->firmware.fw_size += 1149 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1150 1151 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1152 1153 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1154 1155 return 0; 1156 } 1157 1158 static int dm_sw_init(struct amdgpu_ip_block *ip_block) 1159 { 1160 struct amdgpu_device *adev = ip_block->adev; 1161 int r; 1162 1163 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1164 1165 if (!adev->dm.cgs_device) { 1166 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1167 return -EINVAL; 1168 } 1169 1170 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1171 INIT_LIST_HEAD(&adev->dm.da_list); 1172 1173 r = dm_dmub_sw_init(adev); 1174 if (r) 1175 return r; 1176 1177 return load_dmcu_fw(adev); 1178 } 1179 1180 static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1181 { 1182 struct amdgpu_device *adev = ip_block->adev; 1183 struct dal_allocation *da; 1184 1185 list_for_each_entry(da, &adev->dm.da_list, list) { 1186 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1187 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1188 list_del(&da->list); 1189 kfree(da); 1190 adev->dm.bb_from_dmub = NULL; 1191 break; 1192 } 1193 } 1194 1195 1196 kfree(adev->dm.dmub_fb_info); 1197 adev->dm.dmub_fb_info = NULL; 1198 1199 if (adev->dm.dmub_srv) { 1200 dmub_srv_destroy(adev->dm.dmub_srv); 1201 kfree(adev->dm.dmub_srv); 1202 adev->dm.dmub_srv = NULL; 1203 } 1204 1205 amdgpu_ucode_release(&adev->dm.dmub_fw); 1206 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1207 1208 return 0; 1209 } 1210 1211 1212 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1213 { 1214 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1215 struct dmub_srv *dmub = NULL; 1216 union dmub_fw_boot_options option = {0}; 1217 int ret = 0; 1218 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1219 1220 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1221 !adev->dm.dc->ctx->dmub_srv) { 1222 return; 1223 } 1224 1225 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1226 bootcrc_info = &adev->dm.boot_time_crc_info; 1227 1228 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1229 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1230 return; 1231 } 1232 1233 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1234 1235 /* Return if boot time CRC is not enabled */ 1236 if (option.bits.bootcrc_en_at_S0i3 == 0) 1237 return; 1238 1239 /* Create a buffer for boot time CRC */ 1240 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1241 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1242 &bootcrc_info->bo_ptr, 1243 &bootcrc_info->gpu_addr, 1244 &bootcrc_info->cpu_addr); 1245 1246 if (ret) { 1247 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1248 } else { 1249 bootcrc_info->size = fb_size; 1250 1251 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1252 bootcrc_info->gpu_addr, bootcrc_info->size); 1253 1254 /* Send the buffer info to DMUB */ 1255 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1256 bootcrc_info->gpu_addr, bootcrc_info->size); 1257 } 1258 } 1259 1260 static int dm_late_init(struct amdgpu_ip_block *ip_block) 1261 { 1262 struct amdgpu_device *adev = ip_block->adev; 1263 1264 struct dmcu_iram_parameters params; 1265 unsigned int linear_lut[16]; 1266 int i; 1267 struct dmcu *dmcu = NULL; 1268 1269 dmcu = adev->dm.dc->res_pool->dmcu; 1270 1271 /* Init the boot time CRC (skip in resume) */ 1272 if ((adev->in_suspend == 0) && 1273 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1274 amdgpu_dm_boot_time_crc_init(adev); 1275 1276 for (i = 0; i < 16; i++) 1277 linear_lut[i] = 0xFFFF * i / 15; 1278 1279 params.set = 0; 1280 params.backlight_ramping_override = false; 1281 params.backlight_ramping_start = 0xCCCC; 1282 params.backlight_ramping_reduction = 0xCCCCCCCC; 1283 params.backlight_lut_array_size = 16; 1284 params.backlight_lut_array = linear_lut; 1285 1286 /* Min backlight level after ABM reduction, Don't allow below 1% 1287 * 0xFFFF x 0.01 = 0x28F 1288 */ 1289 params.min_abm_backlight = 0x28F; 1290 /* In the case where abm is implemented on dmcub, 1291 * dmcu object will be null. 1292 * ABM 2.4 and up are implemented on dmcub. 1293 */ 1294 if (dmcu) { 1295 if (!dmcu_load_iram(dmcu, params)) 1296 return -EINVAL; 1297 } else if (adev->dm.dc->ctx->dmub_srv) { 1298 struct dc_link *edp_links[MAX_NUM_EDP]; 1299 int edp_num; 1300 1301 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1302 for (i = 0; i < edp_num; i++) { 1303 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1304 return -EINVAL; 1305 } 1306 } 1307 1308 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1309 } 1310 1311 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1312 { 1313 u8 buf[UUID_SIZE]; 1314 guid_t guid; 1315 int ret; 1316 1317 mutex_lock(&mgr->lock); 1318 if (!mgr->mst_primary) 1319 goto out_fail; 1320 1321 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1322 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1323 goto out_fail; 1324 } 1325 1326 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1327 DP_MST_EN | 1328 DP_UP_REQ_EN | 1329 DP_UPSTREAM_IS_SRC); 1330 if (ret < 0) { 1331 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1332 goto out_fail; 1333 } 1334 1335 /* Some hubs forget their guids after they resume */ 1336 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1337 if (ret != sizeof(buf)) { 1338 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1339 goto out_fail; 1340 } 1341 1342 import_guid(&guid, buf); 1343 1344 if (guid_is_null(&guid)) { 1345 guid_gen(&guid); 1346 export_guid(buf, &guid); 1347 1348 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1349 1350 if (ret != sizeof(buf)) { 1351 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1352 goto out_fail; 1353 } 1354 } 1355 1356 guid_copy(&mgr->mst_primary->guid, &guid); 1357 1358 out_fail: 1359 mutex_unlock(&mgr->lock); 1360 } 1361 1362 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1363 { 1364 struct amdgpu_dm_connector *aconnector; 1365 struct drm_connector *connector; 1366 struct drm_connector_list_iter iter; 1367 struct drm_dp_mst_topology_mgr *mgr; 1368 1369 drm_connector_list_iter_begin(dev, &iter); 1370 drm_for_each_connector_iter(connector, &iter) { 1371 1372 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1373 continue; 1374 1375 aconnector = to_amdgpu_dm_connector(connector); 1376 if (aconnector->dc_link->type != dc_connection_mst_branch || 1377 aconnector->mst_root) 1378 continue; 1379 1380 mgr = &aconnector->mst_mgr; 1381 1382 if (suspend) { 1383 drm_dp_mst_topology_mgr_suspend(mgr); 1384 } else { 1385 /* if extended timeout is supported in hardware, 1386 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1387 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1388 */ 1389 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1390 if (!dp_is_lttpr_present(aconnector->dc_link)) 1391 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1392 1393 /* TODO: move resume_mst_branch_status() into drm mst resume again 1394 * once topology probing work is pulled out from mst resume into mst 1395 * resume 2nd step. mst resume 2nd step should be called after old 1396 * state getting restored (i.e. drm_atomic_helper_resume()). 1397 */ 1398 resume_mst_branch_status(mgr); 1399 } 1400 } 1401 drm_connector_list_iter_end(&iter); 1402 } 1403 1404 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 1405 { 1406 int ret = 0; 1407 1408 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 1409 * on window driver dc implementation. 1410 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 1411 * should be passed to smu during boot up and resume from s3. 1412 * boot up: dc calculate dcn watermark clock settings within dc_create, 1413 * dcn20_resource_construct 1414 * then call pplib functions below to pass the settings to smu: 1415 * smu_set_watermarks_for_clock_ranges 1416 * smu_set_watermarks_table 1417 * navi10_set_watermarks_table 1418 * smu_write_watermarks_table 1419 * 1420 * For Renoir, clock settings of dcn watermark are also fixed values. 1421 * dc has implemented different flow for window driver: 1422 * dc_hardware_init / dc_set_power_state 1423 * dcn10_init_hw 1424 * notify_wm_ranges 1425 * set_wm_ranges 1426 * -- Linux 1427 * smu_set_watermarks_for_clock_ranges 1428 * renoir_set_watermarks_table 1429 * smu_write_watermarks_table 1430 * 1431 * For Linux, 1432 * dc_hardware_init -> amdgpu_dm_init 1433 * dc_set_power_state --> dm_resume 1434 * 1435 * therefore, this function apply to navi10/12/14 but not Renoir 1436 * * 1437 */ 1438 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1439 case IP_VERSION(2, 0, 2): 1440 case IP_VERSION(2, 0, 0): 1441 break; 1442 default: 1443 return 0; 1444 } 1445 1446 ret = amdgpu_dpm_write_watermarks_table(adev); 1447 if (ret) { 1448 drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); 1449 return ret; 1450 } 1451 1452 return 0; 1453 } 1454 1455 static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1456 { 1457 struct amdgpu_display_manager *dm = &adev->dm; 1458 struct amdgpu_i2c_adapter *oem_i2c; 1459 struct ddc_service *oem_ddc_service; 1460 int r; 1461 1462 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1463 if (oem_ddc_service) { 1464 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1465 if (!oem_i2c) { 1466 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1467 return -ENOMEM; 1468 } 1469 1470 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1471 if (r) { 1472 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1473 kfree(oem_i2c); 1474 return r; 1475 } 1476 dm->oem_i2c = oem_i2c; 1477 } 1478 1479 return 0; 1480 } 1481 1482 /** 1483 * dm_hw_init() - Initialize DC device 1484 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1485 * 1486 * Initialize the &struct amdgpu_display_manager device. This involves calling 1487 * the initializers of each DM component, then populating the struct with them. 1488 * 1489 * Although the function implies hardware initialization, both hardware and 1490 * software are initialized here. Splitting them out to their relevant init 1491 * hooks is a future TODO item. 1492 * 1493 * Some notable things that are initialized here: 1494 * 1495 * - Display Core, both software and hardware 1496 * - DC modules that we need (freesync and color management) 1497 * - DRM software states 1498 * - Interrupt sources and handlers 1499 * - Vblank support 1500 * - Debug FS entries, if enabled 1501 */ 1502 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1503 { 1504 struct amdgpu_device *adev = ip_block->adev; 1505 int r; 1506 1507 adev->dm.i2c_devres_group = devres_open_group(adev->dev, NULL, GFP_KERNEL); 1508 if (!adev->dm.i2c_devres_group) 1509 return -ENOMEM; 1510 1511 /* Create DAL display manager */ 1512 r = amdgpu_dm_init(adev); 1513 if (r) 1514 goto err_release_i2c; 1515 amdgpu_dm_hpd_init(adev); 1516 1517 r = dm_oem_i2c_hw_init(adev); 1518 if (r) 1519 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1520 1521 devres_close_group(adev->dev, adev->dm.i2c_devres_group); 1522 return 0; 1523 1524 err_release_i2c: 1525 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1526 return r; 1527 } 1528 1529 /** 1530 * dm_hw_fini() - Teardown DC device 1531 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1532 * 1533 * Teardown components within &struct amdgpu_display_manager that require 1534 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1535 * were loaded. Also flush IRQ workqueues and disable them. 1536 */ 1537 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1538 { 1539 struct amdgpu_device *adev = ip_block->adev; 1540 1541 if (adev->dm.i2c_devres_group) 1542 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1543 1544 amdgpu_dm_hpd_fini(adev); 1545 1546 amdgpu_dm_irq_fini(adev); 1547 amdgpu_dm_fini(adev); 1548 return 0; 1549 } 1550 1551 1552 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1553 struct dc_state *state, bool enable) 1554 { 1555 enum dc_irq_source irq_source; 1556 struct amdgpu_crtc *acrtc; 1557 int rc = -EBUSY; 1558 int i = 0; 1559 1560 for (i = 0; i < state->stream_count; i++) { 1561 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1562 adev, state->stream_status[i].primary_otg_inst); 1563 1564 if (acrtc && state->stream_status[i].plane_count != 0) { 1565 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1566 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1567 if (rc) 1568 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1569 enable ? "enable" : "disable"); 1570 1571 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1572 if (enable) { 1573 if (amdgpu_dm_crtc_vrr_active( 1574 to_dm_crtc_state(acrtc->base.state))) 1575 rc = amdgpu_dm_crtc_set_vupdate_irq( 1576 &acrtc->base, true); 1577 } else 1578 rc = amdgpu_dm_crtc_set_vupdate_irq( 1579 &acrtc->base, false); 1580 1581 if (rc) 1582 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1583 enable ? "en" : "dis"); 1584 } 1585 1586 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1587 /* During gpu-reset we disable and then enable vblank irq, so 1588 * don't use amdgpu_irq_get/put() to avoid refcount change. 1589 */ 1590 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 1591 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1592 } 1593 } 1594 1595 } 1596 1597 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 1598 1599 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1600 { 1601 struct dc_state *context __free(state_release) = NULL; 1602 int i; 1603 struct dc_stream_state *del_streams[MAX_PIPES]; 1604 int del_streams_count = 0; 1605 struct dc_commit_streams_params params = {}; 1606 1607 memset(del_streams, 0, sizeof(del_streams)); 1608 1609 context = dc_state_create_current_copy(dc); 1610 if (context == NULL) 1611 return DC_ERROR_UNEXPECTED; 1612 1613 /* First remove from context all streams */ 1614 for (i = 0; i < context->stream_count; i++) { 1615 struct dc_stream_state *stream = context->streams[i]; 1616 1617 del_streams[del_streams_count++] = stream; 1618 } 1619 1620 /* Remove all planes for removed streams and then remove the streams */ 1621 for (i = 0; i < del_streams_count; i++) { 1622 enum dc_status res; 1623 1624 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1625 return DC_FAIL_DETACH_SURFACES; 1626 1627 res = dc_state_remove_stream(dc, context, del_streams[i]); 1628 if (res != DC_OK) 1629 return res; 1630 } 1631 1632 params.streams = context->streams; 1633 params.stream_count = context->stream_count; 1634 1635 return dc_commit_streams(dc, ¶ms); 1636 } 1637 1638 static int dm_cache_state(struct amdgpu_device *adev) 1639 { 1640 int r; 1641 1642 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1643 if (IS_ERR(adev->dm.cached_state)) { 1644 r = PTR_ERR(adev->dm.cached_state); 1645 adev->dm.cached_state = NULL; 1646 } 1647 1648 return adev->dm.cached_state ? 0 : r; 1649 } 1650 1651 static void dm_destroy_cached_state(struct amdgpu_device *adev) 1652 { 1653 struct amdgpu_display_manager *dm = &adev->dm; 1654 struct drm_device *ddev = adev_to_drm(adev); 1655 struct dm_plane_state *dm_new_plane_state; 1656 struct drm_plane_state *new_plane_state; 1657 struct dm_crtc_state *dm_new_crtc_state; 1658 struct drm_crtc_state *new_crtc_state; 1659 struct drm_plane *plane; 1660 struct drm_crtc *crtc; 1661 int i; 1662 1663 if (!dm->cached_state) 1664 return; 1665 1666 /* Force mode set in atomic commit */ 1667 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1668 new_crtc_state->active_changed = true; 1669 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1670 reset_freesync_config_for_crtc(dm_new_crtc_state); 1671 } 1672 1673 /* 1674 * atomic_check is expected to create the dc states. We need to release 1675 * them here, since they were duplicated as part of the suspend 1676 * procedure. 1677 */ 1678 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1679 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1680 if (dm_new_crtc_state->stream) { 1681 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1682 dc_stream_release(dm_new_crtc_state->stream); 1683 dm_new_crtc_state->stream = NULL; 1684 } 1685 dm_new_crtc_state->base.color_mgmt_changed = true; 1686 } 1687 1688 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1689 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1690 if (dm_new_plane_state->dc_state) { 1691 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1692 dc_plane_state_release(dm_new_plane_state->dc_state); 1693 dm_new_plane_state->dc_state = NULL; 1694 } 1695 } 1696 1697 drm_atomic_helper_resume(ddev, dm->cached_state); 1698 1699 dm->cached_state = NULL; 1700 } 1701 1702 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1703 { 1704 struct amdgpu_device *adev = ip_block->adev; 1705 struct amdgpu_display_manager *dm = &adev->dm; 1706 1707 if (amdgpu_in_reset(adev)) { 1708 enum dc_status res; 1709 1710 /* Quiesce ISM workers before taking dc_lock (workers take 1711 * dc_lock themselves; syncing under it would deadlock). 1712 */ 1713 amdgpu_dm_ism_disable(dm); 1714 1715 mutex_lock(&dm->dc_lock); 1716 1717 amdgpu_dm_ism_force_full_power(dm); 1718 dc_allow_idle_optimizations(adev->dm.dc, false); 1719 1720 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1721 1722 if (dm->cached_dc_state) 1723 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1724 1725 res = amdgpu_dm_commit_zero_streams(dm->dc); 1726 if (res != DC_OK) { 1727 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1728 return -EINVAL; 1729 } 1730 1731 amdgpu_dm_irq_suspend(adev); 1732 1733 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1734 1735 return 0; 1736 } 1737 1738 if (!adev->dm.cached_state) { 1739 int r = dm_cache_state(adev); 1740 1741 if (r) 1742 return r; 1743 } 1744 1745 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1746 1747 s3_handle_mst(adev_to_drm(adev), true); 1748 1749 amdgpu_dm_irq_suspend(adev); 1750 1751 /* 1752 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1753 * themselves; syncing under it would deadlock). 1754 */ 1755 amdgpu_dm_ism_disable(dm); 1756 scoped_guard(mutex, &dm->dc_lock) 1757 amdgpu_dm_ism_force_full_power(dm); 1758 1759 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1760 1761 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1762 1763 if (dm->dc->caps.ips_support && adev->in_s0ix) 1764 dc_allow_idle_optimizations(dm->dc, true); 1765 1766 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1767 1768 return 0; 1769 } 1770 1771 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1772 { 1773 struct dc_sink_init_data sink_init_data = { 0 }; 1774 struct display_sink_capability sink_caps = { 0 }; 1775 enum dc_edid_status edid_status; 1776 struct dc_context *dc_ctx = link->ctx; 1777 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1778 struct dc_sink *sink = NULL; 1779 struct dc_sink *prev_sink = NULL; 1780 1781 link->type = dc_connection_none; 1782 prev_sink = link->local_sink; 1783 1784 if (prev_sink) 1785 dc_sink_release(prev_sink); 1786 1787 switch (link->connector_signal) { 1788 case SIGNAL_TYPE_HDMI_TYPE_A: { 1789 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1790 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1791 break; 1792 } 1793 1794 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1795 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1796 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1797 break; 1798 } 1799 1800 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1801 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1802 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1803 break; 1804 } 1805 1806 case SIGNAL_TYPE_LVDS: { 1807 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1808 sink_caps.signal = SIGNAL_TYPE_LVDS; 1809 break; 1810 } 1811 1812 case SIGNAL_TYPE_EDP: { 1813 sink_caps.transaction_type = 1814 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1815 sink_caps.signal = SIGNAL_TYPE_EDP; 1816 break; 1817 } 1818 1819 case SIGNAL_TYPE_DISPLAY_PORT: { 1820 sink_caps.transaction_type = 1821 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1822 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1823 break; 1824 } 1825 1826 default: 1827 drm_err(dev, "Invalid connector type! signal:%d\n", 1828 link->connector_signal); 1829 return; 1830 } 1831 1832 sink_init_data.link = link; 1833 sink_init_data.sink_signal = sink_caps.signal; 1834 1835 sink = dc_sink_create(&sink_init_data); 1836 if (!sink) { 1837 drm_err(dev, "Failed to create sink!\n"); 1838 return; 1839 } 1840 1841 /* dc_sink_create returns a new reference */ 1842 link->local_sink = sink; 1843 1844 edid_status = dm_helpers_read_local_edid( 1845 link->ctx, 1846 link, 1847 sink); 1848 1849 if (edid_status != EDID_OK) 1850 drm_err(dev, "Failed to read EDID\n"); 1851 1852 } 1853 1854 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1855 struct amdgpu_display_manager *dm) 1856 { 1857 struct { 1858 struct dc_surface_update surface_updates[MAX_SURFACES]; 1859 struct dc_plane_info plane_infos[MAX_SURFACES]; 1860 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1861 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1862 struct dc_stream_update stream_update; 1863 } *bundle __free(kfree); 1864 int k, m; 1865 1866 bundle = kzalloc_obj(*bundle); 1867 1868 if (!bundle) { 1869 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1870 return; 1871 } 1872 1873 for (k = 0; k < dc_state->stream_count; k++) { 1874 bundle->stream_update.stream = dc_state->streams[k]; 1875 1876 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1877 bundle->surface_updates[m].surface = 1878 dc_state->stream_status[k].plane_states[m]; 1879 bundle->surface_updates[m].surface->force_full_update = 1880 true; 1881 } 1882 1883 update_planes_and_stream_adapter(dm->dc, 1884 UPDATE_TYPE_FULL, 1885 dc_state->stream_status[k].plane_count, 1886 dc_state->streams[k], 1887 &bundle->stream_update, 1888 bundle->surface_updates); 1889 } 1890 } 1891 1892 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1893 struct dc_sink *sink) 1894 { 1895 struct dc_panel_patch *ppatch = NULL; 1896 1897 if (!sink) 1898 return; 1899 1900 ppatch = &sink->edid_caps.panel_patch; 1901 if (ppatch->wait_after_dpcd_poweroff_ms) { 1902 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1903 drm_dbg_driver(adev_to_drm(adev), 1904 "%s: adding a %ds delay as w/a for panel\n", 1905 __func__, 1906 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1907 } 1908 } 1909 1910 /** 1911 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1912 * @adev: amdgpu device pointer 1913 * 1914 * Iterates through all DC links and dumps information about local and remote 1915 * (MST) sinks. Should be called after connector detection is complete to see 1916 * the final state of all links. 1917 */ 1918 static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1919 { 1920 struct dc *dc = adev->dm.dc; 1921 struct drm_device *dev = adev_to_drm(adev); 1922 int li; 1923 1924 if (!dc) 1925 return; 1926 1927 for (li = 0; li < dc->link_count; li++) { 1928 struct dc_link *l = dc->links[li]; 1929 const char *name = NULL; 1930 int rs; 1931 1932 if (!l) 1933 continue; 1934 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1935 name = l->local_sink->edid_caps.display_name; 1936 else 1937 name = "n/a"; 1938 1939 drm_dbg_kms(dev, 1940 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1941 li, 1942 l->local_sink, 1943 l->type, 1944 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1945 l->sink_count, 1946 name, 1947 l->dpcd_caps.is_mst_capable, 1948 l->mst_stream_alloc_table.stream_count); 1949 1950 /* Dump remote (MST) sinks if any */ 1951 for (rs = 0; rs < l->sink_count; rs++) { 1952 struct dc_sink *rsink = l->remote_sinks[rs]; 1953 const char *rname = NULL; 1954 1955 if (!rsink) 1956 continue; 1957 if (rsink->edid_caps.display_name[0]) 1958 rname = rsink->edid_caps.display_name; 1959 else 1960 rname = "n/a"; 1961 drm_dbg_kms(dev, 1962 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1963 li, rs, 1964 rsink, 1965 rsink->sink_signal, 1966 rname); 1967 } 1968 } 1969 } 1970 1971 static int dm_resume(struct amdgpu_ip_block *ip_block) 1972 { 1973 struct amdgpu_device *adev = ip_block->adev; 1974 struct drm_device *ddev = adev_to_drm(adev); 1975 struct amdgpu_display_manager *dm = &adev->dm; 1976 struct amdgpu_dm_connector *aconnector; 1977 struct drm_connector *connector; 1978 struct drm_connector_list_iter iter; 1979 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1980 enum dc_connection_type new_connection_type = dc_connection_none; 1981 struct dc_state *dc_state; 1982 int i, r, j; 1983 struct dc_commit_streams_params commit_params = {}; 1984 1985 if (dm->dc->caps.ips_support) { 1986 if (!amdgpu_in_reset(adev)) 1987 mutex_lock(&dm->dc_lock); 1988 1989 /* Need to set POWER_STATE_D0 first or it will not execute 1990 * idle_power_optimizations command to DMUB. 1991 */ 1992 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 1993 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 1994 1995 if (!amdgpu_in_reset(adev)) 1996 mutex_unlock(&dm->dc_lock); 1997 } 1998 1999 if (amdgpu_in_reset(adev)) { 2000 dc_state = dm->cached_dc_state; 2001 2002 /* 2003 * The dc->current_state is backed up into dm->cached_dc_state 2004 * before we commit 0 streams. 2005 * 2006 * DC will clear link encoder assignments on the real state 2007 * but the changes won't propagate over to the copy we made 2008 * before the 0 streams commit. 2009 * 2010 * DC expects that link encoder assignments are *not* valid 2011 * when committing a state, so as a workaround we can copy 2012 * off of the current state. 2013 * 2014 * We lose the previous assignments, but we had already 2015 * commit 0 streams anyway. 2016 */ 2017 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2018 2019 r = dm_dmub_hw_init(adev); 2020 if (r) { 2021 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 2022 return r; 2023 } 2024 2025 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2026 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2027 2028 dc_resume(dm->dc); 2029 2030 amdgpu_dm_ism_enable(dm); 2031 amdgpu_dm_irq_resume_early(adev); 2032 2033 for (i = 0; i < dc_state->stream_count; i++) { 2034 dc_state->streams[i]->mode_changed = true; 2035 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2036 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 2037 } 2038 } 2039 2040 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2041 amdgpu_dm_outbox_init(adev); 2042 dc_enable_dmub_outbox(adev->dm.dc); 2043 } 2044 2045 commit_params.streams = dc_state->streams; 2046 commit_params.stream_count = dc_state->stream_count; 2047 dc_exit_ips_for_hw_access(dm->dc); 2048 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 2049 2050 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2051 2052 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2053 2054 dc_state_release(dm->cached_dc_state); 2055 dm->cached_dc_state = NULL; 2056 2057 amdgpu_dm_irq_resume_late(adev); 2058 2059 mutex_unlock(&dm->dc_lock); 2060 2061 /* set the backlight after a reset */ 2062 for (i = 0; i < dm->num_of_edps; i++) { 2063 if (dm->backlight_dev[i]) 2064 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 2065 } 2066 2067 return 0; 2068 } 2069 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2070 dc_state_release(dm_state->context); 2071 dm_state->context = dc_state_create(dm->dc, NULL); 2072 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2073 2074 /* Before powering on DC we need to re-initialize DMUB. */ 2075 dm_dmub_hw_resume(adev); 2076 2077 /* Re-enable outbox interrupts for DPIA. */ 2078 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2079 amdgpu_dm_outbox_init(adev); 2080 dc_enable_dmub_outbox(adev->dm.dc); 2081 } 2082 2083 /* power on hardware */ 2084 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2085 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2086 2087 /* program HPD filter */ 2088 dc_resume(dm->dc); 2089 2090 scoped_guard(mutex, &dm->dc_lock) 2091 amdgpu_dm_ism_enable(dm); 2092 2093 /* 2094 * early enable HPD Rx IRQ, should be done before set mode as short 2095 * pulse interrupts are used for MST 2096 */ 2097 amdgpu_dm_irq_resume_early(adev); 2098 2099 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 2100 2101 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2102 s3_handle_mst(ddev, false); 2103 2104 /* Do detection*/ 2105 drm_connector_list_iter_begin(ddev, &iter); 2106 drm_for_each_connector_iter(connector, &iter) { 2107 bool ret; 2108 2109 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2110 continue; 2111 2112 aconnector = to_amdgpu_dm_connector(connector); 2113 2114 if (!aconnector->dc_link) 2115 continue; 2116 2117 /* 2118 * this is the case when traversing through already created end sink 2119 * MST connectors, should be skipped 2120 */ 2121 if (aconnector->mst_root) 2122 continue; 2123 2124 /* Skip eDP detection, when there is no sink present */ 2125 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 2126 !aconnector->dc_link->edp_sink_present) 2127 continue; 2128 2129 guard(mutex)(&aconnector->hpd_lock); 2130 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2131 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2132 2133 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2134 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 2135 } else { 2136 guard(mutex)(&dm->dc_lock); 2137 dc_exit_ips_for_hw_access(dm->dc); 2138 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 2139 if (ret) { 2140 /* w/a delay for certain panels */ 2141 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2142 } 2143 } 2144 2145 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2146 aconnector->fake_enable = false; 2147 2148 if (aconnector->dc_sink) 2149 dc_sink_release(aconnector->dc_sink); 2150 aconnector->dc_sink = NULL; 2151 amdgpu_dm_update_connector_after_detect(aconnector); 2152 } 2153 drm_connector_list_iter_end(&iter); 2154 2155 dm_destroy_cached_state(adev); 2156 2157 /* Do mst topology probing after resuming cached state*/ 2158 drm_connector_list_iter_begin(ddev, &iter); 2159 drm_for_each_connector_iter(connector, &iter) { 2160 bool init = false; 2161 2162 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2163 continue; 2164 2165 aconnector = to_amdgpu_dm_connector(connector); 2166 if (aconnector->dc_link->type != dc_connection_mst_branch || 2167 aconnector->mst_root) 2168 continue; 2169 2170 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2171 init = !aconnector->mst_mgr.mst_primary; 2172 } 2173 if (init) 2174 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2175 aconnector->dc_link, false); 2176 else 2177 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2178 } 2179 drm_connector_list_iter_end(&iter); 2180 2181 /* Debug dump: list all DC links and their associated sinks after detection 2182 * is complete for all connectors. This provides a comprehensive view of the 2183 * final state without repeating the dump for each connector. 2184 */ 2185 amdgpu_dm_dump_links_and_sinks(adev); 2186 2187 amdgpu_dm_irq_resume_late(adev); 2188 2189 amdgpu_dm_smu_write_watermarks_table(adev); 2190 2191 drm_kms_helper_hotplug_event(ddev); 2192 2193 return 0; 2194 } 2195 2196 /** 2197 * DOC: DM Lifecycle 2198 * 2199 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2200 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2201 * the base driver's device list to be initialized and torn down accordingly. 2202 * 2203 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2204 */ 2205 2206 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2207 .name = "dm", 2208 .early_init = dm_early_init, 2209 .late_init = dm_late_init, 2210 .sw_init = dm_sw_init, 2211 .sw_fini = dm_sw_fini, 2212 .early_fini = amdgpu_dm_early_fini, 2213 .hw_init = dm_hw_init, 2214 .hw_fini = dm_hw_fini, 2215 .suspend = dm_suspend, 2216 .resume = dm_resume, 2217 .is_idle = dm_is_idle, 2218 .wait_for_idle = dm_wait_for_idle, 2219 .soft_reset = dm_soft_reset, 2220 .set_clockgating_state = dm_set_clockgating_state, 2221 .set_powergating_state = dm_set_powergating_state, 2222 }; 2223 2224 const struct amdgpu_ip_block_version dm_ip_block = { 2225 .type = AMD_IP_BLOCK_TYPE_DCE, 2226 .major = 1, 2227 .minor = 0, 2228 .rev = 0, 2229 .funcs = &amdgpu_dm_funcs, 2230 }; 2231 2232 2233 /** 2234 * DOC: atomic 2235 * 2236 * *WIP* 2237 */ 2238 2239 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2240 .fb_create = amdgpu_display_user_framebuffer_create, 2241 .get_format_info = amdgpu_dm_plane_get_format_info, 2242 .atomic_check = amdgpu_dm_atomic_check, 2243 .atomic_commit = drm_atomic_helper_commit, 2244 }; 2245 2246 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2247 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2248 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2249 }; 2250 2251 /* 2252 * Acquires the lock for the atomic state object and returns 2253 * the new atomic state. 2254 * 2255 * This should only be called during atomic check. 2256 */ 2257 int dm_atomic_get_state(struct drm_atomic_commit *state, 2258 struct dm_atomic_state **dm_state) 2259 { 2260 struct drm_device *dev = state->dev; 2261 struct amdgpu_device *adev = drm_to_adev(dev); 2262 struct amdgpu_display_manager *dm = &adev->dm; 2263 struct drm_private_state *priv_state; 2264 2265 if (*dm_state) 2266 return 0; 2267 2268 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2269 if (IS_ERR(priv_state)) 2270 return PTR_ERR(priv_state); 2271 2272 *dm_state = to_dm_atomic_state(priv_state); 2273 2274 return 0; 2275 } 2276 2277 static struct dm_atomic_state * 2278 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2279 { 2280 struct drm_device *dev = state->dev; 2281 struct amdgpu_device *adev = drm_to_adev(dev); 2282 struct amdgpu_display_manager *dm = &adev->dm; 2283 struct drm_private_obj *obj; 2284 struct drm_private_state *new_obj_state; 2285 int i; 2286 2287 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2288 if (obj->funcs == dm->atomic_obj.funcs) 2289 return to_dm_atomic_state(new_obj_state); 2290 } 2291 2292 return NULL; 2293 } 2294 2295 static struct drm_private_state * 2296 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2297 { 2298 struct dm_atomic_state *old_state, *new_state; 2299 2300 new_state = kzalloc_obj(*new_state); 2301 if (!new_state) 2302 return NULL; 2303 2304 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2305 2306 old_state = to_dm_atomic_state(obj->state); 2307 2308 if (old_state && old_state->context) 2309 new_state->context = dc_state_create_copy(old_state->context); 2310 2311 if (!new_state->context) { 2312 kfree(new_state); 2313 return NULL; 2314 } 2315 2316 return &new_state->base; 2317 } 2318 2319 static void dm_atomic_destroy_state(struct drm_private_obj *obj, 2320 struct drm_private_state *state) 2321 { 2322 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2323 2324 if (dm_state && dm_state->context) 2325 dc_state_release(dm_state->context); 2326 2327 kfree(dm_state); 2328 } 2329 2330 static struct drm_private_state * 2331 dm_atomic_create_state(struct drm_private_obj *obj) 2332 { 2333 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2334 struct dm_atomic_state *dm_state; 2335 struct dc_state *context; 2336 2337 dm_state = kzalloc_obj(*dm_state); 2338 if (!dm_state) 2339 return ERR_PTR(-ENOMEM); 2340 2341 context = dc_state_create_current_copy(adev->dm.dc); 2342 if (!context) { 2343 kfree(dm_state); 2344 return ERR_PTR(-ENOMEM); 2345 } 2346 2347 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2348 dm_state->context = context; 2349 2350 return &dm_state->base; 2351 } 2352 2353 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2354 .atomic_create_state = dm_atomic_create_state, 2355 .atomic_duplicate_state = dm_atomic_duplicate_state, 2356 .atomic_destroy_state = dm_atomic_destroy_state, 2357 }; 2358 2359 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2360 { 2361 int r; 2362 2363 adev->mode_info.mode_config_initialized = true; 2364 2365 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2366 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2367 2368 adev_to_drm(adev)->mode_config.max_width = 16384; 2369 adev_to_drm(adev)->mode_config.max_height = 16384; 2370 2371 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2372 if (adev->asic_type == CHIP_HAWAII) 2373 /* disable prefer shadow for now due to hibernation issues */ 2374 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2375 else 2376 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2377 /* indicates support for immediate flip */ 2378 adev_to_drm(adev)->mode_config.async_page_flip = true; 2379 2380 drm_atomic_private_obj_init(adev_to_drm(adev), 2381 &adev->dm.atomic_obj, 2382 &dm_atomic_state_funcs); 2383 2384 r = amdgpu_display_modeset_create_props(adev); 2385 if (r) 2386 return r; 2387 2388 #ifdef AMD_PRIVATE_COLOR 2389 if (amdgpu_dm_create_color_properties(adev)) 2390 return -ENOMEM; 2391 #endif 2392 2393 r = amdgpu_dm_audio_init(adev); 2394 if (r) 2395 return r; 2396 2397 return 0; 2398 } 2399 2400 static int initialize_plane(struct amdgpu_display_manager *dm, 2401 struct amdgpu_mode_info *mode_info, int plane_id, 2402 enum drm_plane_type plane_type, 2403 const struct dc_plane_cap *plane_cap) 2404 { 2405 struct drm_plane *plane; 2406 unsigned long possible_crtcs; 2407 int ret = 0; 2408 2409 plane = kzalloc_obj(struct drm_plane); 2410 if (!plane) { 2411 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2412 return -ENOMEM; 2413 } 2414 plane->type = plane_type; 2415 2416 /* 2417 * HACK: IGT tests expect that the primary plane for a CRTC 2418 * can only have one possible CRTC. Only expose support for 2419 * any CRTC if they're not going to be used as a primary plane 2420 * for a CRTC - like overlay or underlay planes. 2421 */ 2422 possible_crtcs = 1 << plane_id; 2423 if (plane_id >= dm->dc->caps.max_streams) 2424 possible_crtcs = 0xff; 2425 2426 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2427 2428 if (ret) { 2429 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2430 kfree(plane); 2431 return ret; 2432 } 2433 2434 if (mode_info) 2435 mode_info->planes[plane_id] = plane; 2436 2437 return ret; 2438 } 2439 2440 2441 /* 2442 * In this architecture, the association 2443 * connector -> encoder -> crtc 2444 * id not really requried. The crtc and connector will hold the 2445 * display_index as an abstraction to use with DAL component 2446 * 2447 * Returns 0 on success 2448 */ 2449 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2450 { 2451 struct amdgpu_display_manager *dm = &adev->dm; 2452 s32 i; 2453 struct amdgpu_dm_connector *aconnector = NULL; 2454 struct amdgpu_encoder *aencoder = NULL; 2455 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2456 u32 link_cnt; 2457 s32 primary_planes; 2458 enum dc_connection_type new_connection_type = dc_connection_none; 2459 const struct dc_plane_cap *plane; 2460 bool psr_feature_enabled = false; 2461 bool replay_feature_enabled = false; 2462 int max_overlay = dm->dc->caps.max_slave_planes; 2463 2464 dm->display_indexes_num = dm->dc->caps.max_streams; 2465 /* Update the actual used number of crtc */ 2466 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2467 2468 amdgpu_dm_set_irq_funcs(adev); 2469 2470 link_cnt = dm->dc->caps.max_links; 2471 if (amdgpu_dm_mode_config_init(dm->adev)) { 2472 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2473 return -EINVAL; 2474 } 2475 2476 /* There is one primary plane per CRTC */ 2477 primary_planes = dm->dc->caps.max_streams; 2478 if (primary_planes > AMDGPU_MAX_PLANES) { 2479 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2480 return -EINVAL; 2481 } 2482 2483 /* 2484 * Initialize primary planes, implicit planes for legacy IOCTLS. 2485 * Order is reversed to match iteration order in atomic check. 2486 */ 2487 for (i = (primary_planes - 1); i >= 0; i--) { 2488 plane = &dm->dc->caps.planes[i]; 2489 2490 if (initialize_plane(dm, mode_info, i, 2491 DRM_PLANE_TYPE_PRIMARY, plane)) { 2492 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2493 goto fail; 2494 } 2495 } 2496 2497 /* 2498 * Initialize overlay planes, index starting after primary planes. 2499 * These planes have a higher DRM index than the primary planes since 2500 * they should be considered as having a higher z-order. 2501 * Order is reversed to match iteration order in atomic check. 2502 * 2503 * Only support DCN for now, and only expose one so we don't encourage 2504 * userspace to use up all the pipes. 2505 */ 2506 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2507 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2508 2509 /* Do not create overlay if MPO disabled */ 2510 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2511 break; 2512 2513 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2514 continue; 2515 2516 if (!plane->pixel_format_support.argb8888) 2517 continue; 2518 2519 if (max_overlay-- == 0) 2520 break; 2521 2522 if (initialize_plane(dm, NULL, primary_planes + i, 2523 DRM_PLANE_TYPE_OVERLAY, plane)) { 2524 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2525 goto fail; 2526 } 2527 } 2528 2529 for (i = 0; i < dm->dc->caps.max_streams; i++) 2530 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2531 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2532 goto fail; 2533 } 2534 2535 /* Use Outbox interrupt */ 2536 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2537 case IP_VERSION(3, 0, 0): 2538 case IP_VERSION(3, 1, 2): 2539 case IP_VERSION(3, 1, 3): 2540 case IP_VERSION(3, 1, 4): 2541 case IP_VERSION(3, 1, 5): 2542 case IP_VERSION(3, 1, 6): 2543 case IP_VERSION(3, 2, 0): 2544 case IP_VERSION(3, 2, 1): 2545 case IP_VERSION(2, 1, 0): 2546 case IP_VERSION(3, 5, 0): 2547 case IP_VERSION(3, 5, 1): 2548 case IP_VERSION(3, 6, 0): 2549 case IP_VERSION(4, 0, 1): 2550 case IP_VERSION(4, 2, 0): 2551 case IP_VERSION(4, 2, 1): 2552 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2553 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2554 goto fail; 2555 } 2556 break; 2557 default: 2558 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2559 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2560 } 2561 2562 /* Determine whether to enable PSR support by default. */ 2563 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2564 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2565 case IP_VERSION(3, 1, 2): 2566 case IP_VERSION(3, 1, 3): 2567 case IP_VERSION(3, 1, 4): 2568 case IP_VERSION(3, 1, 5): 2569 case IP_VERSION(3, 1, 6): 2570 case IP_VERSION(3, 2, 0): 2571 case IP_VERSION(3, 2, 1): 2572 case IP_VERSION(3, 5, 0): 2573 case IP_VERSION(3, 5, 1): 2574 case IP_VERSION(3, 6, 0): 2575 case IP_VERSION(4, 0, 1): 2576 case IP_VERSION(4, 2, 0): 2577 case IP_VERSION(4, 2, 1): 2578 psr_feature_enabled = true; 2579 break; 2580 default: 2581 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2582 break; 2583 } 2584 } 2585 2586 /* Determine whether to enable Replay support by default. */ 2587 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2588 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2589 case IP_VERSION(3, 1, 4): 2590 case IP_VERSION(3, 2, 0): 2591 case IP_VERSION(3, 2, 1): 2592 case IP_VERSION(3, 5, 0): 2593 case IP_VERSION(3, 5, 1): 2594 case IP_VERSION(3, 6, 0): 2595 case IP_VERSION(4, 2, 0): 2596 case IP_VERSION(4, 2, 1): 2597 replay_feature_enabled = true; 2598 break; 2599 2600 default: 2601 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2602 break; 2603 } 2604 } 2605 2606 if (link_cnt > MAX_LINKS) { 2607 drm_err(adev_to_drm(adev), 2608 "KMS: Cannot support more than %d display indexes\n", 2609 MAX_LINKS); 2610 goto fail; 2611 } 2612 2613 /* loops over all connectors on the board */ 2614 for (i = 0; i < link_cnt; i++) { 2615 struct dc_link *link = NULL; 2616 2617 link = dc_get_link_at_index(dm->dc, i); 2618 2619 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2620 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2621 2622 if (!wbcon) { 2623 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2624 continue; 2625 } 2626 2627 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2628 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2629 kfree(wbcon); 2630 continue; 2631 } 2632 2633 link->psr_settings.psr_feature_enabled = false; 2634 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2635 2636 continue; 2637 } 2638 2639 aconnector = kzalloc_obj(*aconnector); 2640 if (!aconnector) 2641 goto fail; 2642 2643 aencoder = kzalloc_obj(*aencoder); 2644 if (!aencoder) 2645 goto fail; 2646 2647 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2648 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2649 goto fail; 2650 } 2651 2652 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2653 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2654 goto fail; 2655 } 2656 2657 if (dm->hpd_rx_offload_wq) 2658 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2659 aconnector; 2660 2661 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2662 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2663 2664 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2665 amdgpu_dm_emulated_link_detect(link); 2666 amdgpu_dm_update_connector_after_detect(aconnector); 2667 } else { 2668 bool ret = false; 2669 2670 mutex_lock(&dm->dc_lock); 2671 dc_exit_ips_for_hw_access(dm->dc); 2672 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2673 mutex_unlock(&dm->dc_lock); 2674 2675 if (ret) { 2676 amdgpu_dm_update_connector_after_detect(aconnector); 2677 amdgpu_dm_setup_backlight_device(dm, aconnector); 2678 2679 /* Disable PSR if Replay can be enabled */ 2680 if (replay_feature_enabled) 2681 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2682 psr_feature_enabled = false; 2683 2684 if (psr_feature_enabled) { 2685 amdgpu_dm_set_psr_caps(link, aconnector); 2686 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2687 aconnector->base.name, 2688 link->psr_settings.psr_feature_enabled, 2689 link->psr_settings.psr_version, 2690 link->dpcd_caps.psr_info.psr_version, 2691 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2692 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2693 } 2694 } 2695 } 2696 amdgpu_set_panel_orientation(&aconnector->base); 2697 } 2698 2699 /* Debug dump: list all DC links and their associated sinks after detection 2700 * is complete for all connectors. This provides a comprehensive view of the 2701 * final state without repeating the dump for each connector. 2702 */ 2703 amdgpu_dm_dump_links_and_sinks(adev); 2704 2705 /* Software is initialized. Now we can register interrupt handlers. */ 2706 switch (adev->asic_type) { 2707 #if defined(CONFIG_DRM_AMD_DC_SI) 2708 case CHIP_TAHITI: 2709 case CHIP_PITCAIRN: 2710 case CHIP_VERDE: 2711 case CHIP_OLAND: 2712 #endif 2713 case CHIP_BONAIRE: 2714 case CHIP_HAWAII: 2715 case CHIP_KAVERI: 2716 case CHIP_KABINI: 2717 case CHIP_MULLINS: 2718 case CHIP_TONGA: 2719 case CHIP_FIJI: 2720 case CHIP_CARRIZO: 2721 case CHIP_STONEY: 2722 case CHIP_POLARIS11: 2723 case CHIP_POLARIS10: 2724 case CHIP_POLARIS12: 2725 case CHIP_VEGAM: 2726 case CHIP_VEGA10: 2727 case CHIP_VEGA12: 2728 case CHIP_VEGA20: 2729 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2730 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2731 goto fail; 2732 } 2733 break; 2734 default: 2735 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2736 case IP_VERSION(1, 0, 0): 2737 case IP_VERSION(1, 0, 1): 2738 case IP_VERSION(2, 0, 2): 2739 case IP_VERSION(2, 0, 3): 2740 case IP_VERSION(2, 0, 0): 2741 case IP_VERSION(2, 1, 0): 2742 case IP_VERSION(3, 0, 0): 2743 case IP_VERSION(3, 0, 2): 2744 case IP_VERSION(3, 0, 3): 2745 case IP_VERSION(3, 0, 1): 2746 case IP_VERSION(3, 1, 2): 2747 case IP_VERSION(3, 1, 3): 2748 case IP_VERSION(3, 1, 4): 2749 case IP_VERSION(3, 1, 5): 2750 case IP_VERSION(3, 1, 6): 2751 case IP_VERSION(3, 2, 0): 2752 case IP_VERSION(3, 2, 1): 2753 case IP_VERSION(3, 5, 0): 2754 case IP_VERSION(3, 5, 1): 2755 case IP_VERSION(3, 6, 0): 2756 case IP_VERSION(4, 0, 1): 2757 case IP_VERSION(4, 2, 0): 2758 case IP_VERSION(4, 2, 1): 2759 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2760 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2761 goto fail; 2762 } 2763 break; 2764 default: 2765 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2766 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2767 goto fail; 2768 } 2769 break; 2770 } 2771 2772 return 0; 2773 fail: 2774 kfree(aencoder); 2775 kfree(aconnector); 2776 2777 return -EINVAL; 2778 } 2779 2780 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2781 { 2782 if (dm->atomic_obj.state) 2783 drm_atomic_private_obj_fini(&dm->atomic_obj); 2784 } 2785 2786 /****************************************************************************** 2787 * amdgpu_display_funcs functions 2788 *****************************************************************************/ 2789 2790 /* 2791 * dm_bandwidth_update - program display watermarks 2792 * 2793 * @adev: amdgpu_device pointer 2794 * 2795 * Calculate and program the display watermarks and line buffer allocation. 2796 */ 2797 static void dm_bandwidth_update(struct amdgpu_device *adev) 2798 { 2799 /* TODO: implement later */ 2800 } 2801 2802 static const struct amdgpu_display_funcs dm_display_funcs = { 2803 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2804 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2805 .backlight_set_level = NULL, /* never called for DC */ 2806 .backlight_get_level = NULL, /* never called for DC */ 2807 .hpd_sense = NULL,/* called unconditionally */ 2808 .hpd_set_polarity = NULL, /* called unconditionally */ 2809 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2810 .page_flip_get_scanoutpos = 2811 dm_crtc_get_scanoutpos,/* called unconditionally */ 2812 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2813 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2814 }; 2815 2816 #if defined(CONFIG_DEBUG_KERNEL_DC) 2817 2818 static ssize_t s3_debug_store(struct device *device, 2819 struct device_attribute *attr, 2820 const char *buf, 2821 size_t count) 2822 { 2823 int ret; 2824 int s3_state; 2825 struct drm_device *drm_dev = dev_get_drvdata(device); 2826 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2827 struct amdgpu_ip_block *ip_block; 2828 2829 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2830 if (!ip_block) 2831 return -EINVAL; 2832 2833 ret = kstrtoint(buf, 0, &s3_state); 2834 2835 if (ret == 0) { 2836 if (s3_state) { 2837 dm_resume(ip_block); 2838 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2839 } else 2840 dm_suspend(ip_block); 2841 } 2842 2843 return ret == 0 ? count : 0; 2844 } 2845 2846 DEVICE_ATTR_WO(s3_debug); 2847 2848 #endif 2849 2850 static int dm_early_init(struct amdgpu_ip_block *ip_block) 2851 { 2852 struct amdgpu_device *adev = ip_block->adev; 2853 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2854 struct atom_context *ctx = mode_info->atom_context; 2855 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2856 u16 data_offset; 2857 2858 /* if there is no object header, skip DM */ 2859 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2860 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2861 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2862 return -ENOENT; 2863 } 2864 2865 switch (adev->asic_type) { 2866 #if defined(CONFIG_DRM_AMD_DC_SI) 2867 case CHIP_TAHITI: 2868 case CHIP_PITCAIRN: 2869 case CHIP_VERDE: 2870 adev->mode_info.num_crtc = 6; 2871 adev->mode_info.num_hpd = 6; 2872 adev->mode_info.num_dig = 6; 2873 break; 2874 case CHIP_OLAND: 2875 adev->mode_info.num_crtc = 2; 2876 adev->mode_info.num_hpd = 2; 2877 adev->mode_info.num_dig = 2; 2878 break; 2879 #endif 2880 case CHIP_BONAIRE: 2881 case CHIP_HAWAII: 2882 adev->mode_info.num_crtc = 6; 2883 adev->mode_info.num_hpd = 6; 2884 adev->mode_info.num_dig = 6; 2885 break; 2886 case CHIP_KAVERI: 2887 adev->mode_info.num_crtc = 4; 2888 adev->mode_info.num_hpd = 6; 2889 adev->mode_info.num_dig = 7; 2890 break; 2891 case CHIP_KABINI: 2892 case CHIP_MULLINS: 2893 adev->mode_info.num_crtc = 2; 2894 adev->mode_info.num_hpd = 6; 2895 adev->mode_info.num_dig = 6; 2896 break; 2897 case CHIP_FIJI: 2898 case CHIP_TONGA: 2899 adev->mode_info.num_crtc = 6; 2900 adev->mode_info.num_hpd = 6; 2901 adev->mode_info.num_dig = 7; 2902 break; 2903 case CHIP_CARRIZO: 2904 adev->mode_info.num_crtc = 3; 2905 adev->mode_info.num_hpd = 6; 2906 adev->mode_info.num_dig = 9; 2907 break; 2908 case CHIP_STONEY: 2909 adev->mode_info.num_crtc = 2; 2910 adev->mode_info.num_hpd = 6; 2911 adev->mode_info.num_dig = 9; 2912 break; 2913 case CHIP_POLARIS11: 2914 case CHIP_POLARIS12: 2915 adev->mode_info.num_crtc = 5; 2916 adev->mode_info.num_hpd = 5; 2917 adev->mode_info.num_dig = 5; 2918 break; 2919 case CHIP_POLARIS10: 2920 case CHIP_VEGAM: 2921 adev->mode_info.num_crtc = 6; 2922 adev->mode_info.num_hpd = 6; 2923 adev->mode_info.num_dig = 6; 2924 break; 2925 case CHIP_VEGA10: 2926 case CHIP_VEGA12: 2927 case CHIP_VEGA20: 2928 adev->mode_info.num_crtc = 6; 2929 adev->mode_info.num_hpd = 6; 2930 adev->mode_info.num_dig = 6; 2931 break; 2932 default: 2933 2934 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2935 case IP_VERSION(2, 0, 2): 2936 case IP_VERSION(3, 0, 0): 2937 adev->mode_info.num_crtc = 6; 2938 adev->mode_info.num_hpd = 6; 2939 adev->mode_info.num_dig = 6; 2940 break; 2941 case IP_VERSION(2, 0, 0): 2942 case IP_VERSION(3, 0, 2): 2943 adev->mode_info.num_crtc = 5; 2944 adev->mode_info.num_hpd = 5; 2945 adev->mode_info.num_dig = 5; 2946 break; 2947 case IP_VERSION(2, 0, 3): 2948 case IP_VERSION(3, 0, 3): 2949 adev->mode_info.num_crtc = 2; 2950 adev->mode_info.num_hpd = 2; 2951 adev->mode_info.num_dig = 2; 2952 break; 2953 case IP_VERSION(1, 0, 0): 2954 case IP_VERSION(1, 0, 1): 2955 case IP_VERSION(3, 0, 1): 2956 case IP_VERSION(2, 1, 0): 2957 case IP_VERSION(3, 1, 2): 2958 case IP_VERSION(3, 1, 3): 2959 case IP_VERSION(3, 1, 4): 2960 case IP_VERSION(3, 1, 5): 2961 case IP_VERSION(3, 1, 6): 2962 case IP_VERSION(3, 2, 0): 2963 case IP_VERSION(3, 2, 1): 2964 case IP_VERSION(3, 5, 0): 2965 case IP_VERSION(3, 5, 1): 2966 case IP_VERSION(3, 6, 0): 2967 case IP_VERSION(4, 0, 1): 2968 case IP_VERSION(4, 2, 0): 2969 case IP_VERSION(4, 2, 1): 2970 adev->mode_info.num_crtc = 4; 2971 adev->mode_info.num_hpd = 4; 2972 adev->mode_info.num_dig = 4; 2973 break; 2974 default: 2975 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2976 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2977 return -EINVAL; 2978 } 2979 break; 2980 } 2981 2982 if (adev->mode_info.funcs == NULL) 2983 adev->mode_info.funcs = &dm_display_funcs; 2984 2985 /* 2986 * Note: Do NOT change adev->reg.audio_endpt.rreg and 2987 * adev->reg.audio_endpt.wreg because they are initialised in 2988 * amdgpu_device_init() 2989 */ 2990 #if defined(CONFIG_DEBUG_KERNEL_DC) 2991 device_create_file( 2992 adev_to_drm(adev)->dev, 2993 &dev_attr_s3_debug); 2994 #endif 2995 adev->dc_enabled = true; 2996 2997 return dm_init_microcode(adev); 2998 } 2999 3000 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 3001 { 3002 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 3003 } 3004 EXPORT_IF_KUNIT(modereset_required); 3005 3006 STATIC_IFN_KUNIT int 3007 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 3008 const enum surface_pixel_format format, 3009 enum dc_color_space *color_space) 3010 { 3011 bool full_range; 3012 3013 *color_space = COLOR_SPACE_SRGB; 3014 3015 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 3016 if (plane_state->state && plane_state->state->plane_color_pipeline) 3017 return 0; 3018 3019 /* DRM color properties only affect non-RGB formats. */ 3020 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3021 return 0; 3022 3023 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 3024 3025 switch (plane_state->color_encoding) { 3026 case DRM_COLOR_YCBCR_BT601: 3027 if (full_range) 3028 *color_space = COLOR_SPACE_YCBCR601; 3029 else 3030 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 3031 break; 3032 3033 case DRM_COLOR_YCBCR_BT709: 3034 if (full_range) 3035 *color_space = COLOR_SPACE_YCBCR709; 3036 else 3037 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 3038 break; 3039 3040 case DRM_COLOR_YCBCR_BT2020: 3041 if (full_range) 3042 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 3043 else 3044 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 3045 break; 3046 3047 default: 3048 return -EINVAL; 3049 } 3050 3051 return 0; 3052 } 3053 EXPORT_IF_KUNIT(fill_plane_color_attributes); 3054 3055 static int 3056 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 3057 const struct drm_plane_state *plane_state, 3058 const u64 tiling_flags, 3059 struct dc_plane_info *plane_info, 3060 struct dc_plane_address *address, 3061 bool tmz_surface) 3062 { 3063 const struct drm_framebuffer *fb = plane_state->fb; 3064 const struct amdgpu_framebuffer *afb = 3065 to_amdgpu_framebuffer(plane_state->fb); 3066 int ret; 3067 3068 memset(plane_info, 0, sizeof(*plane_info)); 3069 3070 switch (fb->format->format) { 3071 case DRM_FORMAT_C8: 3072 plane_info->format = 3073 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3074 break; 3075 case DRM_FORMAT_RGB565: 3076 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3077 break; 3078 case DRM_FORMAT_XRGB8888: 3079 case DRM_FORMAT_ARGB8888: 3080 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3081 break; 3082 case DRM_FORMAT_XRGB2101010: 3083 case DRM_FORMAT_ARGB2101010: 3084 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3085 break; 3086 case DRM_FORMAT_XBGR2101010: 3087 case DRM_FORMAT_ABGR2101010: 3088 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3089 break; 3090 case DRM_FORMAT_XBGR8888: 3091 case DRM_FORMAT_ABGR8888: 3092 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3093 break; 3094 case DRM_FORMAT_NV21: 3095 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3096 break; 3097 case DRM_FORMAT_NV12: 3098 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3099 break; 3100 case DRM_FORMAT_P010: 3101 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 3102 break; 3103 case DRM_FORMAT_XRGB16161616F: 3104 case DRM_FORMAT_ARGB16161616F: 3105 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 3106 break; 3107 case DRM_FORMAT_XBGR16161616F: 3108 case DRM_FORMAT_ABGR16161616F: 3109 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 3110 break; 3111 case DRM_FORMAT_XRGB16161616: 3112 case DRM_FORMAT_ARGB16161616: 3113 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 3114 break; 3115 case DRM_FORMAT_XBGR16161616: 3116 case DRM_FORMAT_ABGR16161616: 3117 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 3118 break; 3119 default: 3120 drm_err(adev_to_drm(adev), 3121 "Unsupported screen format %p4cc\n", 3122 &fb->format->format); 3123 return -EINVAL; 3124 } 3125 3126 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3127 case DRM_MODE_ROTATE_0: 3128 plane_info->rotation = ROTATION_ANGLE_0; 3129 break; 3130 case DRM_MODE_ROTATE_90: 3131 plane_info->rotation = ROTATION_ANGLE_90; 3132 break; 3133 case DRM_MODE_ROTATE_180: 3134 plane_info->rotation = ROTATION_ANGLE_180; 3135 break; 3136 case DRM_MODE_ROTATE_270: 3137 plane_info->rotation = ROTATION_ANGLE_270; 3138 break; 3139 default: 3140 plane_info->rotation = ROTATION_ANGLE_0; 3141 break; 3142 } 3143 3144 3145 plane_info->visible = true; 3146 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3147 3148 plane_info->layer_index = plane_state->normalized_zpos; 3149 3150 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3151 &plane_info->color_space); 3152 if (ret) 3153 return ret; 3154 3155 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3156 plane_info->rotation, tiling_flags, 3157 &plane_info->tiling_info, 3158 &plane_info->plane_size, 3159 &plane_info->dcc, address, 3160 tmz_surface); 3161 if (ret) 3162 return ret; 3163 3164 amdgpu_dm_plane_fill_blending_from_plane_state( 3165 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3166 &plane_info->global_alpha, &plane_info->global_alpha_value); 3167 3168 return 0; 3169 } 3170 3171 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3172 struct dc_plane_state *dc_plane_state, 3173 struct drm_plane_state *plane_state, 3174 struct drm_crtc_state *crtc_state) 3175 { 3176 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3177 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3178 struct dc_scaling_info scaling_info; 3179 struct dc_plane_info plane_info; 3180 int ret; 3181 3182 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3183 if (ret) 3184 return ret; 3185 3186 dc_plane_state->src_rect = scaling_info.src_rect; 3187 dc_plane_state->dst_rect = scaling_info.dst_rect; 3188 dc_plane_state->clip_rect = scaling_info.clip_rect; 3189 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3190 3191 ret = fill_dc_plane_info_and_addr(adev, plane_state, 3192 afb->tiling_flags, 3193 &plane_info, 3194 &dc_plane_state->address, 3195 afb->tmz_surface); 3196 if (ret) 3197 return ret; 3198 3199 dc_plane_state->format = plane_info.format; 3200 dc_plane_state->color_space = plane_info.color_space; 3201 dc_plane_state->format = plane_info.format; 3202 dc_plane_state->plane_size = plane_info.plane_size; 3203 dc_plane_state->rotation = plane_info.rotation; 3204 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3205 dc_plane_state->stereo_format = plane_info.stereo_format; 3206 dc_plane_state->tiling_info = plane_info.tiling_info; 3207 dc_plane_state->visible = plane_info.visible; 3208 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3209 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3210 dc_plane_state->global_alpha = plane_info.global_alpha; 3211 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3212 dc_plane_state->dcc = plane_info.dcc; 3213 dc_plane_state->layer_index = plane_info.layer_index; 3214 dc_plane_state->flip_int_enabled = true; 3215 3216 /* 3217 * Always set input transfer function, since plane state is refreshed 3218 * every time. 3219 */ 3220 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3221 plane_state, 3222 dc_plane_state); 3223 if (ret) 3224 return ret; 3225 3226 return 0; 3227 } 3228 3229 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3230 struct rect *dirty_rect, int32_t x, 3231 s32 y, s32 width, s32 height, 3232 int *i, bool ffu) 3233 { 3234 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3235 3236 dirty_rect->x = x; 3237 dirty_rect->y = y; 3238 dirty_rect->width = width; 3239 dirty_rect->height = height; 3240 3241 if (ffu) 3242 drm_dbg(plane->dev, 3243 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3244 plane->base.id, width, height); 3245 else 3246 drm_dbg(plane->dev, 3247 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3248 plane->base.id, x, y, width, height); 3249 3250 (*i)++; 3251 } 3252 3253 /** 3254 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3255 * 3256 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3257 * remote fb 3258 * @old_plane_state: Old state of @plane 3259 * @new_plane_state: New state of @plane 3260 * @crtc_state: New state of CRTC connected to the @plane 3261 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3262 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3263 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3264 * that have changed will be updated. If PSR SU is not enabled, 3265 * or if damage clips are not available, the entire screen will be updated. 3266 * @dirty_regions_changed: dirty regions changed 3267 * 3268 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3269 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3270 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3271 * amdgpu_dm's. 3272 * 3273 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3274 * plane with regions that require flushing to the eDP remote buffer. In 3275 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3276 * implicitly provide damage clips without any client support via the plane 3277 * bounds. 3278 */ 3279 static void fill_dc_dirty_rects(struct drm_plane *plane, 3280 struct drm_plane_state *old_plane_state, 3281 struct drm_plane_state *new_plane_state, 3282 struct drm_crtc_state *crtc_state, 3283 struct dc_flip_addrs *flip_addrs, 3284 bool is_psr_su, 3285 bool *dirty_regions_changed) 3286 { 3287 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3288 struct rect *dirty_rects = flip_addrs->dirty_rects; 3289 u32 num_clips = 0; 3290 struct drm_mode_rect *clips = NULL; 3291 bool bb_changed; 3292 bool fb_changed; 3293 u32 i = 0; 3294 *dirty_regions_changed = false; 3295 3296 /* 3297 * Cursor plane has it's own dirty rect update interface. See 3298 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3299 */ 3300 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3301 return; 3302 3303 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3304 goto ffu; 3305 3306 if (!new_plane_state->ignore_damage_clips) { 3307 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3308 clips = drm_plane_get_damage_clips(new_plane_state); 3309 } 3310 3311 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3312 is_psr_su))) 3313 goto ffu; 3314 3315 if (!dm_crtc_state->mpo_requested) { 3316 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3317 goto ffu; 3318 3319 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3320 fill_dc_dirty_rect(new_plane_state->plane, 3321 &dirty_rects[flip_addrs->dirty_rect_count], 3322 clips->x1, clips->y1, 3323 clips->x2 - clips->x1, clips->y2 - clips->y1, 3324 &flip_addrs->dirty_rect_count, 3325 false); 3326 return; 3327 } 3328 3329 /* 3330 * MPO is requested. Add entire plane bounding box to dirty rects if 3331 * flipped to or damaged. 3332 * 3333 * If plane is moved or resized, also add old bounding box to dirty 3334 * rects. 3335 */ 3336 fb_changed = old_plane_state->fb->base.id != 3337 new_plane_state->fb->base.id; 3338 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3339 old_plane_state->crtc_y != new_plane_state->crtc_y || 3340 old_plane_state->crtc_w != new_plane_state->crtc_w || 3341 old_plane_state->crtc_h != new_plane_state->crtc_h); 3342 3343 drm_dbg(plane->dev, 3344 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3345 new_plane_state->plane->base.id, 3346 bb_changed, fb_changed, num_clips); 3347 3348 *dirty_regions_changed = bb_changed; 3349 3350 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3351 goto ffu; 3352 3353 if (bb_changed) { 3354 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3355 new_plane_state->crtc_x, 3356 new_plane_state->crtc_y, 3357 new_plane_state->crtc_w, 3358 new_plane_state->crtc_h, &i, false); 3359 3360 /* Add old plane bounding-box if plane is moved or resized */ 3361 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3362 old_plane_state->crtc_x, 3363 old_plane_state->crtc_y, 3364 old_plane_state->crtc_w, 3365 old_plane_state->crtc_h, &i, false); 3366 } 3367 3368 if (num_clips) { 3369 for (; i < num_clips; clips++) 3370 fill_dc_dirty_rect(new_plane_state->plane, 3371 &dirty_rects[i], clips->x1, 3372 clips->y1, clips->x2 - clips->x1, 3373 clips->y2 - clips->y1, &i, false); 3374 } else if (fb_changed && !bb_changed) { 3375 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3376 new_plane_state->crtc_x, 3377 new_plane_state->crtc_y, 3378 new_plane_state->crtc_w, 3379 new_plane_state->crtc_h, &i, false); 3380 } 3381 3382 flip_addrs->dirty_rect_count = i; 3383 return; 3384 3385 ffu: 3386 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3387 dm_crtc_state->base.mode.crtc_hdisplay, 3388 dm_crtc_state->base.mode.crtc_vdisplay, 3389 &flip_addrs->dirty_rect_count, true); 3390 } 3391 3392 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 3393 const struct drm_display_mode *mode, 3394 const struct dm_connector_state *dm_state, 3395 struct dc_stream_state *stream) 3396 { 3397 enum amdgpu_rmx_type rmx_type; 3398 3399 struct rect src = { 0 }; /* viewport in composition space*/ 3400 struct rect dst = { 0 }; /* stream addressable area */ 3401 3402 /* no mode. nothing to be done */ 3403 if (!mode) 3404 return; 3405 3406 /* Full screen scaling by default */ 3407 src.width = mode->hdisplay; 3408 src.height = mode->vdisplay; 3409 dst.width = stream->timing.h_addressable; 3410 dst.height = stream->timing.v_addressable; 3411 3412 if (dm_state) { 3413 rmx_type = dm_state->scaling; 3414 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3415 if (src.width * dst.height < 3416 src.height * dst.width) { 3417 /* height needs less upscaling/more downscaling */ 3418 dst.width = src.width * 3419 dst.height / src.height; 3420 } else { 3421 /* width needs less upscaling/more downscaling */ 3422 dst.height = src.height * 3423 dst.width / src.width; 3424 } 3425 } else if (rmx_type == RMX_CENTER) { 3426 dst = src; 3427 } 3428 3429 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3430 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3431 3432 if (dm_state->underscan_enable) { 3433 dst.x += dm_state->underscan_hborder / 2; 3434 dst.y += dm_state->underscan_vborder / 2; 3435 dst.width -= dm_state->underscan_hborder; 3436 dst.height -= dm_state->underscan_vborder; 3437 } 3438 } 3439 3440 stream->src = src; 3441 stream->dst = dst; 3442 3443 drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 3444 dst.x, dst.y, dst.width, dst.height); 3445 3446 } 3447 3448 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3449 struct dc_state *dc_state, 3450 struct dsc_mst_fairness_vars *vars) 3451 { 3452 struct dc_stream_state *stream = NULL; 3453 struct drm_connector *connector; 3454 struct drm_connector_state *new_con_state; 3455 struct amdgpu_dm_connector *aconnector; 3456 struct dm_connector_state *dm_conn_state; 3457 int i, j, ret; 3458 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3459 3460 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3461 3462 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3463 continue; 3464 3465 aconnector = to_amdgpu_dm_connector(connector); 3466 3467 if (!aconnector->mst_output_port) 3468 continue; 3469 3470 if (!new_con_state || !new_con_state->crtc) 3471 continue; 3472 3473 dm_conn_state = to_dm_connector_state(new_con_state); 3474 3475 for (j = 0; j < dc_state->stream_count; j++) { 3476 stream = dc_state->streams[j]; 3477 if (!stream) 3478 continue; 3479 3480 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3481 break; 3482 3483 stream = NULL; 3484 } 3485 3486 if (!stream) 3487 continue; 3488 3489 pbn_div = dm_mst_get_pbn_divider(stream->link); 3490 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3491 for (j = 0; j < dc_state->stream_count; j++) { 3492 if (vars[j].aconnector == aconnector) { 3493 pbn = vars[j].pbn; 3494 break; 3495 } 3496 } 3497 3498 if (j == dc_state->stream_count || pbn_div == 0) 3499 continue; 3500 3501 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3502 3503 if (stream->timing.flags.DSC != 1) { 3504 dm_conn_state->pbn = pbn; 3505 dm_conn_state->vcpi_slots = slot_num; 3506 3507 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3508 dm_conn_state->pbn, false); 3509 if (ret < 0) 3510 return ret; 3511 3512 continue; 3513 } 3514 3515 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3516 if (vcpi < 0) 3517 return vcpi; 3518 3519 dm_conn_state->pbn = pbn; 3520 dm_conn_state->vcpi_slots = vcpi; 3521 } 3522 return 0; 3523 } 3524 3525 static void manage_dm_interrupts(struct amdgpu_device *adev, 3526 struct amdgpu_crtc *acrtc, 3527 struct dm_crtc_state *acrtc_state) 3528 { /* 3529 * We cannot be sure that the frontend index maps to the same 3530 * backend index - some even map to more than one. 3531 * So we have to go through the CRTC to find the right IRQ. 3532 */ 3533 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3534 adev, 3535 acrtc->crtc_id); 3536 struct drm_device *dev = adev_to_drm(adev); 3537 3538 struct drm_vblank_crtc_config config = {0}; 3539 struct dc_crtc_timing *timing; 3540 int offdelay; 3541 3542 if (acrtc_state) { 3543 timing = &acrtc_state->stream->timing; 3544 3545 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= 3546 IP_VERSION(3, 2, 0) && 3547 !(adev->flags & AMD_IS_APU)) { 3548 /* 3549 * DGPUs NV3x and newer that support idle optimizations 3550 * experience intermittent flip-done timeouts on cursor 3551 * updates. Restore 5s offdelay behavior for now. 3552 * 3553 * Discussion on the issue: 3554 * https://lore.kernel.org/amd-gfx/20260217191632.1243826-1-sysdadmin@m1k.cloud/ 3555 */ 3556 config.offdelay_ms = 5000; 3557 config.disable_immediate = false; 3558 } else if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3559 IP_VERSION(3, 5, 0)) { 3560 /* 3561 * Older HW and DGPU have issues with instant off; 3562 * use a 2 frame offdelay. 3563 */ 3564 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3565 timing->v_total * 3566 timing->h_total, 3567 timing->pix_clk_100hz); 3568 3569 config.offdelay_ms = offdelay ?: 30; 3570 } else { 3571 /* offdelay_ms = 0 will never disable vblank */ 3572 config.offdelay_ms = 1; 3573 config.disable_immediate = true; 3574 } 3575 3576 drm_crtc_vblank_on_config(&acrtc->base, 3577 &config); 3578 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_get.*/ 3579 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3580 case IP_VERSION(3, 0, 0): 3581 case IP_VERSION(3, 0, 2): 3582 case IP_VERSION(3, 0, 3): 3583 case IP_VERSION(3, 2, 0): 3584 if (amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type)) 3585 drm_err(dev, "DM_IRQ: Cannot get pageflip irq!\n"); 3586 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3587 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3588 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3589 #endif 3590 } 3591 3592 } else { 3593 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3594 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3595 case IP_VERSION(3, 0, 0): 3596 case IP_VERSION(3, 0, 2): 3597 case IP_VERSION(3, 0, 3): 3598 case IP_VERSION(3, 2, 0): 3599 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3600 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3601 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3602 #endif 3603 if (amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type)) 3604 drm_err(dev, "DM_IRQ: Cannot put pageflip irq!\n"); 3605 } 3606 3607 drm_crtc_vblank_off(&acrtc->base); 3608 } 3609 } 3610 3611 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3612 struct amdgpu_crtc *acrtc) 3613 { 3614 int irq_type = 3615 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3616 3617 /** 3618 * This reads the current state for the IRQ and force reapplies 3619 * the setting to hardware. 3620 */ 3621 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3622 } 3623 3624 STATIC_IFN_KUNIT bool 3625 is_scaling_state_different(const struct dm_connector_state *dm_state, 3626 const struct dm_connector_state *old_dm_state) 3627 { 3628 if (dm_state->scaling != old_dm_state->scaling) 3629 return true; 3630 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3631 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3632 return true; 3633 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3634 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3635 return true; 3636 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3637 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3638 return true; 3639 return false; 3640 } 3641 EXPORT_IF_KUNIT(is_scaling_state_different); 3642 3643 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3644 struct drm_crtc_state *old_crtc_state, 3645 struct drm_connector_state *new_conn_state, 3646 struct drm_connector_state *old_conn_state, 3647 const struct drm_connector *connector, 3648 struct hdcp_workqueue *hdcp_w) 3649 { 3650 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3651 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3652 3653 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3654 connector->index, connector->status, connector->dpms); 3655 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3656 old_conn_state->content_protection, new_conn_state->content_protection); 3657 3658 if (old_crtc_state) 3659 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3660 old_crtc_state->enable, 3661 old_crtc_state->active, 3662 old_crtc_state->mode_changed, 3663 old_crtc_state->active_changed, 3664 old_crtc_state->connectors_changed); 3665 3666 if (new_crtc_state) 3667 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3668 new_crtc_state->enable, 3669 new_crtc_state->active, 3670 new_crtc_state->mode_changed, 3671 new_crtc_state->active_changed, 3672 new_crtc_state->connectors_changed); 3673 3674 /* hdcp content type change */ 3675 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3676 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3677 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3678 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3679 return true; 3680 } 3681 3682 /* CP is being re enabled, ignore this */ 3683 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3684 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3685 if (new_crtc_state && new_crtc_state->mode_changed) { 3686 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3687 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3688 return true; 3689 } 3690 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3691 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3692 return false; 3693 } 3694 3695 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3696 * 3697 * Handles: UNDESIRED -> ENABLED 3698 */ 3699 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3700 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3701 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3702 3703 /* Stream removed and re-enabled 3704 * 3705 * Can sometimes overlap with the HPD case, 3706 * thus set update_hdcp to false to avoid 3707 * setting HDCP multiple times. 3708 * 3709 * Handles: DESIRED -> DESIRED (Special case) 3710 */ 3711 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3712 new_conn_state->crtc && new_conn_state->crtc->enabled && 3713 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3714 dm_con_state->update_hdcp = false; 3715 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3716 __func__); 3717 return true; 3718 } 3719 3720 /* Hot-plug, headless s3, dpms 3721 * 3722 * Only start HDCP if the display is connected/enabled. 3723 * update_hdcp flag will be set to false until the next 3724 * HPD comes in. 3725 * 3726 * Handles: DESIRED -> DESIRED (Special case) 3727 */ 3728 if (dm_con_state->update_hdcp && 3729 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3730 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3731 dm_con_state->update_hdcp = false; 3732 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3733 __func__); 3734 return true; 3735 } 3736 3737 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3738 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3739 if (new_crtc_state && new_crtc_state->mode_changed) { 3740 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3741 __func__); 3742 return true; 3743 } 3744 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3745 __func__); 3746 return false; 3747 } 3748 3749 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3750 return false; 3751 } 3752 3753 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3754 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3755 __func__); 3756 return true; 3757 } 3758 3759 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3760 return false; 3761 } 3762 3763 static void remove_stream(struct amdgpu_device *adev, 3764 struct amdgpu_crtc *acrtc, 3765 struct dc_stream_state *stream) 3766 { 3767 /* this is the update mode case */ 3768 3769 acrtc->otg_inst = -1; 3770 acrtc->enabled = false; 3771 } 3772 3773 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 3774 { 3775 3776 assert_spin_locked(&acrtc->base.dev->event_lock); 3777 WARN_ON(acrtc->event); 3778 3779 acrtc->event = acrtc->base.state->event; 3780 3781 /* Set the flip status */ 3782 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3783 3784 /* Mark this event as consumed */ 3785 acrtc->base.state->event = NULL; 3786 3787 drm_dbg_state(acrtc->base.dev, 3788 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3789 acrtc->crtc_id); 3790 } 3791 3792 static void update_freesync_state_on_stream( 3793 struct amdgpu_display_manager *dm, 3794 struct dm_crtc_state *new_crtc_state, 3795 struct dc_stream_state *new_stream, 3796 struct dc_plane_state *surface, 3797 u32 flip_timestamp_in_us) 3798 { 3799 struct mod_vrr_params vrr_params; 3800 struct dc_info_packet vrr_infopacket = {0}; 3801 struct amdgpu_device *adev = dm->adev; 3802 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3803 unsigned long flags; 3804 bool pack_sdp_v1_3 = false; 3805 struct amdgpu_dm_connector *aconn; 3806 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 3807 3808 if (!new_stream) 3809 return; 3810 3811 /* 3812 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3813 * For now it's sufficient to just guard against these conditions. 3814 */ 3815 3816 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3817 return; 3818 3819 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3820 vrr_params = acrtc->dm_irq_params.vrr_params; 3821 3822 if (surface) { 3823 mod_freesync_handle_preflip( 3824 dm->freesync_module, 3825 surface, 3826 new_stream, 3827 flip_timestamp_in_us, 3828 &vrr_params); 3829 3830 if (adev->family < AMDGPU_FAMILY_AI && 3831 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 3832 mod_freesync_handle_v_update(dm->freesync_module, 3833 new_stream, &vrr_params); 3834 3835 /* Need to call this before the frame ends. */ 3836 dc_stream_adjust_vmin_vmax(dm->dc, 3837 new_crtc_state->stream, 3838 &vrr_params.adjust); 3839 } 3840 } 3841 3842 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 3843 3844 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 3845 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 3846 3847 if (aconn->vsdb_info.amd_vsdb_version == 1) 3848 packet_type = PACKET_TYPE_FS_V1; 3849 else if (aconn->vsdb_info.amd_vsdb_version == 2) 3850 packet_type = PACKET_TYPE_FS_V2; 3851 else if (aconn->vsdb_info.amd_vsdb_version == 3) 3852 packet_type = PACKET_TYPE_FS_V3; 3853 3854 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 3855 &new_stream->adaptive_sync_infopacket); 3856 } 3857 3858 mod_freesync_build_vrr_infopacket( 3859 dm->freesync_module, 3860 new_stream, 3861 &vrr_params, 3862 packet_type, 3863 TRANSFER_FUNC_UNKNOWN, 3864 &vrr_infopacket, 3865 pack_sdp_v1_3); 3866 3867 new_crtc_state->freesync_vrr_info_changed |= 3868 (memcmp(&new_crtc_state->vrr_infopacket, 3869 &vrr_infopacket, 3870 sizeof(vrr_infopacket)) != 0); 3871 3872 acrtc->dm_irq_params.vrr_params = vrr_params; 3873 new_crtc_state->vrr_infopacket = vrr_infopacket; 3874 3875 new_stream->vrr_infopacket = vrr_infopacket; 3876 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 3877 3878 if (new_crtc_state->freesync_vrr_info_changed) 3879 drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", 3880 new_crtc_state->base.crtc->base.id, 3881 (int)new_crtc_state->base.vrr_enabled, 3882 (int)vrr_params.state); 3883 3884 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3885 } 3886 3887 static void update_stream_irq_parameters( 3888 struct amdgpu_display_manager *dm, 3889 struct dm_crtc_state *new_crtc_state) 3890 { 3891 struct dc_stream_state *new_stream = new_crtc_state->stream; 3892 struct mod_vrr_params vrr_params; 3893 struct mod_freesync_config config = new_crtc_state->freesync_config; 3894 struct amdgpu_device *adev = dm->adev; 3895 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3896 unsigned long flags; 3897 3898 if (!new_stream) 3899 return; 3900 3901 /* 3902 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3903 * For now it's sufficient to just guard against these conditions. 3904 */ 3905 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3906 return; 3907 3908 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3909 vrr_params = acrtc->dm_irq_params.vrr_params; 3910 3911 if (new_crtc_state->vrr_supported && 3912 config.min_refresh_in_uhz && 3913 config.max_refresh_in_uhz) { 3914 /* 3915 * if freesync compatible mode was set, config.state will be set 3916 * in atomic check 3917 */ 3918 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 3919 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 3920 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 3921 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 3922 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 3923 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 3924 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 3925 } else { 3926 config.state = new_crtc_state->base.vrr_enabled ? 3927 VRR_STATE_ACTIVE_VARIABLE : 3928 VRR_STATE_INACTIVE; 3929 } 3930 } else { 3931 config.state = VRR_STATE_UNSUPPORTED; 3932 } 3933 3934 mod_freesync_build_vrr_params(dm->freesync_module, 3935 new_stream, 3936 &config, &vrr_params); 3937 3938 new_crtc_state->freesync_config = config; 3939 /* Copy state for access from DM IRQ handler */ 3940 acrtc->dm_irq_params.freesync_config = config; 3941 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 3942 acrtc->dm_irq_params.vrr_params = vrr_params; 3943 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3944 } 3945 3946 static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, 3947 struct dm_crtc_state *old_state, 3948 struct dm_crtc_state *new_state) 3949 { 3950 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 3951 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 3952 3953 if (!old_vrr_active && new_vrr_active) { 3954 /* Transition VRR inactive -> active: 3955 * While VRR is active, we must not disable vblank irq, as a 3956 * reenable after disable would compute bogus vblank/pflip 3957 * timestamps if it likely happened inside display front-porch. 3958 * 3959 * We also need vupdate irq for the actual core vblank handling 3960 * at end of vblank. 3961 */ 3962 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 3963 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 3964 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", 3965 __func__, new_state->base.crtc->base.id); 3966 3967 scoped_guard(mutex, &dm->dc_lock) { 3968 dc_exit_ips_for_hw_access(dm->dc); 3969 amdgpu_dm_psr_set_event(dm, new_state->stream, true, 3970 psr_event_vrr_transition, true); 3971 amdgpu_dm_replay_set_event(dm, new_state->stream, true, 3972 replay_event_vrr, true); 3973 } 3974 } else if (old_vrr_active && !new_vrr_active) { 3975 /* Transition VRR active -> inactive: 3976 * Allow vblank irq disable again for fixed refresh rate. 3977 */ 3978 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 3979 drm_crtc_vblank_put(new_state->base.crtc); 3980 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", 3981 __func__, new_state->base.crtc->base.id); 3982 3983 scoped_guard(mutex, &dm->dc_lock) { 3984 dc_exit_ips_for_hw_access(dm->dc); 3985 amdgpu_dm_psr_set_event(dm, new_state->stream, false, 3986 psr_event_vrr_transition, false); 3987 amdgpu_dm_replay_set_event(dm, new_state->stream, false, 3988 replay_event_vrr, false); 3989 } 3990 } 3991 } 3992 3993 static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 3994 { 3995 struct drm_plane *plane; 3996 struct drm_plane_state *old_plane_state; 3997 int i; 3998 3999 /* 4000 * TODO: Make this per-stream so we don't issue redundant updates for 4001 * commits with multiple streams. 4002 */ 4003 for_each_old_plane_in_state(state, plane, old_plane_state, i) 4004 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4005 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 4006 } 4007 4008 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 4009 { 4010 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 4011 4012 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 4013 } 4014 4015 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 4016 struct drm_plane_state *old_plane_state, 4017 struct dc_stream_update *update) 4018 { 4019 struct amdgpu_device *adev = drm_to_adev(plane->dev); 4020 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4021 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4022 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4023 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4024 uint64_t address = afb ? afb->address : 0; 4025 struct dc_cursor_position position = {0}; 4026 struct dc_cursor_attributes attributes; 4027 int ret; 4028 4029 if (!plane->state->fb && !old_plane_state->fb) 4030 return; 4031 4032 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 4033 amdgpu_crtc->crtc_id, plane->state->crtc_w, 4034 plane->state->crtc_h); 4035 4036 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 4037 if (ret) 4038 return; 4039 4040 if (!position.enable) { 4041 /* turn off cursor */ 4042 if (crtc_state && crtc_state->stream) { 4043 dc_stream_set_cursor_position(crtc_state->stream, 4044 &position); 4045 update->cursor_position = &crtc_state->stream->cursor_position; 4046 } 4047 return; 4048 } 4049 4050 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4051 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4052 4053 memset(&attributes, 0, sizeof(attributes)); 4054 attributes.address.high_part = upper_32_bits(address); 4055 attributes.address.low_part = lower_32_bits(address); 4056 attributes.width = plane->state->crtc_w; 4057 attributes.height = plane->state->crtc_h; 4058 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4059 attributes.rotation_angle = 0; 4060 attributes.attribute_flags.value = 0; 4061 4062 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 4063 * legacy gamma setup. 4064 */ 4065 if (crtc_state->cm_is_degamma_srgb && 4066 adev->dm.dc->caps.color.dpp.gamma_corr) 4067 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 4068 4069 if (afb) 4070 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 4071 4072 if (crtc_state->stream) { 4073 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4074 &attributes)) 4075 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 4076 4077 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 4078 4079 if (!dc_stream_set_cursor_position(crtc_state->stream, 4080 &position)) 4081 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 4082 4083 update->cursor_position = &crtc_state->stream->cursor_position; 4084 } 4085 } 4086 4087 static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 4088 struct amdgpu_crtc *acrtc_attach, 4089 const struct dm_crtc_state *acrtc_state, 4090 const u64 current_ts) 4091 { 4092 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 4093 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 4094 struct amdgpu_dm_connector *aconn = 4095 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 4096 4097 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 4098 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 4099 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 4100 if (aconn->sr_skip_count > 0) 4101 aconn->sr_skip_count--; 4102 4103 /* Allow SR when skip count is 0. */ 4104 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 4105 4106 /* 4107 * If sink supports PSR SU/Panel Replay, there is no need to rely on 4108 * a vblank event disable request to enable PSR/RP. PSR SU/RP 4109 * can be enabled immediately once OS demonstrates an 4110 * adequate number of fast atomic commits to notify KMD 4111 * of update events. 4112 * See `amdgpu_dm_crtc_vblank_control_worker()`. 4113 */ 4114 if (acrtc_attach->dm_irq_params.allow_sr_entry && 4115 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 4116 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 4117 psr_event_hw_programming, false); 4118 4119 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 4120 replay_event_hw_programming, false); 4121 } 4122 } else { 4123 acrtc_attach->dm_irq_params.allow_sr_entry = false; 4124 } 4125 } 4126 4127 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 4128 struct drm_device *dev, 4129 struct amdgpu_display_manager *dm, 4130 struct drm_crtc *pcrtc, 4131 bool wait_for_vblank) 4132 { 4133 u32 i; 4134 u64 timestamp_ns = ktime_get_ns(); 4135 struct drm_plane *plane; 4136 struct drm_plane_state *old_plane_state, *new_plane_state; 4137 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4138 struct drm_crtc_state *new_pcrtc_state = 4139 drm_atomic_get_new_crtc_state(state, pcrtc); 4140 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4141 struct dm_crtc_state *dm_old_crtc_state = 4142 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4143 int planes_count = 0, vpos, hpos; 4144 unsigned long flags; 4145 u32 target_vblank, last_flip_vblank; 4146 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 4147 bool cursor_update = false; 4148 bool pflip_present = false; 4149 bool dirty_rects_changed = false; 4150 bool updated_planes_and_streams = false; 4151 struct { 4152 struct dc_surface_update surface_updates[MAX_SURFACES]; 4153 struct dc_plane_info plane_infos[MAX_SURFACES]; 4154 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 4155 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 4156 struct dc_stream_update stream_update; 4157 } *bundle; 4158 4159 bundle = kzalloc_obj(*bundle); 4160 4161 if (!bundle) { 4162 drm_err(dev, "Failed to allocate update bundle\n"); 4163 goto cleanup; 4164 } 4165 4166 /* 4167 * Disable the cursor first if we're disabling all the planes. 4168 * It'll remain on the screen after the planes are re-enabled 4169 * if we don't. 4170 * 4171 * If the cursor is transitioning from native to overlay mode, the 4172 * native cursor needs to be disabled first. 4173 */ 4174 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 4175 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4176 struct dc_cursor_position cursor_position = {0}; 4177 4178 if (!dc_stream_set_cursor_position(acrtc_state->stream, 4179 &cursor_position)) 4180 drm_err(dev, "DC failed to disable native cursor\n"); 4181 4182 bundle->stream_update.cursor_position = 4183 &acrtc_state->stream->cursor_position; 4184 } 4185 4186 if (acrtc_state->active_planes == 0 && 4187 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4188 amdgpu_dm_commit_cursors(state); 4189 4190 /* update planes when needed */ 4191 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4192 struct drm_crtc *crtc = new_plane_state->crtc; 4193 struct drm_crtc_state *new_crtc_state; 4194 struct drm_framebuffer *fb = new_plane_state->fb; 4195 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 4196 bool plane_needs_flip; 4197 struct dc_plane_state *dc_plane; 4198 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4199 4200 /* Cursor plane is handled after stream updates */ 4201 if (plane->type == DRM_PLANE_TYPE_CURSOR && 4202 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4203 if ((fb && crtc == pcrtc) || 4204 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 4205 cursor_update = true; 4206 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 4207 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 4208 } 4209 4210 continue; 4211 } 4212 4213 if (!fb || !crtc || pcrtc != crtc) 4214 continue; 4215 4216 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4217 if (!new_crtc_state->active) 4218 continue; 4219 4220 dc_plane = dm_new_plane_state->dc_state; 4221 if (!dc_plane) 4222 continue; 4223 4224 bundle->surface_updates[planes_count].surface = dc_plane; 4225 if (new_pcrtc_state->color_mgmt_changed) { 4226 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 4227 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 4228 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 4229 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 4230 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 4231 } 4232 4233 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 4234 &bundle->scaling_infos[planes_count]); 4235 4236 bundle->surface_updates[planes_count].scaling_info = 4237 &bundle->scaling_infos[planes_count]; 4238 4239 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 4240 4241 pflip_present = pflip_present || plane_needs_flip; 4242 4243 if (!plane_needs_flip) { 4244 planes_count += 1; 4245 continue; 4246 } 4247 4248 fill_dc_plane_info_and_addr( 4249 dm->adev, new_plane_state, 4250 afb->tiling_flags, 4251 &bundle->plane_infos[planes_count], 4252 &bundle->flip_addrs[planes_count].address, 4253 afb->tmz_surface); 4254 4255 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 4256 new_plane_state->plane->index, 4257 bundle->plane_infos[planes_count].dcc.enable); 4258 4259 bundle->surface_updates[planes_count].plane_info = 4260 &bundle->plane_infos[planes_count]; 4261 4262 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 4263 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 4264 fill_dc_dirty_rects(plane, old_plane_state, 4265 new_plane_state, new_crtc_state, 4266 &bundle->flip_addrs[planes_count], 4267 acrtc_state->stream->link->psr_settings.psr_version == 4268 DC_PSR_VERSION_SU_1, 4269 &dirty_rects_changed); 4270 4271 /* 4272 * If the dirty regions changed, PSR-SU need to be disabled temporarily 4273 * and enabled it again after dirty regions are stable to avoid video glitch. 4274 * PSR-SU will be enabled in 4275 * amdgpu_dm_crtc_vblank_control_worker() if user 4276 * pause the video during the PSR-SU was disabled. 4277 */ 4278 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 4279 acrtc_attach->dm_irq_params.allow_sr_entry && 4280 dirty_rects_changed) { 4281 mutex_lock(&dm->dc_lock); 4282 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 4283 timestamp_ns; 4284 dc_exit_ips_for_hw_access(dm->dc); 4285 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 4286 psr_event_hw_programming, true); 4287 mutex_unlock(&dm->dc_lock); 4288 } 4289 } 4290 4291 /* 4292 * Only allow immediate flips for fast updates that don't 4293 * change memory domain, FB pitch, DCC state, rotation or 4294 * mirroring. 4295 * 4296 * dm_crtc_helper_atomic_check() only accepts async flips with 4297 * fast updates. 4298 */ 4299 if (crtc->state->async_flip && 4300 (acrtc_state->update_type != UPDATE_TYPE_FAST || 4301 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 4302 drm_warn_once(state->dev, 4303 "[PLANE:%d:%s] async flip with non-fast update\n", 4304 plane->base.id, plane->name); 4305 4306 bundle->flip_addrs[planes_count].flip_immediate = 4307 crtc->state->async_flip && 4308 acrtc_state->update_type == UPDATE_TYPE_FAST && 4309 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 4310 4311 timestamp_ns = ktime_get_ns(); 4312 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 4313 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 4314 bundle->surface_updates[planes_count].surface = dc_plane; 4315 4316 if (!bundle->surface_updates[planes_count].surface) { 4317 drm_err(dev, "No surface for CRTC: id=%d\n", 4318 acrtc_attach->crtc_id); 4319 continue; 4320 } 4321 4322 if (plane == pcrtc->primary) 4323 update_freesync_state_on_stream( 4324 dm, 4325 acrtc_state, 4326 acrtc_state->stream, 4327 dc_plane, 4328 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 4329 4330 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 4331 __func__, 4332 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4333 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4334 4335 planes_count += 1; 4336 4337 } 4338 4339 if (pflip_present) { 4340 if (!vrr_active) { 4341 /* Use old throttling in non-vrr fixed refresh rate mode 4342 * to keep flip scheduling based on target vblank counts 4343 * working in a backwards compatible way, e.g., for 4344 * clients using the GLX_OML_sync_control extension or 4345 * DRI3/Present extension with defined target_msc. 4346 */ 4347 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 4348 } else { 4349 /* For variable refresh rate mode only: 4350 * Get vblank of last completed flip to avoid > 1 vrr 4351 * flips per video frame by use of throttling, but allow 4352 * flip programming anywhere in the possibly large 4353 * variable vrr vblank interval for fine-grained flip 4354 * timing control and more opportunity to avoid stutter 4355 * on late submission of flips. 4356 */ 4357 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4358 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4359 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4360 } 4361 4362 target_vblank = last_flip_vblank + wait_for_vblank; 4363 4364 /* 4365 * Wait until we're out of the vertical blank period before the one 4366 * targeted by the flip 4367 */ 4368 while ((acrtc_attach->enabled && 4369 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4370 0, &vpos, &hpos, NULL, 4371 NULL, &pcrtc->hwmode) 4372 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4373 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4374 (int)(target_vblank - 4375 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4376 usleep_range(1000, 1100); 4377 } 4378 4379 /** 4380 * Prepare the flip event for the pageflip interrupt to handle. 4381 * 4382 * This only works in the case where we've already turned on the 4383 * appropriate hardware blocks (eg. HUBP) so in the transition case 4384 * from 0 -> n planes we have to skip a hardware generated event 4385 * and rely on sending it from software. 4386 */ 4387 if (acrtc_attach->base.state->event && 4388 acrtc_state->active_planes > 0) { 4389 drm_crtc_vblank_get(pcrtc); 4390 4391 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4392 4393 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE); 4394 prepare_flip_isr(acrtc_attach); 4395 4396 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4397 } 4398 4399 if (acrtc_state->stream) { 4400 if (acrtc_state->freesync_vrr_info_changed) 4401 bundle->stream_update.vrr_infopacket = 4402 &acrtc_state->stream->vrr_infopacket; 4403 } 4404 } else if (cursor_update && acrtc_state->active_planes > 0) { 4405 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4406 if (acrtc_attach->base.state->event) { 4407 drm_crtc_vblank_get(pcrtc); 4408 acrtc_attach->event = acrtc_attach->base.state->event; 4409 acrtc_attach->base.state->event = NULL; 4410 } 4411 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4412 } 4413 4414 /* Update the planes if changed or disable if we don't have any. */ 4415 if ((planes_count || acrtc_state->active_planes == 0) && 4416 acrtc_state->stream) { 4417 /* 4418 * If PSR or idle optimizations are enabled then flush out 4419 * any pending work before hardware programming. 4420 */ 4421 if (dm->vblank_control_workqueue) 4422 flush_workqueue(dm->vblank_control_workqueue); 4423 4424 bundle->stream_update.stream = acrtc_state->stream; 4425 if (new_pcrtc_state->mode_changed) { 4426 bundle->stream_update.src = acrtc_state->stream->src; 4427 bundle->stream_update.dst = acrtc_state->stream->dst; 4428 } 4429 4430 if (new_pcrtc_state->color_mgmt_changed) { 4431 /* 4432 * TODO: This isn't fully correct since we've actually 4433 * already modified the stream in place. 4434 */ 4435 bundle->stream_update.gamut_remap = 4436 &acrtc_state->stream->gamut_remap_matrix; 4437 bundle->stream_update.output_csc_transform = 4438 &acrtc_state->stream->csc_color_matrix; 4439 bundle->stream_update.out_transfer_func = 4440 &acrtc_state->stream->out_transfer_func; 4441 bundle->stream_update.lut3d_func = 4442 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4443 bundle->stream_update.func_shaper = 4444 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4445 } 4446 4447 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4448 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4449 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4450 4451 /* 4452 * If FreeSync state on the stream has changed then we need to 4453 * re-adjust the min/max bounds now that DC doesn't handle this 4454 * as part of commit. 4455 */ 4456 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4457 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4458 dc_stream_adjust_vmin_vmax( 4459 dm->dc, acrtc_state->stream, 4460 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4461 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4462 } 4463 mutex_lock(&dm->dc_lock); 4464 update_planes_and_stream_adapter(dm->dc, 4465 acrtc_state->update_type, 4466 planes_count, 4467 acrtc_state->stream, 4468 &bundle->stream_update, 4469 bundle->surface_updates); 4470 updated_planes_and_streams = true; 4471 4472 /** 4473 * Enable or disable the interrupts on the backend. 4474 * 4475 * Most pipes are put into power gating when unused. 4476 * 4477 * When power gating is enabled on a pipe we lose the 4478 * interrupt enablement state when power gating is disabled. 4479 * 4480 * So we need to update the IRQ control state in hardware 4481 * whenever the pipe turns on (since it could be previously 4482 * power gated) or off (since some pipes can't be power gated 4483 * on some ASICs). 4484 */ 4485 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4486 dm_update_pflip_irq_state(drm_to_adev(dev), 4487 acrtc_attach); 4488 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4489 timestamp_ns); 4490 mutex_unlock(&dm->dc_lock); 4491 } 4492 4493 /* 4494 * Update cursor state *after* programming all the planes. 4495 * This avoids redundant programming in the case where we're going 4496 * to be disabling a single plane - those pipes are being disabled. 4497 */ 4498 if (acrtc_state->active_planes && 4499 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4500 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4501 amdgpu_dm_commit_cursors(state); 4502 4503 cleanup: 4504 kfree(bundle); 4505 } 4506 4507 /* 4508 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4509 * @crtc_state: the DRM CRTC state 4510 * @stream_state: the DC stream state. 4511 * 4512 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4513 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4514 */ 4515 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4516 struct dc_stream_state *stream_state) 4517 { 4518 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4519 } 4520 4521 /** 4522 * amdgpu_dm_crtc_complete_writeback - finish a pending writeback job 4523 * @acrtc: the CRTC whose pending writeback should be completed 4524 * 4525 * Clears the pending state, signals the writeback out fence and releases the 4526 * vblank reference taken in dm_set_writeback() while the writeback was armed. 4527 * The pending flag is tested and cleared under the writeback job lock, so this 4528 * is safe to call concurrently from the completion vblank IRQ 4529 * (dm_crtc_high_irq()) and from the writeback teardown path 4530 * (dm_clear_writeback()); only the caller that observes the pending job 4531 * performs the completion. 4532 * 4533 * Return: true if a pending writeback job was completed by this call. 4534 */ 4535 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc) 4536 { 4537 unsigned long flags; 4538 bool pending; 4539 4540 if (!acrtc->wb_conn) 4541 return false; 4542 4543 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 4544 pending = acrtc->wb_pending; 4545 acrtc->wb_pending = false; 4546 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 4547 4548 if (!pending) 4549 return false; 4550 4551 drm_writeback_signal_completion(acrtc->wb_conn, 0); 4552 drm_crtc_vblank_put(&acrtc->base); 4553 4554 return true; 4555 } 4556 4557 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 4558 struct amdgpu_crtc *acrtc, 4559 struct dm_crtc_state *crtc_state) 4560 { 4561 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4562 4563 /* 4564 * If the writeback is still pending when it is torn down (its 4565 * completion vblank IRQ never fired), signal the out fence so a 4566 * waiting client does not stall and release the vblank reference 4567 * taken in dm_set_writeback(). 4568 */ 4569 amdgpu_dm_crtc_complete_writeback(acrtc); 4570 } 4571 4572 /** 4573 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4574 * @state: the drm atomic state 4575 * @dm: the display manager to update mod_power on 4576 * 4577 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4578 * in preparation for hardware programming. See also 4579 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4580 */ 4581 static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4582 struct amdgpu_display_manager *dm) 4583 { 4584 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4585 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4586 struct amdgpu_dm_connector *aconnector; 4587 struct drm_crtc *crtc; 4588 int i = 0; 4589 4590 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4591 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4592 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4593 4594 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4595 continue; 4596 4597 /* 4598 * Update mod_power on modeset event in preparation for hw 4599 * programming. Always use the old stream, since it would have 4600 * been previously added to mod_power. If old stream is null (on 4601 * crtc enable, for example), mod_power will no-op, which is the 4602 * desried behavior. 4603 */ 4604 if (old_crtc_state->active) { 4605 scoped_guard(mutex, &dm->dc_lock) { 4606 dc_exit_ips_for_hw_access(dm->dc); 4607 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4608 psr_event_hw_programming, true); 4609 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4610 replay_event_hw_programming, true); 4611 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4612 replay_event_general_ui, false); 4613 } 4614 } 4615 4616 if (new_crtc_state->active) { 4617 aconnector = (struct amdgpu_dm_connector *) 4618 dm_new_crtc_state->stream->dm_stream_context; 4619 if (old_crtc_state->active) { 4620 mod_power_replace_stream(dm->power_module, 4621 dm_old_crtc_state->stream, 4622 dm_new_crtc_state->stream, 4623 &aconnector->psr_caps); 4624 } else { 4625 mod_power_add_stream(dm->power_module, 4626 dm_new_crtc_state->stream, 4627 &aconnector->psr_caps); 4628 } 4629 } else if (old_crtc_state->active) { 4630 mod_power_remove_stream(dm->power_module, 4631 dm_old_crtc_state->stream); 4632 } 4633 } 4634 } 4635 4636 /** 4637 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4638 * @state: the drm atomic state 4639 * @dm: the display manager to update mod_power on 4640 * 4641 * Notify mod_power of mode_change. This needs to be done after dc_stream 4642 * updates have been committed, and VRR parameters have been updated. 4643 */ 4644 static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4645 struct amdgpu_display_manager *dm) 4646 { 4647 struct dm_crtc_state *dm_new_crtc_state; 4648 struct drm_crtc_state *new_crtc_state; 4649 struct amdgpu_crtc *acrtc; 4650 struct drm_crtc *crtc; 4651 int i = 0; 4652 4653 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4654 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4655 acrtc = to_amdgpu_crtc(crtc); 4656 4657 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4658 continue; 4659 4660 if (new_crtc_state->active) { 4661 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4662 &acrtc->dm_irq_params.vrr_params); 4663 mod_power_notify_mode_change(dm->power_module, 4664 dm_new_crtc_state->stream, 4665 false); 4666 4667 /* 4668 * Block PSR / Replay on the new stream until display settles post-modeset. 4669 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4670 * allow_sr_entry becomes true. 4671 */ 4672 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4673 psr_event_hw_programming, true); 4674 4675 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4676 replay_event_hw_programming | replay_event_general_ui, 4677 true); 4678 } 4679 } 4680 4681 } 4682 4683 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4684 struct dc_state *dc_state) 4685 { 4686 struct drm_device *dev = state->dev; 4687 struct amdgpu_device *adev = drm_to_adev(dev); 4688 struct amdgpu_display_manager *dm = &adev->dm; 4689 struct drm_crtc *crtc; 4690 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4691 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4692 struct drm_connector_state *old_con_state; 4693 struct drm_connector *connector; 4694 bool mode_set_reset_required = false; 4695 u32 i; 4696 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4697 bool set_backlight_level = false; 4698 4699 /* Disable writeback */ 4700 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4701 struct dm_connector_state *dm_old_con_state; 4702 struct amdgpu_crtc *acrtc; 4703 4704 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4705 continue; 4706 4707 old_crtc_state = NULL; 4708 4709 dm_old_con_state = to_dm_connector_state(old_con_state); 4710 if (!dm_old_con_state->base.crtc) 4711 continue; 4712 4713 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4714 if (acrtc) 4715 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4716 4717 if (!acrtc || !acrtc->wb_enabled) 4718 continue; 4719 4720 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4721 4722 dm_clear_writeback(dm, acrtc, dm_old_crtc_state); 4723 acrtc->wb_enabled = false; 4724 } 4725 4726 amdgpu_dm_mod_power_update_streams(state, dm); 4727 4728 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4729 new_crtc_state, i) { 4730 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4731 4732 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4733 4734 if (old_crtc_state->active && 4735 (!new_crtc_state->active || 4736 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4737 manage_dm_interrupts(adev, acrtc, NULL); 4738 dc_stream_release(dm_old_crtc_state->stream); 4739 } 4740 } 4741 4742 drm_atomic_helper_calc_timestamping_constants(state); 4743 4744 /* update changed items */ 4745 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4746 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4747 4748 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4749 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4750 4751 drm_dbg_state(state->dev, 4752 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4753 acrtc->crtc_id, 4754 new_crtc_state->enable, 4755 new_crtc_state->active, 4756 new_crtc_state->planes_changed, 4757 new_crtc_state->mode_changed, 4758 new_crtc_state->active_changed, 4759 new_crtc_state->connectors_changed); 4760 4761 /* Disable cursor if disabling crtc */ 4762 if (old_crtc_state->active && !new_crtc_state->active) { 4763 struct dc_cursor_position position; 4764 4765 memset(&position, 0, sizeof(position)); 4766 mutex_lock(&dm->dc_lock); 4767 dc_exit_ips_for_hw_access(dm->dc); 4768 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4769 mutex_unlock(&dm->dc_lock); 4770 } 4771 4772 /* Copy all transient state flags into dc state */ 4773 if (dm_new_crtc_state->stream) { 4774 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4775 dm_new_crtc_state->stream); 4776 } 4777 4778 /* handles headless hotplug case, updating new_state and 4779 * aconnector as needed 4780 */ 4781 4782 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4783 4784 drm_dbg_atomic(dev, 4785 "Atomic commit: SET crtc id %d: [%p]\n", 4786 acrtc->crtc_id, acrtc); 4787 4788 if (!dm_new_crtc_state->stream) { 4789 /* 4790 * this could happen because of issues with 4791 * userspace notifications delivery. 4792 * In this case userspace tries to set mode on 4793 * display which is disconnected in fact. 4794 * dc_sink is NULL in this case on aconnector. 4795 * We expect reset mode will come soon. 4796 * 4797 * This can also happen when unplug is done 4798 * during resume sequence ended 4799 * 4800 * In this case, we want to pretend we still 4801 * have a sink to keep the pipe running so that 4802 * hw state is consistent with the sw state 4803 */ 4804 drm_dbg_atomic(dev, 4805 "Failed to create new stream for crtc %d\n", 4806 acrtc->base.base.id); 4807 continue; 4808 } 4809 4810 if (dm_old_crtc_state->stream) 4811 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4812 4813 pm_runtime_get_noresume(dev->dev); 4814 4815 acrtc->enabled = true; 4816 acrtc->hw_mode = new_crtc_state->mode; 4817 crtc->hwmode = new_crtc_state->mode; 4818 mode_set_reset_required = true; 4819 set_backlight_level = true; 4820 } else if (modereset_required(new_crtc_state)) { 4821 drm_dbg_atomic(dev, 4822 "Atomic commit: RESET. crtc id %d:[%p]\n", 4823 acrtc->crtc_id, acrtc); 4824 /* i.e. reset mode */ 4825 if (dm_old_crtc_state->stream) 4826 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4827 4828 mode_set_reset_required = true; 4829 } 4830 } /* for_each_crtc_in_state() */ 4831 4832 /* if there mode set or reset, flush vblank work queue */ 4833 if (mode_set_reset_required) { 4834 if (dm->vblank_control_workqueue) 4835 flush_workqueue(dm->vblank_control_workqueue); 4836 } 4837 4838 dm_enable_per_frame_crtc_master_sync(dc_state); 4839 mutex_lock(&dm->dc_lock); 4840 dc_exit_ips_for_hw_access(dm->dc); 4841 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4842 4843 bool frl_stream_found = false; 4844 4845 for (i = 0; i < params.stream_count; i++) { 4846 struct dc_stream_state *stream = params.streams[i]; 4847 4848 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4849 frl_stream_found = true; 4850 break; 4851 } 4852 } 4853 if (frl_stream_found) { 4854 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 4855 &dm->hdmi_frl_status_polling_work, 4856 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 4857 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 4858 } else { 4859 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 4860 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 4861 } 4862 /* Allow idle optimization when vblank count is 0 for display off */ 4863 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 4864 dc_allow_idle_optimizations(dm->dc, true); 4865 mutex_unlock(&dm->dc_lock); 4866 4867 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4868 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4869 4870 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4871 4872 if (dm_new_crtc_state->stream != NULL) { 4873 const struct dc_stream_status *status = 4874 dc_stream_get_status(dm_new_crtc_state->stream); 4875 4876 if (!status) 4877 status = dc_state_get_stream_status(dc_state, 4878 dm_new_crtc_state->stream); 4879 if (!status) 4880 drm_err(dev, 4881 "got no status for stream %p on acrtc%p\n", 4882 dm_new_crtc_state->stream, acrtc); 4883 else 4884 acrtc->otg_inst = status->primary_otg_inst; 4885 } 4886 } 4887 4888 /* During boot up and resume the DC layer will reset the panel brightness 4889 * to fix a flicker issue. 4890 * It will cause the dm->actual_brightness is not the current panel brightness 4891 * level. (the dm->brightness is the correct panel level) 4892 * So we set the backlight level with dm->brightness value after set mode 4893 */ 4894 if (set_backlight_level) { 4895 for (i = 0; i < dm->num_of_edps; i++) { 4896 if (dm->backlight_dev[i]) 4897 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 4898 } 4899 } 4900 } 4901 4902 static void dm_set_writeback(struct amdgpu_display_manager *dm, 4903 struct dm_crtc_state *crtc_state, 4904 struct drm_connector *connector, 4905 struct drm_connector_state *new_con_state) 4906 { 4907 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 4908 struct amdgpu_device *adev = dm->adev; 4909 struct amdgpu_crtc *acrtc; 4910 struct dc_writeback_info *wb_info; 4911 struct pipe_ctx *pipe = NULL; 4912 struct amdgpu_framebuffer *afb; 4913 int i = 0; 4914 4915 wb_info = kzalloc_obj(*wb_info); 4916 if (!wb_info) { 4917 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 4918 return; 4919 } 4920 4921 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 4922 if (!acrtc) { 4923 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 4924 kfree(wb_info); 4925 return; 4926 } 4927 4928 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 4929 if (!afb) { 4930 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 4931 kfree(wb_info); 4932 return; 4933 } 4934 4935 for (i = 0; i < MAX_PIPES; i++) { 4936 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 4937 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 4938 break; 4939 } 4940 } 4941 4942 /* fill in wb_info */ 4943 wb_info->wb_enabled = true; 4944 4945 wb_info->dwb_pipe_inst = 0; 4946 wb_info->dwb_params.dwbscl_black_color = 0; 4947 wb_info->dwb_params.hdr_mult = 0x1F000; 4948 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 4949 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 4950 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 4951 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 4952 4953 /* width & height from crtc */ 4954 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 4955 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 4956 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 4957 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 4958 4959 wb_info->dwb_params.cnv_params.crop_en = false; 4960 wb_info->dwb_params.stereo_params.stereo_enabled = false; 4961 4962 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 4963 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 4964 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 4965 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 4966 4967 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 4968 4969 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 4970 4971 wb_info->dwb_params.scaler_taps.h_taps = 1; 4972 wb_info->dwb_params.scaler_taps.v_taps = 1; 4973 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 4974 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 4975 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 4976 4977 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 4978 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 4979 4980 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 4981 wb_info->mcif_buf_params.luma_address[i] = afb->address; 4982 wb_info->mcif_buf_params.chroma_address[i] = 0; 4983 } 4984 4985 wb_info->mcif_buf_params.p_vmid = 1; 4986 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 4987 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 4988 wb_info->mcif_warmup_params.region_size = 4989 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 4990 } 4991 wb_info->mcif_warmup_params.p_vmid = 1; 4992 wb_info->writeback_source_plane = pipe->plane_state; 4993 4994 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 4995 4996 acrtc->wb_conn = wb_conn; 4997 drm_writeback_queue_job(wb_conn, new_con_state); 4998 4999 /* 5000 * Writeback completion is detected in the CRTC vblank IRQ 5001 * (dm_crtc_high_irq()). Take a vblank reference so the vblank interrupt 5002 * stays enabled while the writeback is pending; otherwise a 5003 * writeback-only commit right after drm_crtc_vblank_on() (e.g. 5004 * re-enabling a CRTC that was disabled) has no other vblank reference, 5005 * the IRQ never fires and the out fence times out. The matching put 5006 * happens once completion is signalled in dm_crtc_high_irq(), or when 5007 * the writeback is torn down in dm_clear_writeback(). 5008 * 5009 * Arm wb_pending only after the reference is held so the completion IRQ 5010 * cannot run its matching vblank_put before this get. 5011 */ 5012 WARN_ON(drm_crtc_vblank_get(&acrtc->base)); 5013 acrtc->wb_pending = true; 5014 } 5015 5016 static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 5017 { 5018 struct drm_connector_state *old_con_state, *new_con_state; 5019 struct drm_device *dev = state->dev; 5020 struct drm_connector *connector; 5021 struct amdgpu_device *adev = drm_to_adev(dev); 5022 int i; 5023 5024 if (!adev->dm.hdcp_workqueue) 5025 return; 5026 5027 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5028 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5029 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5030 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5031 struct dm_crtc_state *dm_new_crtc_state; 5032 struct amdgpu_dm_connector *aconnector; 5033 5034 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5035 continue; 5036 5037 aconnector = to_amdgpu_dm_connector(connector); 5038 5039 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 5040 5041 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 5042 connector->index, connector->status, connector->dpms); 5043 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 5044 old_con_state->content_protection, new_con_state->content_protection); 5045 5046 if (aconnector->dc_sink) { 5047 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 5048 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 5049 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 5050 aconnector->dc_sink->edid_caps.display_name); 5051 } 5052 } 5053 5054 new_crtc_state = NULL; 5055 old_crtc_state = NULL; 5056 5057 if (acrtc) { 5058 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5059 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5060 } 5061 5062 if (old_crtc_state) 5063 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 5064 old_crtc_state->enable, 5065 old_crtc_state->active, 5066 old_crtc_state->mode_changed, 5067 old_crtc_state->active_changed, 5068 old_crtc_state->connectors_changed); 5069 5070 if (new_crtc_state) 5071 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 5072 new_crtc_state->enable, 5073 new_crtc_state->active, 5074 new_crtc_state->mode_changed, 5075 new_crtc_state->active_changed, 5076 new_crtc_state->connectors_changed); 5077 5078 5079 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5080 5081 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 5082 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 5083 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 5084 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5085 dm_new_con_state->update_hdcp = true; 5086 continue; 5087 } 5088 5089 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 5090 old_con_state, connector, adev->dm.hdcp_workqueue)) { 5091 /* when display is unplugged from mst hub, connctor will 5092 * be destroyed within dm_dp_mst_connector_destroy. connector 5093 * hdcp perperties, like type, undesired, desired, enabled, 5094 * will be lost. So, save hdcp properties into hdcp_work within 5095 * amdgpu_dm_atomic_commit_tail. if the same display is 5096 * plugged back with same display index, its hdcp properties 5097 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 5098 */ 5099 5100 bool enable_encryption = false; 5101 5102 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 5103 enable_encryption = true; 5104 5105 if (aconnector->dc_link && aconnector->dc_sink && 5106 aconnector->dc_link->type == dc_connection_mst_branch) { 5107 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 5108 struct hdcp_workqueue *hdcp_w = 5109 &hdcp_work[aconnector->dc_link->link_index]; 5110 5111 hdcp_w->hdcp_content_type[connector->index] = 5112 new_con_state->hdcp_content_type; 5113 hdcp_w->content_protection[connector->index] = 5114 new_con_state->content_protection; 5115 } 5116 5117 if (new_crtc_state && new_crtc_state->mode_changed && 5118 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 5119 enable_encryption = true; 5120 5121 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 5122 5123 if (aconnector->dc_link) 5124 hdcp_update_display( 5125 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 5126 new_con_state->hdcp_content_type, enable_encryption); 5127 } 5128 } 5129 } 5130 5131 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 5132 { 5133 struct drm_crtc *crtc; 5134 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5135 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5136 int i, ret; 5137 5138 ret = drm_dp_mst_atomic_setup_commit(state); 5139 if (ret) 5140 return ret; 5141 5142 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5143 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5144 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5145 /* 5146 * Color management settings. We also update color properties 5147 * when a modeset is needed, to ensure it gets reprogrammed. 5148 */ 5149 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 5150 (dm_new_crtc_state->base.color_mgmt_changed || 5151 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5152 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5153 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 5154 if (ret) { 5155 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 5156 return ret; 5157 } 5158 } 5159 } 5160 5161 return 0; 5162 } 5163 5164 STATIC_IFN_KUNIT void set_multisync_trigger_params( 5165 struct dc_stream_state *stream) 5166 { 5167 struct dc_stream_state *master = NULL; 5168 5169 if (stream->triggered_crtc_reset.enabled) { 5170 master = stream->triggered_crtc_reset.event_source; 5171 stream->triggered_crtc_reset.event = 5172 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5173 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5174 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5175 } 5176 } 5177 EXPORT_IF_KUNIT(set_multisync_trigger_params); 5178 5179 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 5180 int stream_count) 5181 { 5182 int j, highest_rfr = 0, master_stream = 0; 5183 5184 for (j = 0; j < stream_count; j++) { 5185 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5186 int refresh_rate = 0; 5187 5188 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5189 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5190 if (refresh_rate > highest_rfr) { 5191 highest_rfr = refresh_rate; 5192 master_stream = j; 5193 } 5194 } 5195 } 5196 for (j = 0; j < stream_count; j++) { 5197 if (stream_set[j]) 5198 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5199 } 5200 } 5201 EXPORT_IF_KUNIT(set_master_stream); 5202 5203 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5204 { 5205 int i = 0; 5206 struct dc_stream_state *stream; 5207 5208 if (context->stream_count < 2) 5209 return; 5210 for (i = 0; i < context->stream_count ; i++) { 5211 if (!context->streams[i]) 5212 continue; 5213 /* 5214 * TODO: add a function to read AMD VSDB bits and set 5215 * crtc_sync_master.multi_sync_enabled flag 5216 * For now it's set to false 5217 */ 5218 } 5219 5220 set_master_stream(context->streams, context->stream_count); 5221 5222 for (i = 0; i < context->stream_count ; i++) { 5223 stream = context->streams[i]; 5224 5225 if (!stream) 5226 continue; 5227 5228 set_multisync_trigger_params(stream); 5229 } 5230 } 5231 5232 /** 5233 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5234 * @state: The atomic state to commit 5235 * 5236 * This will tell DC to commit the constructed DC state from atomic_check, 5237 * programming the hardware. Any failures here implies a hardware failure, since 5238 * atomic check should have filtered anything non-kosher. 5239 */ 5240 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 5241 { 5242 struct drm_device *dev = state->dev; 5243 struct amdgpu_device *adev = drm_to_adev(dev); 5244 struct amdgpu_display_manager *dm = &adev->dm; 5245 struct dm_atomic_state *dm_state; 5246 struct dc_state *dc_state = NULL; 5247 u32 i, j; 5248 struct drm_crtc *crtc; 5249 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5250 unsigned long flags; 5251 bool wait_for_vblank = true; 5252 struct drm_connector *connector; 5253 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5254 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5255 int crtc_disable_count = 0; 5256 5257 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5258 5259 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5260 drm_dp_mst_atomic_wait_for_dependencies(state); 5261 5262 dm_state = dm_atomic_get_new_state(state); 5263 if (dm_state && dm_state->context) { 5264 dc_state = dm_state->context; 5265 amdgpu_dm_commit_streams(state, dc_state); 5266 } 5267 5268 amdgpu_dm_update_hdcp(state); 5269 5270 /* Handle connector state changes */ 5271 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5272 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5273 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5274 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5275 struct dc_surface_update *dummy_updates; 5276 struct dc_stream_update stream_update; 5277 struct dc_info_packet hdr_packet; 5278 struct dc_stream_status *status = NULL; 5279 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5280 5281 memset(&stream_update, 0, sizeof(stream_update)); 5282 5283 if (acrtc) { 5284 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5285 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5286 } 5287 5288 /* Skip any modesets/resets */ 5289 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5290 continue; 5291 5292 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5293 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5294 5295 scaling_changed = is_scaling_state_different(dm_new_con_state, 5296 dm_old_con_state); 5297 5298 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5299 (dm_old_crtc_state->stream->output_color_space != 5300 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5301 output_color_space_changed = true; 5302 5303 abm_changed = dm_new_crtc_state->abm_level != 5304 dm_old_crtc_state->abm_level; 5305 5306 hdr_changed = 5307 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5308 5309 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5310 continue; 5311 5312 stream_update.stream = dm_new_crtc_state->stream; 5313 if (scaling_changed) { 5314 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5315 dm_new_con_state, dm_new_crtc_state->stream); 5316 5317 stream_update.src = dm_new_crtc_state->stream->src; 5318 stream_update.dst = dm_new_crtc_state->stream->dst; 5319 } 5320 5321 if (output_color_space_changed) { 5322 dm_new_crtc_state->stream->output_color_space 5323 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5324 5325 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5326 } 5327 5328 if (abm_changed) { 5329 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5330 5331 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5332 } 5333 5334 if (hdr_changed) { 5335 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5336 stream_update.hdr_static_metadata = &hdr_packet; 5337 } 5338 5339 status = dc_stream_get_status(dm_new_crtc_state->stream); 5340 5341 if (WARN_ON(!status)) 5342 continue; 5343 5344 WARN_ON(!status->plane_count); 5345 5346 /* 5347 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5348 * Here we create an empty update on each plane. 5349 * To fix this, DC should permit updating only stream properties. 5350 */ 5351 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5352 if (!dummy_updates) { 5353 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5354 continue; 5355 } 5356 for (j = 0; j < status->plane_count; j++) 5357 dummy_updates[j].surface = status->plane_states[j]; 5358 5359 sort(dummy_updates, status->plane_count, 5360 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5361 5362 mutex_lock(&dm->dc_lock); 5363 dc_exit_ips_for_hw_access(dm->dc); 5364 dc_update_planes_and_stream(dm->dc, 5365 dummy_updates, 5366 status->plane_count, 5367 dm_new_crtc_state->stream, 5368 &stream_update); 5369 mutex_unlock(&dm->dc_lock); 5370 kfree(dummy_updates); 5371 5372 drm_connector_update_privacy_screen(new_con_state); 5373 } 5374 5375 /** 5376 * Enable interrupts for CRTCs that are newly enabled or went through 5377 * a modeset. It was intentionally deferred until after the front end 5378 * state was modified to wait until the OTG was on and so the IRQ 5379 * handlers didn't access stale or invalid state. 5380 */ 5381 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5382 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5383 #ifdef CONFIG_DEBUG_FS 5384 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5385 #endif 5386 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5387 if (old_crtc_state->active && !new_crtc_state->active) 5388 crtc_disable_count++; 5389 5390 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5391 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5392 5393 /* For freesync config update on crtc state and params for irq */ 5394 update_stream_irq_parameters(dm, dm_new_crtc_state); 5395 5396 #ifdef CONFIG_DEBUG_FS 5397 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5398 cur_crc_src = acrtc->dm_irq_params.crc_src; 5399 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5400 #endif 5401 5402 if (new_crtc_state->active && 5403 (!old_crtc_state->active || 5404 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5405 dc_stream_retain(dm_new_crtc_state->stream); 5406 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5407 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5408 } 5409 /* Handle vrr on->off / off->on transitions */ 5410 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5411 5412 #ifdef CONFIG_DEBUG_FS 5413 if (new_crtc_state->active && 5414 (!old_crtc_state->active || 5415 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5416 /** 5417 * Frontend may have changed so reapply the CRC capture 5418 * settings for the stream. 5419 */ 5420 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5421 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5422 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5423 uint8_t cnt; 5424 5425 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5426 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5427 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5428 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5429 5430 /** 5431 * It takes 2 frames for HW to stably generate CRC when 5432 * resuming from suspend, so we set skip_frame_cnt 2. 5433 */ 5434 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5435 } 5436 } 5437 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5438 } 5439 #endif 5440 if (amdgpu_dm_crtc_configure_crc_source( 5441 crtc, dm_new_crtc_state, cur_crc_src)) 5442 drm_dbg_atomic(dev, "Failed to configure crc source"); 5443 } 5444 } 5445 #endif 5446 } 5447 5448 amdgpu_dm_mod_power_setup_streams(state, dm); 5449 5450 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5451 if (new_crtc_state->async_flip) 5452 wait_for_vblank = false; 5453 5454 /* update planes when needed per crtc*/ 5455 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5456 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5457 5458 if (dm_new_crtc_state->stream) 5459 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5460 } 5461 5462 /* Enable writeback */ 5463 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5464 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5465 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5466 5467 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5468 continue; 5469 5470 if (!new_con_state->writeback_job) 5471 continue; 5472 5473 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5474 5475 if (!new_crtc_state) 5476 continue; 5477 5478 if (acrtc->wb_enabled) 5479 continue; 5480 5481 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5482 5483 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5484 acrtc->wb_enabled = true; 5485 } 5486 5487 /* Update audio instances for each connector. */ 5488 amdgpu_dm_commit_audio(dev, state); 5489 5490 /* restore the backlight level */ 5491 for (i = 0; i < dm->num_of_edps; i++) { 5492 if (dm->backlight_dev[i] && 5493 (dm->actual_brightness[i] != dm->brightness[i])) 5494 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5495 } 5496 5497 /* 5498 * send vblank event on all events not handled in flip and 5499 * mark consumed event for drm_atomic_helper_commit_hw_done 5500 */ 5501 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5502 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5503 5504 if (new_crtc_state->event) 5505 drm_send_event_locked(dev, &new_crtc_state->event->base); 5506 5507 new_crtc_state->event = NULL; 5508 } 5509 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5510 5511 /* Signal HW programming completion */ 5512 drm_atomic_helper_commit_hw_done(state); 5513 5514 if (wait_for_vblank) 5515 drm_atomic_helper_wait_for_flip_done(dev, state); 5516 5517 drm_atomic_helper_cleanup_planes(dev, state); 5518 5519 /* Don't free the memory if we are hitting this as part of suspend. 5520 * This way we don't free any memory during suspend; see 5521 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5522 * non-suspend modeset or when the driver is torn down. 5523 */ 5524 if (!adev->in_suspend) { 5525 /* return the stolen vga memory back to VRAM */ 5526 if (!adev->mman.keep_stolen_vga_memory) 5527 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5528 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5529 } 5530 5531 /* 5532 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5533 * so we can put the GPU into runtime suspend if we're not driving any 5534 * displays anymore 5535 */ 5536 for (i = 0; i < crtc_disable_count; i++) 5537 pm_runtime_put_autosuspend(dev->dev); 5538 pm_runtime_mark_last_busy(dev->dev); 5539 5540 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5541 } 5542 5543 /* 5544 * Grabs all modesetting locks to serialize against any blocking commits, 5545 * Waits for completion of all non blocking commits. 5546 */ 5547 static int do_aquire_global_lock(struct drm_device *dev, 5548 struct drm_atomic_commit *state) 5549 { 5550 struct drm_crtc *crtc; 5551 struct drm_crtc_commit *commit; 5552 long ret; 5553 5554 /* 5555 * Adding all modeset locks to aquire_ctx will 5556 * ensure that when the framework release it the 5557 * extra locks we are locking here will get released to 5558 */ 5559 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5560 if (ret) 5561 return ret; 5562 5563 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5564 spin_lock(&crtc->commit_lock); 5565 commit = list_first_entry_or_null(&crtc->commit_list, 5566 struct drm_crtc_commit, commit_entry); 5567 if (commit) 5568 drm_crtc_commit_get(commit); 5569 spin_unlock(&crtc->commit_lock); 5570 5571 if (!commit) 5572 continue; 5573 5574 /* 5575 * Make sure all pending HW programming completed and 5576 * page flips done 5577 */ 5578 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5579 5580 if (ret > 0) 5581 ret = wait_for_completion_interruptible_timeout( 5582 &commit->flip_done, 10*HZ); 5583 5584 if (ret == 0) 5585 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5586 crtc->base.id, crtc->name); 5587 5588 drm_crtc_commit_put(commit); 5589 } 5590 5591 return ret < 0 ? ret : 0; 5592 } 5593 5594 static void get_freesync_config_for_crtc( 5595 struct dm_crtc_state *new_crtc_state, 5596 struct dm_connector_state *new_con_state) 5597 { 5598 struct mod_freesync_config config = {0}; 5599 struct amdgpu_dm_connector *aconnector; 5600 struct drm_display_mode *mode = &new_crtc_state->base.mode; 5601 int vrefresh = drm_mode_vrefresh(mode); 5602 bool fs_vid_mode = false; 5603 5604 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5605 return; 5606 5607 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 5608 5609 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 5610 vrefresh >= aconnector->min_vfreq && 5611 vrefresh <= aconnector->max_vfreq; 5612 5613 if (new_crtc_state->vrr_supported) { 5614 new_crtc_state->stream->ignore_msa_timing_param = true; 5615 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 5616 5617 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 5618 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 5619 config.vsif_supported = true; 5620 config.btr = true; 5621 5622 if (fs_vid_mode) { 5623 config.state = VRR_STATE_ACTIVE_FIXED; 5624 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 5625 goto out; 5626 } else if (new_crtc_state->base.vrr_enabled) { 5627 config.state = VRR_STATE_ACTIVE_VARIABLE; 5628 } else { 5629 config.state = VRR_STATE_INACTIVE; 5630 } 5631 } else { 5632 config.state = VRR_STATE_UNSUPPORTED; 5633 } 5634 out: 5635 new_crtc_state->freesync_config = config; 5636 } 5637 5638 static void reset_freesync_config_for_crtc( 5639 struct dm_crtc_state *new_crtc_state) 5640 { 5641 new_crtc_state->vrr_supported = false; 5642 5643 memset(&new_crtc_state->vrr_infopacket, 0, 5644 sizeof(new_crtc_state->vrr_infopacket)); 5645 } 5646 5647 STATIC_IFN_KUNIT bool 5648 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 5649 struct drm_crtc_state *new_crtc_state) 5650 { 5651 const struct drm_display_mode *old_mode, *new_mode; 5652 5653 if (!old_crtc_state || !new_crtc_state) 5654 return false; 5655 5656 old_mode = &old_crtc_state->mode; 5657 new_mode = &new_crtc_state->mode; 5658 5659 if (old_mode->clock == new_mode->clock && 5660 old_mode->hdisplay == new_mode->hdisplay && 5661 old_mode->vdisplay == new_mode->vdisplay && 5662 old_mode->htotal == new_mode->htotal && 5663 old_mode->vtotal != new_mode->vtotal && 5664 old_mode->hsync_start == new_mode->hsync_start && 5665 old_mode->vsync_start != new_mode->vsync_start && 5666 old_mode->hsync_end == new_mode->hsync_end && 5667 old_mode->vsync_end != new_mode->vsync_end && 5668 old_mode->hskew == new_mode->hskew && 5669 old_mode->vscan == new_mode->vscan && 5670 (old_mode->vsync_end - old_mode->vsync_start) == 5671 (new_mode->vsync_end - new_mode->vsync_start)) 5672 return true; 5673 5674 return false; 5675 } 5676 EXPORT_IF_KUNIT(is_timing_unchanged_for_freesync); 5677 5678 STATIC_IFN_KUNIT void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 5679 { 5680 u64 num, den, res; 5681 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 5682 5683 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 5684 5685 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 5686 den = (unsigned long long)new_crtc_state->mode.htotal * 5687 (unsigned long long)new_crtc_state->mode.vtotal; 5688 5689 res = div_u64(num, den); 5690 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 5691 } 5692 EXPORT_IF_KUNIT(set_freesync_fixed_config); 5693 5694 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5695 struct drm_atomic_commit *state, 5696 struct drm_crtc *crtc, 5697 struct drm_crtc_state *old_crtc_state, 5698 struct drm_crtc_state *new_crtc_state, 5699 bool enable, 5700 bool *lock_and_validation_needed) 5701 { 5702 struct dm_atomic_state *dm_state = NULL; 5703 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5704 struct dc_stream_state *new_stream; 5705 struct amdgpu_device *adev = dm->adev; 5706 int ret = 0; 5707 5708 /* 5709 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5710 * update changed items 5711 */ 5712 struct amdgpu_crtc *acrtc = NULL; 5713 struct drm_connector *connector = NULL; 5714 struct amdgpu_dm_connector *aconnector = NULL; 5715 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5716 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5717 5718 new_stream = NULL; 5719 5720 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5721 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5722 acrtc = to_amdgpu_crtc(crtc); 5723 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5724 if (connector) 5725 aconnector = to_amdgpu_dm_connector(connector); 5726 5727 /* TODO This hack should go away */ 5728 if (connector && enable) { 5729 /* Make sure fake sink is created in plug-in scenario */ 5730 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5731 connector); 5732 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5733 connector); 5734 5735 if (WARN_ON(!drm_new_conn_state)) { 5736 ret = -EINVAL; 5737 goto fail; 5738 } 5739 5740 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5741 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5742 5743 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5744 goto skip_modeset; 5745 5746 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5747 &new_crtc_state->mode, 5748 dm_new_conn_state, 5749 dm_old_crtc_state->stream); 5750 5751 /* 5752 * we can have no stream on ACTION_SET if a display 5753 * was disconnected during S3, in this case it is not an 5754 * error, the OS will be updated after detection, and 5755 * will do the right thing on next atomic commit 5756 */ 5757 5758 if (!new_stream) { 5759 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5760 __func__, acrtc->base.base.id); 5761 ret = -ENOMEM; 5762 goto fail; 5763 } 5764 5765 /* 5766 * TODO: Check VSDB bits to decide whether this should 5767 * be enabled or not. 5768 */ 5769 new_stream->triggered_crtc_reset.enabled = 5770 dm->force_timing_sync; 5771 5772 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5773 5774 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5775 &new_stream->hdr_static_metadata); 5776 if (ret) 5777 goto fail; 5778 5779 /* 5780 * If we already removed the old stream from the context 5781 * (and set the new stream to NULL) then we can't reuse 5782 * the old stream even if the stream and scaling are unchanged. 5783 * We'll hit the BUG_ON and black screen. 5784 * 5785 * TODO: Refactor this function to allow this check to work 5786 * in all conditions. 5787 */ 5788 if (amdgpu_freesync_vid_mode && 5789 dm_new_crtc_state->stream && 5790 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5791 goto skip_modeset; 5792 5793 if (dm_new_crtc_state->stream && 5794 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5795 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5796 new_crtc_state->mode_changed = false; 5797 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5798 new_crtc_state->mode_changed); 5799 } 5800 } 5801 5802 /* mode_changed flag may get updated above, need to check again */ 5803 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5804 goto skip_modeset; 5805 5806 drm_dbg_state(state->dev, 5807 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5808 acrtc->crtc_id, 5809 new_crtc_state->enable, 5810 new_crtc_state->active, 5811 new_crtc_state->planes_changed, 5812 new_crtc_state->mode_changed, 5813 new_crtc_state->active_changed, 5814 new_crtc_state->connectors_changed); 5815 5816 /* Remove stream for any changed/disabled CRTC */ 5817 if (!enable) { 5818 5819 if (!dm_old_crtc_state->stream) 5820 goto skip_modeset; 5821 5822 /* Unset freesync video if it was active before */ 5823 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5824 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5825 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5826 } 5827 5828 /* Now check if we should set freesync video mode */ 5829 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5830 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5831 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5832 is_timing_unchanged_for_freesync(new_crtc_state, 5833 old_crtc_state)) { 5834 new_crtc_state->mode_changed = false; 5835 drm_dbg_driver(adev_to_drm(adev), 5836 "Mode change not required for front porch change, setting mode_changed to %d", 5837 new_crtc_state->mode_changed); 5838 5839 set_freesync_fixed_config(dm_new_crtc_state); 5840 5841 goto skip_modeset; 5842 } else if (amdgpu_freesync_vid_mode && aconnector && 5843 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5844 aconnector)) { 5845 struct drm_display_mode *high_mode; 5846 5847 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5848 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 5849 set_freesync_fixed_config(dm_new_crtc_state); 5850 } 5851 5852 ret = dm_atomic_get_state(state, &dm_state); 5853 if (ret) 5854 goto fail; 5855 5856 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 5857 crtc->base.id); 5858 5859 /* i.e. reset mode */ 5860 if (dc_state_remove_stream( 5861 dm->dc, 5862 dm_state->context, 5863 dm_old_crtc_state->stream) != DC_OK) { 5864 ret = -EINVAL; 5865 goto fail; 5866 } 5867 5868 dc_stream_release(dm_old_crtc_state->stream); 5869 dm_new_crtc_state->stream = NULL; 5870 5871 reset_freesync_config_for_crtc(dm_new_crtc_state); 5872 5873 *lock_and_validation_needed = true; 5874 5875 } else {/* Add stream for any updated/enabled CRTC */ 5876 /* 5877 * Quick fix to prevent NULL pointer on new_stream when 5878 * added MST connectors not found in existing crtc_state in the chained mode 5879 * TODO: need to dig out the root cause of that 5880 */ 5881 if (!connector) 5882 goto skip_modeset; 5883 5884 if (modereset_required(new_crtc_state)) 5885 goto skip_modeset; 5886 5887 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 5888 dm_old_crtc_state->stream)) { 5889 5890 WARN_ON(dm_new_crtc_state->stream); 5891 5892 ret = dm_atomic_get_state(state, &dm_state); 5893 if (ret) 5894 goto fail; 5895 5896 dm_new_crtc_state->stream = new_stream; 5897 5898 dc_stream_retain(new_stream); 5899 5900 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 5901 crtc->base.id); 5902 5903 if (dc_state_add_stream( 5904 dm->dc, 5905 dm_state->context, 5906 dm_new_crtc_state->stream) != DC_OK) { 5907 ret = -EINVAL; 5908 goto fail; 5909 } 5910 5911 *lock_and_validation_needed = true; 5912 } 5913 } 5914 5915 skip_modeset: 5916 /* Release extra reference */ 5917 if (new_stream) 5918 dc_stream_release(new_stream); 5919 5920 /* 5921 * We want to do dc stream updates that do not require a 5922 * full modeset below. 5923 */ 5924 if (!(enable && connector && new_crtc_state->active)) 5925 return 0; 5926 /* 5927 * Given above conditions, the dc state cannot be NULL because: 5928 * 1. We're in the process of enabling CRTCs (just been added 5929 * to the dc context, or already is on the context) 5930 * 2. Has a valid connector attached, and 5931 * 3. Is currently active and enabled. 5932 * => The dc stream state currently exists. 5933 */ 5934 BUG_ON(dm_new_crtc_state->stream == NULL); 5935 5936 /* Scaling or underscan settings */ 5937 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 5938 drm_atomic_crtc_needs_modeset(new_crtc_state)) 5939 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 5940 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 5941 5942 /* ABM settings */ 5943 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5944 5945 /* 5946 * Color management settings. We also update color properties 5947 * when a modeset is needed, to ensure it gets reprogrammed. 5948 */ 5949 if (dm_new_crtc_state->base.color_mgmt_changed || 5950 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5951 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 5952 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 5953 if (ret) 5954 goto fail; 5955 } 5956 5957 /* Update Freesync settings. */ 5958 get_freesync_config_for_crtc(dm_new_crtc_state, 5959 dm_new_conn_state); 5960 5961 return ret; 5962 5963 fail: 5964 if (new_stream) 5965 dc_stream_release(new_stream); 5966 return ret; 5967 } 5968 5969 static bool should_reset_plane(struct drm_atomic_commit *state, 5970 struct drm_plane *plane, 5971 struct drm_plane_state *old_plane_state, 5972 struct drm_plane_state *new_plane_state) 5973 { 5974 struct drm_plane *other; 5975 struct drm_plane_state *old_other_state, *new_other_state; 5976 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5977 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 5978 struct amdgpu_device *adev = drm_to_adev(plane->dev); 5979 struct drm_connector_state *new_con_state; 5980 struct drm_connector *connector; 5981 int i; 5982 5983 /* 5984 * TODO: Remove this hack for all asics once it proves that the 5985 * fast updates works fine on DCN3.2+. 5986 */ 5987 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 5988 state->allow_modeset) 5989 return true; 5990 5991 /* Check for writeback commit */ 5992 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5993 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5994 continue; 5995 5996 if (new_con_state->writeback_job) 5997 return true; 5998 } 5999 6000 if (amdgpu_in_reset(adev) && state->allow_modeset) 6001 return true; 6002 6003 /* Exit early if we know that we're adding or removing the plane. */ 6004 if (old_plane_state->crtc != new_plane_state->crtc) 6005 return true; 6006 6007 /* old crtc == new_crtc == NULL, plane not in context. */ 6008 if (!new_plane_state->crtc) 6009 return false; 6010 6011 new_crtc_state = 6012 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 6013 old_crtc_state = 6014 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 6015 6016 if (!new_crtc_state) 6017 return true; 6018 6019 /* 6020 * A change in cursor mode means a new dc pipe needs to be acquired or 6021 * released from the state 6022 */ 6023 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 6024 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6025 if (plane->type == DRM_PLANE_TYPE_CURSOR && 6026 old_dm_crtc_state != NULL && 6027 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 6028 return true; 6029 } 6030 6031 /* CRTC Degamma changes currently require us to recreate planes. */ 6032 if (new_crtc_state->color_mgmt_changed) 6033 return true; 6034 6035 /* 6036 * On zpos change, planes need to be reordered by removing and re-adding 6037 * them one by one to the dc state, in order of descending zpos. 6038 * 6039 * TODO: We can likely skip bandwidth validation if the only thing that 6040 * changed about the plane was it'z z-ordering. 6041 */ 6042 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 6043 return true; 6044 6045 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 6046 return true; 6047 6048 /* 6049 * If there are any new primary or overlay planes being added or 6050 * removed then the z-order can potentially change. To ensure 6051 * correct z-order and pipe acquisition the current DC architecture 6052 * requires us to remove and recreate all existing planes. 6053 * 6054 * TODO: Come up with a more elegant solution for this. 6055 */ 6056 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 6057 struct amdgpu_framebuffer *old_afb, *new_afb; 6058 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 6059 6060 dm_new_other_state = to_dm_plane_state(new_other_state); 6061 dm_old_other_state = to_dm_plane_state(old_other_state); 6062 6063 if (other->type == DRM_PLANE_TYPE_CURSOR) 6064 continue; 6065 6066 if (old_other_state->crtc != new_plane_state->crtc && 6067 new_other_state->crtc != new_plane_state->crtc) 6068 continue; 6069 6070 if (old_other_state->crtc != new_other_state->crtc) 6071 return true; 6072 6073 /* Src/dst size and scaling updates. */ 6074 if (old_other_state->src_w != new_other_state->src_w || 6075 old_other_state->src_h != new_other_state->src_h || 6076 old_other_state->crtc_w != new_other_state->crtc_w || 6077 old_other_state->crtc_h != new_other_state->crtc_h) 6078 return true; 6079 6080 /* Rotation / mirroring updates. */ 6081 if (old_other_state->rotation != new_other_state->rotation) 6082 return true; 6083 6084 /* Blending updates. */ 6085 if (old_other_state->pixel_blend_mode != 6086 new_other_state->pixel_blend_mode) 6087 return true; 6088 6089 /* Alpha updates. */ 6090 if (old_other_state->alpha != new_other_state->alpha) 6091 return true; 6092 6093 /* Colorspace changes. */ 6094 if (old_other_state->color_range != new_other_state->color_range || 6095 old_other_state->color_encoding != new_other_state->color_encoding) 6096 return true; 6097 6098 /* HDR/Transfer Function changes. */ 6099 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 6100 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 6101 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 6102 dm_old_other_state->ctm != dm_new_other_state->ctm || 6103 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 6104 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 6105 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 6106 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 6107 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 6108 return true; 6109 6110 /* Framebuffer checks fall at the end. */ 6111 if (!old_other_state->fb || !new_other_state->fb) 6112 continue; 6113 6114 /* Pixel format changes can require bandwidth updates. */ 6115 if (old_other_state->fb->format != new_other_state->fb->format) 6116 return true; 6117 6118 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 6119 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 6120 6121 /* Tiling and DCC changes also require bandwidth updates. */ 6122 if (old_afb->tiling_flags != new_afb->tiling_flags || 6123 old_afb->base.modifier != new_afb->base.modifier) 6124 return true; 6125 } 6126 6127 return false; 6128 } 6129 6130 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 6131 struct drm_plane_state *new_plane_state, 6132 struct drm_framebuffer *fb) 6133 { 6134 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 6135 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 6136 unsigned int pitch; 6137 bool linear; 6138 6139 if (fb->width > new_acrtc->max_cursor_width || 6140 fb->height > new_acrtc->max_cursor_height) { 6141 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB size %dx%d\n", 6142 new_plane_state->fb->width, 6143 new_plane_state->fb->height); 6144 return -EINVAL; 6145 } 6146 if (new_plane_state->src_w != fb->width << 16 || 6147 new_plane_state->src_h != fb->height << 16) { 6148 drm_dbg_atomic(adev_to_drm(adev), "Cropping not supported for cursor plane\n"); 6149 return -EINVAL; 6150 } 6151 6152 /* Pitch in pixels */ 6153 pitch = fb->pitches[0] / fb->format->cpp[0]; 6154 6155 if (fb->width != pitch) { 6156 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB width %d doesn't match pitch %d", 6157 fb->width, pitch); 6158 return -EINVAL; 6159 } 6160 6161 switch (pitch) { 6162 case 64: 6163 case 128: 6164 case 256: 6165 /* FB pitch is supported by cursor plane */ 6166 break; 6167 default: 6168 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB pitch %d px\n", pitch); 6169 return -EINVAL; 6170 } 6171 6172 /* Core DRM takes care of checking FB modifiers, so we only need to 6173 * check tiling flags when the FB doesn't have a modifier. 6174 */ 6175 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 6176 if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 6177 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 6178 } else if (adev->family >= AMDGPU_FAMILY_AI) { 6179 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 6180 } else { 6181 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 6182 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 6183 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 6184 } 6185 if (!linear) { 6186 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB not linear"); 6187 return -EINVAL; 6188 } 6189 } 6190 6191 return 0; 6192 } 6193 6194 /* 6195 * Helper function for checking the cursor in native mode 6196 */ 6197 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 6198 struct drm_plane *plane, 6199 struct drm_plane_state *new_plane_state, 6200 bool enable) 6201 { 6202 6203 struct amdgpu_crtc *new_acrtc; 6204 int ret; 6205 6206 if (!enable || !new_plane_crtc || 6207 drm_atomic_plane_disabling(plane->state, new_plane_state)) 6208 return 0; 6209 6210 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 6211 6212 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 6213 drm_dbg_atomic(new_plane_crtc->dev, "Cropping not supported for cursor plane\n"); 6214 return -EINVAL; 6215 } 6216 6217 if (new_plane_state->fb) { 6218 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 6219 new_plane_state->fb); 6220 if (ret) 6221 return ret; 6222 } 6223 6224 return 0; 6225 } 6226 6227 static bool dm_should_update_native_cursor(struct drm_atomic_commit *state, 6228 struct drm_crtc *old_plane_crtc, 6229 struct drm_crtc *new_plane_crtc, 6230 bool enable) 6231 { 6232 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6233 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6234 6235 if (!enable) { 6236 if (old_plane_crtc == NULL) 6237 return true; 6238 6239 old_crtc_state = drm_atomic_get_old_crtc_state( 6240 state, old_plane_crtc); 6241 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6242 6243 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6244 } else { 6245 if (new_plane_crtc == NULL) 6246 return true; 6247 6248 new_crtc_state = drm_atomic_get_new_crtc_state( 6249 state, new_plane_crtc); 6250 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6251 6252 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6253 } 6254 } 6255 6256 static int dm_update_plane_state(struct dc *dc, 6257 struct drm_atomic_commit *state, 6258 struct drm_plane *plane, 6259 struct drm_plane_state *old_plane_state, 6260 struct drm_plane_state *new_plane_state, 6261 bool enable, 6262 bool *lock_and_validation_needed, 6263 bool *is_top_most_overlay) 6264 { 6265 6266 struct dm_atomic_state *dm_state = NULL; 6267 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6268 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6269 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6270 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6271 bool needs_reset, update_native_cursor; 6272 int ret = 0; 6273 6274 6275 new_plane_crtc = new_plane_state->crtc; 6276 old_plane_crtc = old_plane_state->crtc; 6277 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6278 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6279 6280 update_native_cursor = dm_should_update_native_cursor(state, 6281 old_plane_crtc, 6282 new_plane_crtc, 6283 enable); 6284 6285 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 6286 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6287 new_plane_state, enable); 6288 if (ret) 6289 return ret; 6290 6291 return 0; 6292 } 6293 6294 needs_reset = should_reset_plane(state, plane, old_plane_state, 6295 new_plane_state); 6296 6297 /* Remove any changed/removed planes */ 6298 if (!enable) { 6299 if (!needs_reset) 6300 return 0; 6301 6302 if (!old_plane_crtc) 6303 return 0; 6304 6305 old_crtc_state = drm_atomic_get_old_crtc_state( 6306 state, old_plane_crtc); 6307 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6308 6309 if (!dm_old_crtc_state->stream) 6310 return 0; 6311 6312 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 6313 plane->base.id, old_plane_crtc->base.id); 6314 6315 ret = dm_atomic_get_state(state, &dm_state); 6316 if (ret) 6317 return ret; 6318 6319 if (!dc_state_remove_plane( 6320 dc, 6321 dm_old_crtc_state->stream, 6322 dm_old_plane_state->dc_state, 6323 dm_state->context)) { 6324 6325 return -EINVAL; 6326 } 6327 6328 if (dm_old_plane_state->dc_state) 6329 dc_plane_state_release(dm_old_plane_state->dc_state); 6330 6331 dm_new_plane_state->dc_state = NULL; 6332 6333 *lock_and_validation_needed = true; 6334 6335 } else { /* Add new planes */ 6336 struct dc_plane_state *dc_new_plane_state; 6337 6338 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6339 return 0; 6340 6341 if (!new_plane_crtc) 6342 return 0; 6343 6344 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6345 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6346 6347 if (!dm_new_crtc_state->stream) 6348 return 0; 6349 6350 if (!needs_reset) 6351 return 0; 6352 6353 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 6354 if (ret) 6355 goto out; 6356 6357 WARN_ON(dm_new_plane_state->dc_state); 6358 6359 dc_new_plane_state = dc_create_plane_state(dc); 6360 if (!dc_new_plane_state) { 6361 ret = -ENOMEM; 6362 goto out; 6363 } 6364 6365 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 6366 plane->base.id, new_plane_crtc->base.id); 6367 6368 ret = fill_dc_plane_attributes( 6369 drm_to_adev(new_plane_crtc->dev), 6370 dc_new_plane_state, 6371 new_plane_state, 6372 new_crtc_state); 6373 if (ret) { 6374 dc_plane_state_release(dc_new_plane_state); 6375 goto out; 6376 } 6377 6378 ret = dm_atomic_get_state(state, &dm_state); 6379 if (ret) { 6380 dc_plane_state_release(dc_new_plane_state); 6381 goto out; 6382 } 6383 6384 /* 6385 * Any atomic check errors that occur after this will 6386 * not need a release. The plane state will be attached 6387 * to the stream, and therefore part of the atomic 6388 * state. It'll be released when the atomic state is 6389 * cleaned. 6390 */ 6391 if (!dc_state_add_plane( 6392 dc, 6393 dm_new_crtc_state->stream, 6394 dc_new_plane_state, 6395 dm_state->context)) { 6396 6397 dc_plane_state_release(dc_new_plane_state); 6398 ret = -EINVAL; 6399 goto out; 6400 } 6401 6402 dm_new_plane_state->dc_state = dc_new_plane_state; 6403 6404 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 6405 6406 /* Tell DC to do a full surface update every time there 6407 * is a plane change. Inefficient, but works for now. 6408 */ 6409 dm_new_plane_state->dc_state->update_bits.full_update = 1; 6410 6411 *lock_and_validation_needed = true; 6412 } 6413 6414 out: 6415 /* If enabling cursor overlay failed, attempt fallback to native mode */ 6416 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 6417 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6418 new_plane_state, enable); 6419 if (ret) 6420 return ret; 6421 6422 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 6423 } 6424 6425 return ret; 6426 } 6427 6428 STATIC_IFN_KUNIT void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 6429 int *src_w, int *src_h) 6430 { 6431 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 6432 case DRM_MODE_ROTATE_90: 6433 case DRM_MODE_ROTATE_270: 6434 *src_w = plane_state->src_h >> 16; 6435 *src_h = plane_state->src_w >> 16; 6436 break; 6437 case DRM_MODE_ROTATE_0: 6438 case DRM_MODE_ROTATE_180: 6439 default: 6440 *src_w = plane_state->src_w >> 16; 6441 *src_h = plane_state->src_h >> 16; 6442 break; 6443 } 6444 } 6445 EXPORT_IF_KUNIT(dm_get_oriented_plane_size); 6446 6447 STATIC_IFN_KUNIT void 6448 dm_get_plane_scale(struct drm_plane_state *plane_state, 6449 int *out_plane_scale_w, int *out_plane_scale_h) 6450 { 6451 int plane_src_w, plane_src_h; 6452 6453 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 6454 *out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0; 6455 *out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0; 6456 } 6457 EXPORT_IF_KUNIT(dm_get_plane_scale); 6458 6459 /* 6460 * The normalized_zpos value cannot be used by this iterator directly. It's only 6461 * calculated for enabled planes, potentially causing normalized_zpos collisions 6462 * between enabled/disabled planes in the atomic state. We need a unique value 6463 * so that the iterator will not generate the same object twice, or loop 6464 * indefinitely. 6465 */ 6466 static inline struct __drm_planes_state *__get_next_zpos( 6467 struct drm_atomic_commit *state, 6468 struct __drm_planes_state *prev) 6469 { 6470 unsigned int highest_zpos = 0, prev_zpos = 256; 6471 uint32_t highest_id = 0, prev_id = UINT_MAX; 6472 struct drm_plane_state *new_plane_state; 6473 struct drm_plane *plane; 6474 int i, highest_i = -1; 6475 6476 if (prev != NULL) { 6477 prev_zpos = prev->new_state->zpos; 6478 prev_id = prev->ptr->base.id; 6479 } 6480 6481 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 6482 /* Skip planes with higher zpos than the previously returned */ 6483 if (new_plane_state->zpos > prev_zpos || 6484 (new_plane_state->zpos == prev_zpos && 6485 plane->base.id >= prev_id)) 6486 continue; 6487 6488 /* Save the index of the plane with highest zpos */ 6489 if (new_plane_state->zpos > highest_zpos || 6490 (new_plane_state->zpos == highest_zpos && 6491 plane->base.id > highest_id)) { 6492 highest_zpos = new_plane_state->zpos; 6493 highest_id = plane->base.id; 6494 highest_i = i; 6495 } 6496 } 6497 6498 if (highest_i < 0) 6499 return NULL; 6500 6501 return &state->planes[highest_i]; 6502 } 6503 6504 /* 6505 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 6506 * by descending zpos, as read from the new plane state. This is the same 6507 * ordering as defined by drm_atomic_normalize_zpos(). 6508 */ 6509 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 6510 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 6511 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 6512 for_each_if(((plane) = __i->ptr, \ 6513 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 6514 (old_plane_state) = __i->old_state, \ 6515 (new_plane_state) = __i->new_state, 1)) 6516 6517 static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) 6518 { 6519 struct drm_connector *connector; 6520 struct drm_connector_state *conn_state, *old_conn_state; 6521 struct amdgpu_dm_connector *aconnector = NULL; 6522 int i; 6523 6524 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6525 if (!conn_state->crtc) 6526 conn_state = old_conn_state; 6527 6528 if (conn_state->crtc != crtc) 6529 continue; 6530 6531 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6532 continue; 6533 6534 aconnector = to_amdgpu_dm_connector(connector); 6535 if (!aconnector->mst_output_port || !aconnector->mst_root) 6536 aconnector = NULL; 6537 else 6538 break; 6539 } 6540 6541 if (!aconnector) 6542 return 0; 6543 6544 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6545 } 6546 6547 /** 6548 * DOC: Cursor Modes - Native vs Overlay 6549 * 6550 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 6551 * plane. It does not require a dedicated hw plane to enable, but it is 6552 * subjected to the same z-order and scaling as the hw plane. It also has format 6553 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 6554 * hw plane. 6555 * 6556 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 6557 * own scaling and z-pos. It also has no blending restrictions. It lends to a 6558 * cursor behavior more akin to a DRM client's expectations. However, it does 6559 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 6560 * available. 6561 */ 6562 6563 /** 6564 * dm_plane_color_pipeline_active() - Check if a plane's color pipeline active. 6565 * @state: DRM atomic state 6566 * @plane: DRM plane to check 6567 * @use_old: if true, inspect the old colorop states; otherwise the new ones 6568 * 6569 * A color pipeline may be selected (color_pipeline != NULL) but still is 6570 * inactive if every colorop in the chain is bypassed. Only return 6571 * true when at least one colorop has bypass == false, meaning the cursor 6572 * would be subjected to the transformation in native mode. 6573 * 6574 * Return: true if the pipeline modifies pixels, false otherwise. 6575 */ 6576 static bool dm_plane_color_pipeline_active(struct drm_atomic_commit *state, 6577 struct drm_plane *plane, 6578 bool use_old) 6579 { 6580 struct drm_colorop *colorop; 6581 struct drm_colorop_state *old_colorop_state, *new_colorop_state; 6582 int i; 6583 6584 for_each_oldnew_colorop_in_state(state, colorop, old_colorop_state, new_colorop_state, i) { 6585 struct drm_colorop_state *cstate = use_old ? old_colorop_state : new_colorop_state; 6586 6587 if (cstate->colorop->plane != plane) 6588 continue; 6589 if (!cstate->bypass) 6590 return true; 6591 } 6592 return false; 6593 } 6594 6595 /** 6596 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 6597 * @adev: amdgpu device 6598 * @state: DRM atomic state 6599 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 6600 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 6601 * 6602 * Get whether the cursor should be enabled in native mode, or overlay mode, on 6603 * the dm_crtc_state. 6604 * 6605 * The cursor should be enabled in overlay mode if there exists an underlying 6606 * plane - on which the cursor may be blended - that is either YUV formatted, 6607 * scaled differently from the cursor, or has a color pipeline active. 6608 * 6609 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 6610 * calling this function. 6611 * 6612 * Return: 0 on success, or an error code if getting the cursor plane state 6613 * failed. 6614 */ 6615 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 6616 struct drm_atomic_commit *state, 6617 struct dm_crtc_state *dm_crtc_state, 6618 enum amdgpu_dm_cursor_mode *cursor_mode) 6619 { 6620 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 6621 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 6622 struct drm_plane *plane; 6623 bool consider_mode_change = false; 6624 bool entire_crtc_covered = false; 6625 bool cursor_changed = false; 6626 int underlying_scale_w, underlying_scale_h; 6627 int cursor_scale_w, cursor_scale_h; 6628 int i; 6629 6630 /* Overlay cursor not supported on HW before DCN 6631 * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 6632 * as previous DCN generations, so enable native mode on DCN401/420 6633 */ 6634 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || 6635 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 6636 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1)) { 6637 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6638 return 0; 6639 } 6640 6641 /* Init cursor_mode to be the same as current */ 6642 *cursor_mode = dm_crtc_state->cursor_mode; 6643 6644 /* 6645 * Cursor mode can change if a plane's format changes, scale changes, is 6646 * enabled/disabled, z-order changes, or color management properties change. 6647 */ 6648 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 6649 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 6650 6651 /* Only care about planes on this CRTC */ 6652 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 6653 continue; 6654 6655 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6656 cursor_changed = true; 6657 6658 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 6659 drm_atomic_plane_disabling(old_plane_state, plane_state) || 6660 old_plane_state->fb->format != plane_state->fb->format) { 6661 consider_mode_change = true; 6662 break; 6663 } 6664 6665 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 6666 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 6667 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 6668 consider_mode_change = true; 6669 break; 6670 } 6671 6672 /* 6673 * A plane moving or resizing (without a scale change) changes how 6674 * much of the CRTC it covers. This can create/remove holes under 6675 * the cursor and thus flip the required cursor mode (native vs 6676 * overlay), so the destination rect must be re-evaluated too. 6677 */ 6678 if (old_plane_state->crtc_x != plane_state->crtc_x || 6679 old_plane_state->crtc_y != plane_state->crtc_y || 6680 old_plane_state->crtc_w != plane_state->crtc_w || 6681 old_plane_state->crtc_h != plane_state->crtc_h) { 6682 consider_mode_change = true; 6683 break; 6684 } 6685 6686 if (dm_plane_color_pipeline_active(state, plane, true) != 6687 dm_plane_color_pipeline_active(state, plane, false)) { 6688 consider_mode_change = true; 6689 break; 6690 } 6691 } 6692 6693 if (!consider_mode_change && !crtc_state->zpos_changed) 6694 return 0; 6695 6696 /* 6697 * If no cursor change on this CRTC, and not enabled on this CRTC, then 6698 * no need to set cursor mode. This avoids needlessly locking the cursor 6699 * state. 6700 */ 6701 if (!cursor_changed && 6702 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 6703 return 0; 6704 } 6705 6706 cursor_state = drm_atomic_get_plane_state(state, 6707 crtc_state->crtc->cursor); 6708 if (IS_ERR(cursor_state)) 6709 return PTR_ERR(cursor_state); 6710 6711 /* Cursor is disabled */ 6712 if (!cursor_state->fb) 6713 return 0; 6714 6715 /* For all planes in descending z-order (all of which are below cursor 6716 * as per zpos definitions), check their scaling and format 6717 */ 6718 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 6719 6720 /* Only care about non-cursor planes on this CRTC */ 6721 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 6722 plane->type == DRM_PLANE_TYPE_CURSOR) 6723 continue; 6724 6725 /* Underlying plane is YUV format - use overlay cursor */ 6726 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 6727 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6728 return 0; 6729 } 6730 6731 /* Underlying plane has an active color pipeline - cursor would be transformed */ 6732 if (dm_plane_color_pipeline_active(state, plane, false)) { 6733 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6734 return 0; 6735 } 6736 6737 dm_get_plane_scale(plane_state, 6738 &underlying_scale_w, &underlying_scale_h); 6739 dm_get_plane_scale(cursor_state, 6740 &cursor_scale_w, &cursor_scale_h); 6741 6742 /* Underlying plane has different scale - use overlay cursor */ 6743 if (cursor_scale_w != underlying_scale_w && 6744 cursor_scale_h != underlying_scale_h) { 6745 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6746 return 0; 6747 } 6748 6749 /* If this plane covers the whole CRTC, no need to check planes underneath */ 6750 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 6751 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 6752 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 6753 entire_crtc_covered = true; 6754 break; 6755 } 6756 } 6757 6758 /* If planes do not cover the entire CRTC, use overlay mode to enable 6759 * cursor over holes 6760 */ 6761 if (entire_crtc_covered) 6762 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6763 else 6764 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6765 6766 return 0; 6767 } 6768 6769 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6770 struct drm_atomic_commit *state, 6771 struct drm_crtc_state *crtc_state) 6772 { 6773 struct drm_plane *plane; 6774 struct drm_plane_state *new_plane_state, *old_plane_state; 6775 6776 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6777 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6778 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6779 6780 if (!old_plane_state || !new_plane_state) 6781 continue; 6782 6783 if (old_plane_state->fb && new_plane_state->fb && 6784 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6785 return true; 6786 } 6787 6788 return false; 6789 } 6790 6791 /** 6792 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6793 * 6794 * @dev: The DRM device 6795 * @state: The atomic state to commit 6796 * 6797 * Validate that the given atomic state is programmable by DC into hardware. 6798 * This involves constructing a &struct dc_state reflecting the new hardware 6799 * state we wish to commit, then querying DC to see if it is programmable. It's 6800 * important not to modify the existing DC state. Otherwise, atomic_check 6801 * may unexpectedly commit hardware changes. 6802 * 6803 * When validating the DC state, it's important that the right locks are 6804 * acquired. For full updates case which removes/adds/updates streams on one 6805 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6806 * that any such full update commit will wait for completion of any outstanding 6807 * flip using DRMs synchronization events. 6808 * 6809 * Note that DM adds the affected connectors for all CRTCs in state, when that 6810 * might not seem necessary. This is because DC stream creation requires the 6811 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6812 * be possible but non-trivial - a possible TODO item. 6813 * 6814 * Return: -Error code if validation failed. 6815 */ 6816 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6817 struct drm_atomic_commit *state) 6818 { 6819 struct amdgpu_device *adev = drm_to_adev(dev); 6820 struct dm_atomic_state *dm_state = NULL; 6821 struct dc *dc = adev->dm.dc; 6822 struct drm_connector *connector; 6823 struct drm_connector_state *old_con_state, *new_con_state; 6824 struct drm_crtc *crtc; 6825 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6826 struct drm_plane *plane; 6827 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6828 enum dc_status status; 6829 int ret, i; 6830 bool lock_and_validation_needed = false; 6831 bool is_top_most_overlay = true; 6832 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6833 struct drm_dp_mst_topology_mgr *mgr; 6834 struct drm_dp_mst_topology_state *mst_state; 6835 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 6836 6837 trace_amdgpu_dm_atomic_check_begin(state); 6838 6839 ret = drm_atomic_helper_check_modeset(dev, state); 6840 if (ret) { 6841 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed\n"); 6842 goto fail; 6843 } 6844 6845 /* Check connector changes */ 6846 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 6847 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 6848 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 6849 6850 /* Skip connectors that are disabled or part of modeset already. */ 6851 if (!new_con_state->crtc) 6852 continue; 6853 6854 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 6855 if (IS_ERR(new_crtc_state)) { 6856 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed\n"); 6857 ret = PTR_ERR(new_crtc_state); 6858 goto fail; 6859 } 6860 6861 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 6862 dm_old_con_state->scaling != dm_new_con_state->scaling) 6863 new_crtc_state->connectors_changed = true; 6864 } 6865 6866 if (dc_resource_is_dsc_encoding_supported(dc)) { 6867 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6868 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6869 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 6870 } 6871 6872 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6873 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6874 ret = add_affected_mst_dsc_crtcs(state, crtc); 6875 if (ret) { 6876 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed\n"); 6877 goto fail; 6878 } 6879 } 6880 } 6881 } 6882 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 6883 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6884 6885 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 6886 !new_crtc_state->color_mgmt_changed && 6887 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 6888 dm_old_crtc_state->dsc_force_changed == false) 6889 continue; 6890 6891 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 6892 if (ret) { 6893 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed\n"); 6894 goto fail; 6895 } 6896 6897 if (!new_crtc_state->enable) 6898 continue; 6899 6900 ret = drm_atomic_add_affected_connectors(state, crtc); 6901 if (ret) { 6902 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed\n"); 6903 goto fail; 6904 } 6905 6906 ret = drm_atomic_add_affected_planes(state, crtc); 6907 if (ret) { 6908 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed\n"); 6909 goto fail; 6910 } 6911 6912 if (dm_old_crtc_state->dsc_force_changed) 6913 new_crtc_state->mode_changed = true; 6914 } 6915 6916 /* 6917 * Add all primary and overlay planes on the CRTC to the state 6918 * whenever a plane is enabled to maintain correct z-ordering 6919 * and to enable fast surface updates. 6920 */ 6921 drm_for_each_crtc(crtc, dev) { 6922 bool modified = false; 6923 6924 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 6925 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6926 continue; 6927 6928 if (new_plane_state->crtc == crtc || 6929 old_plane_state->crtc == crtc) { 6930 modified = true; 6931 break; 6932 } 6933 } 6934 6935 if (!modified) 6936 continue; 6937 6938 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 6939 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6940 continue; 6941 6942 new_plane_state = 6943 drm_atomic_get_plane_state(state, plane); 6944 6945 if (IS_ERR(new_plane_state)) { 6946 ret = PTR_ERR(new_plane_state); 6947 drm_dbg_atomic(dev, "new_plane_state is BAD\n"); 6948 goto fail; 6949 } 6950 } 6951 } 6952 6953 /* 6954 * DC consults the zpos (layer_index in DC terminology) to determine the 6955 * hw plane on which to enable the hw cursor (see 6956 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 6957 * atomic state, so call drm helper to normalize zpos. 6958 */ 6959 ret = drm_atomic_normalize_zpos(dev, state); 6960 if (ret) { 6961 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n"); 6962 goto fail; 6963 } 6964 6965 /* 6966 * Determine whether cursors on each CRTC should be enabled in native or 6967 * overlay mode. 6968 */ 6969 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 6970 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6971 6972 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 6973 &dm_new_crtc_state->cursor_mode); 6974 if (ret) { 6975 drm_dbg(dev, "Failed to determine cursor mode\n"); 6976 goto fail; 6977 } 6978 6979 /* 6980 * If overlay cursor is needed, DC cannot go through the 6981 * native cursor update path. All enabled planes on the CRTC 6982 * need to be added for DC to not disable a plane by mistake 6983 */ 6984 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 6985 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 6986 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 6987 ret = -EINVAL; 6988 goto fail; 6989 } 6990 6991 ret = drm_atomic_add_affected_planes(state, crtc); 6992 if (ret) 6993 goto fail; 6994 } 6995 } 6996 6997 /* Remove exiting planes if they are modified */ 6998 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 6999 7000 ret = dm_update_plane_state(dc, state, plane, 7001 old_plane_state, 7002 new_plane_state, 7003 false, 7004 &lock_and_validation_needed, 7005 &is_top_most_overlay); 7006 if (ret) { 7007 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 7008 goto fail; 7009 } 7010 } 7011 7012 /* Disable all crtcs which require disable */ 7013 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7014 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7015 old_crtc_state, 7016 new_crtc_state, 7017 false, 7018 &lock_and_validation_needed); 7019 if (ret) { 7020 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed\n"); 7021 goto fail; 7022 } 7023 } 7024 7025 /* Enable all crtcs which require enable */ 7026 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7027 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7028 old_crtc_state, 7029 new_crtc_state, 7030 true, 7031 &lock_and_validation_needed); 7032 if (ret) { 7033 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed\n"); 7034 goto fail; 7035 } 7036 } 7037 7038 /* Add new/modified planes */ 7039 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 7040 ret = dm_update_plane_state(dc, state, plane, 7041 old_plane_state, 7042 new_plane_state, 7043 true, 7044 &lock_and_validation_needed, 7045 &is_top_most_overlay); 7046 if (ret) { 7047 drm_dbg_atomic(dev, "dm_update_plane_state() failed\n"); 7048 goto fail; 7049 } 7050 } 7051 7052 #if defined(CONFIG_DRM_AMD_DC_FP) 7053 if (dc_resource_is_dsc_encoding_supported(dc)) { 7054 ret = pre_validate_dsc(state, &dm_state, vars); 7055 if (ret != 0) 7056 goto fail; 7057 } 7058 #endif 7059 7060 /* Run this here since we want to validate the streams we created */ 7061 ret = drm_atomic_helper_check_planes(dev, state); 7062 if (ret) { 7063 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed\n"); 7064 goto fail; 7065 } 7066 7067 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7068 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7069 if (dm_new_crtc_state->mpo_requested) 7070 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 7071 } 7072 7073 /* Check cursor restrictions */ 7074 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7075 enum amdgpu_dm_cursor_mode required_cursor_mode; 7076 int is_rotated, is_scaled; 7077 7078 /* Overlay cusor not subject to native cursor restrictions */ 7079 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7080 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 7081 continue; 7082 7083 /* Check if rotation or scaling is enabled on DCN401 */ 7084 if ((drm_plane_mask(crtc->cursor) & 7085 new_crtc_state->plane_mask) && 7086 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1) || 7087 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 7088 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { 7089 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 7090 7091 is_rotated = new_cursor_state && 7092 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 7093 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 7094 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 7095 7096 if (is_rotated || is_scaled) { 7097 drm_dbg_driver( 7098 crtc->dev, 7099 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 7100 crtc->base.id, crtc->name); 7101 ret = -EINVAL; 7102 goto fail; 7103 } 7104 } 7105 7106 /* If HW can only do native cursor, check restrictions again */ 7107 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 7108 &required_cursor_mode); 7109 if (ret) { 7110 drm_dbg_driver(crtc->dev, 7111 "[CRTC:%d:%s] Checking cursor mode failed\n", 7112 crtc->base.id, crtc->name); 7113 goto fail; 7114 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 7115 drm_dbg_driver(crtc->dev, 7116 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 7117 crtc->base.id, crtc->name); 7118 ret = -EINVAL; 7119 goto fail; 7120 } 7121 } 7122 7123 if (state->legacy_cursor_update) { 7124 /* 7125 * This is a fast cursor update coming from the plane update 7126 * helper, check if it can be done asynchronously for better 7127 * performance. 7128 */ 7129 state->async_update = 7130 !drm_atomic_helper_async_check(dev, state); 7131 7132 /* 7133 * Skip the remaining global validation if this is an async 7134 * update. Cursor updates can be done without affecting 7135 * state or bandwidth calcs and this avoids the performance 7136 * penalty of locking the private state object and 7137 * allocating a new dc_state. 7138 */ 7139 if (state->async_update) 7140 return 0; 7141 } 7142 7143 /* Check scaling and underscan changes*/ 7144 /* TODO Removed scaling changes validation due to inability to commit 7145 * new stream into context w\o causing full reset. Need to 7146 * decide how to handle. 7147 */ 7148 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7149 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7150 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7151 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7152 7153 /* Skip any modesets/resets */ 7154 if (!acrtc || drm_atomic_crtc_needs_modeset( 7155 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7156 continue; 7157 7158 /* Skip any thing not scale or underscan changes */ 7159 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7160 continue; 7161 7162 lock_and_validation_needed = true; 7163 } 7164 7165 /* set the slot info for each mst_state based on the link encoding format */ 7166 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 7167 struct amdgpu_dm_connector *aconnector; 7168 struct drm_connector *connector; 7169 struct drm_connector_list_iter iter; 7170 u8 link_coding_cap; 7171 7172 drm_connector_list_iter_begin(dev, &iter); 7173 drm_for_each_connector_iter(connector, &iter) { 7174 if (connector->index == mst_state->mgr->conn_base_id) { 7175 aconnector = to_amdgpu_dm_connector(connector); 7176 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 7177 drm_dp_mst_update_slots(mst_state, link_coding_cap); 7178 7179 break; 7180 } 7181 } 7182 drm_connector_list_iter_end(&iter); 7183 } 7184 7185 /** 7186 * Streams and planes are reset when there are changes that affect 7187 * bandwidth. Anything that affects bandwidth needs to go through 7188 * DC global validation to ensure that the configuration can be applied 7189 * to hardware. 7190 * 7191 * We have to currently stall out here in atomic_check for outstanding 7192 * commits to finish in this case because our IRQ handlers reference 7193 * DRM state directly - we can end up disabling interrupts too early 7194 * if we don't. 7195 * 7196 * TODO: Remove this stall and drop DM state private objects. 7197 */ 7198 if (lock_and_validation_needed) { 7199 ret = dm_atomic_get_state(state, &dm_state); 7200 if (ret) { 7201 drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); 7202 goto fail; 7203 } 7204 7205 ret = do_aquire_global_lock(dev, state); 7206 if (ret) { 7207 drm_dbg_atomic(dev, "do_aquire_global_lock() failed\n"); 7208 goto fail; 7209 } 7210 7211 #if defined(CONFIG_DRM_AMD_DC_FP) 7212 if (dc_resource_is_dsc_encoding_supported(dc)) { 7213 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 7214 if (ret) { 7215 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n"); 7216 ret = -EINVAL; 7217 goto fail; 7218 } 7219 } 7220 #endif 7221 7222 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 7223 if (ret) { 7224 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); 7225 goto fail; 7226 } 7227 7228 /* 7229 * Perform validation of MST topology in the state: 7230 * We need to perform MST atomic check before calling 7231 * dc_validate_global_state(), or there is a chance 7232 * to get stuck in an infinite loop and hang eventually. 7233 */ 7234 ret = drm_dp_mst_atomic_check(state); 7235 if (ret) { 7236 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); 7237 goto fail; 7238 } 7239 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 7240 if (status != DC_OK) { 7241 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 7242 dc_status_to_str(status), status); 7243 ret = -EINVAL; 7244 goto fail; 7245 } 7246 } else { 7247 /* 7248 * The commit is a fast update. Fast updates shouldn't change 7249 * the DC context, affect global validation, and can have their 7250 * commit work done in parallel with other commits not touching 7251 * the same resource. If we have a new DC context as part of 7252 * the DM atomic state from validation we need to free it and 7253 * retain the existing one instead. 7254 * 7255 * Furthermore, since the DM atomic state only contains the DC 7256 * context and can safely be annulled, we can free the state 7257 * and clear the associated private object now to free 7258 * some memory and avoid a possible use-after-free later. 7259 */ 7260 7261 for (i = 0; i < state->num_private_objs; i++) { 7262 struct drm_private_obj *obj = state->private_objs[i].ptr; 7263 7264 if (obj->funcs == adev->dm.atomic_obj.funcs) { 7265 int j = state->num_private_objs-1; 7266 7267 dm_atomic_destroy_state(obj, 7268 state->private_objs[i].state_to_destroy); 7269 7270 /* If i is not at the end of the array then the 7271 * last element needs to be moved to where i was 7272 * before the array can safely be truncated. 7273 */ 7274 if (i != j) 7275 state->private_objs[i] = 7276 state->private_objs[j]; 7277 7278 state->private_objs[j].ptr = NULL; 7279 state->private_objs[j].state_to_destroy = NULL; 7280 state->private_objs[j].old_state = NULL; 7281 state->private_objs[j].new_state = NULL; 7282 7283 state->num_private_objs = j; 7284 break; 7285 } 7286 } 7287 } 7288 7289 /* Store the overall update type for use later in atomic check. */ 7290 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7291 struct dm_crtc_state *dm_new_crtc_state = 7292 to_dm_crtc_state(new_crtc_state); 7293 7294 /* 7295 * Only allow async flips for fast updates that don't change 7296 * the FB pitch, the DCC state, rotation, mem_type, etc. 7297 */ 7298 if (new_crtc_state->async_flip && 7299 (lock_and_validation_needed || 7300 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 7301 drm_dbg_atomic(crtc->dev, 7302 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 7303 crtc->base.id, crtc->name); 7304 ret = -EINVAL; 7305 goto fail; 7306 } 7307 7308 dm_new_crtc_state->update_type = lock_and_validation_needed ? 7309 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 7310 } 7311 7312 /* Must be success */ 7313 WARN_ON(ret); 7314 7315 trace_amdgpu_dm_atomic_check_finish(state, ret); 7316 7317 return ret; 7318 7319 fail: 7320 if (ret == -EDEADLK) 7321 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 7322 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7323 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 7324 else 7325 drm_dbg_atomic(dev, "Atomic check failed with err: %d\n", ret); 7326 7327 trace_amdgpu_dm_atomic_check_finish(state, ret); 7328 7329 return ret; 7330 } 7331 7332 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 7333 { 7334 struct amdgpu_device *adev = drm_to_adev(dev); 7335 struct dc *dc = adev->dm.dc; 7336 int i; 7337 7338 mutex_lock(&adev->dm.dc_lock); 7339 if (dc->current_state) { 7340 for (i = 0; i < dc->current_state->stream_count; ++i) 7341 dc->current_state->streams[i] 7342 ->triggered_crtc_reset.enabled = 7343 adev->dm.force_timing_sync; 7344 7345 dm_enable_per_frame_crtc_master_sync(dc->current_state); 7346 dc_trigger_sync(dc, dc->current_state); 7347 } 7348 mutex_unlock(&adev->dm.dc_lock); 7349 } 7350 7351 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 7352 u32 value, const char *func_name) 7353 { 7354 #ifdef DM_CHECK_ADDR_0 7355 if (address == 0) { 7356 drm_err(adev_to_drm(ctx->driver_context), 7357 "invalid register write. address = 0"); 7358 return; 7359 } 7360 #endif 7361 7362 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7363 cgs_write_register(ctx->cgs_device, address, value); 7364 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 7365 } 7366 7367 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 7368 const char *func_name) 7369 { 7370 u32 value; 7371 #ifdef DM_CHECK_ADDR_0 7372 if (address == 0) { 7373 drm_err(adev_to_drm(ctx->driver_context), 7374 "invalid register read; address = 0\n"); 7375 return 0; 7376 } 7377 #endif 7378 7379 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7380 7381 value = cgs_read_register(ctx->cgs_device, address); 7382 7383 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 7384 7385 return value; 7386 } 7387 7388 void dm_acpi_process_phy_transition_interlock( 7389 const struct dc_context *ctx, 7390 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 7391 { 7392 // Not yet implemented 7393 } 7394