1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2015-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 /* The caprices of the preprocessor require that this be declared right here */ 28 #define CREATE_TRACE_POINTS 29 30 #include "dm_services_types.h" 31 #include "dc.h" 32 #include "link_enc_cfg.h" 33 #include "dc/inc/core_types.h" 34 #include "dal_asic_id.h" 35 #include "dmub/dmub_srv.h" 36 #include "dc/inc/hw/dmcu.h" 37 #include "dc/inc/hw/abm.h" 38 #include "dc/dc_dmub_srv.h" 39 #include "dc/dc_edid_parser.h" 40 #include "dc/dc_stat.h" 41 #include "dc/dc_state.h" 42 #include "amdgpu_dm_trace.h" 43 #include "link/protocols/link_dpcd.h" 44 #include "link_service_types.h" 45 #include "link/protocols/link_dp_capability.h" 46 #include "link/protocols/link_ddc.h" 47 48 #include "amdgpu.h" 49 #include "amdgpu_display.h" 50 #include "amdgpu_ucode.h" 51 #include "atom.h" 52 #include "amdgpu_dm.h" 53 #include "amdgpu_dm_plane.h" 54 #include "amdgpu_dm_crtc.h" 55 #include "amdgpu_dm_hdcp.h" 56 #include <drm/display/drm_hdcp_helper.h> 57 #include "amdgpu_dm_wb.h" 58 #include "amdgpu_atombios.h" 59 60 #include "amd_shared.h" 61 #include "amdgpu_dm_irq.h" 62 #include "dm_helpers.h" 63 #include "amdgpu_dm_mst_types.h" 64 #if defined(CONFIG_DEBUG_FS) 65 #include "amdgpu_dm_debugfs.h" 66 #endif 67 #include "amdgpu_dm_psr.h" 68 #include "amdgpu_dm_replay.h" 69 #include "amdgpu_dm_backlight.h" 70 #include "amdgpu_dm_audio.h" 71 #include "amdgpu_dm_dmub.h" 72 #include "amdgpu_dm_connector.h" 73 74 #include "ivsrcid/ivsrcid_vislands30.h" 75 76 #include <linux/backlight.h> 77 #include <linux/module.h> 78 #include <linux/moduleparam.h> 79 #include <linux/types.h> 80 #include <linux/pm_runtime.h> 81 #include <linux/pci.h> 82 #include <linux/power_supply.h> 83 #include <linux/firmware.h> 84 #include <linux/component.h> 85 #include <linux/sort.h> 86 87 #include <drm/drm_privacy_screen_consumer.h> 88 #include <drm/display/drm_dp_mst_helper.h> 89 #include <drm/display/drm_hdmi_helper.h> 90 #include <drm/drm_atomic.h> 91 #include <drm/drm_atomic_uapi.h> 92 #include <drm/drm_atomic_helper.h> 93 #include <drm/drm_blend.h> 94 #include <drm/drm_fixed.h> 95 #include <drm/drm_fourcc.h> 96 #include <drm/drm_edid.h> 97 #include <drm/drm_eld.h> 98 #include <drm/drm_mode.h> 99 #include <drm/drm_utils.h> 100 #include <drm/drm_vblank.h> 101 #include <drm/drm_colorop.h> 102 #include <drm/drm_gem_atomic_helper.h> 103 104 #include <media/cec-notifier.h> 105 #include <acpi/video.h> 106 107 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 108 109 #include "modules/inc/mod_freesync.h" 110 #include "modules/inc/mod_power.h" 111 #include "modules/power/power_helpers.h" 112 113 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); 114 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); 115 116 /** 117 * DOC: overview 118 * 119 * The AMDgpu display manager, **amdgpu_dm** (or even simpler, 120 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM 121 * requests into DC requests, and DC responses into DRM responses. 122 * 123 * The root control structure is &struct amdgpu_display_manager. 124 */ 125 126 /* basic init/fini API */ 127 static int amdgpu_dm_init(struct amdgpu_device *adev); 128 static void amdgpu_dm_fini(struct amdgpu_device *adev); 129 STATIC_IFN_KUNIT void reset_freesync_config_for_crtc(struct dm_crtc_state *new_crtc_state); 130 131 /* 132 * initializes drm_device display related structures, based on the information 133 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, 134 * drm_encoder, drm_mode_config 135 * 136 * Returns 0 on success 137 */ 138 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); 139 /* removes and deallocates the drm structures, created by the above function */ 140 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); 141 142 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state); 143 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state); 144 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context); 145 146 static int amdgpu_dm_atomic_check(struct drm_device *dev, 147 struct drm_atomic_commit *state); 148 149 STATIC_IFN_KUNIT bool 150 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 151 struct drm_crtc_state *new_crtc_state); 152 153 static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) 154 { 155 if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter) 156 dc_exit_ips_for_hw_access(dc); 157 } 158 159 /* 160 * dm_vblank_get_counter 161 * 162 * @brief 163 * Get counter for number of vertical blanks 164 * 165 * @param 166 * struct amdgpu_device *adev - [in] desired amdgpu device 167 * int disp_idx - [in] which CRTC to get the counter from 168 * 169 * @return 170 * Counter for vertical blanks 171 */ 172 STATIC_IFN_KUNIT u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) 173 { 174 struct amdgpu_crtc *acrtc = NULL; 175 176 if (crtc >= adev->mode_info.num_crtc) 177 return 0; 178 179 acrtc = adev->mode_info.crtcs[crtc]; 180 181 if (!acrtc->dm_irq_params.stream) { 182 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 183 crtc); 184 return 0; 185 } 186 187 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); 188 } 189 EXPORT_IF_KUNIT(dm_vblank_get_counter); 190 191 STATIC_IFN_KUNIT int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 192 u32 *vbl, u32 *position) 193 { 194 u32 v_blank_start = 0, v_blank_end = 0, h_position = 0, v_position = 0; 195 struct amdgpu_crtc *acrtc = NULL; 196 struct dc *dc = adev->dm.dc; 197 198 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 199 return -EINVAL; 200 201 acrtc = adev->mode_info.crtcs[crtc]; 202 203 if (!acrtc->dm_irq_params.stream) { 204 drm_err(adev_to_drm(adev), "dc_stream_state is NULL for crtc '%d'!\n", 205 crtc); 206 return 0; 207 } 208 209 if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) 210 dc_allow_idle_optimizations(dc, false); 211 212 /* 213 * TODO rework base driver to use values directly. 214 * for now parse it back into reg-format 215 */ 216 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, 217 &v_blank_start, 218 &v_blank_end, 219 &h_position, 220 &v_position); 221 222 *position = v_position | (h_position << 16); 223 *vbl = v_blank_start | (v_blank_end << 16); 224 225 return 0; 226 } 227 EXPORT_IF_KUNIT(dm_crtc_get_scanoutpos); 228 229 STATIC_IFN_KUNIT bool dm_is_idle(struct amdgpu_ip_block *ip_block) 230 { 231 /* XXX todo */ 232 return true; 233 } 234 EXPORT_IF_KUNIT(dm_is_idle); 235 236 STATIC_IFN_KUNIT int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) 237 { 238 /* XXX todo */ 239 return 0; 240 } 241 EXPORT_IF_KUNIT(dm_wait_for_idle); 242 243 STATIC_IFN_KUNIT int dm_soft_reset(struct amdgpu_ip_block *ip_block) 244 { 245 /* XXX todo */ 246 return 0; 247 } 248 EXPORT_IF_KUNIT(dm_soft_reset); 249 250 STATIC_IFN_KUNIT bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, 251 struct dm_crtc_state *new_state) 252 { 253 if (new_state->stream->adjust.timing_adjust_pending) 254 return true; 255 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) 256 return true; 257 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state)) 258 return true; 259 else 260 return false; 261 } 262 EXPORT_IF_KUNIT(is_dc_timing_adjust_needed); 263 264 /* 265 * DC will program planes with their z-order determined by their ordering 266 * in the dc_surface_updates array. This comparator is used to sort them 267 * by descending zpos. 268 */ 269 STATIC_IFN_KUNIT int dm_plane_layer_index_cmp(const void *a, const void *b) 270 { 271 const struct dc_surface_update *sa = (struct dc_surface_update *)a; 272 const struct dc_surface_update *sb = (struct dc_surface_update *)b; 273 274 /* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */ 275 return sb->surface->layer_index - sa->surface->layer_index; 276 } 277 EXPORT_IF_KUNIT(dm_plane_layer_index_cmp); 278 279 /** 280 * update_planes_and_stream_adapter() - Send planes to be updated in DC 281 * 282 * DC has a generic way to update planes and stream via 283 * dc_update_planes_and_stream function; however, DM might need some 284 * adjustments and preparation before calling it. This function is a wrapper 285 * for the dc_update_planes_and_stream that does any required configuration 286 * before passing control to DC. 287 * 288 * @dc: Display Core control structure 289 * @update_type: specify whether it is FULL/MEDIUM/FAST update 290 * @planes_count: planes count to update 291 * @stream: stream state 292 * @stream_update: stream update 293 * @array_of_surface_update: dc surface update pointer 294 * 295 */ 296 static inline bool update_planes_and_stream_adapter(struct dc *dc, 297 int update_type, 298 int planes_count, 299 struct dc_stream_state *stream, 300 struct dc_stream_update *stream_update, 301 struct dc_surface_update *array_of_surface_update) 302 { 303 sort(array_of_surface_update, planes_count, 304 sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL); 305 306 /* 307 * Previous frame finished and HW is ready for optimization. 308 */ 309 dc_post_update_surfaces_to_stream(dc); 310 311 return dc_update_planes_and_stream(dc, 312 array_of_surface_update, 313 planes_count, 314 stream, 315 stream_update); 316 } 317 318 STATIC_IFN_KUNIT int dm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 319 enum amd_clockgating_state state) 320 { 321 return 0; 322 } 323 EXPORT_IF_KUNIT(dm_set_clockgating_state); 324 325 STATIC_IFN_KUNIT int dm_set_powergating_state(struct amdgpu_ip_block *ip_block, 326 enum amd_powergating_state state) 327 { 328 return 0; 329 } 330 EXPORT_IF_KUNIT(dm_set_powergating_state); 331 332 /* Prototypes of private functions */ 333 static int dm_early_init(struct amdgpu_ip_block *ip_block); 334 335 /* Allocate memory for FBC compressed data */ 336 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) 337 { 338 u64 pt_base; 339 u32 logical_addr_low; 340 u32 logical_addr_high; 341 u32 agp_base, agp_bot, agp_top; 342 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base; 343 344 memset(pa_config, 0, sizeof(*pa_config)); 345 346 agp_base = 0; 347 agp_bot = adev->gmc.agp_start >> 24; 348 agp_top = adev->gmc.agp_end >> 24; 349 350 /* AGP aperture is disabled */ 351 if (agp_bot > agp_top) { 352 logical_addr_low = adev->gmc.fb_start >> 18; 353 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 354 AMD_APU_IS_RENOIR | 355 AMD_APU_IS_GREEN_SARDINE)) 356 /* 357 * Raven2 has a HW issue that it is unable to use the vram which 358 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 359 * workaround that increase system aperture high address (add 1) 360 * to get rid of the VM fault and hardware hang. 361 */ 362 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; 363 else 364 logical_addr_high = adev->gmc.fb_end >> 18; 365 } else { 366 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18; 367 if (adev->apu_flags & (AMD_APU_IS_RAVEN2 | 368 AMD_APU_IS_RENOIR | 369 AMD_APU_IS_GREEN_SARDINE)) 370 /* 371 * Raven2 has a HW issue that it is unable to use the vram which 372 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the 373 * workaround that increase system aperture high address (add 1) 374 * to get rid of the VM fault and hardware hang. 375 */ 376 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18); 377 else 378 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18; 379 } 380 381 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 382 383 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> 384 AMDGPU_GPU_PAGE_SHIFT); 385 page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> 386 AMDGPU_GPU_PAGE_SHIFT); 387 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> 388 AMDGPU_GPU_PAGE_SHIFT); 389 page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> 390 AMDGPU_GPU_PAGE_SHIFT); 391 page_table_base.high_part = upper_32_bits(pt_base); 392 page_table_base.low_part = lower_32_bits(pt_base); 393 394 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; 395 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; 396 397 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; 398 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; 399 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; 400 401 pa_config->system_aperture.fb_base = adev->gmc.fb_start; 402 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset; 403 pa_config->system_aperture.fb_top = adev->gmc.fb_end; 404 405 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; 406 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; 407 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; 408 409 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; 410 411 } 412 413 struct amdgpu_stutter_quirk { 414 u16 chip_vendor; 415 u16 chip_device; 416 u16 subsys_vendor; 417 u16 subsys_device; 418 u8 revision; 419 }; 420 421 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { 422 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ 423 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 424 { 0, 0, 0, 0, 0 }, 425 }; 426 427 STATIC_IFN_KUNIT bool dm_should_disable_stutter(struct pci_dev *pdev) 428 { 429 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; 430 431 while (p && p->chip_device != 0) { 432 if (pdev->vendor == p->chip_vendor && 433 pdev->device == p->chip_device && 434 pdev->subsystem_vendor == p->subsys_vendor && 435 pdev->subsystem_device == p->subsys_device && 436 pdev->revision == p->revision) { 437 return true; 438 } 439 ++p; 440 } 441 return false; 442 } 443 EXPORT_IF_KUNIT(dm_should_disable_stutter); 444 445 446 void* 447 dm_allocate_gpu_mem( 448 struct amdgpu_device *adev, 449 enum dc_gpu_mem_alloc_type type, 450 size_t size, 451 long long *addr) 452 { 453 struct dal_allocation *da; 454 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ? 455 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM; 456 int ret; 457 458 da = kzalloc_obj(struct dal_allocation); 459 if (!da) 460 return NULL; 461 462 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, 463 domain, &da->bo, 464 &da->gpu_addr, &da->cpu_ptr); 465 466 *addr = da->gpu_addr; 467 468 if (ret) { 469 kfree(da); 470 return NULL; 471 } 472 473 /* add da to list in dm */ 474 list_add(&da->list, &adev->dm.da_list); 475 476 return da->cpu_ptr; 477 } 478 479 void 480 dm_free_gpu_mem( 481 struct amdgpu_device *adev, 482 enum dc_gpu_mem_alloc_type type, 483 void *pvMem) 484 { 485 struct dal_allocation *da; 486 487 /* walk the da list in DM */ 488 list_for_each_entry(da, &adev->dm.da_list, list) { 489 if (pvMem == da->cpu_ptr) { 490 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 491 list_del(&da->list); 492 kfree(da); 493 break; 494 } 495 } 496 497 } 498 499 static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm) 500 { 501 struct mod_power_init_params init_data[MAX_NUM_EDP]; 502 503 if (dm->num_of_edps == 0) { 504 drm_dbg_driver( 505 dm->ddev, 506 "amdgpu: No eDP detected, skip initializing power module\n"); 507 return 0; 508 } 509 510 /* Initialize all the power module parameters */ 511 for (int i = 0; i < dm->num_of_edps; i++) { 512 init_data[i].allow_psr_smu_optimizations = 513 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT); 514 init_data[i].allow_psr_multi_disp_optimizations = 515 !!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 516 /* See dm_late_init */ 517 init_data[i].backlight_ramping_override = false; 518 init_data[i].backlight_ramping_start = 0xCCCC; 519 init_data[i].backlight_ramping_reduction = 0xCCCCCCCC; 520 init_data[i].def_varibright_level = 0; 521 init_data[i].abm_config_setting = 0; 522 init_data[i].num_backlight_levels = 101; 523 init_data[i].use_nits_based_brightness = false; 524 init_data[i].panel_max_millinits = 0; 525 init_data[i].panel_min_millinits = 0; 526 init_data[i].disable_fractional_pwm = 527 !(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK); 528 init_data[i].use_custom_backlight_caps = false; 529 init_data[i].custom_backlight_caps_config_no = 0; 530 init_data[i].use_linear_backlight_curve = false; 531 init_data[i].def_varibright_enable = 0; 532 init_data[i].varibright_level = 0; 533 /* 534 * Power module uses 16-bit backlight levels (0xFFFF max) rather 535 * than 8-bit(0XFF max) 536 */ 537 init_data[i].min_backlight_pwm = 538 dm->backlight_caps[i].min_input_signal * 0x101; 539 init_data[i].max_backlight_pwm = 540 dm->backlight_caps[i].max_input_signal * 0x101; 541 init_data[i].min_abm_backlight = 542 dm->backlight_caps[i].min_input_signal * 0x101; 543 544 /* Min backlight level after ABM reduction, Don't allow below 1% 545 * 0xFFFF x 0.01 = 0x28F 546 */ 547 init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ? 548 0x28F : init_data[i].min_abm_backlight; 549 } 550 551 dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps); 552 if (!dm->power_module) { 553 drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n"); 554 return -ENOMEM; 555 } 556 557 mod_power_hw_init(dm->power_module); 558 drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n"); 559 560 return 0; 561 } 562 563 static int amdgpu_dm_init(struct amdgpu_device *adev) 564 { 565 struct dc_init_data init_data; 566 struct dc_callback_init init_params; 567 int r; 568 569 adev->dm.ddev = adev_to_drm(adev); 570 adev->dm.adev = adev; 571 572 /* Zero all the fields */ 573 memset(&init_data, 0, sizeof(init_data)); 574 memset(&init_params, 0, sizeof(init_params)); 575 576 mutex_init(&adev->dm.dpia_aux_lock); 577 mutex_init(&adev->dm.dc_lock); 578 mutex_init(&adev->dm.audio_lock); 579 580 spin_lock_init(&adev->dm.dmub_lock); 581 582 if (amdgpu_dm_irq_init(adev)) { 583 drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n"); 584 goto error; 585 } 586 587 /* special handling for early revisions of GC 11.5.4 */ 588 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) 589 init_data.asic_id.chip_family = AMDGPU_FAMILY_GC_11_5_4; 590 else 591 init_data.asic_id.chip_family = adev->family; 592 593 init_data.asic_id.pci_revision_id = adev->pdev->revision; 594 init_data.asic_id.hw_internal_rev = adev->external_rev_id; 595 init_data.asic_id.chip_id = adev->pdev->device; 596 597 init_data.asic_id.vram_width = adev->gmc.vram_width; 598 /* TODO: initialize init_data.asic_id.vram_type here!!!! */ 599 init_data.asic_id.atombios_base_address = 600 adev->mode_info.atom_context->bios; 601 602 init_data.driver = adev; 603 604 /* cgs_device was created in dm_sw_init() */ 605 init_data.cgs_device = adev->dm.cgs_device; 606 607 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; 608 609 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 610 case IP_VERSION(2, 1, 0): 611 switch (adev->dm.dmcub_fw_version) { 612 case 0: /* development */ 613 case 0x1: /* linux-firmware.git hash 6d9f399 */ 614 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ 615 init_data.flags.disable_dmcu = false; 616 break; 617 default: 618 init_data.flags.disable_dmcu = true; 619 } 620 break; 621 case IP_VERSION(2, 0, 3): 622 init_data.flags.disable_dmcu = true; 623 break; 624 default: 625 break; 626 } 627 628 /* APU support S/G display by default except: 629 * ASICs before Carrizo, 630 * RAVEN1 (Users reported stability issue) 631 */ 632 633 if (adev->asic_type < CHIP_CARRIZO) { 634 init_data.flags.gpu_vm_support = false; 635 } else if (adev->asic_type == CHIP_RAVEN) { 636 if (adev->apu_flags & AMD_APU_IS_RAVEN) 637 init_data.flags.gpu_vm_support = false; 638 else 639 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0); 640 } else { 641 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(2, 0, 3)) 642 init_data.flags.gpu_vm_support = (amdgpu_sg_display == 1); 643 else 644 init_data.flags.gpu_vm_support = 645 (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU); 646 } 647 648 adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support; 649 650 if (amdgpu_dc_feature_mask & DC_FBC_MASK) 651 init_data.flags.fbc_support = true; 652 653 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) 654 init_data.flags.multi_mon_pp_mclk_switch = true; 655 656 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) 657 init_data.flags.disable_fractional_pwm = true; 658 659 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) 660 init_data.flags.edp_no_power_sequencing = true; 661 662 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) 663 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true; 664 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) 665 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true; 666 667 if (amdgpu_dc_feature_mask & DC_FRL_MASK) 668 init_data.flags.enable_frl = true; 669 670 init_data.flags.seamless_boot_edp_requested = false; 671 672 if (amdgpu_device_seamless_boot_supported(adev)) { 673 init_data.flags.seamless_boot_edp_requested = true; 674 init_data.flags.allow_seamless_boot_optimization = true; 675 drm_dbg(adev->dm.ddev, "Seamless boot requested\n"); 676 } 677 678 init_data.flags.enable_mipi_converter_optimization = true; 679 680 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; 681 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; 682 init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0]; 683 684 if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) 685 init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; 686 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) 687 init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; 688 else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) 689 init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; 690 else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) 691 init_data.flags.disable_ips = DMUB_IPS_ENABLE; 692 else 693 init_data.flags.disable_ips = dm_get_default_ips_mode(adev); 694 695 init_data.flags.disable_ips_in_vpb = 0; 696 697 /* DCN35 and above supports dynamic DTBCLK switch */ 698 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) 699 init_data.flags.allow_0_dtb_clk = true; 700 701 /* Enable DWB for tested platforms only */ 702 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) 703 init_data.num_virtual_links = 1; 704 705 /* DCN42 and above dpia switch to unified link training path */ 706 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { 707 init_data.flags.consolidated_dpia_dp_lt = true; 708 init_data.flags.enable_dpia_pre_training = true; 709 init_data.flags.unify_link_enc_assignment = true; 710 init_data.flags.usb4_bw_alloc_support = true; 711 } 712 retrieve_dmi_info(&adev->dm); 713 if (adev->dm.edp0_on_dp1_quirk) 714 init_data.flags.support_edp0_on_dp1 = true; 715 716 if (adev->dm.bb_from_dmub) 717 init_data.bb_from_dmub = adev->dm.bb_from_dmub; 718 else 719 init_data.bb_from_dmub = NULL; 720 721 /* Display Core create. */ 722 adev->dm.dc = dc_create(&init_data); 723 724 if (adev->dm.dc) { 725 drm_info(adev_to_drm(adev), "Display Core v%s initialized on %s\n", DC_VER, 726 dce_version_to_string(adev->dm.dc->ctx->dce_version)); 727 } else { 728 drm_info(adev_to_drm(adev), "Display Core failed to initialize with v%s!\n", DC_VER); 729 goto error; 730 } 731 732 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { 733 adev->dm.dc->debug.force_single_disp_pipe_split = false; 734 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; 735 } 736 737 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) 738 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true; 739 if (dm_should_disable_stutter(adev->pdev)) 740 adev->dm.dc->debug.disable_stutter = true; 741 742 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) 743 adev->dm.dc->debug.disable_stutter = true; 744 745 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) 746 adev->dm.dc->debug.disable_dsc = true; 747 748 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) 749 adev->dm.dc->debug.disable_clock_gate = true; 750 751 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) 752 adev->dm.dc->debug.force_subvp_mclk_switch = true; 753 754 if (amdgpu_dc_debug_mask & DC_DISABLE_SUBVP_FAMS) { 755 adev->dm.dc->debug.force_disable_subvp = true; 756 adev->dm.dc->debug.fams2_config.bits.enable = false; 757 } 758 759 if (amdgpu_dc_debug_mask & DC_ENABLE_DML2) { 760 adev->dm.dc->debug.using_dml2 = true; 761 adev->dm.dc->debug.using_dml21 = true; 762 } 763 764 if (amdgpu_dc_debug_mask & DC_HDCP_LC_FORCE_FW_ENABLE) 765 adev->dm.dc->debug.hdcp_lc_force_fw_enable = true; 766 767 if (amdgpu_dc_debug_mask & DC_HDCP_LC_ENABLE_SW_FALLBACK) 768 adev->dm.dc->debug.hdcp_lc_enable_sw_fallback = true; 769 770 if (amdgpu_dc_debug_mask & DC_SKIP_DETECTION_LT) 771 adev->dm.dc->debug.skip_detection_link_training = true; 772 773 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; 774 775 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ 776 adev->dm.dc->debug.ignore_cable_id = true; 777 778 if (adev->dm.dc->caps.dp_hdmi21_pcon_support) 779 drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); 780 781 r = dm_dmub_hw_init(adev); 782 if (r) { 783 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 784 goto error; 785 } 786 787 dc_hardware_init(adev->dm.dc); 788 789 /* GOP/vBIOS may leave an OPTC enabled for a display present at power-on 790 * but no longer driven (e.g. an external DP unplugged at boot). Such a 791 * dangling pipe keeps DCN out of idle and blocks s0i3. Power it down 792 * here when nothing needs to be preserved. 793 */ 794 if (adev->flags & AMD_IS_APU) 795 dc_disable_dangling_timing_generators(adev->dm.dc); 796 797 adev->dm.hpd_rx_offload_wq = amdgpu_dm_hpd_rx_irq_create_workqueue(adev); 798 if (!adev->dm.hpd_rx_offload_wq) { 799 drm_err(adev_to_drm(adev), "failed to create hpd rx offload workqueue.\n"); 800 goto error; 801 } 802 803 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { 804 struct dc_phy_addr_space_config pa_config; 805 806 mmhub_read_system_context(adev, &pa_config); 807 808 // Call the DC init_memory func 809 dc_setup_system_context(adev->dm.dc, &pa_config); 810 } 811 812 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); 813 if (!adev->dm.freesync_module) { 814 drm_err(adev_to_drm(adev), 815 "failed to initialize freesync_module.\n"); 816 } else 817 drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", 818 adev->dm.freesync_module); 819 820 amdgpu_dm_init_color_mod(); 821 822 if (adev->dm.dc->caps.max_links > 0) { 823 adev->dm.vblank_control_workqueue = 824 create_singlethread_workqueue("dm_vblank_control_workqueue"); 825 if (!adev->dm.vblank_control_workqueue) 826 drm_err(adev_to_drm(adev), "failed to initialize vblank_workqueue.\n"); 827 } 828 829 if (adev->dm.dc->caps.ips_support && 830 adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) 831 adev->dm.idle_workqueue = idle_create_workqueue(adev); 832 833 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { 834 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); 835 836 if (!adev->dm.hdcp_workqueue) 837 drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); 838 else 839 drm_dbg_driver(adev_to_drm(adev), 840 "hdcp_workqueue init done %p.\n", 841 adev->dm.hdcp_workqueue); 842 843 dc_init_callbacks(adev->dm.dc, &init_params); 844 } 845 if (adev->dm.dc->caps.max_links > 0) { 846 adev->dm.hdmi_frl_status_polling_wq = 847 create_singlethread_workqueue("hdmi_frl_status_polling_workqueue"); 848 if (!adev->dm.hdmi_frl_status_polling_wq) 849 drm_err(adev_to_drm(adev), "failed to initialize hdmi_frl_status_polling_workqueue\n"); 850 } 851 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 852 init_completion(&adev->dm.dmub_aux_transfer_done); 853 adev->dm.dmub_notify = kzalloc_obj(struct dmub_notification); 854 if (!adev->dm.dmub_notify) { 855 drm_info(adev_to_drm(adev), "fail to allocate adev->dm.dmub_notify"); 856 goto error; 857 } 858 859 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); 860 if (!adev->dm.delayed_hpd_wq) { 861 drm_err(adev_to_drm(adev), "failed to create hpd offload workqueue.\n"); 862 goto error; 863 } 864 865 amdgpu_dm_outbox_init(adev); 866 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, 867 dm_dmub_aux_setconfig_callback, false)) { 868 drm_err(adev_to_drm(adev), "fail to register dmub aux callback"); 869 goto error; 870 } 871 872 for (size_t i = 0; i < ARRAY_SIZE(adev->dm.fused_io); i++) 873 init_completion(&adev->dm.fused_io[i].replied); 874 875 if (!dm_register_dmub_notify_callback(adev, DMUB_NOTIFICATION_FUSED_IO, 876 dm_dmub_aux_fused_io_callback, false)) { 877 drm_err(adev_to_drm(adev), "fail to register dmub fused io callback"); 878 goto error; 879 } 880 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. 881 * It is expected that DMUB will resend any pending notifications at this point. Note 882 * that hpd and hpd_irq handler registration are deferred to 883 * amdgpu_dm_register_hpd_handlers() to align legacy interface initialization 884 * sequence. Connection status will be proactivly detected once in the 885 * amdgpu_dm_initialize_drm_device. 886 */ 887 dc_enable_dmub_outbox(adev->dm.dc); 888 889 /* DPIA trace goes to dmesg logs only if outbox is enabled */ 890 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE) 891 dc_dmub_srv_enable_dpia_trace(adev->dm.dc); 892 } 893 894 if (amdgpu_dm_initialize_drm_device(adev)) { 895 drm_err(adev_to_drm(adev), 896 "failed to initialize sw for display support.\n"); 897 goto error; 898 } 899 900 if (amdgpu_dm_init_power_module(&adev->dm)) 901 goto error; 902 903 /* create fake encoders for MST */ 904 dm_dp_create_fake_mst_encoders(adev); 905 906 /* TODO: Add_display_info? */ 907 908 /* TODO use dynamic cursor width */ 909 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; 910 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; 911 912 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { 913 drm_err(adev_to_drm(adev), 914 "failed to initialize vblank for display support.\n"); 915 goto error; 916 } 917 918 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 919 amdgpu_dm_crtc_secure_display_create_contexts(adev); 920 if (!adev->dm.secure_display_ctx.crtc_ctx) 921 drm_err(adev_to_drm(adev), "failed to initialize secure display contexts.\n"); 922 923 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 0, 1)) 924 adev->dm.secure_display_ctx.support_mul_roi = true; 925 926 #endif 927 928 drm_dbg_driver(adev_to_drm(adev), "KMS initialized.\n"); 929 930 return 0; 931 error: 932 amdgpu_dm_fini(adev); 933 934 return -EINVAL; 935 } 936 937 static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) 938 { 939 struct amdgpu_device *adev = ip_block->adev; 940 941 amdgpu_dm_audio_fini(adev); 942 943 return 0; 944 } 945 946 static void amdgpu_dm_fini(struct amdgpu_device *adev) 947 { 948 int i; 949 950 if (adev->dm.vblank_control_workqueue) { 951 destroy_workqueue(adev->dm.vblank_control_workqueue); 952 adev->dm.vblank_control_workqueue = NULL; 953 } 954 955 if (adev->dm.idle_workqueue) { 956 if (adev->dm.idle_workqueue->running) { 957 adev->dm.idle_workqueue->enable = false; 958 flush_work(&adev->dm.idle_workqueue->work); 959 } 960 961 kfree(adev->dm.idle_workqueue); 962 adev->dm.idle_workqueue = NULL; 963 } 964 965 /* 966 * Disable ISM before dc_destroy() invalidates dm->dc. 967 * 968 * Quiesce workers first without dc_lock (they take dc_lock 969 * themselves, so syncing under it would deadlock), then drive the 970 * FSM back to FULL_POWER_RUNNING under dc_lock. 971 */ 972 amdgpu_dm_ism_disable(&adev->dm); 973 scoped_guard(mutex, &adev->dm.dc_lock) 974 amdgpu_dm_ism_force_full_power(&adev->dm); 975 976 amdgpu_dm_destroy_drm_device(&adev->dm); 977 978 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 979 if (adev->dm.secure_display_ctx.crtc_ctx) { 980 for (i = 0; i < adev->mode_info.num_crtc; i++) { 981 if (adev->dm.secure_display_ctx.crtc_ctx[i].crtc) { 982 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].notify_ta_work); 983 flush_work(&adev->dm.secure_display_ctx.crtc_ctx[i].forward_roi_work); 984 } 985 } 986 kfree(adev->dm.secure_display_ctx.crtc_ctx); 987 adev->dm.secure_display_ctx.crtc_ctx = NULL; 988 } 989 #endif 990 if (adev->dm.hdcp_workqueue) { 991 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); 992 adev->dm.hdcp_workqueue = NULL; 993 } 994 995 if (adev->dm.dc) { 996 dc_deinit_callbacks(adev->dm.dc); 997 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); 998 if (dc_enable_dmub_notifications(adev->dm.dc)) { 999 kfree(adev->dm.dmub_notify); 1000 adev->dm.dmub_notify = NULL; 1001 destroy_workqueue(adev->dm.delayed_hpd_wq); 1002 adev->dm.delayed_hpd_wq = NULL; 1003 } 1004 } 1005 1006 if (adev->dm.dmub_bo) 1007 amdgpu_bo_free_kernel(&adev->dm.dmub_bo, 1008 &adev->dm.dmub_bo_gpu_addr, 1009 &adev->dm.dmub_bo_cpu_addr); 1010 1011 if (adev->dm.boot_time_crc_info.bo_ptr) 1012 amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, 1013 &adev->dm.boot_time_crc_info.gpu_addr, 1014 &adev->dm.boot_time_crc_info.cpu_addr); 1015 1016 if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { 1017 for (i = 0; i < adev->dm.dc->caps.max_links; i++) { 1018 if (adev->dm.hpd_rx_offload_wq[i].wq) { 1019 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); 1020 adev->dm.hpd_rx_offload_wq[i].wq = NULL; 1021 } 1022 } 1023 1024 kfree(adev->dm.hpd_rx_offload_wq); 1025 adev->dm.hpd_rx_offload_wq = NULL; 1026 } 1027 1028 amdgpu_dm_irq_fini(adev); 1029 1030 /* DC Destroy TODO: Replace destroy DAL */ 1031 if (adev->dm.dc) 1032 dc_destroy(&adev->dm.dc); 1033 1034 if (adev->dm.cgs_device) { 1035 amdgpu_cgs_destroy_device(adev->dm.cgs_device); 1036 adev->dm.cgs_device = NULL; 1037 } 1038 if (adev->dm.freesync_module) { 1039 mod_freesync_destroy(adev->dm.freesync_module); 1040 adev->dm.freesync_module = NULL; 1041 } 1042 1043 if (adev->dm.power_module) { 1044 mod_power_destroy(adev->dm.power_module); 1045 adev->dm.power_module = NULL; 1046 } 1047 mutex_destroy(&adev->dm.audio_lock); 1048 mutex_destroy(&adev->dm.dc_lock); 1049 mutex_destroy(&adev->dm.dpia_aux_lock); 1050 } 1051 1052 static int load_dmcu_fw(struct amdgpu_device *adev) 1053 { 1054 const char *fw_name_dmcu = NULL; 1055 int r; 1056 const struct dmcu_firmware_header_v1_0 *hdr; 1057 1058 switch (adev->asic_type) { 1059 #if defined(CONFIG_DRM_AMD_DC_SI) 1060 case CHIP_TAHITI: 1061 case CHIP_PITCAIRN: 1062 case CHIP_VERDE: 1063 case CHIP_OLAND: 1064 #endif 1065 case CHIP_BONAIRE: 1066 case CHIP_HAWAII: 1067 case CHIP_KAVERI: 1068 case CHIP_KABINI: 1069 case CHIP_MULLINS: 1070 case CHIP_TONGA: 1071 case CHIP_FIJI: 1072 case CHIP_CARRIZO: 1073 case CHIP_STONEY: 1074 case CHIP_POLARIS11: 1075 case CHIP_POLARIS10: 1076 case CHIP_POLARIS12: 1077 case CHIP_VEGAM: 1078 case CHIP_VEGA10: 1079 case CHIP_VEGA12: 1080 case CHIP_VEGA20: 1081 return 0; 1082 case CHIP_NAVI12: 1083 fw_name_dmcu = FIRMWARE_NAVI12_DMCU; 1084 break; 1085 case CHIP_RAVEN: 1086 if (ASICREV_IS_PICASSO(adev->external_rev_id)) 1087 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1088 else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) 1089 fw_name_dmcu = FIRMWARE_RAVEN_DMCU; 1090 else 1091 return 0; 1092 break; 1093 default: 1094 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1095 case IP_VERSION(2, 0, 2): 1096 case IP_VERSION(2, 0, 3): 1097 case IP_VERSION(2, 0, 0): 1098 case IP_VERSION(2, 1, 0): 1099 case IP_VERSION(3, 0, 0): 1100 case IP_VERSION(3, 0, 2): 1101 case IP_VERSION(3, 0, 3): 1102 case IP_VERSION(3, 0, 1): 1103 case IP_VERSION(3, 1, 2): 1104 case IP_VERSION(3, 1, 3): 1105 case IP_VERSION(3, 1, 4): 1106 case IP_VERSION(3, 1, 5): 1107 case IP_VERSION(3, 1, 6): 1108 case IP_VERSION(3, 2, 0): 1109 case IP_VERSION(3, 2, 1): 1110 case IP_VERSION(3, 5, 0): 1111 case IP_VERSION(3, 5, 1): 1112 case IP_VERSION(3, 6, 0): 1113 case IP_VERSION(4, 0, 1): 1114 case IP_VERSION(4, 2, 0): 1115 case IP_VERSION(4, 2, 1): 1116 return 0; 1117 default: 1118 break; 1119 } 1120 drm_err(adev_to_drm(adev), "Unsupported ASIC type: 0x%X\n", adev->asic_type); 1121 return -EINVAL; 1122 } 1123 1124 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1125 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); 1126 return 0; 1127 } 1128 1129 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, AMDGPU_UCODE_REQUIRED, 1130 "%s", fw_name_dmcu); 1131 if (r == -ENODEV) { 1132 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ 1133 drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); 1134 adev->dm.fw_dmcu = NULL; 1135 return 0; 1136 } 1137 if (r) { 1138 drm_err(adev_to_drm(adev), "amdgpu_dm: Can't validate firmware \"%s\"\n", 1139 fw_name_dmcu); 1140 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1141 return r; 1142 } 1143 1144 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; 1145 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; 1146 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; 1147 adev->firmware.fw_size += 1148 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1149 1150 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; 1151 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; 1152 adev->firmware.fw_size += 1153 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE); 1154 1155 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); 1156 1157 drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); 1158 1159 return 0; 1160 } 1161 1162 static int dm_sw_init(struct amdgpu_ip_block *ip_block) 1163 { 1164 struct amdgpu_device *adev = ip_block->adev; 1165 int r; 1166 1167 adev->dm.cgs_device = amdgpu_cgs_create_device(adev); 1168 1169 if (!adev->dm.cgs_device) { 1170 drm_err(adev_to_drm(adev), "failed to create cgs device.\n"); 1171 return -EINVAL; 1172 } 1173 1174 /* Moved from dm init since we need to use allocations for storing bounding box data */ 1175 INIT_LIST_HEAD(&adev->dm.da_list); 1176 1177 r = dm_dmub_sw_init(adev); 1178 if (r) 1179 return r; 1180 1181 return load_dmcu_fw(adev); 1182 } 1183 1184 static int dm_sw_fini(struct amdgpu_ip_block *ip_block) 1185 { 1186 struct amdgpu_device *adev = ip_block->adev; 1187 struct dal_allocation *da; 1188 1189 list_for_each_entry(da, &adev->dm.da_list, list) { 1190 if (adev->dm.bb_from_dmub == (void *) da->cpu_ptr) { 1191 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); 1192 list_del(&da->list); 1193 kfree(da); 1194 adev->dm.bb_from_dmub = NULL; 1195 break; 1196 } 1197 } 1198 1199 1200 kfree(adev->dm.dmub_fb_info); 1201 adev->dm.dmub_fb_info = NULL; 1202 1203 if (adev->dm.dmub_srv) { 1204 dmub_srv_destroy(adev->dm.dmub_srv); 1205 kfree(adev->dm.dmub_srv); 1206 adev->dm.dmub_srv = NULL; 1207 } 1208 1209 amdgpu_ucode_release(&adev->dm.dmub_fw); 1210 amdgpu_ucode_release(&adev->dm.fw_dmcu); 1211 1212 return 0; 1213 } 1214 1215 1216 static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) 1217 { 1218 struct dm_boot_time_crc_info *bootcrc_info = NULL; 1219 struct dmub_srv *dmub = NULL; 1220 union dmub_fw_boot_options option = {0}; 1221 int ret = 0; 1222 const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ 1223 1224 if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || 1225 !adev->dm.dc->ctx->dmub_srv) { 1226 return; 1227 } 1228 1229 dmub = adev->dm.dc->ctx->dmub_srv->dmub; 1230 bootcrc_info = &adev->dm.boot_time_crc_info; 1231 1232 if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { 1233 drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); 1234 return; 1235 } 1236 1237 option = dmub->hw_funcs.get_fw_boot_option(dmub); 1238 1239 /* Return if boot time CRC is not enabled */ 1240 if (option.bits.bootcrc_en_at_S0i3 == 0) 1241 return; 1242 1243 /* Create a buffer for boot time CRC */ 1244 ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, 1245 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, 1246 &bootcrc_info->bo_ptr, 1247 &bootcrc_info->gpu_addr, 1248 &bootcrc_info->cpu_addr); 1249 1250 if (ret) { 1251 drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); 1252 } else { 1253 bootcrc_info->size = fb_size; 1254 1255 drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", 1256 bootcrc_info->gpu_addr, bootcrc_info->size); 1257 1258 /* Send the buffer info to DMUB */ 1259 dc_dmub_srv_boot_time_crc_init(adev->dm.dc, 1260 bootcrc_info->gpu_addr, bootcrc_info->size); 1261 } 1262 } 1263 1264 static int dm_late_init(struct amdgpu_ip_block *ip_block) 1265 { 1266 struct amdgpu_device *adev = ip_block->adev; 1267 1268 struct dmcu_iram_parameters params; 1269 unsigned int linear_lut[16]; 1270 int i; 1271 struct dmcu *dmcu = NULL; 1272 1273 dmcu = adev->dm.dc->res_pool->dmcu; 1274 1275 /* Init the boot time CRC (skip in resume) */ 1276 if ((adev->in_suspend == 0) && 1277 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) 1278 amdgpu_dm_boot_time_crc_init(adev); 1279 1280 for (i = 0; i < 16; i++) 1281 linear_lut[i] = 0xFFFF * i / 15; 1282 1283 params.set = 0; 1284 params.backlight_ramping_override = false; 1285 params.backlight_ramping_start = 0xCCCC; 1286 params.backlight_ramping_reduction = 0xCCCCCCCC; 1287 params.backlight_lut_array_size = 16; 1288 params.backlight_lut_array = linear_lut; 1289 1290 /* Min backlight level after ABM reduction, Don't allow below 1% 1291 * 0xFFFF x 0.01 = 0x28F 1292 */ 1293 params.min_abm_backlight = 0x28F; 1294 /* In the case where abm is implemented on dmcub, 1295 * dmcu object will be null. 1296 * ABM 2.4 and up are implemented on dmcub. 1297 */ 1298 if (dmcu) { 1299 if (!dmcu_load_iram(dmcu, params)) 1300 return -EINVAL; 1301 } else if (adev->dm.dc->ctx->dmub_srv) { 1302 struct dc_link *edp_links[MAX_NUM_EDP]; 1303 int edp_num; 1304 1305 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num); 1306 for (i = 0; i < edp_num; i++) { 1307 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) 1308 return -EINVAL; 1309 } 1310 } 1311 1312 return amdgpu_dm_detect_mst_link_for_all_connectors(adev_to_drm(adev)); 1313 } 1314 1315 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) 1316 { 1317 u8 buf[UUID_SIZE]; 1318 guid_t guid; 1319 int ret; 1320 1321 mutex_lock(&mgr->lock); 1322 if (!mgr->mst_primary) 1323 goto out_fail; 1324 1325 if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { 1326 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1327 goto out_fail; 1328 } 1329 1330 ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, 1331 DP_MST_EN | 1332 DP_UP_REQ_EN | 1333 DP_UPSTREAM_IS_SRC); 1334 if (ret < 0) { 1335 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); 1336 goto out_fail; 1337 } 1338 1339 /* Some hubs forget their guids after they resume */ 1340 ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); 1341 if (ret != sizeof(buf)) { 1342 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); 1343 goto out_fail; 1344 } 1345 1346 import_guid(&guid, buf); 1347 1348 if (guid_is_null(&guid)) { 1349 guid_gen(&guid); 1350 export_guid(buf, &guid); 1351 1352 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); 1353 1354 if (ret != sizeof(buf)) { 1355 drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); 1356 goto out_fail; 1357 } 1358 } 1359 1360 guid_copy(&mgr->mst_primary->guid, &guid); 1361 1362 out_fail: 1363 mutex_unlock(&mgr->lock); 1364 } 1365 1366 static void s3_handle_mst(struct drm_device *dev, bool suspend) 1367 { 1368 struct amdgpu_dm_connector *aconnector; 1369 struct drm_connector *connector; 1370 struct drm_connector_list_iter iter; 1371 struct drm_dp_mst_topology_mgr *mgr; 1372 1373 drm_connector_list_iter_begin(dev, &iter); 1374 drm_for_each_connector_iter(connector, &iter) { 1375 1376 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 1377 continue; 1378 1379 aconnector = to_amdgpu_dm_connector(connector); 1380 if (aconnector->dc_link->type != dc_connection_mst_branch || 1381 aconnector->mst_root) 1382 continue; 1383 1384 mgr = &aconnector->mst_mgr; 1385 1386 if (suspend) { 1387 drm_dp_mst_topology_mgr_suspend(mgr); 1388 } else { 1389 /* if extended timeout is supported in hardware, 1390 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer 1391 * CTS 4.2.1.1 regression introduced by CTS specs requirement update. 1392 */ 1393 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD); 1394 if (!dp_is_lttpr_present(aconnector->dc_link)) 1395 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); 1396 1397 /* TODO: move resume_mst_branch_status() into drm mst resume again 1398 * once topology probing work is pulled out from mst resume into mst 1399 * resume 2nd step. mst resume 2nd step should be called after old 1400 * state getting restored (i.e. drm_atomic_helper_resume()). 1401 */ 1402 resume_mst_branch_status(mgr); 1403 } 1404 } 1405 drm_connector_list_iter_end(&iter); 1406 } 1407 1408 STATIC_IFN_KUNIT int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) 1409 { 1410 int ret = 0; 1411 1412 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends 1413 * on window driver dc implementation. 1414 * For Navi1x, clock settings of dcn watermarks are fixed. the settings 1415 * should be passed to smu during boot up and resume from s3. 1416 * boot up: dc calculate dcn watermark clock settings within dc_create, 1417 * dcn20_resource_construct 1418 * then call pplib functions below to pass the settings to smu: 1419 * smu_set_watermarks_for_clock_ranges 1420 * smu_set_watermarks_table 1421 * navi10_set_watermarks_table 1422 * smu_write_watermarks_table 1423 * 1424 * For Renoir, clock settings of dcn watermark are also fixed values. 1425 * dc has implemented different flow for window driver: 1426 * dc_hardware_init / dc_set_power_state 1427 * dcn10_init_hw 1428 * notify_wm_ranges 1429 * set_wm_ranges 1430 * -- Linux 1431 * smu_set_watermarks_for_clock_ranges 1432 * renoir_set_watermarks_table 1433 * smu_write_watermarks_table 1434 * 1435 * For Linux, 1436 * dc_hardware_init -> amdgpu_dm_init 1437 * dc_set_power_state --> dm_resume 1438 * 1439 * therefore, this function apply to navi10/12/14 but not Renoir 1440 * * 1441 */ 1442 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1443 case IP_VERSION(2, 0, 2): 1444 case IP_VERSION(2, 0, 0): 1445 break; 1446 default: 1447 return 0; 1448 } 1449 1450 ret = amdgpu_dpm_write_watermarks_table(adev); 1451 if (ret) { 1452 drm_err(adev_to_drm(adev), "Failed to update WMTABLE!\n"); 1453 return ret; 1454 } 1455 1456 return 0; 1457 } 1458 EXPORT_IF_KUNIT(amdgpu_dm_smu_write_watermarks_table); 1459 1460 static int dm_oem_i2c_hw_init(struct amdgpu_device *adev) 1461 { 1462 struct amdgpu_display_manager *dm = &adev->dm; 1463 struct amdgpu_i2c_adapter *oem_i2c; 1464 struct ddc_service *oem_ddc_service; 1465 int r; 1466 1467 oem_ddc_service = dc_get_oem_i2c_device(adev->dm.dc); 1468 if (oem_ddc_service) { 1469 oem_i2c = amdgpu_dm_create_i2c(oem_ddc_service, true); 1470 if (!oem_i2c) { 1471 drm_info(adev_to_drm(adev), "Failed to create oem i2c adapter data\n"); 1472 return -ENOMEM; 1473 } 1474 1475 r = devm_i2c_add_adapter(adev->dev, &oem_i2c->base); 1476 if (r) { 1477 drm_info(adev_to_drm(adev), "Failed to register oem i2c\n"); 1478 kfree(oem_i2c); 1479 return r; 1480 } 1481 dm->oem_i2c = oem_i2c; 1482 } 1483 1484 return 0; 1485 } 1486 1487 /** 1488 * dm_hw_init() - Initialize DC device 1489 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1490 * 1491 * Initialize the &struct amdgpu_display_manager device. This involves calling 1492 * the initializers of each DM component, then populating the struct with them. 1493 * 1494 * Although the function implies hardware initialization, both hardware and 1495 * software are initialized here. Splitting them out to their relevant init 1496 * hooks is a future TODO item. 1497 * 1498 * Some notable things that are initialized here: 1499 * 1500 * - Display Core, both software and hardware 1501 * - DC modules that we need (freesync and color management) 1502 * - DRM software states 1503 * - Interrupt sources and handlers 1504 * - Vblank support 1505 * - Debug FS entries, if enabled 1506 */ 1507 static int dm_hw_init(struct amdgpu_ip_block *ip_block) 1508 { 1509 struct amdgpu_device *adev = ip_block->adev; 1510 int r; 1511 1512 adev->dm.i2c_devres_group = devres_open_group(adev->dev, NULL, GFP_KERNEL); 1513 if (!adev->dm.i2c_devres_group) 1514 return -ENOMEM; 1515 1516 /* Create DAL display manager */ 1517 r = amdgpu_dm_init(adev); 1518 if (r) 1519 goto err_release_i2c; 1520 amdgpu_dm_hpd_init(adev); 1521 1522 r = dm_oem_i2c_hw_init(adev); 1523 if (r) 1524 drm_info(adev_to_drm(adev), "Failed to add OEM i2c bus\n"); 1525 1526 devres_close_group(adev->dev, adev->dm.i2c_devres_group); 1527 return 0; 1528 1529 err_release_i2c: 1530 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1531 return r; 1532 } 1533 1534 /** 1535 * dm_hw_fini() - Teardown DC device 1536 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1537 * 1538 * Teardown components within &struct amdgpu_display_manager that require 1539 * cleanup. This involves cleaning up the DRM device, DC, and any modules that 1540 * were loaded. Also flush IRQ workqueues and disable them. 1541 */ 1542 static int dm_hw_fini(struct amdgpu_ip_block *ip_block) 1543 { 1544 struct amdgpu_device *adev = ip_block->adev; 1545 1546 if (adev->dm.i2c_devres_group) 1547 devres_release_group(adev->dev, adev->dm.i2c_devres_group); 1548 1549 amdgpu_dm_hpd_fini(adev); 1550 1551 amdgpu_dm_fini(adev); 1552 return 0; 1553 } 1554 1555 1556 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, 1557 struct dc_state *state, bool enable) 1558 { 1559 enum dc_irq_source irq_source; 1560 struct amdgpu_crtc *acrtc; 1561 int rc = -EBUSY; 1562 int i = 0; 1563 1564 for (i = 0; i < state->stream_count; i++) { 1565 acrtc = amdgpu_dm_get_crtc_by_otg_inst( 1566 adev, state->stream_status[i].primary_otg_inst); 1567 1568 if (acrtc && state->stream_status[i].plane_count != 0 && 1569 amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 1570 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; 1571 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; 1572 if (rc) 1573 drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n", 1574 enable ? "enable" : "disable"); 1575 1576 if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { 1577 if (enable) { 1578 if (amdgpu_dm_crtc_vrr_active( 1579 to_dm_crtc_state(acrtc->base.state))) 1580 rc = amdgpu_dm_crtc_set_vupdate_irq( 1581 &acrtc->base, true); 1582 } else 1583 rc = amdgpu_dm_crtc_set_vupdate_irq( 1584 &acrtc->base, false); 1585 1586 if (rc) 1587 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1588 enable ? "en" : "dis"); 1589 } 1590 1591 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst; 1592 /* During gpu-reset we disable and then enable vblank irq, so 1593 * don't use amdgpu_irq_get/put() to avoid refcount change. 1594 */ 1595 if (!dc_interrupt_set(adev->dm.dc, irq_source, enable)) 1596 drm_warn(adev_to_drm(adev), "Failed to %sable vblank interrupt\n", enable ? "en" : "dis"); 1597 1598 } else if (acrtc && state->stream_status[i].plane_count != 0) { 1599 /* DCN only needs to toggle VUPDATE_NO_LOCK */ 1600 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, enable); 1601 if (rc) 1602 drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", 1603 enable ? "en" : "dis"); 1604 } 1605 } 1606 1607 } 1608 1609 DEFINE_FREE(state_release, struct dc_state *, if (_T) dc_state_release(_T)) 1610 1611 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) 1612 { 1613 struct dc_state *context __free(state_release) = NULL; 1614 int i; 1615 struct dc_stream_state *del_streams[MAX_PIPES]; 1616 int del_streams_count = 0; 1617 struct dc_commit_streams_params params = {}; 1618 1619 memset(del_streams, 0, sizeof(del_streams)); 1620 1621 context = dc_state_create_current_copy(dc); 1622 if (context == NULL) 1623 return DC_ERROR_UNEXPECTED; 1624 1625 /* First remove from context all streams */ 1626 for (i = 0; i < context->stream_count; i++) { 1627 struct dc_stream_state *stream = context->streams[i]; 1628 1629 del_streams[del_streams_count++] = stream; 1630 } 1631 1632 /* Remove all planes for removed streams and then remove the streams */ 1633 for (i = 0; i < del_streams_count; i++) { 1634 enum dc_status res; 1635 1636 if (!dc_state_rem_all_planes_for_stream(dc, del_streams[i], context)) 1637 return DC_FAIL_DETACH_SURFACES; 1638 1639 res = dc_state_remove_stream(dc, context, del_streams[i]); 1640 if (res != DC_OK) 1641 return res; 1642 } 1643 1644 params.streams = context->streams; 1645 params.stream_count = context->stream_count; 1646 1647 return dc_commit_streams(dc, ¶ms); 1648 } 1649 1650 static int dm_cache_state(struct amdgpu_device *adev) 1651 { 1652 int r; 1653 1654 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); 1655 if (IS_ERR(adev->dm.cached_state)) { 1656 r = PTR_ERR(adev->dm.cached_state); 1657 adev->dm.cached_state = NULL; 1658 } 1659 1660 return adev->dm.cached_state ? 0 : r; 1661 } 1662 1663 static void dm_destroy_cached_state(struct amdgpu_device *adev) 1664 { 1665 struct amdgpu_display_manager *dm = &adev->dm; 1666 struct drm_device *ddev = adev_to_drm(adev); 1667 struct dm_plane_state *dm_new_plane_state; 1668 struct drm_plane_state *new_plane_state; 1669 struct dm_crtc_state *dm_new_crtc_state; 1670 struct drm_crtc_state *new_crtc_state; 1671 struct drm_plane *plane; 1672 struct drm_crtc *crtc; 1673 int i; 1674 1675 if (!dm->cached_state) 1676 return; 1677 1678 /* Force mode set in atomic commit */ 1679 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1680 new_crtc_state->active_changed = true; 1681 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1682 reset_freesync_config_for_crtc(dm_new_crtc_state); 1683 } 1684 1685 /* 1686 * atomic_check is expected to create the dc states. We need to release 1687 * them here, since they were duplicated as part of the suspend 1688 * procedure. 1689 */ 1690 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { 1691 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 1692 if (dm_new_crtc_state->stream) { 1693 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); 1694 dc_stream_release(dm_new_crtc_state->stream); 1695 dm_new_crtc_state->stream = NULL; 1696 } 1697 dm_new_crtc_state->base.color_mgmt_changed = true; 1698 } 1699 1700 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { 1701 dm_new_plane_state = to_dm_plane_state(new_plane_state); 1702 if (dm_new_plane_state->dc_state) { 1703 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); 1704 dc_plane_state_release(dm_new_plane_state->dc_state); 1705 dm_new_plane_state->dc_state = NULL; 1706 } 1707 } 1708 1709 drm_atomic_helper_resume(ddev, dm->cached_state); 1710 1711 dm->cached_state = NULL; 1712 } 1713 1714 static int dm_suspend(struct amdgpu_ip_block *ip_block) 1715 { 1716 struct amdgpu_device *adev = ip_block->adev; 1717 struct amdgpu_display_manager *dm = &adev->dm; 1718 1719 if (amdgpu_in_reset(adev)) { 1720 enum dc_status res; 1721 1722 /* Quiesce ISM workers before taking dc_lock (workers take 1723 * dc_lock themselves; syncing under it would deadlock). 1724 */ 1725 amdgpu_dm_ism_disable(dm); 1726 1727 mutex_lock(&dm->dc_lock); 1728 1729 amdgpu_dm_ism_force_full_power(dm); 1730 dc_allow_idle_optimizations(adev->dm.dc, false); 1731 1732 dm->cached_dc_state = dc_state_create_copy(dm->dc->current_state); 1733 1734 if (dm->cached_dc_state) 1735 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false); 1736 1737 res = amdgpu_dm_commit_zero_streams(dm->dc); 1738 if (res != DC_OK) { 1739 drm_err(adev_to_drm(adev), "Failed to commit zero streams: %d\n", res); 1740 return -EINVAL; 1741 } 1742 1743 amdgpu_dm_irq_suspend(adev); 1744 1745 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1746 1747 return 0; 1748 } 1749 1750 if (!adev->dm.cached_state) { 1751 int r = dm_cache_state(adev); 1752 1753 if (r) 1754 return r; 1755 } 1756 1757 amdgpu_dm_s3_handle_hdmi_cec(adev_to_drm(adev), true); 1758 1759 s3_handle_mst(adev_to_drm(adev), true); 1760 1761 amdgpu_dm_irq_suspend(adev); 1762 1763 /* 1764 * Quiesce ISM workers before taking dc_lock (workers take dc_lock 1765 * themselves; syncing under it would deadlock). 1766 */ 1767 amdgpu_dm_ism_disable(dm); 1768 scoped_guard(mutex, &dm->dc_lock) 1769 amdgpu_dm_ism_force_full_power(dm); 1770 1771 amdgpu_dm_hpd_rx_irq_work_suspend(dm); 1772 1773 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); 1774 1775 if (dm->dc->caps.ips_support && adev->in_s0ix) 1776 dc_allow_idle_optimizations(dm->dc, true); 1777 1778 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3); 1779 1780 return 0; 1781 } 1782 1783 void amdgpu_dm_emulated_link_detect(struct dc_link *link) 1784 { 1785 struct dc_sink_init_data sink_init_data = { 0 }; 1786 struct display_sink_capability sink_caps = { 0 }; 1787 enum dc_edid_status edid_status; 1788 struct dc_context *dc_ctx = link->ctx; 1789 struct drm_device *dev = adev_to_drm(dc_ctx->driver_context); 1790 struct dc_sink *sink = NULL; 1791 struct dc_sink *prev_sink = NULL; 1792 1793 link->type = dc_connection_none; 1794 prev_sink = link->local_sink; 1795 1796 if (prev_sink) 1797 dc_sink_release(prev_sink); 1798 1799 switch (link->connector_signal) { 1800 case SIGNAL_TYPE_HDMI_TYPE_A: { 1801 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1802 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1803 break; 1804 } 1805 1806 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1807 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1808 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1809 break; 1810 } 1811 1812 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1813 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1814 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1815 break; 1816 } 1817 1818 case SIGNAL_TYPE_LVDS: { 1819 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1820 sink_caps.signal = SIGNAL_TYPE_LVDS; 1821 break; 1822 } 1823 1824 case SIGNAL_TYPE_EDP: { 1825 sink_caps.transaction_type = 1826 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1827 sink_caps.signal = SIGNAL_TYPE_EDP; 1828 break; 1829 } 1830 1831 case SIGNAL_TYPE_DISPLAY_PORT: { 1832 sink_caps.transaction_type = 1833 DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1834 sink_caps.signal = SIGNAL_TYPE_VIRTUAL; 1835 break; 1836 } 1837 1838 default: 1839 drm_err(dev, "Invalid connector type! signal:%d\n", 1840 link->connector_signal); 1841 return; 1842 } 1843 1844 sink_init_data.link = link; 1845 sink_init_data.sink_signal = sink_caps.signal; 1846 1847 sink = dc_sink_create(&sink_init_data); 1848 if (!sink) { 1849 drm_err(dev, "Failed to create sink!\n"); 1850 return; 1851 } 1852 1853 /* dc_sink_create returns a new reference */ 1854 link->local_sink = sink; 1855 1856 edid_status = dm_helpers_read_local_edid( 1857 link->ctx, 1858 link, 1859 sink); 1860 1861 if (edid_status != EDID_OK) 1862 drm_err(dev, "Failed to read EDID\n"); 1863 1864 } 1865 1866 static void dm_gpureset_commit_state(struct dc_state *dc_state, 1867 struct amdgpu_display_manager *dm) 1868 { 1869 struct { 1870 struct dc_surface_update surface_updates[MAX_SURFACES]; 1871 struct dc_plane_info plane_infos[MAX_SURFACES]; 1872 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 1873 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 1874 struct dc_stream_update stream_update; 1875 } *bundle __free(kfree); 1876 int k, m; 1877 1878 bundle = kzalloc_obj(*bundle); 1879 1880 if (!bundle) { 1881 drm_err(dm->ddev, "Failed to allocate update bundle\n"); 1882 return; 1883 } 1884 1885 for (k = 0; k < dc_state->stream_count; k++) { 1886 bundle->stream_update.stream = dc_state->streams[k]; 1887 1888 for (m = 0; m < dc_state->stream_status[k].plane_count; m++) { 1889 bundle->surface_updates[m].surface = 1890 dc_state->stream_status[k].plane_states[m]; 1891 bundle->surface_updates[m].surface->force_full_update = 1892 true; 1893 } 1894 1895 update_planes_and_stream_adapter(dm->dc, 1896 UPDATE_TYPE_FULL, 1897 dc_state->stream_status[k].plane_count, 1898 dc_state->streams[k], 1899 &bundle->stream_update, 1900 bundle->surface_updates); 1901 } 1902 } 1903 1904 void amdgpu_dm_apply_delay_after_dpcd_poweroff(struct amdgpu_device *adev, 1905 struct dc_sink *sink) 1906 { 1907 struct dc_panel_patch *ppatch = NULL; 1908 1909 if (!sink) 1910 return; 1911 1912 ppatch = &sink->edid_caps.panel_patch; 1913 if (ppatch->wait_after_dpcd_poweroff_ms) { 1914 msleep(ppatch->wait_after_dpcd_poweroff_ms); 1915 drm_dbg_driver(adev_to_drm(adev), 1916 "%s: adding a %ds delay as w/a for panel\n", 1917 __func__, 1918 ppatch->wait_after_dpcd_poweroff_ms / 1000); 1919 } 1920 } 1921 EXPORT_IF_KUNIT(amdgpu_dm_apply_delay_after_dpcd_poweroff); 1922 1923 /** 1924 * amdgpu_dm_dump_links_and_sinks - Debug dump of all DC links and their sinks 1925 * @adev: amdgpu device pointer 1926 * 1927 * Iterates through all DC links and dumps information about local and remote 1928 * (MST) sinks. Should be called after connector detection is complete to see 1929 * the final state of all links. 1930 */ 1931 static void amdgpu_dm_dump_links_and_sinks(struct amdgpu_device *adev) 1932 { 1933 struct dc *dc = adev->dm.dc; 1934 struct drm_device *dev = adev_to_drm(adev); 1935 int li; 1936 1937 if (!dc) 1938 return; 1939 1940 for (li = 0; li < dc->link_count; li++) { 1941 struct dc_link *l = dc->links[li]; 1942 const char *name = NULL; 1943 int rs; 1944 1945 if (!l) 1946 continue; 1947 if (l->local_sink && l->local_sink->edid_caps.display_name[0]) 1948 name = l->local_sink->edid_caps.display_name; 1949 else 1950 name = "n/a"; 1951 1952 drm_dbg_kms(dev, 1953 "LINK_DUMP[%d]: local_sink=%p type=%d sink_signal=%d sink_count=%u edid_name=%s mst_capable=%d mst_alloc_streams=%d\n", 1954 li, 1955 l->local_sink, 1956 l->type, 1957 l->local_sink ? l->local_sink->sink_signal : SIGNAL_TYPE_NONE, 1958 l->sink_count, 1959 name, 1960 l->dpcd_caps.is_mst_capable, 1961 l->mst_stream_alloc_table.stream_count); 1962 1963 /* Dump remote (MST) sinks if any */ 1964 for (rs = 0; rs < l->sink_count; rs++) { 1965 struct dc_sink *rsink = l->remote_sinks[rs]; 1966 const char *rname = NULL; 1967 1968 if (!rsink) 1969 continue; 1970 if (rsink->edid_caps.display_name[0]) 1971 rname = rsink->edid_caps.display_name; 1972 else 1973 rname = "n/a"; 1974 drm_dbg_kms(dev, 1975 " REMOTE_SINK[%d:%d]: sink=%p signal=%d edid_name=%s\n", 1976 li, rs, 1977 rsink, 1978 rsink->sink_signal, 1979 rname); 1980 } 1981 } 1982 } 1983 1984 static int dm_resume(struct amdgpu_ip_block *ip_block) 1985 { 1986 struct amdgpu_device *adev = ip_block->adev; 1987 struct drm_device *ddev = adev_to_drm(adev); 1988 struct amdgpu_display_manager *dm = &adev->dm; 1989 struct amdgpu_dm_connector *aconnector; 1990 struct drm_connector *connector; 1991 struct drm_connector_list_iter iter; 1992 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); 1993 enum dc_connection_type new_connection_type = dc_connection_none; 1994 struct dc_state *dc_state; 1995 int i, r, j; 1996 struct dc_commit_streams_params commit_params = {}; 1997 1998 if (dm->dc->caps.ips_support) { 1999 if (!amdgpu_in_reset(adev)) 2000 mutex_lock(&dm->dc_lock); 2001 2002 /* Need to set POWER_STATE_D0 first or it will not execute 2003 * idle_power_optimizations command to DMUB. 2004 */ 2005 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2006 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); 2007 2008 if (!amdgpu_in_reset(adev)) 2009 mutex_unlock(&dm->dc_lock); 2010 } 2011 2012 if (amdgpu_in_reset(adev)) { 2013 dc_state = dm->cached_dc_state; 2014 2015 /* 2016 * The dc->current_state is backed up into dm->cached_dc_state 2017 * before we commit 0 streams. 2018 * 2019 * DC will clear link encoder assignments on the real state 2020 * but the changes won't propagate over to the copy we made 2021 * before the 0 streams commit. 2022 * 2023 * DC expects that link encoder assignments are *not* valid 2024 * when committing a state, so as a workaround we can copy 2025 * off of the current state. 2026 * 2027 * We lose the previous assignments, but we had already 2028 * commit 0 streams anyway. 2029 */ 2030 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); 2031 2032 r = dm_dmub_hw_init(adev); 2033 if (r) { 2034 drm_err(adev_to_drm(adev), "DMUB interface failed to initialize: status=%d\n", r); 2035 return r; 2036 } 2037 2038 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2039 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2040 2041 dc_resume(dm->dc); 2042 2043 amdgpu_dm_ism_enable(dm); 2044 amdgpu_dm_irq_resume_early(adev); 2045 2046 for (i = 0; i < dc_state->stream_count; i++) { 2047 dc_state->streams[i]->mode_changed = true; 2048 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { 2049 dc_pipe_update_bits_set_full(&dc_state->stream_status[i].plane_states[j]->update_bits); 2050 } 2051 } 2052 2053 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2054 amdgpu_dm_outbox_init(adev); 2055 dc_enable_dmub_outbox(adev->dm.dc); 2056 } 2057 2058 commit_params.streams = dc_state->streams; 2059 commit_params.stream_count = dc_state->stream_count; 2060 dc_exit_ips_for_hw_access(dm->dc); 2061 WARN_ON(!dc_commit_streams(dm->dc, &commit_params)); 2062 2063 dm_gpureset_commit_state(dm->cached_dc_state, dm); 2064 2065 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true); 2066 2067 dc_state_release(dm->cached_dc_state); 2068 dm->cached_dc_state = NULL; 2069 2070 amdgpu_dm_irq_resume_late(adev); 2071 2072 mutex_unlock(&dm->dc_lock); 2073 2074 /* set the backlight after a reset */ 2075 for (i = 0; i < dm->num_of_edps; i++) { 2076 if (dm->backlight_dev[i]) 2077 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 2078 } 2079 2080 return 0; 2081 } 2082 /* Recreate dc_state - DC invalidates it when setting power state to S3. */ 2083 dc_state_release(dm_state->context); 2084 dm_state->context = dc_state_create(dm->dc, NULL); 2085 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ 2086 2087 /* Before powering on DC we need to re-initialize DMUB. */ 2088 dm_dmub_hw_resume(adev); 2089 2090 /* Re-enable outbox interrupts for DPIA. */ 2091 if (dc_is_dmub_outbox_supported(adev->dm.dc)) { 2092 amdgpu_dm_outbox_init(adev); 2093 dc_enable_dmub_outbox(adev->dm.dc); 2094 } 2095 2096 /* power on hardware */ 2097 dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); 2098 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); 2099 2100 /* program HPD filter */ 2101 dc_resume(dm->dc); 2102 2103 scoped_guard(mutex, &dm->dc_lock) 2104 amdgpu_dm_ism_enable(dm); 2105 2106 /* 2107 * early enable HPD Rx IRQ, should be done before set mode as short 2108 * pulse interrupts are used for MST 2109 */ 2110 amdgpu_dm_irq_resume_early(adev); 2111 2112 amdgpu_dm_s3_handle_hdmi_cec(ddev, false); 2113 2114 /* On resume we need to rewrite the MSTM control bits to enable MST*/ 2115 s3_handle_mst(ddev, false); 2116 2117 /* Do detection*/ 2118 drm_connector_list_iter_begin(ddev, &iter); 2119 drm_for_each_connector_iter(connector, &iter) { 2120 bool ret; 2121 2122 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2123 continue; 2124 2125 aconnector = to_amdgpu_dm_connector(connector); 2126 2127 if (!aconnector->dc_link) 2128 continue; 2129 2130 /* 2131 * this is the case when traversing through already created end sink 2132 * MST connectors, should be skipped 2133 */ 2134 if (aconnector->mst_root) 2135 continue; 2136 2137 /* Skip eDP detection, when there is no sink present */ 2138 if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && 2139 !aconnector->dc_link->edp_sink_present) 2140 continue; 2141 2142 guard(mutex)(&aconnector->hpd_lock); 2143 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 2144 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2145 2146 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2147 amdgpu_dm_emulated_link_detect(aconnector->dc_link); 2148 } else { 2149 guard(mutex)(&dm->dc_lock); 2150 dc_exit_ips_for_hw_access(dm->dc); 2151 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_RESUMEFROMS3S4); 2152 if (ret) { 2153 /* w/a delay for certain panels */ 2154 amdgpu_dm_apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 2155 } 2156 } 2157 2158 if (aconnector->fake_enable && aconnector->dc_link->local_sink) 2159 aconnector->fake_enable = false; 2160 2161 if (aconnector->dc_sink) 2162 dc_sink_release(aconnector->dc_sink); 2163 aconnector->dc_sink = NULL; 2164 amdgpu_dm_update_connector_after_detect(aconnector); 2165 } 2166 drm_connector_list_iter_end(&iter); 2167 2168 dm_destroy_cached_state(adev); 2169 2170 /* Do mst topology probing after resuming cached state*/ 2171 drm_connector_list_iter_begin(ddev, &iter); 2172 drm_for_each_connector_iter(connector, &iter) { 2173 bool init = false; 2174 2175 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 2176 continue; 2177 2178 aconnector = to_amdgpu_dm_connector(connector); 2179 if (aconnector->dc_link->type != dc_connection_mst_branch || 2180 aconnector->mst_root) 2181 continue; 2182 2183 scoped_guard(mutex, &aconnector->mst_mgr.lock) { 2184 init = !aconnector->mst_mgr.mst_primary; 2185 } 2186 if (init) 2187 dm_helpers_dp_mst_start_top_mgr(aconnector->dc_link->ctx, 2188 aconnector->dc_link, false); 2189 else 2190 drm_dp_mst_topology_queue_probe(&aconnector->mst_mgr); 2191 } 2192 drm_connector_list_iter_end(&iter); 2193 2194 /* Debug dump: list all DC links and their associated sinks after detection 2195 * is complete for all connectors. This provides a comprehensive view of the 2196 * final state without repeating the dump for each connector. 2197 */ 2198 amdgpu_dm_dump_links_and_sinks(adev); 2199 2200 amdgpu_dm_irq_resume_late(adev); 2201 2202 amdgpu_dm_smu_write_watermarks_table(adev); 2203 2204 drm_kms_helper_hotplug_event(ddev); 2205 2206 return 0; 2207 } 2208 2209 /** 2210 * DOC: DM Lifecycle 2211 * 2212 * DM (and consequently DC) is registered in the amdgpu base driver as a IP 2213 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to 2214 * the base driver's device list to be initialized and torn down accordingly. 2215 * 2216 * The functions to do so are provided as hooks in &struct amd_ip_funcs. 2217 */ 2218 2219 static const struct amd_ip_funcs amdgpu_dm_funcs = { 2220 .name = "dm", 2221 .early_init = dm_early_init, 2222 .late_init = dm_late_init, 2223 .sw_init = dm_sw_init, 2224 .sw_fini = dm_sw_fini, 2225 .early_fini = amdgpu_dm_early_fini, 2226 .hw_init = dm_hw_init, 2227 .hw_fini = dm_hw_fini, 2228 .suspend = dm_suspend, 2229 .resume = dm_resume, 2230 .is_idle = dm_is_idle, 2231 .wait_for_idle = dm_wait_for_idle, 2232 .soft_reset = dm_soft_reset, 2233 .set_clockgating_state = dm_set_clockgating_state, 2234 .set_powergating_state = dm_set_powergating_state, 2235 }; 2236 2237 const struct amdgpu_ip_block_version dm_ip_block = { 2238 .type = AMD_IP_BLOCK_TYPE_DCE, 2239 .major = 1, 2240 .minor = 0, 2241 .rev = 0, 2242 .funcs = &amdgpu_dm_funcs, 2243 }; 2244 2245 2246 /** 2247 * DOC: atomic 2248 * 2249 * *WIP* 2250 */ 2251 2252 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { 2253 .fb_create = amdgpu_display_user_framebuffer_create, 2254 .get_format_info = amdgpu_dm_plane_get_format_info, 2255 .atomic_check = amdgpu_dm_atomic_check, 2256 .atomic_commit = drm_atomic_helper_commit, 2257 }; 2258 2259 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { 2260 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, 2261 .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, 2262 }; 2263 2264 /* 2265 * Acquires the lock for the atomic state object and returns 2266 * the new atomic state. 2267 * 2268 * This should only be called during atomic check. 2269 */ 2270 int dm_atomic_get_state(struct drm_atomic_commit *state, 2271 struct dm_atomic_state **dm_state) 2272 { 2273 struct drm_device *dev = state->dev; 2274 struct amdgpu_device *adev = drm_to_adev(dev); 2275 struct amdgpu_display_manager *dm = &adev->dm; 2276 struct drm_private_state *priv_state; 2277 2278 if (*dm_state) 2279 return 0; 2280 2281 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); 2282 if (IS_ERR(priv_state)) 2283 return PTR_ERR(priv_state); 2284 2285 *dm_state = to_dm_atomic_state(priv_state); 2286 2287 return 0; 2288 } 2289 2290 STATIC_IFN_KUNIT struct dm_atomic_state * 2291 dm_atomic_get_new_state(struct drm_atomic_commit *state) 2292 { 2293 struct drm_device *dev = state->dev; 2294 struct amdgpu_device *adev = drm_to_adev(dev); 2295 struct amdgpu_display_manager *dm = &adev->dm; 2296 struct drm_private_obj *obj; 2297 struct drm_private_state *new_obj_state; 2298 int i; 2299 2300 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) { 2301 if (obj->funcs == dm->atomic_obj.funcs) 2302 return to_dm_atomic_state(new_obj_state); 2303 } 2304 2305 return NULL; 2306 } 2307 EXPORT_IF_KUNIT(dm_atomic_get_new_state); 2308 2309 static struct drm_private_state * 2310 dm_atomic_duplicate_state(struct drm_private_obj *obj) 2311 { 2312 struct dm_atomic_state *old_state, *new_state; 2313 2314 new_state = kzalloc_obj(*new_state); 2315 if (!new_state) 2316 return NULL; 2317 2318 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); 2319 2320 old_state = to_dm_atomic_state(obj->state); 2321 2322 if (old_state && old_state->context) 2323 new_state->context = dc_state_create_copy(old_state->context); 2324 2325 if (!new_state->context) { 2326 kfree(new_state); 2327 return NULL; 2328 } 2329 2330 return &new_state->base; 2331 } 2332 2333 STATIC_IFN_KUNIT void dm_atomic_destroy_state(struct drm_private_obj *obj, 2334 struct drm_private_state *state) 2335 { 2336 struct dm_atomic_state *dm_state = to_dm_atomic_state(state); 2337 2338 if (dm_state && dm_state->context) 2339 dc_state_release(dm_state->context); 2340 2341 kfree(dm_state); 2342 } 2343 EXPORT_IF_KUNIT(dm_atomic_destroy_state); 2344 2345 static struct drm_private_state * 2346 dm_atomic_create_state(struct drm_private_obj *obj) 2347 { 2348 struct amdgpu_device *adev = drm_to_adev(obj->dev); 2349 struct dm_atomic_state *dm_state; 2350 struct dc_state *context; 2351 2352 dm_state = kzalloc_obj(*dm_state); 2353 if (!dm_state) 2354 return ERR_PTR(-ENOMEM); 2355 2356 context = dc_state_create_current_copy(adev->dm.dc); 2357 if (!context) { 2358 kfree(dm_state); 2359 return ERR_PTR(-ENOMEM); 2360 } 2361 2362 __drm_atomic_helper_private_obj_create_state(obj, &dm_state->base); 2363 dm_state->context = context; 2364 2365 return &dm_state->base; 2366 } 2367 2368 static struct drm_private_state_funcs dm_atomic_state_funcs = { 2369 .atomic_create_state = dm_atomic_create_state, 2370 .atomic_duplicate_state = dm_atomic_duplicate_state, 2371 .atomic_destroy_state = dm_atomic_destroy_state, 2372 }; 2373 2374 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) 2375 { 2376 int r; 2377 2378 adev->mode_info.mode_config_initialized = true; 2379 2380 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; 2381 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; 2382 2383 adev_to_drm(adev)->mode_config.max_width = 16384; 2384 adev_to_drm(adev)->mode_config.max_height = 16384; 2385 2386 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2387 if (adev->asic_type == CHIP_HAWAII) 2388 /* disable prefer shadow for now due to hibernation issues */ 2389 adev_to_drm(adev)->mode_config.prefer_shadow = 0; 2390 else 2391 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2392 /* indicates support for immediate flip */ 2393 adev_to_drm(adev)->mode_config.async_page_flip = true; 2394 2395 drm_atomic_private_obj_init(adev_to_drm(adev), 2396 &adev->dm.atomic_obj, 2397 &dm_atomic_state_funcs); 2398 2399 r = amdgpu_display_modeset_create_props(adev); 2400 if (r) 2401 return r; 2402 2403 #ifdef AMD_PRIVATE_COLOR 2404 if (amdgpu_dm_create_color_properties(adev)) 2405 return -ENOMEM; 2406 #endif 2407 2408 r = amdgpu_dm_audio_init(adev); 2409 if (r) 2410 return r; 2411 2412 return 0; 2413 } 2414 2415 static int initialize_plane(struct amdgpu_display_manager *dm, 2416 struct amdgpu_mode_info *mode_info, int plane_id, 2417 enum drm_plane_type plane_type, 2418 const struct dc_plane_cap *plane_cap) 2419 { 2420 struct drm_plane *plane; 2421 unsigned long possible_crtcs; 2422 int ret = 0; 2423 2424 plane = kzalloc_obj(struct drm_plane); 2425 if (!plane) { 2426 drm_err(adev_to_drm(dm->adev), "KMS: Failed to allocate plane\n"); 2427 return -ENOMEM; 2428 } 2429 plane->type = plane_type; 2430 2431 /* 2432 * HACK: IGT tests expect that the primary plane for a CRTC 2433 * can only have one possible CRTC. Only expose support for 2434 * any CRTC if they're not going to be used as a primary plane 2435 * for a CRTC - like overlay or underlay planes. 2436 */ 2437 possible_crtcs = 1 << plane_id; 2438 if (plane_id >= dm->dc->caps.max_streams) 2439 possible_crtcs = 0xff; 2440 2441 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); 2442 2443 if (ret) { 2444 drm_err(adev_to_drm(dm->adev), "KMS: Failed to initialize plane\n"); 2445 kfree(plane); 2446 return ret; 2447 } 2448 2449 if (mode_info) 2450 mode_info->planes[plane_id] = plane; 2451 2452 return ret; 2453 } 2454 2455 2456 /* 2457 * In this architecture, the association 2458 * connector -> encoder -> crtc 2459 * id not really requried. The crtc and connector will hold the 2460 * display_index as an abstraction to use with DAL component 2461 * 2462 * Returns 0 on success 2463 */ 2464 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 2465 { 2466 struct amdgpu_display_manager *dm = &adev->dm; 2467 s32 i; 2468 struct amdgpu_dm_connector *aconnector = NULL; 2469 struct amdgpu_encoder *aencoder = NULL; 2470 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2471 u32 link_cnt; 2472 s32 primary_planes; 2473 enum dc_connection_type new_connection_type = dc_connection_none; 2474 const struct dc_plane_cap *plane; 2475 bool psr_feature_enabled = false; 2476 bool replay_feature_enabled = false; 2477 int max_overlay = dm->dc->caps.max_slave_planes; 2478 2479 dm->display_indexes_num = dm->dc->caps.max_streams; 2480 /* Update the actual used number of crtc */ 2481 adev->mode_info.num_crtc = adev->dm.display_indexes_num; 2482 2483 amdgpu_dm_set_irq_funcs(adev); 2484 2485 link_cnt = dm->dc->caps.max_links; 2486 if (amdgpu_dm_mode_config_init(dm->adev)) { 2487 drm_err(adev_to_drm(adev), "DM: Failed to initialize mode config\n"); 2488 return -EINVAL; 2489 } 2490 2491 /* There is one primary plane per CRTC */ 2492 primary_planes = dm->dc->caps.max_streams; 2493 if (primary_planes > AMDGPU_MAX_PLANES) { 2494 drm_err(adev_to_drm(adev), "DM: Plane nums out of 6 planes\n"); 2495 return -EINVAL; 2496 } 2497 2498 /* 2499 * Initialize primary planes, implicit planes for legacy IOCTLS. 2500 * Order is reversed to match iteration order in atomic check. 2501 */ 2502 for (i = (primary_planes - 1); i >= 0; i--) { 2503 plane = &dm->dc->caps.planes[i]; 2504 2505 if (initialize_plane(dm, mode_info, i, 2506 DRM_PLANE_TYPE_PRIMARY, plane)) { 2507 drm_err(adev_to_drm(adev), "KMS: Failed to initialize primary plane\n"); 2508 goto fail; 2509 } 2510 } 2511 2512 /* 2513 * Initialize overlay planes, index starting after primary planes. 2514 * These planes have a higher DRM index than the primary planes since 2515 * they should be considered as having a higher z-order. 2516 * Order is reversed to match iteration order in atomic check. 2517 * 2518 * Only support DCN for now, and only expose one so we don't encourage 2519 * userspace to use up all the pipes. 2520 */ 2521 for (i = 0; i < dm->dc->caps.max_planes; ++i) { 2522 struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; 2523 2524 /* Do not create overlay if MPO disabled */ 2525 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) 2526 break; 2527 2528 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) 2529 continue; 2530 2531 if (!plane->pixel_format_support.argb8888) 2532 continue; 2533 2534 if (max_overlay-- == 0) 2535 break; 2536 2537 if (initialize_plane(dm, NULL, primary_planes + i, 2538 DRM_PLANE_TYPE_OVERLAY, plane)) { 2539 drm_err(adev_to_drm(adev), "KMS: Failed to initialize overlay plane\n"); 2540 goto fail; 2541 } 2542 } 2543 2544 for (i = 0; i < dm->dc->caps.max_streams; i++) 2545 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { 2546 drm_err(adev_to_drm(adev), "KMS: Failed to initialize crtc\n"); 2547 goto fail; 2548 } 2549 2550 /* Use Outbox interrupt */ 2551 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2552 case IP_VERSION(3, 0, 0): 2553 case IP_VERSION(3, 1, 2): 2554 case IP_VERSION(3, 1, 3): 2555 case IP_VERSION(3, 1, 4): 2556 case IP_VERSION(3, 1, 5): 2557 case IP_VERSION(3, 1, 6): 2558 case IP_VERSION(3, 2, 0): 2559 case IP_VERSION(3, 2, 1): 2560 case IP_VERSION(2, 1, 0): 2561 case IP_VERSION(3, 5, 0): 2562 case IP_VERSION(3, 5, 1): 2563 case IP_VERSION(3, 6, 0): 2564 case IP_VERSION(4, 0, 1): 2565 case IP_VERSION(4, 2, 0): 2566 case IP_VERSION(4, 2, 1): 2567 if (amdgpu_dm_register_outbox_irq_handlers(dm->adev)) { 2568 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2569 goto fail; 2570 } 2571 break; 2572 default: 2573 drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", 2574 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2575 } 2576 2577 /* Determine whether to enable PSR support by default. */ 2578 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { 2579 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2580 case IP_VERSION(3, 1, 2): 2581 case IP_VERSION(3, 1, 3): 2582 case IP_VERSION(3, 1, 4): 2583 case IP_VERSION(3, 1, 5): 2584 case IP_VERSION(3, 1, 6): 2585 case IP_VERSION(3, 2, 0): 2586 case IP_VERSION(3, 2, 1): 2587 case IP_VERSION(3, 5, 0): 2588 case IP_VERSION(3, 5, 1): 2589 case IP_VERSION(3, 6, 0): 2590 case IP_VERSION(4, 0, 1): 2591 case IP_VERSION(4, 2, 0): 2592 case IP_VERSION(4, 2, 1): 2593 psr_feature_enabled = true; 2594 break; 2595 default: 2596 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; 2597 break; 2598 } 2599 } 2600 2601 /* Determine whether to enable Replay support by default. */ 2602 if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 2603 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2604 case IP_VERSION(3, 1, 4): 2605 case IP_VERSION(3, 2, 0): 2606 case IP_VERSION(3, 2, 1): 2607 case IP_VERSION(3, 5, 0): 2608 case IP_VERSION(3, 5, 1): 2609 case IP_VERSION(3, 6, 0): 2610 case IP_VERSION(4, 2, 0): 2611 case IP_VERSION(4, 2, 1): 2612 replay_feature_enabled = true; 2613 break; 2614 2615 default: 2616 replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; 2617 break; 2618 } 2619 } 2620 2621 if (link_cnt > MAX_LINKS) { 2622 drm_err(adev_to_drm(adev), 2623 "KMS: Cannot support more than %d display indexes\n", 2624 MAX_LINKS); 2625 goto fail; 2626 } 2627 2628 /* loops over all connectors on the board */ 2629 for (i = 0; i < link_cnt; i++) { 2630 struct dc_link *link = NULL; 2631 2632 link = dc_get_link_at_index(dm->dc, i); 2633 2634 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) { 2635 struct amdgpu_dm_wb_connector *wbcon = kzalloc_obj(*wbcon); 2636 2637 if (!wbcon) { 2638 drm_err(adev_to_drm(adev), "KMS: Failed to allocate writeback connector\n"); 2639 continue; 2640 } 2641 2642 if (amdgpu_dm_wb_connector_init(dm, wbcon, i)) { 2643 drm_err(adev_to_drm(adev), "KMS: Failed to initialize writeback connector\n"); 2644 kfree(wbcon); 2645 continue; 2646 } 2647 2648 link->psr_settings.psr_feature_enabled = false; 2649 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 2650 2651 continue; 2652 } 2653 2654 aconnector = kzalloc_obj(*aconnector); 2655 if (!aconnector) 2656 goto fail; 2657 2658 aencoder = kzalloc_obj(*aencoder); 2659 if (!aencoder) 2660 goto fail; 2661 2662 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { 2663 drm_err(adev_to_drm(adev), "KMS: Failed to initialize encoder\n"); 2664 goto fail; 2665 } 2666 2667 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { 2668 drm_err(adev_to_drm(adev), "KMS: Failed to initialize connector\n"); 2669 goto fail; 2670 } 2671 2672 if (dm->hpd_rx_offload_wq) 2673 dm->hpd_rx_offload_wq[aconnector->base.index].aconnector = 2674 aconnector; 2675 2676 if (!dc_link_detect_connection_type(link, &new_connection_type)) 2677 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 2678 2679 if (aconnector->base.force && new_connection_type == dc_connection_none) { 2680 amdgpu_dm_emulated_link_detect(link); 2681 amdgpu_dm_update_connector_after_detect(aconnector); 2682 } else { 2683 bool ret = false; 2684 2685 mutex_lock(&dm->dc_lock); 2686 dc_exit_ips_for_hw_access(dm->dc); 2687 ret = dc_link_detect(link, DETECT_REASON_BOOT); 2688 mutex_unlock(&dm->dc_lock); 2689 2690 if (ret) { 2691 amdgpu_dm_update_connector_after_detect(aconnector); 2692 amdgpu_dm_setup_backlight_device(dm, aconnector); 2693 2694 /* Disable PSR if Replay can be enabled */ 2695 if (replay_feature_enabled) 2696 if (amdgpu_dm_set_replay_caps(link, aconnector)) 2697 psr_feature_enabled = false; 2698 2699 if (psr_feature_enabled) { 2700 amdgpu_dm_set_psr_caps(link, aconnector); 2701 drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n", 2702 aconnector->base.name, 2703 link->psr_settings.psr_feature_enabled, 2704 link->psr_settings.psr_version, 2705 link->dpcd_caps.psr_info.psr_version, 2706 link->dpcd_caps.psr_info.psr_dpcd_caps.raw, 2707 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap); 2708 } 2709 } 2710 } 2711 amdgpu_set_panel_orientation(&aconnector->base); 2712 } 2713 2714 /* Debug dump: list all DC links and their associated sinks after detection 2715 * is complete for all connectors. This provides a comprehensive view of the 2716 * final state without repeating the dump for each connector. 2717 */ 2718 amdgpu_dm_dump_links_and_sinks(adev); 2719 2720 /* Software is initialized. Now we can register interrupt handlers. */ 2721 switch (adev->asic_type) { 2722 #if defined(CONFIG_DRM_AMD_DC_SI) 2723 case CHIP_TAHITI: 2724 case CHIP_PITCAIRN: 2725 case CHIP_VERDE: 2726 case CHIP_OLAND: 2727 #endif 2728 case CHIP_BONAIRE: 2729 case CHIP_HAWAII: 2730 case CHIP_KAVERI: 2731 case CHIP_KABINI: 2732 case CHIP_MULLINS: 2733 case CHIP_TONGA: 2734 case CHIP_FIJI: 2735 case CHIP_CARRIZO: 2736 case CHIP_STONEY: 2737 case CHIP_POLARIS11: 2738 case CHIP_POLARIS10: 2739 case CHIP_POLARIS12: 2740 case CHIP_VEGAM: 2741 case CHIP_VEGA10: 2742 case CHIP_VEGA12: 2743 case CHIP_VEGA20: 2744 if (amdgpu_dm_dce110_register_irq_handlers(dm->adev)) { 2745 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2746 goto fail; 2747 } 2748 break; 2749 default: 2750 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2751 case IP_VERSION(1, 0, 0): 2752 case IP_VERSION(1, 0, 1): 2753 case IP_VERSION(2, 0, 2): 2754 case IP_VERSION(2, 0, 3): 2755 case IP_VERSION(2, 0, 0): 2756 case IP_VERSION(2, 1, 0): 2757 case IP_VERSION(3, 0, 0): 2758 case IP_VERSION(3, 0, 2): 2759 case IP_VERSION(3, 0, 3): 2760 case IP_VERSION(3, 0, 1): 2761 case IP_VERSION(3, 1, 2): 2762 case IP_VERSION(3, 1, 3): 2763 case IP_VERSION(3, 1, 4): 2764 case IP_VERSION(3, 1, 5): 2765 case IP_VERSION(3, 1, 6): 2766 case IP_VERSION(3, 2, 0): 2767 case IP_VERSION(3, 2, 1): 2768 case IP_VERSION(3, 5, 0): 2769 case IP_VERSION(3, 5, 1): 2770 case IP_VERSION(3, 6, 0): 2771 case IP_VERSION(4, 0, 1): 2772 case IP_VERSION(4, 2, 0): 2773 case IP_VERSION(4, 2, 1): 2774 if (amdgpu_dm_dcn10_register_irq_handlers(dm->adev)) { 2775 drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); 2776 goto fail; 2777 } 2778 break; 2779 default: 2780 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%X\n", 2781 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2782 goto fail; 2783 } 2784 break; 2785 } 2786 2787 return 0; 2788 fail: 2789 kfree(aencoder); 2790 kfree(aconnector); 2791 2792 return -EINVAL; 2793 } 2794 2795 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) 2796 { 2797 if (dm->atomic_obj.state) 2798 drm_atomic_private_obj_fini(&dm->atomic_obj); 2799 } 2800 2801 /****************************************************************************** 2802 * amdgpu_display_funcs functions 2803 *****************************************************************************/ 2804 2805 /* 2806 * dm_bandwidth_update - program display watermarks 2807 * 2808 * @adev: amdgpu_device pointer 2809 * 2810 * Calculate and program the display watermarks and line buffer allocation. 2811 */ 2812 STATIC_IFN_KUNIT void dm_bandwidth_update(struct amdgpu_device *adev) 2813 { 2814 /* TODO: implement later */ 2815 } 2816 EXPORT_IF_KUNIT(dm_bandwidth_update); 2817 2818 static const struct amdgpu_display_funcs dm_display_funcs = { 2819 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ 2820 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ 2821 .backlight_set_level = NULL, /* never called for DC */ 2822 .backlight_get_level = NULL, /* never called for DC */ 2823 .hpd_sense = NULL,/* called unconditionally */ 2824 .hpd_set_polarity = NULL, /* called unconditionally */ 2825 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ 2826 .page_flip_get_scanoutpos = 2827 dm_crtc_get_scanoutpos,/* called unconditionally */ 2828 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ 2829 .add_connector = NULL, /* VBIOS parsing. DAL does it. */ 2830 }; 2831 2832 #if defined(CONFIG_DEBUG_KERNEL_DC) 2833 2834 static ssize_t s3_debug_store(struct device *device, 2835 struct device_attribute *attr, 2836 const char *buf, 2837 size_t count) 2838 { 2839 int ret; 2840 int s3_state; 2841 struct drm_device *drm_dev = dev_get_drvdata(device); 2842 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2843 struct amdgpu_ip_block *ip_block; 2844 2845 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); 2846 if (!ip_block) 2847 return -EINVAL; 2848 2849 ret = kstrtoint(buf, 0, &s3_state); 2850 2851 if (ret == 0) { 2852 if (s3_state) { 2853 dm_resume(ip_block); 2854 drm_kms_helper_hotplug_event(adev_to_drm(adev)); 2855 } else 2856 dm_suspend(ip_block); 2857 } 2858 2859 return ret == 0 ? count : 0; 2860 } 2861 2862 DEVICE_ATTR_WO(s3_debug); 2863 2864 #endif 2865 2866 static int dm_early_init(struct amdgpu_ip_block *ip_block) 2867 { 2868 struct amdgpu_device *adev = ip_block->adev; 2869 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2870 struct atom_context *ctx = mode_info->atom_context; 2871 int index = GetIndexIntoMasterTable(DATA, Object_Header); 2872 u16 data_offset; 2873 2874 /* if there is no object header, skip DM */ 2875 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 2876 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 2877 drm_info(adev_to_drm(adev), "No object header, skipping DM\n"); 2878 return -ENOENT; 2879 } 2880 2881 switch (adev->asic_type) { 2882 #if defined(CONFIG_DRM_AMD_DC_SI) 2883 case CHIP_TAHITI: 2884 case CHIP_PITCAIRN: 2885 case CHIP_VERDE: 2886 adev->mode_info.num_crtc = 6; 2887 adev->mode_info.num_hpd = 6; 2888 adev->mode_info.num_dig = 6; 2889 break; 2890 case CHIP_OLAND: 2891 adev->mode_info.num_crtc = 2; 2892 adev->mode_info.num_hpd = 2; 2893 adev->mode_info.num_dig = 2; 2894 break; 2895 #endif 2896 case CHIP_BONAIRE: 2897 case CHIP_HAWAII: 2898 adev->mode_info.num_crtc = 6; 2899 adev->mode_info.num_hpd = 6; 2900 adev->mode_info.num_dig = 6; 2901 break; 2902 case CHIP_KAVERI: 2903 adev->mode_info.num_crtc = 4; 2904 adev->mode_info.num_hpd = 6; 2905 adev->mode_info.num_dig = 7; 2906 break; 2907 case CHIP_KABINI: 2908 case CHIP_MULLINS: 2909 adev->mode_info.num_crtc = 2; 2910 adev->mode_info.num_hpd = 6; 2911 adev->mode_info.num_dig = 6; 2912 break; 2913 case CHIP_FIJI: 2914 case CHIP_TONGA: 2915 adev->mode_info.num_crtc = 6; 2916 adev->mode_info.num_hpd = 6; 2917 adev->mode_info.num_dig = 7; 2918 break; 2919 case CHIP_CARRIZO: 2920 adev->mode_info.num_crtc = 3; 2921 adev->mode_info.num_hpd = 6; 2922 adev->mode_info.num_dig = 9; 2923 break; 2924 case CHIP_STONEY: 2925 adev->mode_info.num_crtc = 2; 2926 adev->mode_info.num_hpd = 6; 2927 adev->mode_info.num_dig = 9; 2928 break; 2929 case CHIP_POLARIS11: 2930 case CHIP_POLARIS12: 2931 adev->mode_info.num_crtc = 5; 2932 adev->mode_info.num_hpd = 5; 2933 adev->mode_info.num_dig = 5; 2934 break; 2935 case CHIP_POLARIS10: 2936 case CHIP_VEGAM: 2937 adev->mode_info.num_crtc = 6; 2938 adev->mode_info.num_hpd = 6; 2939 adev->mode_info.num_dig = 6; 2940 break; 2941 case CHIP_VEGA10: 2942 case CHIP_VEGA12: 2943 case CHIP_VEGA20: 2944 adev->mode_info.num_crtc = 6; 2945 adev->mode_info.num_hpd = 6; 2946 adev->mode_info.num_dig = 6; 2947 break; 2948 default: 2949 2950 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2951 case IP_VERSION(2, 0, 2): 2952 case IP_VERSION(3, 0, 0): 2953 adev->mode_info.num_crtc = 6; 2954 adev->mode_info.num_hpd = 6; 2955 adev->mode_info.num_dig = 6; 2956 break; 2957 case IP_VERSION(2, 0, 0): 2958 case IP_VERSION(3, 0, 2): 2959 adev->mode_info.num_crtc = 5; 2960 adev->mode_info.num_hpd = 5; 2961 adev->mode_info.num_dig = 5; 2962 break; 2963 case IP_VERSION(2, 0, 3): 2964 case IP_VERSION(3, 0, 3): 2965 adev->mode_info.num_crtc = 2; 2966 adev->mode_info.num_hpd = 2; 2967 adev->mode_info.num_dig = 2; 2968 break; 2969 case IP_VERSION(1, 0, 0): 2970 case IP_VERSION(1, 0, 1): 2971 case IP_VERSION(3, 0, 1): 2972 case IP_VERSION(2, 1, 0): 2973 case IP_VERSION(3, 1, 2): 2974 case IP_VERSION(3, 1, 3): 2975 case IP_VERSION(3, 1, 4): 2976 case IP_VERSION(3, 1, 5): 2977 case IP_VERSION(3, 1, 6): 2978 case IP_VERSION(3, 2, 0): 2979 case IP_VERSION(3, 2, 1): 2980 case IP_VERSION(3, 5, 0): 2981 case IP_VERSION(3, 5, 1): 2982 case IP_VERSION(3, 6, 0): 2983 case IP_VERSION(4, 0, 1): 2984 case IP_VERSION(4, 2, 0): 2985 case IP_VERSION(4, 2, 1): 2986 adev->mode_info.num_crtc = 4; 2987 adev->mode_info.num_hpd = 4; 2988 adev->mode_info.num_dig = 4; 2989 break; 2990 default: 2991 drm_err(adev_to_drm(adev), "Unsupported DCE IP versions: 0x%x\n", 2992 amdgpu_ip_version(adev, DCE_HWIP, 0)); 2993 return -EINVAL; 2994 } 2995 break; 2996 } 2997 2998 if (adev->mode_info.funcs == NULL) 2999 adev->mode_info.funcs = &dm_display_funcs; 3000 3001 /* 3002 * Note: Do NOT change adev->reg.audio_endpt.rreg and 3003 * adev->reg.audio_endpt.wreg because they are initialised in 3004 * amdgpu_device_init() 3005 */ 3006 #if defined(CONFIG_DEBUG_KERNEL_DC) 3007 device_create_file( 3008 adev_to_drm(adev)->dev, 3009 &dev_attr_s3_debug); 3010 #endif 3011 adev->dc_enabled = true; 3012 3013 return dm_init_microcode(adev); 3014 } 3015 3016 STATIC_IFN_KUNIT bool modereset_required(struct drm_crtc_state *crtc_state) 3017 { 3018 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); 3019 } 3020 EXPORT_IF_KUNIT(modereset_required); 3021 3022 STATIC_IFN_KUNIT int 3023 fill_plane_color_attributes(const struct drm_plane_state *plane_state, 3024 const enum surface_pixel_format format, 3025 enum dc_color_space *color_space) 3026 { 3027 bool full_range; 3028 3029 *color_space = COLOR_SPACE_SRGB; 3030 3031 /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ 3032 if (plane_state->state && plane_state->state->plane_color_pipeline) 3033 return 0; 3034 3035 /* DRM color properties only affect non-RGB formats. */ 3036 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 3037 return 0; 3038 3039 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); 3040 3041 switch (plane_state->color_encoding) { 3042 case DRM_COLOR_YCBCR_BT601: 3043 if (full_range) 3044 *color_space = COLOR_SPACE_YCBCR601; 3045 else 3046 *color_space = COLOR_SPACE_YCBCR601_LIMITED; 3047 break; 3048 3049 case DRM_COLOR_YCBCR_BT709: 3050 if (full_range) 3051 *color_space = COLOR_SPACE_YCBCR709; 3052 else 3053 *color_space = COLOR_SPACE_YCBCR709_LIMITED; 3054 break; 3055 3056 case DRM_COLOR_YCBCR_BT2020: 3057 if (full_range) 3058 *color_space = COLOR_SPACE_2020_YCBCR_FULL; 3059 else 3060 *color_space = COLOR_SPACE_2020_YCBCR_LIMITED; 3061 break; 3062 3063 default: 3064 return -EINVAL; 3065 } 3066 3067 return 0; 3068 } 3069 EXPORT_IF_KUNIT(fill_plane_color_attributes); 3070 3071 static int 3072 fill_dc_plane_info_and_addr(struct amdgpu_device *adev, 3073 const struct drm_plane_state *plane_state, 3074 const u64 tiling_flags, 3075 struct dc_plane_info *plane_info, 3076 struct dc_plane_address *address, 3077 bool tmz_surface) 3078 { 3079 const struct drm_framebuffer *fb = plane_state->fb; 3080 const struct amdgpu_framebuffer *afb = 3081 to_amdgpu_framebuffer(plane_state->fb); 3082 int ret; 3083 3084 memset(plane_info, 0, sizeof(*plane_info)); 3085 3086 switch (fb->format->format) { 3087 case DRM_FORMAT_C8: 3088 plane_info->format = 3089 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; 3090 break; 3091 case DRM_FORMAT_RGB565: 3092 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; 3093 break; 3094 case DRM_FORMAT_XRGB8888: 3095 case DRM_FORMAT_ARGB8888: 3096 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; 3097 break; 3098 case DRM_FORMAT_XRGB2101010: 3099 case DRM_FORMAT_ARGB2101010: 3100 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; 3101 break; 3102 case DRM_FORMAT_XBGR2101010: 3103 case DRM_FORMAT_ABGR2101010: 3104 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; 3105 break; 3106 case DRM_FORMAT_XBGR8888: 3107 case DRM_FORMAT_ABGR8888: 3108 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; 3109 break; 3110 case DRM_FORMAT_NV21: 3111 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; 3112 break; 3113 case DRM_FORMAT_NV12: 3114 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; 3115 break; 3116 case DRM_FORMAT_P010: 3117 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; 3118 break; 3119 case DRM_FORMAT_XRGB16161616F: 3120 case DRM_FORMAT_ARGB16161616F: 3121 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; 3122 break; 3123 case DRM_FORMAT_XBGR16161616F: 3124 case DRM_FORMAT_ABGR16161616F: 3125 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; 3126 break; 3127 case DRM_FORMAT_XRGB16161616: 3128 case DRM_FORMAT_ARGB16161616: 3129 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; 3130 break; 3131 case DRM_FORMAT_XBGR16161616: 3132 case DRM_FORMAT_ABGR16161616: 3133 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; 3134 break; 3135 default: 3136 drm_err(adev_to_drm(adev), 3137 "Unsupported screen format %p4cc\n", 3138 &fb->format->format); 3139 return -EINVAL; 3140 } 3141 3142 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 3143 case DRM_MODE_ROTATE_0: 3144 plane_info->rotation = ROTATION_ANGLE_0; 3145 break; 3146 case DRM_MODE_ROTATE_90: 3147 plane_info->rotation = ROTATION_ANGLE_90; 3148 break; 3149 case DRM_MODE_ROTATE_180: 3150 plane_info->rotation = ROTATION_ANGLE_180; 3151 break; 3152 case DRM_MODE_ROTATE_270: 3153 plane_info->rotation = ROTATION_ANGLE_270; 3154 break; 3155 default: 3156 plane_info->rotation = ROTATION_ANGLE_0; 3157 break; 3158 } 3159 3160 3161 plane_info->visible = true; 3162 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; 3163 3164 plane_info->layer_index = plane_state->normalized_zpos; 3165 3166 ret = fill_plane_color_attributes(plane_state, plane_info->format, 3167 &plane_info->color_space); 3168 if (ret) 3169 return ret; 3170 3171 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format, 3172 plane_info->rotation, tiling_flags, 3173 &plane_info->tiling_info, 3174 &plane_info->plane_size, 3175 &plane_info->dcc, address, 3176 tmz_surface); 3177 if (ret) 3178 return ret; 3179 3180 amdgpu_dm_plane_fill_blending_from_plane_state( 3181 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, 3182 &plane_info->global_alpha, &plane_info->global_alpha_value); 3183 3184 return 0; 3185 } 3186 3187 static int fill_dc_plane_attributes(struct amdgpu_device *adev, 3188 struct dc_plane_state *dc_plane_state, 3189 struct drm_plane_state *plane_state, 3190 struct drm_crtc_state *crtc_state) 3191 { 3192 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3193 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; 3194 struct dc_scaling_info scaling_info; 3195 struct dc_plane_info plane_info; 3196 int ret; 3197 3198 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info); 3199 if (ret) 3200 return ret; 3201 3202 dc_plane_state->src_rect = scaling_info.src_rect; 3203 dc_plane_state->dst_rect = scaling_info.dst_rect; 3204 dc_plane_state->clip_rect = scaling_info.clip_rect; 3205 dc_plane_state->scaling_quality = scaling_info.scaling_quality; 3206 3207 ret = fill_dc_plane_info_and_addr(adev, plane_state, 3208 afb->tiling_flags, 3209 &plane_info, 3210 &dc_plane_state->address, 3211 afb->tmz_surface); 3212 if (ret) 3213 return ret; 3214 3215 dc_plane_state->format = plane_info.format; 3216 dc_plane_state->color_space = plane_info.color_space; 3217 dc_plane_state->format = plane_info.format; 3218 dc_plane_state->plane_size = plane_info.plane_size; 3219 dc_plane_state->rotation = plane_info.rotation; 3220 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; 3221 dc_plane_state->stereo_format = plane_info.stereo_format; 3222 dc_plane_state->tiling_info = plane_info.tiling_info; 3223 dc_plane_state->visible = plane_info.visible; 3224 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; 3225 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; 3226 dc_plane_state->global_alpha = plane_info.global_alpha; 3227 dc_plane_state->global_alpha_value = plane_info.global_alpha_value; 3228 dc_plane_state->dcc = plane_info.dcc; 3229 dc_plane_state->layer_index = plane_info.layer_index; 3230 dc_plane_state->flip_int_enabled = true; 3231 3232 /* 3233 * Always set input transfer function, since plane state is refreshed 3234 * every time. 3235 */ 3236 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, 3237 plane_state, 3238 dc_plane_state); 3239 if (ret) 3240 return ret; 3241 3242 return 0; 3243 } 3244 3245 static inline void fill_dc_dirty_rect(struct drm_plane *plane, 3246 struct rect *dirty_rect, int32_t x, 3247 s32 y, s32 width, s32 height, 3248 int *i, bool ffu) 3249 { 3250 WARN_ON(*i >= DC_MAX_DIRTY_RECTS); 3251 3252 dirty_rect->x = x; 3253 dirty_rect->y = y; 3254 dirty_rect->width = width; 3255 dirty_rect->height = height; 3256 3257 if (ffu) 3258 drm_dbg(plane->dev, 3259 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n", 3260 plane->base.id, width, height); 3261 else 3262 drm_dbg(plane->dev, 3263 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)", 3264 plane->base.id, x, y, width, height); 3265 3266 (*i)++; 3267 } 3268 3269 /** 3270 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates 3271 * 3272 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP 3273 * remote fb 3274 * @old_plane_state: Old state of @plane 3275 * @new_plane_state: New state of @plane 3276 * @crtc_state: New state of CRTC connected to the @plane 3277 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects 3278 * @is_psr_su: Flag indicating whether Panel Self Refresh Selective Update (PSR SU) is enabled. 3279 * If PSR SU is enabled and damage clips are available, only the regions of the screen 3280 * that have changed will be updated. If PSR SU is not enabled, 3281 * or if damage clips are not available, the entire screen will be updated. 3282 * @dirty_regions_changed: dirty regions changed 3283 * 3284 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions 3285 * (referred to as "damage clips" in DRM nomenclature) that require updating on 3286 * the eDP remote buffer. The responsibility of specifying the dirty regions is 3287 * amdgpu_dm's. 3288 * 3289 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the 3290 * plane with regions that require flushing to the eDP remote buffer. In 3291 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - 3292 * implicitly provide damage clips without any client support via the plane 3293 * bounds. 3294 */ 3295 static void fill_dc_dirty_rects(struct drm_plane *plane, 3296 struct drm_plane_state *old_plane_state, 3297 struct drm_plane_state *new_plane_state, 3298 struct drm_crtc_state *crtc_state, 3299 struct dc_flip_addrs *flip_addrs, 3300 bool is_psr_su, 3301 bool *dirty_regions_changed) 3302 { 3303 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); 3304 struct rect *dirty_rects = flip_addrs->dirty_rects; 3305 u32 num_clips = 0; 3306 struct drm_mode_rect *clips = NULL; 3307 bool bb_changed; 3308 bool fb_changed; 3309 u32 i = 0; 3310 *dirty_regions_changed = false; 3311 3312 /* 3313 * Cursor plane has it's own dirty rect update interface. See 3314 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data 3315 */ 3316 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3317 return; 3318 3319 if (new_plane_state->rotation != DRM_MODE_ROTATE_0) 3320 goto ffu; 3321 3322 if (!new_plane_state->ignore_damage_clips) { 3323 num_clips = drm_plane_get_damage_clips_count(new_plane_state); 3324 clips = drm_plane_get_damage_clips(new_plane_state); 3325 } 3326 3327 if (num_clips && (!amdgpu_damage_clips || (amdgpu_damage_clips < 0 && 3328 is_psr_su))) 3329 goto ffu; 3330 3331 if (!dm_crtc_state->mpo_requested) { 3332 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS) 3333 goto ffu; 3334 3335 for (; flip_addrs->dirty_rect_count < num_clips; clips++) 3336 fill_dc_dirty_rect(new_plane_state->plane, 3337 &dirty_rects[flip_addrs->dirty_rect_count], 3338 clips->x1, clips->y1, 3339 clips->x2 - clips->x1, clips->y2 - clips->y1, 3340 &flip_addrs->dirty_rect_count, 3341 false); 3342 return; 3343 } 3344 3345 /* 3346 * MPO is requested. Add entire plane bounding box to dirty rects if 3347 * flipped to or damaged. 3348 * 3349 * If plane is moved or resized, also add old bounding box to dirty 3350 * rects. 3351 */ 3352 fb_changed = old_plane_state->fb->base.id != 3353 new_plane_state->fb->base.id; 3354 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || 3355 old_plane_state->crtc_y != new_plane_state->crtc_y || 3356 old_plane_state->crtc_w != new_plane_state->crtc_w || 3357 old_plane_state->crtc_h != new_plane_state->crtc_h); 3358 3359 drm_dbg(plane->dev, 3360 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n", 3361 new_plane_state->plane->base.id, 3362 bb_changed, fb_changed, num_clips); 3363 3364 *dirty_regions_changed = bb_changed; 3365 3366 if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS) 3367 goto ffu; 3368 3369 if (bb_changed) { 3370 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3371 new_plane_state->crtc_x, 3372 new_plane_state->crtc_y, 3373 new_plane_state->crtc_w, 3374 new_plane_state->crtc_h, &i, false); 3375 3376 /* Add old plane bounding-box if plane is moved or resized */ 3377 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3378 old_plane_state->crtc_x, 3379 old_plane_state->crtc_y, 3380 old_plane_state->crtc_w, 3381 old_plane_state->crtc_h, &i, false); 3382 } 3383 3384 if (num_clips) { 3385 for (; i < num_clips; clips++) 3386 fill_dc_dirty_rect(new_plane_state->plane, 3387 &dirty_rects[i], clips->x1, 3388 clips->y1, clips->x2 - clips->x1, 3389 clips->y2 - clips->y1, &i, false); 3390 } else if (fb_changed && !bb_changed) { 3391 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], 3392 new_plane_state->crtc_x, 3393 new_plane_state->crtc_y, 3394 new_plane_state->crtc_w, 3395 new_plane_state->crtc_h, &i, false); 3396 } 3397 3398 flip_addrs->dirty_rect_count = i; 3399 return; 3400 3401 ffu: 3402 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, 3403 dm_crtc_state->base.mode.crtc_hdisplay, 3404 dm_crtc_state->base.mode.crtc_vdisplay, 3405 &flip_addrs->dirty_rect_count, true); 3406 } 3407 3408 void amdgpu_dm_update_stream_scaling_settings(struct drm_device *dev, 3409 const struct drm_display_mode *mode, 3410 const struct dm_connector_state *dm_state, 3411 struct dc_stream_state *stream) 3412 { 3413 enum amdgpu_rmx_type rmx_type; 3414 3415 struct rect src = { 0 }; /* viewport in composition space*/ 3416 struct rect dst = { 0 }; /* stream addressable area */ 3417 3418 /* no mode. nothing to be done */ 3419 if (!mode) 3420 return; 3421 3422 /* Full screen scaling by default */ 3423 src.width = mode->hdisplay; 3424 src.height = mode->vdisplay; 3425 dst.width = stream->timing.h_addressable; 3426 dst.height = stream->timing.v_addressable; 3427 3428 if (dm_state) { 3429 rmx_type = dm_state->scaling; 3430 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { 3431 if (src.width * dst.height < 3432 src.height * dst.width) { 3433 /* height needs less upscaling/more downscaling */ 3434 dst.width = src.width * 3435 dst.height / src.height; 3436 } else { 3437 /* width needs less upscaling/more downscaling */ 3438 dst.height = src.height * 3439 dst.width / src.width; 3440 } 3441 } else if (rmx_type == RMX_CENTER) { 3442 dst = src; 3443 } 3444 3445 dst.x = (stream->timing.h_addressable - dst.width) / 2; 3446 dst.y = (stream->timing.v_addressable - dst.height) / 2; 3447 3448 if (dm_state->underscan_enable) { 3449 dst.x += dm_state->underscan_hborder / 2; 3450 dst.y += dm_state->underscan_vborder / 2; 3451 dst.width -= dm_state->underscan_hborder; 3452 dst.height -= dm_state->underscan_vborder; 3453 } 3454 } 3455 3456 stream->src = src; 3457 stream->dst = dst; 3458 3459 drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", 3460 dst.x, dst.y, dst.width, dst.height); 3461 3462 } 3463 EXPORT_IF_KUNIT(amdgpu_dm_update_stream_scaling_settings); 3464 3465 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_commit *state, 3466 struct dc_state *dc_state, 3467 struct dsc_mst_fairness_vars *vars) 3468 { 3469 struct dc_stream_state *stream = NULL; 3470 struct drm_connector *connector; 3471 struct drm_connector_state *new_con_state; 3472 struct amdgpu_dm_connector *aconnector; 3473 struct dm_connector_state *dm_conn_state; 3474 int i, j, ret; 3475 int vcpi, pbn_div, pbn = 0, slot_num = 0; 3476 3477 for_each_new_connector_in_state(state, connector, new_con_state, i) { 3478 3479 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 3480 continue; 3481 3482 aconnector = to_amdgpu_dm_connector(connector); 3483 3484 if (!aconnector->mst_output_port) 3485 continue; 3486 3487 if (!new_con_state || !new_con_state->crtc) 3488 continue; 3489 3490 dm_conn_state = to_dm_connector_state(new_con_state); 3491 3492 for (j = 0; j < dc_state->stream_count; j++) { 3493 stream = dc_state->streams[j]; 3494 if (!stream) 3495 continue; 3496 3497 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector) 3498 break; 3499 3500 stream = NULL; 3501 } 3502 3503 if (!stream) 3504 continue; 3505 3506 pbn_div = dm_mst_get_pbn_divider(stream->link); 3507 /* pbn is calculated by compute_mst_dsc_configs_for_state*/ 3508 for (j = 0; j < dc_state->stream_count; j++) { 3509 if (vars[j].aconnector == aconnector) { 3510 pbn = vars[j].pbn; 3511 break; 3512 } 3513 } 3514 3515 if (j == dc_state->stream_count || pbn_div == 0) 3516 continue; 3517 3518 slot_num = DIV_ROUND_UP(pbn, pbn_div); 3519 3520 if (stream->timing.flags.DSC != 1) { 3521 dm_conn_state->pbn = pbn; 3522 dm_conn_state->vcpi_slots = slot_num; 3523 3524 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, 3525 dm_conn_state->pbn, false); 3526 if (ret < 0) 3527 return ret; 3528 3529 continue; 3530 } 3531 3532 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); 3533 if (vcpi < 0) 3534 return vcpi; 3535 3536 dm_conn_state->pbn = pbn; 3537 dm_conn_state->vcpi_slots = vcpi; 3538 } 3539 return 0; 3540 } 3541 3542 static void manage_dm_interrupts(struct amdgpu_device *adev, 3543 struct amdgpu_crtc *acrtc, 3544 struct dm_crtc_state *acrtc_state) 3545 { /* 3546 * We cannot be sure that the frontend index maps to the same 3547 * backend index - some even map to more than one. 3548 * So we have to go through the CRTC to find the right IRQ. 3549 */ 3550 int irq_type = amdgpu_display_crtc_idx_to_irq_type( 3551 adev, 3552 acrtc->crtc_id); 3553 struct drm_device *dev = adev_to_drm(adev); 3554 3555 struct drm_vblank_crtc_config config = {0}; 3556 struct dc_crtc_timing *timing; 3557 int offdelay; 3558 3559 if (acrtc_state) { 3560 timing = &acrtc_state->stream->timing; 3561 3562 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < 3563 IP_VERSION(3, 5, 0) || 3564 !(adev->flags & AMD_IS_APU)) { 3565 /* 3566 * Older HW and DGPU have issues with instant off; 3567 * use a 2 frame offdelay. 3568 */ 3569 offdelay = DIV64_U64_ROUND_UP((u64)20 * 3570 timing->v_total * 3571 timing->h_total, 3572 timing->pix_clk_100hz); 3573 3574 config.offdelay_ms = offdelay ?: 30; 3575 } else { 3576 /* offdelay_ms = 0 will never disable vblank */ 3577 config.offdelay_ms = 1; 3578 config.disable_immediate = true; 3579 } 3580 3581 drm_crtc_vblank_on_config(&acrtc->base, 3582 &config); 3583 /* 3584 * Since pflip_high_irq is no longer registered for DCN, grab an 3585 * extra reference to vupdate irq instead to workaround this 3586 * issue: 3587 * https://gitlab.freedesktop.org/drm/amd/-/work_items/3936 3588 * 3589 * The callbacks to drm_vblank_on/off should really take care of 3590 * this though. 3591 */ 3592 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3593 case IP_VERSION(3, 0, 0): 3594 case IP_VERSION(3, 0, 2): 3595 case IP_VERSION(3, 0, 3): 3596 case IP_VERSION(3, 2, 0): 3597 if (amdgpu_irq_get(adev, &adev->vupdate_irq, irq_type)) 3598 drm_err(dev, "DM_IRQ: Cannot get vupdate irq!\n"); 3599 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3600 if (amdgpu_irq_get(adev, &adev->vline0_irq, irq_type)) 3601 drm_err(dev, "DM_IRQ: Cannot get vline0 irq!\n"); 3602 #endif 3603 } 3604 3605 } else { 3606 /* Allow RX6xxx, RX7700, RX7800 GPUs to call amdgpu_irq_put.*/ 3607 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 3608 case IP_VERSION(3, 0, 0): 3609 case IP_VERSION(3, 0, 2): 3610 case IP_VERSION(3, 0, 3): 3611 case IP_VERSION(3, 2, 0): 3612 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 3613 if (amdgpu_irq_put(adev, &adev->vline0_irq, irq_type)) 3614 drm_err(dev, "DM_IRQ: Cannot put vline0 irq!\n"); 3615 #endif 3616 if (amdgpu_irq_put(adev, &adev->vupdate_irq, irq_type)) 3617 drm_err(dev, "DM_IRQ: Cannot put vupdate irq!\n"); 3618 } 3619 3620 drm_crtc_vblank_off(&acrtc->base); 3621 } 3622 } 3623 3624 static void dm_update_pflip_irq_state(struct amdgpu_device *adev, 3625 struct amdgpu_crtc *acrtc) 3626 { 3627 int irq_type = 3628 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); 3629 3630 /* GRPH_PFLIP is not used on DCN; nothing to reapply. */ 3631 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) 3632 return; 3633 3634 /** 3635 * This reads the current state for the IRQ and force reapplies 3636 * the setting to hardware. 3637 */ 3638 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type); 3639 } 3640 3641 STATIC_IFN_KUNIT bool 3642 is_scaling_state_different(const struct dm_connector_state *dm_state, 3643 const struct dm_connector_state *old_dm_state) 3644 { 3645 if (dm_state->scaling != old_dm_state->scaling) 3646 return true; 3647 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { 3648 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) 3649 return true; 3650 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { 3651 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) 3652 return true; 3653 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || 3654 dm_state->underscan_vborder != old_dm_state->underscan_vborder) 3655 return true; 3656 return false; 3657 } 3658 EXPORT_IF_KUNIT(is_scaling_state_different); 3659 3660 STATIC_IFN_KUNIT bool 3661 is_content_protection_different(struct drm_crtc_state *new_crtc_state, 3662 struct drm_crtc_state *old_crtc_state, 3663 struct drm_connector_state *new_conn_state, 3664 struct drm_connector_state *old_conn_state, 3665 const struct drm_connector *connector, 3666 struct hdcp_workqueue *hdcp_w) 3667 { 3668 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 3669 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3670 3671 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 3672 connector->index, connector->status, connector->dpms); 3673 pr_debug("[HDCP_DM] state protection old: %x new: %x\n", 3674 old_conn_state->content_protection, new_conn_state->content_protection); 3675 3676 if (old_crtc_state) 3677 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3678 old_crtc_state->enable, 3679 old_crtc_state->active, 3680 old_crtc_state->mode_changed, 3681 old_crtc_state->active_changed, 3682 old_crtc_state->connectors_changed); 3683 3684 if (new_crtc_state) 3685 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 3686 new_crtc_state->enable, 3687 new_crtc_state->active, 3688 new_crtc_state->mode_changed, 3689 new_crtc_state->active_changed, 3690 new_crtc_state->connectors_changed); 3691 3692 /* hdcp content type change */ 3693 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && 3694 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 3695 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3696 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); 3697 return true; 3698 } 3699 3700 /* CP is being re enabled, ignore this */ 3701 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && 3702 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3703 if (new_crtc_state && new_crtc_state->mode_changed) { 3704 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3705 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__); 3706 return true; 3707 } 3708 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED; 3709 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__); 3710 return false; 3711 } 3712 3713 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED 3714 * 3715 * Handles: UNDESIRED -> ENABLED 3716 */ 3717 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED && 3718 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) 3719 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 3720 3721 /* Stream removed and re-enabled 3722 * 3723 * Can sometimes overlap with the HPD case, 3724 * thus set update_hdcp to false to avoid 3725 * setting HDCP multiple times. 3726 * 3727 * Handles: DESIRED -> DESIRED (Special case) 3728 */ 3729 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) && 3730 new_conn_state->crtc && new_conn_state->crtc->enabled && 3731 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3732 dm_con_state->update_hdcp = false; 3733 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n", 3734 __func__); 3735 return true; 3736 } 3737 3738 /* Hot-plug, headless s3, dpms 3739 * 3740 * Only start HDCP if the display is connected/enabled. 3741 * update_hdcp flag will be set to false until the next 3742 * HPD comes in. 3743 * 3744 * Handles: DESIRED -> DESIRED (Special case) 3745 */ 3746 if (dm_con_state->update_hdcp && 3747 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && 3748 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) { 3749 dm_con_state->update_hdcp = false; 3750 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n", 3751 __func__); 3752 return true; 3753 } 3754 3755 if (old_conn_state->content_protection == new_conn_state->content_protection) { 3756 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) { 3757 if (new_crtc_state && new_crtc_state->mode_changed) { 3758 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n", 3759 __func__); 3760 return true; 3761 } 3762 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n", 3763 __func__); 3764 return false; 3765 } 3766 3767 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__); 3768 return false; 3769 } 3770 3771 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) { 3772 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n", 3773 __func__); 3774 return true; 3775 } 3776 3777 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__); 3778 return false; 3779 } 3780 EXPORT_IF_KUNIT(is_content_protection_different); 3781 3782 static void remove_stream(struct amdgpu_device *adev, 3783 struct amdgpu_crtc *acrtc, 3784 struct dc_stream_state *stream) 3785 { 3786 /* this is the update mode case */ 3787 3788 acrtc->otg_inst = -1; 3789 acrtc->enabled = false; 3790 } 3791 3792 static void prepare_flip_isr(struct amdgpu_crtc *acrtc) 3793 { 3794 3795 assert_spin_locked(&acrtc->base.dev->event_lock); 3796 WARN_ON(acrtc->event); 3797 3798 acrtc->event = acrtc->base.state->event; 3799 3800 /* Set the flip status */ 3801 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 3802 3803 /* Mark this event as consumed */ 3804 acrtc->base.state->event = NULL; 3805 3806 drm_dbg_state(acrtc->base.dev, 3807 "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", 3808 acrtc->crtc_id); 3809 } 3810 3811 static void update_freesync_state_on_stream( 3812 struct amdgpu_display_manager *dm, 3813 struct dm_crtc_state *new_crtc_state, 3814 struct dc_stream_state *new_stream, 3815 struct dc_plane_state *surface, 3816 u32 flip_timestamp_in_us) 3817 { 3818 struct mod_vrr_params vrr_params; 3819 struct dc_info_packet vrr_infopacket = {0}; 3820 struct amdgpu_device *adev = dm->adev; 3821 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3822 unsigned long flags; 3823 bool pack_sdp_v1_3 = false; 3824 struct amdgpu_dm_connector *aconn; 3825 enum vrr_packet_type packet_type = PACKET_TYPE_VRR; 3826 3827 if (!new_stream) 3828 return; 3829 3830 /* 3831 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3832 * For now it's sufficient to just guard against these conditions. 3833 */ 3834 3835 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3836 return; 3837 3838 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3839 vrr_params = acrtc->dm_irq_params.vrr_params; 3840 3841 if (surface) { 3842 mod_freesync_handle_preflip( 3843 dm->freesync_module, 3844 surface, 3845 new_stream, 3846 flip_timestamp_in_us, 3847 &vrr_params); 3848 3849 if (adev->family < AMDGPU_FAMILY_AI && 3850 amdgpu_dm_crtc_vrr_active(new_crtc_state)) { 3851 mod_freesync_handle_v_update(dm->freesync_module, 3852 new_stream, &vrr_params); 3853 3854 /* Need to call this before the frame ends. */ 3855 dc_stream_adjust_vmin_vmax(dm->dc, 3856 new_crtc_state->stream, 3857 &vrr_params.adjust); 3858 } 3859 } 3860 3861 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context; 3862 3863 if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) { 3864 pack_sdp_v1_3 = aconn->pack_sdp_v1_3; 3865 3866 if (aconn->vsdb_info.amd_vsdb_version == 1) 3867 packet_type = PACKET_TYPE_FS_V1; 3868 else if (aconn->vsdb_info.amd_vsdb_version == 2) 3869 packet_type = PACKET_TYPE_FS_V2; 3870 else if (aconn->vsdb_info.amd_vsdb_version == 3) 3871 packet_type = PACKET_TYPE_FS_V3; 3872 3873 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL, 3874 &new_stream->adaptive_sync_infopacket); 3875 } 3876 3877 mod_freesync_build_vrr_infopacket( 3878 dm->freesync_module, 3879 new_stream, 3880 &vrr_params, 3881 packet_type, 3882 TRANSFER_FUNC_UNKNOWN, 3883 &vrr_infopacket, 3884 pack_sdp_v1_3); 3885 3886 new_crtc_state->freesync_vrr_info_changed |= 3887 (memcmp(&new_crtc_state->vrr_infopacket, 3888 &vrr_infopacket, 3889 sizeof(vrr_infopacket)) != 0); 3890 3891 acrtc->dm_irq_params.vrr_params = vrr_params; 3892 new_crtc_state->vrr_infopacket = vrr_infopacket; 3893 3894 new_stream->vrr_infopacket = vrr_infopacket; 3895 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); 3896 3897 if (new_crtc_state->freesync_vrr_info_changed) 3898 drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", 3899 new_crtc_state->base.crtc->base.id, 3900 (int)new_crtc_state->base.vrr_enabled, 3901 (int)vrr_params.state); 3902 3903 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3904 } 3905 3906 static void update_stream_irq_parameters( 3907 struct amdgpu_display_manager *dm, 3908 struct dm_crtc_state *new_crtc_state) 3909 { 3910 struct dc_stream_state *new_stream = new_crtc_state->stream; 3911 struct mod_vrr_params vrr_params; 3912 struct mod_freesync_config config = new_crtc_state->freesync_config; 3913 struct amdgpu_device *adev = dm->adev; 3914 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc); 3915 unsigned long flags; 3916 3917 if (!new_stream) 3918 return; 3919 3920 /* 3921 * TODO: Determine why min/max totals and vrefresh can be 0 here. 3922 * For now it's sufficient to just guard against these conditions. 3923 */ 3924 if (!new_stream->timing.h_total || !new_stream->timing.v_total) 3925 return; 3926 3927 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3928 vrr_params = acrtc->dm_irq_params.vrr_params; 3929 3930 if (new_crtc_state->vrr_supported && 3931 config.min_refresh_in_uhz && 3932 config.max_refresh_in_uhz) { 3933 /* 3934 * if freesync compatible mode was set, config.state will be set 3935 * in atomic check 3936 */ 3937 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz && 3938 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) || 3939 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) { 3940 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz; 3941 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz; 3942 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz; 3943 vrr_params.state = VRR_STATE_ACTIVE_FIXED; 3944 } else { 3945 config.state = new_crtc_state->base.vrr_enabled ? 3946 VRR_STATE_ACTIVE_VARIABLE : 3947 VRR_STATE_INACTIVE; 3948 } 3949 } else { 3950 config.state = VRR_STATE_UNSUPPORTED; 3951 } 3952 3953 mod_freesync_build_vrr_params(dm->freesync_module, 3954 new_stream, 3955 &config, &vrr_params); 3956 3957 new_crtc_state->freesync_config = config; 3958 /* Copy state for access from DM IRQ handler */ 3959 acrtc->dm_irq_params.freesync_config = config; 3960 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes; 3961 acrtc->dm_irq_params.vrr_params = vrr_params; 3962 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3963 } 3964 3965 static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, 3966 struct dm_crtc_state *old_state, 3967 struct dm_crtc_state *new_state) 3968 { 3969 struct amdgpu_device *adev = dm->adev; 3970 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state); 3971 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state); 3972 3973 /* Only DCE gates vupdate on VRR, keep it enabled for DCN */ 3974 bool vrr_gates_vupdate = amdgpu_ip_version(adev, DCE_HWIP, 0) == 0; 3975 3976 if (!old_vrr_active && new_vrr_active) { 3977 /* Transition VRR inactive -> active: 3978 * While VRR is active, we must not disable vblank irq, as a 3979 * reenable after disable would compute bogus vblank/pflip 3980 * timestamps if it likely happened inside display front-porch. 3981 * 3982 * We also need vupdate irq for the actual core vblank handling 3983 * at end of vblank. 3984 */ 3985 if (vrr_gates_vupdate) 3986 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0); 3987 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0); 3988 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n", 3989 __func__, new_state->base.crtc->base.id); 3990 3991 scoped_guard(mutex, &dm->dc_lock) { 3992 dc_exit_ips_for_hw_access(dm->dc); 3993 amdgpu_dm_psr_set_event(dm, new_state->stream, true, 3994 psr_event_vrr_transition, true); 3995 amdgpu_dm_replay_set_event(dm, new_state->stream, true, 3996 replay_event_vrr, true); 3997 } 3998 } else if (old_vrr_active && !new_vrr_active) { 3999 /* Transition VRR active -> inactive: 4000 * Allow vblank irq disable again for fixed refresh rate. 4001 */ 4002 if (vrr_gates_vupdate) 4003 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0); 4004 drm_crtc_vblank_put(new_state->base.crtc); 4005 drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n", 4006 __func__, new_state->base.crtc->base.id); 4007 4008 scoped_guard(mutex, &dm->dc_lock) { 4009 dc_exit_ips_for_hw_access(dm->dc); 4010 amdgpu_dm_psr_set_event(dm, new_state->stream, false, 4011 psr_event_vrr_transition, false); 4012 amdgpu_dm_replay_set_event(dm, new_state->stream, false, 4013 replay_event_vrr, false); 4014 } 4015 } 4016 } 4017 4018 static void amdgpu_dm_commit_cursors(struct drm_atomic_commit *state) 4019 { 4020 struct drm_plane *plane; 4021 struct drm_plane_state *old_plane_state; 4022 int i; 4023 4024 /* 4025 * TODO: Make this per-stream so we don't issue redundant updates for 4026 * commits with multiple streams. 4027 */ 4028 for_each_old_plane_in_state(state, plane, old_plane_state, i) 4029 if (plane->type == DRM_PLANE_TYPE_CURSOR) 4030 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state); 4031 } 4032 4033 static inline uint32_t get_mem_type(struct drm_framebuffer *fb) 4034 { 4035 struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]); 4036 4037 return abo->tbo.resource ? abo->tbo.resource->mem_type : 0; 4038 } 4039 4040 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 4041 struct drm_plane_state *old_plane_state, 4042 struct dc_stream_update *update) 4043 { 4044 struct amdgpu_device *adev = drm_to_adev(plane->dev); 4045 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 4046 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; 4047 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 4048 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 4049 uint64_t address = afb ? afb->address : 0; 4050 struct dc_cursor_position position = {0}; 4051 struct dc_cursor_attributes attributes; 4052 int ret; 4053 4054 if (!plane->state->fb && !old_plane_state->fb) 4055 return; 4056 4057 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 4058 amdgpu_crtc->crtc_id, plane->state->crtc_w, 4059 plane->state->crtc_h); 4060 4061 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 4062 if (ret) 4063 return; 4064 4065 if (!position.enable) { 4066 /* turn off cursor */ 4067 if (crtc_state && crtc_state->stream) { 4068 dc_stream_set_cursor_position(crtc_state->stream, 4069 &position); 4070 update->cursor_position = &crtc_state->stream->cursor_position; 4071 } 4072 return; 4073 } 4074 4075 amdgpu_crtc->cursor_width = plane->state->crtc_w; 4076 amdgpu_crtc->cursor_height = plane->state->crtc_h; 4077 4078 memset(&attributes, 0, sizeof(attributes)); 4079 attributes.address.high_part = upper_32_bits(address); 4080 attributes.address.low_part = lower_32_bits(address); 4081 attributes.width = plane->state->crtc_w; 4082 attributes.height = plane->state->crtc_h; 4083 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 4084 attributes.rotation_angle = 0; 4085 attributes.attribute_flags.value = 0; 4086 4087 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 4088 * legacy gamma setup. 4089 */ 4090 if (crtc_state->cm_is_degamma_srgb && 4091 adev->dm.dc->caps.color.dpp.gamma_corr) 4092 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 4093 4094 if (afb) 4095 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; 4096 4097 if (crtc_state->stream) { 4098 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 4099 &attributes)) 4100 drm_err(adev_to_drm(adev), "DC failed to set cursor attributes\n"); 4101 4102 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 4103 4104 if (!dc_stream_set_cursor_position(crtc_state->stream, 4105 &position)) 4106 drm_err(adev_to_drm(adev), "DC failed to set cursor position\n"); 4107 4108 update->cursor_position = &crtc_state->stream->cursor_position; 4109 } 4110 } 4111 4112 static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, 4113 struct amdgpu_crtc *acrtc_attach, 4114 const struct dm_crtc_state *acrtc_state, 4115 const u64 current_ts) 4116 { 4117 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; 4118 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; 4119 struct amdgpu_dm_connector *aconn = 4120 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context; 4121 4122 /* Decrement skip count when SR is enabled and we're doing fast updates. */ 4123 if (acrtc_state->update_type == UPDATE_TYPE_FAST && 4124 (psr->psr_feature_enabled || pr->replay_feature_enabled)) { 4125 if (aconn->sr_skip_count > 0) 4126 aconn->sr_skip_count--; 4127 4128 /* Allow SR when skip count is 0. */ 4129 acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count; 4130 4131 /* 4132 * If sink supports PSR SU/Panel Replay, there is no need to rely on 4133 * a vblank event disable request to enable PSR/RP. PSR SU/RP 4134 * can be enabled immediately once OS demonstrates an 4135 * adequate number of fast atomic commits to notify KMD 4136 * of update events. 4137 * See `amdgpu_dm_crtc_vblank_control_worker()`. 4138 */ 4139 if (acrtc_attach->dm_irq_params.allow_sr_entry && 4140 (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) { 4141 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, 4142 psr_event_hw_programming, false); 4143 4144 amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, 4145 replay_event_hw_programming, false); 4146 } 4147 } else { 4148 acrtc_attach->dm_irq_params.allow_sr_entry = false; 4149 } 4150 } 4151 4152 static void dm_arm_vblank_event(struct amdgpu_crtc *acrtc, 4153 struct dm_crtc_state *acrtc_state, 4154 bool pflip_update, 4155 bool cursor_update) 4156 { 4157 assert_spin_locked(&acrtc->base.dev->event_lock); 4158 4159 if (!acrtc->base.state->event || acrtc_state->active_planes == 0) 4160 return; 4161 4162 if (pflip_update) { 4163 drm_crtc_vblank_get(&acrtc->base); 4164 WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); 4165 /* Arm flip completion handling and event delivery after programming. */ 4166 prepare_flip_isr(acrtc); 4167 } else if (cursor_update) { 4168 drm_crtc_vblank_get(&acrtc->base); 4169 acrtc->event = acrtc->base.state->event; 4170 acrtc->base.state->event = NULL; 4171 } 4172 } 4173 4174 static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, 4175 struct drm_device *dev, 4176 struct amdgpu_display_manager *dm, 4177 struct drm_crtc *pcrtc, 4178 bool wait_for_vblank) 4179 { 4180 u32 i; 4181 u64 timestamp_ns = ktime_get_ns(); 4182 struct drm_plane *plane; 4183 struct drm_plane_state *old_plane_state, *new_plane_state; 4184 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); 4185 struct drm_crtc_state *new_pcrtc_state = 4186 drm_atomic_get_new_crtc_state(state, pcrtc); 4187 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); 4188 struct dm_crtc_state *dm_old_crtc_state = 4189 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc)); 4190 int planes_count = 0, vpos, hpos; 4191 unsigned long flags; 4192 u32 target_vblank, last_flip_vblank; 4193 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); 4194 bool cursor_update = false; 4195 bool pflip_present = false; 4196 bool immediate_flip = false; 4197 bool flip_latched_during_prog = false; 4198 bool dirty_rects_changed = false; 4199 bool updated_planes_and_streams = false; 4200 struct { 4201 struct dc_surface_update surface_updates[MAX_SURFACES]; 4202 struct dc_plane_info plane_infos[MAX_SURFACES]; 4203 struct dc_scaling_info scaling_infos[MAX_SURFACES]; 4204 struct dc_flip_addrs flip_addrs[MAX_SURFACES]; 4205 struct dc_stream_update stream_update; 4206 } *bundle; 4207 4208 bundle = kzalloc_obj(*bundle); 4209 4210 if (!bundle) { 4211 drm_err(dev, "Failed to allocate update bundle\n"); 4212 goto cleanup; 4213 } 4214 4215 /* 4216 * Disable the cursor first if we're disabling all the planes. 4217 * It'll remain on the screen after the planes are re-enabled 4218 * if we don't. 4219 * 4220 * If the cursor is transitioning from native to overlay mode, the 4221 * native cursor needs to be disabled first. 4222 */ 4223 if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE && 4224 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4225 struct dc_cursor_position cursor_position = {0}; 4226 4227 if (!dc_stream_set_cursor_position(acrtc_state->stream, 4228 &cursor_position)) 4229 drm_err(dev, "DC failed to disable native cursor\n"); 4230 4231 bundle->stream_update.cursor_position = 4232 &acrtc_state->stream->cursor_position; 4233 } 4234 4235 if (acrtc_state->active_planes == 0 && 4236 dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4237 amdgpu_dm_commit_cursors(state); 4238 4239 /* update planes when needed */ 4240 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 4241 struct drm_crtc *crtc = new_plane_state->crtc; 4242 struct drm_crtc_state *new_crtc_state; 4243 struct drm_framebuffer *fb = new_plane_state->fb; 4244 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb; 4245 bool plane_needs_flip; 4246 struct dc_plane_state *dc_plane; 4247 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); 4248 4249 /* Cursor plane is handled after stream updates */ 4250 if (plane->type == DRM_PLANE_TYPE_CURSOR && 4251 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) { 4252 if ((fb && crtc == pcrtc) || 4253 (old_plane_state->fb && old_plane_state->crtc == pcrtc)) { 4254 cursor_update = true; 4255 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) 4256 amdgpu_dm_update_cursor(plane, old_plane_state, &bundle->stream_update); 4257 } 4258 4259 continue; 4260 } 4261 4262 if (!fb || !crtc || pcrtc != crtc) 4263 continue; 4264 4265 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 4266 if (!new_crtc_state->active) 4267 continue; 4268 4269 dc_plane = dm_new_plane_state->dc_state; 4270 if (!dc_plane) 4271 continue; 4272 4273 bundle->surface_updates[planes_count].surface = dc_plane; 4274 if (new_pcrtc_state->color_mgmt_changed) { 4275 bundle->surface_updates[planes_count].gamma = &dc_plane->gamma_correction; 4276 bundle->surface_updates[planes_count].in_transfer_func = &dc_plane->in_transfer_func; 4277 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; 4278 bundle->surface_updates[planes_count].hdr_mult = dc_plane->hdr_mult; 4279 bundle->surface_updates[planes_count].cm = &dc_plane->cm; 4280 } 4281 4282 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, 4283 &bundle->scaling_infos[planes_count]); 4284 4285 bundle->surface_updates[planes_count].scaling_info = 4286 &bundle->scaling_infos[planes_count]; 4287 4288 plane_needs_flip = old_plane_state->fb && new_plane_state->fb; 4289 4290 pflip_present = pflip_present || plane_needs_flip; 4291 4292 if (!plane_needs_flip) { 4293 planes_count += 1; 4294 continue; 4295 } 4296 4297 fill_dc_plane_info_and_addr( 4298 dm->adev, new_plane_state, 4299 afb->tiling_flags, 4300 &bundle->plane_infos[planes_count], 4301 &bundle->flip_addrs[planes_count].address, 4302 afb->tmz_surface); 4303 4304 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", 4305 new_plane_state->plane->index, 4306 bundle->plane_infos[planes_count].dcc.enable); 4307 4308 bundle->surface_updates[planes_count].plane_info = 4309 &bundle->plane_infos[planes_count]; 4310 4311 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || 4312 acrtc_state->stream->link->replay_settings.replay_feature_enabled) { 4313 fill_dc_dirty_rects(plane, old_plane_state, 4314 new_plane_state, new_crtc_state, 4315 &bundle->flip_addrs[planes_count], 4316 acrtc_state->stream->link->psr_settings.psr_version == 4317 DC_PSR_VERSION_SU_1, 4318 &dirty_rects_changed); 4319 4320 /* 4321 * If the dirty regions changed, PSR-SU need to be disabled temporarily 4322 * and enabled it again after dirty regions are stable to avoid video glitch. 4323 * PSR-SU will be enabled in 4324 * amdgpu_dm_crtc_vblank_control_worker() if user 4325 * pause the video during the PSR-SU was disabled. 4326 */ 4327 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && 4328 acrtc_attach->dm_irq_params.allow_sr_entry && 4329 dirty_rects_changed) { 4330 mutex_lock(&dm->dc_lock); 4331 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = 4332 timestamp_ns; 4333 dc_exit_ips_for_hw_access(dm->dc); 4334 amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, 4335 psr_event_hw_programming, true); 4336 mutex_unlock(&dm->dc_lock); 4337 } 4338 } 4339 4340 /* 4341 * Only allow immediate flips for fast updates that don't 4342 * change memory domain, FB pitch, DCC state, rotation or 4343 * mirroring. 4344 * 4345 * dm_crtc_helper_atomic_check() only accepts async flips with 4346 * fast updates. 4347 */ 4348 if (crtc->state->async_flip && 4349 (acrtc_state->update_type != UPDATE_TYPE_FAST || 4350 get_mem_type(old_plane_state->fb) != get_mem_type(fb))) 4351 drm_warn_once(state->dev, 4352 "[PLANE:%d:%s] async flip with non-fast update\n", 4353 plane->base.id, plane->name); 4354 4355 bundle->flip_addrs[planes_count].flip_immediate = 4356 crtc->state->async_flip && 4357 acrtc_state->update_type == UPDATE_TYPE_FAST && 4358 get_mem_type(old_plane_state->fb) == get_mem_type(fb); 4359 4360 immediate_flip |= bundle->flip_addrs[planes_count].flip_immediate; 4361 4362 timestamp_ns = ktime_get_ns(); 4363 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000); 4364 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count]; 4365 bundle->surface_updates[planes_count].surface = dc_plane; 4366 4367 if (!bundle->surface_updates[planes_count].surface) { 4368 drm_err(dev, "No surface for CRTC: id=%d\n", 4369 acrtc_attach->crtc_id); 4370 continue; 4371 } 4372 4373 if (plane == pcrtc->primary) 4374 update_freesync_state_on_stream( 4375 dm, 4376 acrtc_state, 4377 acrtc_state->stream, 4378 dc_plane, 4379 bundle->flip_addrs[planes_count].flip_timestamp_in_us); 4380 4381 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n", 4382 __func__, 4383 bundle->flip_addrs[planes_count].address.grph.addr.high_part, 4384 bundle->flip_addrs[planes_count].address.grph.addr.low_part); 4385 4386 planes_count += 1; 4387 4388 } 4389 4390 if (pflip_present) { 4391 if (!vrr_active) { 4392 /* Use old throttling in non-vrr fixed refresh rate mode 4393 * to keep flip scheduling based on target vblank counts 4394 * working in a backwards compatible way, e.g., for 4395 * clients using the GLX_OML_sync_control extension or 4396 * DRI3/Present extension with defined target_msc. 4397 */ 4398 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc); 4399 } else { 4400 /* For variable refresh rate mode only: 4401 * Get vblank of last completed flip to avoid > 1 vrr 4402 * flips per video frame by use of throttling, but allow 4403 * flip programming anywhere in the possibly large 4404 * variable vrr vblank interval for fine-grained flip 4405 * timing control and more opportunity to avoid stutter 4406 * on late submission of flips. 4407 */ 4408 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4409 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank; 4410 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4411 } 4412 4413 target_vblank = last_flip_vblank + wait_for_vblank; 4414 4415 /* 4416 * Wait until we're out of the vertical blank period before the one 4417 * targeted by the flip 4418 */ 4419 while ((acrtc_attach->enabled && 4420 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id, 4421 0, &vpos, &hpos, NULL, 4422 NULL, &pcrtc->hwmode) 4423 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 4424 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 4425 (int)(target_vblank - 4426 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) { 4427 usleep_range(1000, 1100); 4428 } 4429 4430 if (acrtc_state->stream) { 4431 if (acrtc_state->freesync_vrr_info_changed) 4432 bundle->stream_update.vrr_infopacket = 4433 &acrtc_state->stream->vrr_infopacket; 4434 } 4435 } 4436 4437 /* 4438 * DCE depends on a combination of GRPH_FLIP, VLINE0, and VUPDATE for 4439 * event delivery. Only GRPH_FLIP handler can send pflip events, and it 4440 * only fires if HW latched to the flip. Maintain legacy behavior by 4441 * arming event before programming. 4442 */ 4443 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) { 4444 scoped_guard(spinlock_irqsave, &pcrtc->dev->event_lock) { 4445 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4446 pflip_present, cursor_update); 4447 } 4448 } 4449 4450 /* Update the planes if changed or disable if we don't have any. */ 4451 if ((planes_count || acrtc_state->active_planes == 0) && 4452 acrtc_state->stream) { 4453 /* 4454 * If PSR or idle optimizations are enabled then flush out 4455 * any pending work before hardware programming. 4456 */ 4457 if (dm->vblank_control_workqueue) 4458 flush_workqueue(dm->vblank_control_workqueue); 4459 4460 bundle->stream_update.stream = acrtc_state->stream; 4461 if (new_pcrtc_state->mode_changed) { 4462 bundle->stream_update.src = acrtc_state->stream->src; 4463 bundle->stream_update.dst = acrtc_state->stream->dst; 4464 } 4465 4466 if (new_pcrtc_state->color_mgmt_changed) { 4467 /* 4468 * TODO: This isn't fully correct since we've actually 4469 * already modified the stream in place. 4470 */ 4471 bundle->stream_update.gamut_remap = 4472 &acrtc_state->stream->gamut_remap_matrix; 4473 bundle->stream_update.output_csc_transform = 4474 &acrtc_state->stream->csc_color_matrix; 4475 bundle->stream_update.out_transfer_func = 4476 &acrtc_state->stream->out_transfer_func; 4477 bundle->stream_update.lut3d_func = 4478 (struct dc_3dlut *) acrtc_state->stream->lut3d_func; 4479 bundle->stream_update.func_shaper = 4480 (struct dc_transfer_func *) acrtc_state->stream->func_shaper; 4481 } 4482 4483 acrtc_state->stream->abm_level = acrtc_state->abm_level; 4484 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) 4485 bundle->stream_update.abm_level = &acrtc_state->abm_level; 4486 4487 /* 4488 * If FreeSync state on the stream has changed then we need to 4489 * re-adjust the min/max bounds now that DC doesn't handle this 4490 * as part of commit. 4491 */ 4492 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) { 4493 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4494 dc_stream_adjust_vmin_vmax( 4495 dm->dc, acrtc_state->stream, 4496 &acrtc_attach->dm_irq_params.vrr_params.adjust); 4497 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4498 } 4499 mutex_lock(&dm->dc_lock); 4500 update_planes_and_stream_adapter(dm->dc, 4501 acrtc_state->update_type, 4502 planes_count, 4503 acrtc_state->stream, 4504 &bundle->stream_update, 4505 bundle->surface_updates); 4506 updated_planes_and_streams = true; 4507 4508 /** 4509 * Enable or disable the interrupts on the backend. 4510 * 4511 * Most pipes are put into power gating when unused. 4512 * 4513 * When power gating is enabled on a pipe we lose the 4514 * interrupt enablement state when power gating is disabled. 4515 * 4516 * So we need to update the IRQ control state in hardware 4517 * whenever the pipe turns on (since it could be previously 4518 * power gated) or off (since some pipes can't be power gated 4519 * on some ASICs). 4520 */ 4521 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes) 4522 dm_update_pflip_irq_state(drm_to_adev(dev), 4523 acrtc_attach); 4524 amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state, 4525 timestamp_ns); 4526 mutex_unlock(&dm->dc_lock); 4527 } 4528 4529 /* 4530 * Update cursor state *after* programming all the planes. 4531 * This avoids redundant programming in the case where we're going 4532 * to be disabling a single plane - those pipes are being disabled. 4533 */ 4534 if (acrtc_state->active_planes && 4535 (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) && 4536 acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) 4537 amdgpu_dm_commit_cursors(state); 4538 4539 /* 4540 * DCN specific vblank handling 4541 * ============================ 4542 * 4543 * With the event_lock held, arm the vblank event, and determine whether 4544 * deliver it immediately, or in VUPDATE_NO_LOCK IRQ (i.e. HW latch 4545 * point) handler. Do this *after* programming so that the IRQ handler 4546 * will not deliver the event before HW laches onto the programmed 4547 * values: 4548 * 4549 * Commit thread IRQ handler HW 4550 * ----------------------------------------------------------------- 4551 * arm_vblank_event() 4552 * vupdate() 4553 * vupdate_handler() 4554 * cook_timestamp() 4555 * # prev flip already latched, 4556 * # so flip_latched == true. 4557 * if event_armed && flip_latched: 4558 * send_vblank_event() 4559 * # sent before latch, **BAD!** 4560 * hw_program() 4561 * vupdate() 4562 * **latch** 4563 * 4564 * There's a consequence of arming after: it's possible for HW to latch 4565 * between start of HW programming and acrtc->event/pflip_status arming. 4566 * When this happens, the IRQ handler will send the event on the next 4567 * immediate latch point, even though HW has already latched. This is 4568 * handled by optimistically checking for HW latch after programming, 4569 * and if latched, send the event immediately: 4570 * 4571 * Commit thread IRQ handler HW 4572 * ----------------------------------------------------------------- 4573 * hw_program() 4574 * vupdate() 4575 * **latch** 4576 * vupdate_handler() 4577 * cook_timestamp() 4578 * # event_armed == false 4579 * # **no event sent!** 4580 * arm_vblank_event() 4581 * if flip_latched: 4582 * **send_vblank_event()** 4583 * disarm_vblank_event() 4584 * 4585 * The IRQ handler is expected to cook the timestamp, but we need to 4586 * cook the timestamp before optimistic sending as well. That's because 4587 * the following sequence is possible: 4588 * 4589 * Commit thread IRQ handler HW 4590 * ----------------------------------------------------------------- 4591 * hw_program() 4592 * arm_vblank_event() 4593 * vupdate() 4594 * **latch** 4595 * if flip_latched: 4596 * # Need cook before send! 4597 * **cook_timestamp()** 4598 * send_vblank_event() 4599 * disarm_vblank_event() 4600 * vupdate_handler() 4601 * cook_timestamp() 4602 * # event_armed == false 4603 * # no event sent! 4604 * 4605 * Cooking twice is OK, since DRM scanout accurate timestamps report A) 4606 * the previous vactive start if currently in vactive, or B) the next 4607 * vactive start if currently in vblank (see &get_vblank_counter). 'A)' 4608 * is what we want for the optimistic send, and for 'B)', we'll cook a 4609 * timestamp no later than the next IRQ handler run. 4610 * 4611 * The more correct fix is to wrap programming and arming with the 4612 * event_lock and thus serializing it with the IRQ handler. However, 4613 * there are various sleep-waits within 4614 * update_planes_and_stream_adapter() that makes spin locking illegal. 4615 * And on full updates, it can take 1-2 frame-times to return (see 4616 * commit_planes_for_stream). 4617 * 4618 * On DCE, GRPH_PFLIP IRQ is used and takes care of this. 4619 */ 4620 if (amdgpu_ip_version(dm->adev, DCE_HWIP, 0) != 0) { 4621 spin_lock_irqsave(&pcrtc->dev->event_lock, flags); 4622 4623 if (updated_planes_and_streams) { 4624 flip_latched_during_prog = 4625 !dc_get_flip_pending_on_otg(dm->dc, acrtc_attach->otg_inst); 4626 } 4627 4628 dm_arm_vblank_event(acrtc_attach, acrtc_state, 4629 pflip_present, cursor_update); 4630 4631 /* 4632 * Deliver the event immediately on immediate flip, or on a 4633 * update that has already latched. 4634 */ 4635 if ((immediate_flip || flip_latched_during_prog) && 4636 acrtc_attach->pflip_status == AMDGPU_FLIP_SUBMITTED && 4637 acrtc_attach->event) { 4638 drm_crtc_accurate_vblank_count(&acrtc_attach->base); 4639 drm_crtc_send_vblank_event(&acrtc_attach->base, 4640 acrtc_attach->event); 4641 acrtc_attach->event = NULL; 4642 drm_crtc_vblank_put(&acrtc_attach->base); 4643 acrtc_attach->pflip_status = AMDGPU_FLIP_NONE; 4644 } 4645 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); 4646 } 4647 4648 cleanup: 4649 kfree(bundle); 4650 } 4651 4652 /* 4653 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC 4654 * @crtc_state: the DRM CRTC state 4655 * @stream_state: the DC stream state. 4656 * 4657 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring 4658 * a dc_stream_state's flags in sync with a drm_crtc_state's flags. 4659 */ 4660 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, 4661 struct dc_stream_state *stream_state) 4662 { 4663 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); 4664 } 4665 4666 /** 4667 * amdgpu_dm_crtc_complete_writeback - finish a pending writeback job 4668 * @acrtc: the CRTC whose pending writeback should be completed 4669 * 4670 * Clears the pending state, signals the writeback out fence and releases the 4671 * vblank reference taken in dm_set_writeback() while the writeback was armed. 4672 * The pending flag is tested and cleared under the writeback job lock, so this 4673 * is safe to call concurrently from the completion vblank IRQ 4674 * (dm_crtc_high_irq()) and from the writeback teardown path 4675 * (dm_clear_writeback()); only the caller that observes the pending job 4676 * performs the completion. 4677 * 4678 * Return: true if a pending writeback job was completed by this call. 4679 */ 4680 bool amdgpu_dm_crtc_complete_writeback(struct amdgpu_crtc *acrtc) 4681 { 4682 unsigned long flags; 4683 bool pending; 4684 4685 if (!acrtc->wb_conn) 4686 return false; 4687 4688 spin_lock_irqsave(&acrtc->wb_conn->job_lock, flags); 4689 pending = acrtc->wb_pending; 4690 acrtc->wb_pending = false; 4691 acrtc->wb_frame_done = false; 4692 spin_unlock_irqrestore(&acrtc->wb_conn->job_lock, flags); 4693 4694 if (!pending) 4695 return false; 4696 4697 drm_writeback_signal_completion(acrtc->wb_conn, 0); 4698 drm_crtc_vblank_put(&acrtc->base); 4699 4700 return true; 4701 } 4702 EXPORT_IF_KUNIT(amdgpu_dm_crtc_complete_writeback); 4703 4704 static void dm_clear_writeback(struct amdgpu_display_manager *dm, 4705 struct amdgpu_crtc *acrtc, 4706 struct dm_crtc_state *crtc_state) 4707 { 4708 dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0); 4709 4710 /* 4711 * If the writeback is still pending when it is torn down (its 4712 * completion vblank IRQ never fired), signal the out fence so a 4713 * waiting client does not stall and release the vblank reference 4714 * taken in dm_set_writeback(). 4715 */ 4716 amdgpu_dm_crtc_complete_writeback(acrtc); 4717 } 4718 4719 /** 4720 * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset 4721 * @state: the drm atomic state 4722 * @dm: the display manager to update mod_power on 4723 * 4724 * Notify mod_power of stream changes on modeset events, and disable PSR/Replay 4725 * in preparation for hardware programming. See also 4726 * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup. 4727 */ 4728 static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, 4729 struct amdgpu_display_manager *dm) 4730 { 4731 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4732 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4733 struct amdgpu_dm_connector *aconnector; 4734 struct drm_crtc *crtc; 4735 int i = 0; 4736 4737 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4738 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4739 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4740 4741 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4742 continue; 4743 4744 /* 4745 * Update mod_power on modeset event in preparation for hw 4746 * programming. Always use the old stream, since it would have 4747 * been previously added to mod_power. If old stream is null (on 4748 * crtc enable, for example), mod_power will no-op, which is the 4749 * desried behavior. 4750 */ 4751 if (old_crtc_state->active) { 4752 scoped_guard(mutex, &dm->dc_lock) { 4753 dc_exit_ips_for_hw_access(dm->dc); 4754 amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, 4755 psr_event_hw_programming, true); 4756 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, 4757 replay_event_hw_programming, true); 4758 amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, 4759 replay_event_general_ui, false); 4760 } 4761 } 4762 4763 if (new_crtc_state->active) { 4764 aconnector = (struct amdgpu_dm_connector *) 4765 dm_new_crtc_state->stream->dm_stream_context; 4766 if (old_crtc_state->active) { 4767 mod_power_replace_stream(dm->power_module, 4768 dm_old_crtc_state->stream, 4769 dm_new_crtc_state->stream, 4770 &aconnector->psr_caps); 4771 } else { 4772 mod_power_add_stream(dm->power_module, 4773 dm_new_crtc_state->stream, 4774 &aconnector->psr_caps); 4775 } 4776 } else if (old_crtc_state->active) { 4777 mod_power_remove_stream(dm->power_module, 4778 dm_old_crtc_state->stream); 4779 } 4780 } 4781 } 4782 4783 /** 4784 * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset 4785 * @state: the drm atomic state 4786 * @dm: the display manager to update mod_power on 4787 * 4788 * Notify mod_power of mode_change. This needs to be done after dc_stream 4789 * updates have been committed, and VRR parameters have been updated. 4790 */ 4791 static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, 4792 struct amdgpu_display_manager *dm) 4793 { 4794 struct dm_crtc_state *dm_new_crtc_state; 4795 struct drm_crtc_state *new_crtc_state; 4796 struct amdgpu_crtc *acrtc; 4797 struct drm_crtc *crtc; 4798 int i = 0; 4799 4800 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 4801 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4802 acrtc = to_amdgpu_crtc(crtc); 4803 4804 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 4805 continue; 4806 4807 if (new_crtc_state->active) { 4808 amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream, 4809 &acrtc->dm_irq_params.vrr_params); 4810 mod_power_notify_mode_change(dm->power_module, 4811 dm_new_crtc_state->stream, 4812 false); 4813 4814 /* 4815 * Block PSR / Replay on the new stream until display settles post-modeset. 4816 * These events will be cleared by amdgpu_dm_enable_self_refresh() once 4817 * allow_sr_entry becomes true. 4818 */ 4819 amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, 4820 psr_event_hw_programming, true); 4821 4822 amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, 4823 replay_event_hw_programming | replay_event_general_ui, 4824 true); 4825 } 4826 } 4827 4828 } 4829 4830 static void amdgpu_dm_commit_streams(struct drm_atomic_commit *state, 4831 struct dc_state *dc_state) 4832 { 4833 struct drm_device *dev = state->dev; 4834 struct amdgpu_device *adev = drm_to_adev(dev); 4835 struct amdgpu_display_manager *dm = &adev->dm; 4836 struct drm_crtc *crtc; 4837 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 4838 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 4839 struct drm_connector_state *old_con_state; 4840 struct drm_connector *connector; 4841 bool mode_set_reset_required = false; 4842 u32 i; 4843 struct dc_commit_streams_params params = {dc_state->streams, dc_state->stream_count}; 4844 bool set_backlight_level = false; 4845 4846 /* Disable writeback */ 4847 for_each_old_connector_in_state(state, connector, old_con_state, i) { 4848 struct dm_connector_state *dm_old_con_state; 4849 struct amdgpu_crtc *acrtc; 4850 4851 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 4852 continue; 4853 4854 old_crtc_state = NULL; 4855 4856 dm_old_con_state = to_dm_connector_state(old_con_state); 4857 if (!dm_old_con_state->base.crtc) 4858 continue; 4859 4860 acrtc = to_amdgpu_crtc(dm_old_con_state->base.crtc); 4861 if (acrtc) 4862 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 4863 4864 if (!acrtc || !acrtc->wb_enabled) 4865 continue; 4866 4867 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4868 4869 dm_clear_writeback(dm, acrtc, dm_old_crtc_state); 4870 acrtc->wb_enabled = false; 4871 } 4872 4873 amdgpu_dm_mod_power_update_streams(state, dm); 4874 4875 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 4876 new_crtc_state, i) { 4877 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4878 4879 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4880 4881 if (old_crtc_state->active && 4882 (!new_crtc_state->active || 4883 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 4884 manage_dm_interrupts(adev, acrtc, NULL); 4885 dc_stream_release(dm_old_crtc_state->stream); 4886 } 4887 } 4888 4889 drm_atomic_helper_calc_timestamping_constants(state); 4890 4891 /* update changed items */ 4892 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 4893 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4894 4895 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 4896 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 4897 4898 drm_dbg_state(state->dev, 4899 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 4900 acrtc->crtc_id, 4901 new_crtc_state->enable, 4902 new_crtc_state->active, 4903 new_crtc_state->planes_changed, 4904 new_crtc_state->mode_changed, 4905 new_crtc_state->active_changed, 4906 new_crtc_state->connectors_changed); 4907 4908 /* Disable cursor if disabling crtc */ 4909 if (old_crtc_state->active && !new_crtc_state->active) { 4910 struct dc_cursor_position position; 4911 4912 memset(&position, 0, sizeof(position)); 4913 mutex_lock(&dm->dc_lock); 4914 dc_exit_ips_for_hw_access(dm->dc); 4915 dc_stream_program_cursor_position(dm_old_crtc_state->stream, &position); 4916 mutex_unlock(&dm->dc_lock); 4917 } 4918 4919 /* Copy all transient state flags into dc state */ 4920 if (dm_new_crtc_state->stream) { 4921 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, 4922 dm_new_crtc_state->stream); 4923 } 4924 4925 /* handles headless hotplug case, updating new_state and 4926 * aconnector as needed 4927 */ 4928 4929 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { 4930 4931 drm_dbg_atomic(dev, 4932 "Atomic commit: SET crtc id %d: [%p]\n", 4933 acrtc->crtc_id, acrtc); 4934 4935 if (!dm_new_crtc_state->stream) { 4936 /* 4937 * this could happen because of issues with 4938 * userspace notifications delivery. 4939 * In this case userspace tries to set mode on 4940 * display which is disconnected in fact. 4941 * dc_sink is NULL in this case on aconnector. 4942 * We expect reset mode will come soon. 4943 * 4944 * This can also happen when unplug is done 4945 * during resume sequence ended 4946 * 4947 * In this case, we want to pretend we still 4948 * have a sink to keep the pipe running so that 4949 * hw state is consistent with the sw state 4950 */ 4951 drm_dbg_atomic(dev, 4952 "Failed to create new stream for crtc %d\n", 4953 acrtc->base.base.id); 4954 continue; 4955 } 4956 4957 if (dm_old_crtc_state->stream) 4958 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4959 4960 pm_runtime_get_noresume(dev->dev); 4961 4962 acrtc->enabled = true; 4963 acrtc->hw_mode = new_crtc_state->mode; 4964 crtc->hwmode = new_crtc_state->mode; 4965 mode_set_reset_required = true; 4966 set_backlight_level = true; 4967 } else if (modereset_required(new_crtc_state)) { 4968 drm_dbg_atomic(dev, 4969 "Atomic commit: RESET. crtc id %d:[%p]\n", 4970 acrtc->crtc_id, acrtc); 4971 /* i.e. reset mode */ 4972 if (dm_old_crtc_state->stream) 4973 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 4974 4975 mode_set_reset_required = true; 4976 } 4977 } /* for_each_crtc_in_state() */ 4978 4979 /* if there mode set or reset, flush vblank work queue */ 4980 if (mode_set_reset_required) { 4981 if (dm->vblank_control_workqueue) 4982 flush_workqueue(dm->vblank_control_workqueue); 4983 } 4984 4985 dm_enable_per_frame_crtc_master_sync(dc_state); 4986 mutex_lock(&dm->dc_lock); 4987 dc_exit_ips_for_hw_access(dm->dc); 4988 WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); 4989 4990 bool frl_stream_found = false; 4991 4992 for (i = 0; i < params.stream_count; i++) { 4993 struct dc_stream_state *stream = params.streams[i]; 4994 4995 if (stream->signal == SIGNAL_TYPE_HDMI_FRL) { 4996 frl_stream_found = true; 4997 break; 4998 } 4999 } 5000 if (frl_stream_found) { 5001 if (queue_delayed_work(dm->hdmi_frl_status_polling_wq, 5002 &dm->hdmi_frl_status_polling_work, 5003 msecs_to_jiffies(dm->hdmi_frl_status_polling_delay_ms))) 5004 drm_dbg_kms(dev, "200ms frl status polling starts ...\n"); 5005 } else { 5006 if (cancel_delayed_work_sync(&dm->hdmi_frl_status_polling_work)) 5007 drm_dbg_kms(dev, "200ms frl status polling stops ...\n"); 5008 } 5009 /* Allow idle optimization when vblank count is 0 for display off */ 5010 if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) 5011 dc_allow_idle_optimizations(dm->dc, true); 5012 mutex_unlock(&dm->dc_lock); 5013 5014 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5015 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5016 5017 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5018 5019 if (dm_new_crtc_state->stream != NULL) { 5020 const struct dc_stream_status *status = 5021 dc_stream_get_status(dm_new_crtc_state->stream); 5022 5023 if (!status) 5024 status = dc_state_get_stream_status(dc_state, 5025 dm_new_crtc_state->stream); 5026 if (!status) 5027 drm_err(dev, 5028 "got no status for stream %p on acrtc%p\n", 5029 dm_new_crtc_state->stream, acrtc); 5030 else 5031 acrtc->otg_inst = status->primary_otg_inst; 5032 } 5033 } 5034 5035 /* During boot up and resume the DC layer will reset the panel brightness 5036 * to fix a flicker issue. 5037 * It will cause the dm->actual_brightness is not the current panel brightness 5038 * level. (the dm->brightness is the correct panel level) 5039 * So we set the backlight level with dm->brightness value after set mode 5040 */ 5041 if (set_backlight_level) { 5042 for (i = 0; i < dm->num_of_edps; i++) { 5043 if (dm->backlight_dev[i]) 5044 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5045 } 5046 } 5047 } 5048 5049 static void dm_set_writeback(struct amdgpu_display_manager *dm, 5050 struct dm_crtc_state *crtc_state, 5051 struct drm_connector *connector, 5052 struct drm_connector_state *new_con_state) 5053 { 5054 struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); 5055 struct amdgpu_device *adev = dm->adev; 5056 struct amdgpu_crtc *acrtc; 5057 struct dc_writeback_info *wb_info; 5058 struct pipe_ctx *pipe = NULL; 5059 struct amdgpu_framebuffer *afb; 5060 int i = 0; 5061 5062 wb_info = kzalloc_obj(*wb_info); 5063 if (!wb_info) { 5064 drm_err(adev_to_drm(adev), "Failed to allocate wb_info\n"); 5065 return; 5066 } 5067 5068 acrtc = to_amdgpu_crtc(wb_conn->encoder.crtc); 5069 if (!acrtc) { 5070 drm_err(adev_to_drm(adev), "no amdgpu_crtc found\n"); 5071 kfree(wb_info); 5072 return; 5073 } 5074 5075 afb = to_amdgpu_framebuffer(new_con_state->writeback_job->fb); 5076 if (!afb) { 5077 drm_err(adev_to_drm(adev), "No amdgpu_framebuffer found\n"); 5078 kfree(wb_info); 5079 return; 5080 } 5081 5082 for (i = 0; i < MAX_PIPES; i++) { 5083 if (dm->dc->current_state->res_ctx.pipe_ctx[i].stream == crtc_state->stream) { 5084 pipe = &dm->dc->current_state->res_ctx.pipe_ctx[i]; 5085 break; 5086 } 5087 } 5088 5089 /* fill in wb_info */ 5090 wb_info->wb_enabled = true; 5091 5092 wb_info->dwb_pipe_inst = 0; 5093 wb_info->dwb_params.dwbscl_black_color = 0; 5094 wb_info->dwb_params.hdr_mult = 0x1F000; 5095 wb_info->dwb_params.csc_params.gamut_adjust_type = CM_GAMUT_ADJUST_TYPE_BYPASS; 5096 wb_info->dwb_params.csc_params.gamut_coef_format = CM_GAMUT_REMAP_COEF_FORMAT_S2_13; 5097 wb_info->dwb_params.output_depth = DWB_OUTPUT_PIXEL_DEPTH_10BPC; 5098 wb_info->dwb_params.cnv_params.cnv_out_bpc = DWB_CNV_OUT_BPC_10BPC; 5099 5100 /* width & height from crtc */ 5101 wb_info->dwb_params.cnv_params.src_width = acrtc->base.mode.crtc_hdisplay; 5102 wb_info->dwb_params.cnv_params.src_height = acrtc->base.mode.crtc_vdisplay; 5103 wb_info->dwb_params.dest_width = acrtc->base.mode.crtc_hdisplay; 5104 wb_info->dwb_params.dest_height = acrtc->base.mode.crtc_vdisplay; 5105 5106 wb_info->dwb_params.cnv_params.crop_en = false; 5107 wb_info->dwb_params.stereo_params.stereo_enabled = false; 5108 5109 wb_info->dwb_params.cnv_params.out_max_pix_val = 0x3ff; // 10 bits 5110 wb_info->dwb_params.cnv_params.out_min_pix_val = 0; 5111 wb_info->dwb_params.cnv_params.fc_out_format = DWB_OUT_FORMAT_32BPP_ARGB; 5112 wb_info->dwb_params.cnv_params.out_denorm_mode = DWB_OUT_DENORM_BYPASS; 5113 5114 wb_info->dwb_params.out_format = dwb_scaler_mode_bypass444; 5115 5116 wb_info->dwb_params.capture_rate = dwb_capture_rate_0; 5117 5118 wb_info->dwb_params.scaler_taps.h_taps = 1; 5119 wb_info->dwb_params.scaler_taps.v_taps = 1; 5120 wb_info->dwb_params.scaler_taps.h_taps_c = 1; 5121 wb_info->dwb_params.scaler_taps.v_taps_c = 1; 5122 wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; 5123 5124 wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; 5125 wb_info->mcif_buf_params.chroma_pitch = afb->base.pitches[1]; 5126 5127 for (i = 0; i < DWB_MCIF_BUF_COUNT; i++) { 5128 wb_info->mcif_buf_params.luma_address[i] = afb->address; 5129 wb_info->mcif_buf_params.chroma_address[i] = 0; 5130 } 5131 5132 wb_info->mcif_buf_params.p_vmid = 1; 5133 if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) { 5134 wb_info->mcif_warmup_params.start_address.quad_part = afb->address; 5135 wb_info->mcif_warmup_params.region_size = 5136 wb_info->mcif_buf_params.luma_pitch * wb_info->dwb_params.dest_height; 5137 } 5138 wb_info->mcif_warmup_params.p_vmid = 1; 5139 wb_info->writeback_source_plane = pipe->plane_state; 5140 5141 dc_stream_add_writeback(dm->dc, crtc_state->stream, wb_info); 5142 5143 acrtc->wb_conn = wb_conn; 5144 drm_writeback_queue_job(wb_conn, new_con_state); 5145 5146 /* 5147 * Writeback completion is detected in the CRTC vblank IRQ 5148 * (dm_crtc_high_irq()). Take a vblank reference so the vblank interrupt 5149 * stays enabled while the writeback is pending; otherwise a 5150 * writeback-only commit right after drm_crtc_vblank_on() (e.g. 5151 * re-enabling a CRTC that was disabled) has no other vblank reference, 5152 * the IRQ never fires and the out fence times out. The matching put 5153 * happens once completion is signalled in dm_crtc_high_irq(), or when 5154 * the writeback is torn down in dm_clear_writeback(). 5155 * 5156 * Arm wb_pending only after the reference is held so the completion IRQ 5157 * cannot run its matching vblank_put before this get. 5158 */ 5159 WARN_ON(drm_crtc_vblank_get(&acrtc->base)); 5160 acrtc->wb_frame_done = false; 5161 acrtc->wb_pending = true; 5162 } 5163 5164 static void amdgpu_dm_update_hdcp(struct drm_atomic_commit *state) 5165 { 5166 struct drm_connector_state *old_con_state, *new_con_state; 5167 struct drm_device *dev = state->dev; 5168 struct drm_connector *connector; 5169 struct amdgpu_device *adev = drm_to_adev(dev); 5170 int i; 5171 5172 if (!adev->dm.hdcp_workqueue) 5173 return; 5174 5175 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5176 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5177 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5178 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5179 struct dm_crtc_state *dm_new_crtc_state; 5180 struct amdgpu_dm_connector *aconnector; 5181 5182 if (!connector || connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5183 continue; 5184 5185 aconnector = to_amdgpu_dm_connector(connector); 5186 5187 drm_dbg(dev, "[HDCP_DM] -------------- i : %x ----------\n", i); 5188 5189 drm_dbg(dev, "[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n", 5190 connector->index, connector->status, connector->dpms); 5191 drm_dbg(dev, "[HDCP_DM] state protection old: %x new: %x\n", 5192 old_con_state->content_protection, new_con_state->content_protection); 5193 5194 if (aconnector->dc_sink) { 5195 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 5196 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) { 5197 drm_dbg(dev, "[HDCP_DM] pipe_ctx dispname=%s\n", 5198 aconnector->dc_sink->edid_caps.display_name); 5199 } 5200 } 5201 5202 new_crtc_state = NULL; 5203 old_crtc_state = NULL; 5204 5205 if (acrtc) { 5206 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5207 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5208 } 5209 5210 if (old_crtc_state) 5211 drm_dbg(dev, "old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 5212 old_crtc_state->enable, 5213 old_crtc_state->active, 5214 old_crtc_state->mode_changed, 5215 old_crtc_state->active_changed, 5216 old_crtc_state->connectors_changed); 5217 5218 if (new_crtc_state) 5219 drm_dbg(dev, "NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n", 5220 new_crtc_state->enable, 5221 new_crtc_state->active, 5222 new_crtc_state->mode_changed, 5223 new_crtc_state->active_changed, 5224 new_crtc_state->connectors_changed); 5225 5226 5227 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5228 5229 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL && 5230 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 5231 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); 5232 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; 5233 dm_new_con_state->update_hdcp = true; 5234 continue; 5235 } 5236 5237 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state, 5238 old_con_state, connector, adev->dm.hdcp_workqueue)) { 5239 /* when display is unplugged from mst hub, connctor will 5240 * be destroyed within dm_dp_mst_connector_destroy. connector 5241 * hdcp perperties, like type, undesired, desired, enabled, 5242 * will be lost. So, save hdcp properties into hdcp_work within 5243 * amdgpu_dm_atomic_commit_tail. if the same display is 5244 * plugged back with same display index, its hdcp properties 5245 * will be retrieved from hdcp_work within dm_dp_mst_get_modes 5246 */ 5247 5248 bool enable_encryption = false; 5249 5250 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) 5251 enable_encryption = true; 5252 5253 if (aconnector->dc_link && aconnector->dc_sink && 5254 aconnector->dc_link->type == dc_connection_mst_branch) { 5255 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; 5256 struct hdcp_workqueue *hdcp_w = 5257 &hdcp_work[aconnector->dc_link->link_index]; 5258 5259 hdcp_w->hdcp_content_type[connector->index] = 5260 new_con_state->hdcp_content_type; 5261 hdcp_w->content_protection[connector->index] = 5262 new_con_state->content_protection; 5263 } 5264 5265 if (new_crtc_state && new_crtc_state->mode_changed && 5266 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) 5267 enable_encryption = true; 5268 5269 drm_info(dev, "[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption); 5270 5271 if (aconnector->dc_link) 5272 hdcp_update_display( 5273 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, 5274 new_con_state->hdcp_content_type, enable_encryption); 5275 } 5276 } 5277 } 5278 5279 static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_commit *state) 5280 { 5281 struct drm_crtc *crtc; 5282 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5283 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5284 int i, ret; 5285 5286 ret = drm_dp_mst_atomic_setup_commit(state); 5287 if (ret) 5288 return ret; 5289 5290 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5291 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5292 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5293 /* 5294 * Color management settings. We also update color properties 5295 * when a modeset is needed, to ensure it gets reprogrammed. 5296 */ 5297 if (dm_new_crtc_state->base.active && dm_new_crtc_state->stream && 5298 (dm_new_crtc_state->base.color_mgmt_changed || 5299 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 5300 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5301 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); 5302 if (ret) { 5303 drm_dbg_atomic(state->dev, "Failed to update color state\n"); 5304 return ret; 5305 } 5306 } 5307 } 5308 5309 return 0; 5310 } 5311 5312 STATIC_IFN_KUNIT void set_multisync_trigger_params( 5313 struct dc_stream_state *stream) 5314 { 5315 struct dc_stream_state *master = NULL; 5316 5317 if (stream->triggered_crtc_reset.enabled) { 5318 master = stream->triggered_crtc_reset.event_source; 5319 stream->triggered_crtc_reset.event = 5320 master->timing.flags.VSYNC_POSITIVE_POLARITY ? 5321 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; 5322 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; 5323 } 5324 } 5325 EXPORT_IF_KUNIT(set_multisync_trigger_params); 5326 5327 STATIC_IFN_KUNIT void set_master_stream(struct dc_stream_state *stream_set[], 5328 int stream_count) 5329 { 5330 int j, highest_rfr = 0, master_stream = 0; 5331 5332 for (j = 0; j < stream_count; j++) { 5333 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { 5334 int refresh_rate = 0; 5335 5336 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ 5337 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); 5338 if (refresh_rate > highest_rfr) { 5339 highest_rfr = refresh_rate; 5340 master_stream = j; 5341 } 5342 } 5343 } 5344 for (j = 0; j < stream_count; j++) { 5345 if (stream_set[j]) 5346 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; 5347 } 5348 } 5349 EXPORT_IF_KUNIT(set_master_stream); 5350 5351 STATIC_IFN_KUNIT void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) 5352 { 5353 int i = 0; 5354 struct dc_stream_state *stream; 5355 5356 if (context->stream_count < 2) 5357 return; 5358 for (i = 0; i < context->stream_count ; i++) { 5359 if (!context->streams[i]) 5360 continue; 5361 /* 5362 * TODO: add a function to read AMD VSDB bits and set 5363 * crtc_sync_master.multi_sync_enabled flag 5364 * For now it's set to false 5365 */ 5366 } 5367 5368 set_master_stream(context->streams, context->stream_count); 5369 5370 for (i = 0; i < context->stream_count ; i++) { 5371 stream = context->streams[i]; 5372 5373 if (!stream) 5374 continue; 5375 5376 set_multisync_trigger_params(stream); 5377 } 5378 } 5379 EXPORT_IF_KUNIT(dm_enable_per_frame_crtc_master_sync); 5380 5381 /** 5382 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. 5383 * @state: The atomic state to commit 5384 * 5385 * This will tell DC to commit the constructed DC state from atomic_check, 5386 * programming the hardware. Any failures here implies a hardware failure, since 5387 * atomic check should have filtered anything non-kosher. 5388 */ 5389 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_commit *state) 5390 { 5391 struct drm_device *dev = state->dev; 5392 struct amdgpu_device *adev = drm_to_adev(dev); 5393 struct amdgpu_display_manager *dm = &adev->dm; 5394 struct dm_atomic_state *dm_state; 5395 struct dc_state *dc_state = NULL; 5396 u32 i, j; 5397 struct drm_crtc *crtc; 5398 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 5399 unsigned long flags; 5400 bool wait_for_vblank = true; 5401 struct drm_connector *connector; 5402 struct drm_connector_state *old_con_state = NULL, *new_con_state = NULL; 5403 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5404 int crtc_disable_count = 0; 5405 5406 trace_amdgpu_dm_atomic_commit_tail_begin(state); 5407 5408 drm_atomic_helper_update_legacy_modeset_state(dev, state); 5409 drm_dp_mst_atomic_wait_for_dependencies(state); 5410 5411 dm_state = dm_atomic_get_new_state(state); 5412 if (dm_state && dm_state->context) { 5413 dc_state = dm_state->context; 5414 amdgpu_dm_commit_streams(state, dc_state); 5415 } 5416 5417 amdgpu_dm_update_hdcp(state); 5418 5419 /* Handle connector state changes */ 5420 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 5421 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5422 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 5423 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5424 struct dc_surface_update *dummy_updates; 5425 struct dc_stream_update stream_update; 5426 struct dc_info_packet hdr_packet; 5427 struct dc_stream_status *status = NULL; 5428 bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; 5429 5430 memset(&stream_update, 0, sizeof(stream_update)); 5431 5432 if (acrtc) { 5433 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5434 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base); 5435 } 5436 5437 /* Skip any modesets/resets */ 5438 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) 5439 continue; 5440 5441 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5442 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5443 5444 scaling_changed = is_scaling_state_different(dm_new_con_state, 5445 dm_old_con_state); 5446 5447 if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && 5448 (dm_old_crtc_state->stream->output_color_space != 5449 amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) 5450 output_color_space_changed = true; 5451 5452 abm_changed = dm_new_crtc_state->abm_level != 5453 dm_old_crtc_state->abm_level; 5454 5455 hdr_changed = 5456 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); 5457 5458 if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) 5459 continue; 5460 5461 stream_update.stream = dm_new_crtc_state->stream; 5462 if (scaling_changed) { 5463 amdgpu_dm_update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, 5464 dm_new_con_state, dm_new_crtc_state->stream); 5465 5466 stream_update.src = dm_new_crtc_state->stream->src; 5467 stream_update.dst = dm_new_crtc_state->stream->dst; 5468 } 5469 5470 if (output_color_space_changed) { 5471 dm_new_crtc_state->stream->output_color_space 5472 = amdgpu_dm_get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state); 5473 5474 stream_update.output_color_space = &dm_new_crtc_state->stream->output_color_space; 5475 } 5476 5477 if (abm_changed) { 5478 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; 5479 5480 stream_update.abm_level = &dm_new_crtc_state->abm_level; 5481 } 5482 5483 if (hdr_changed) { 5484 amdgpu_dm_fill_hdr_info_packet(new_con_state, &hdr_packet); 5485 stream_update.hdr_static_metadata = &hdr_packet; 5486 } 5487 5488 status = dc_stream_get_status(dm_new_crtc_state->stream); 5489 5490 if (WARN_ON(!status)) 5491 continue; 5492 5493 WARN_ON(!status->plane_count); 5494 5495 /* 5496 * TODO: DC refuses to perform stream updates without a dc_surface_update. 5497 * Here we create an empty update on each plane. 5498 * To fix this, DC should permit updating only stream properties. 5499 */ 5500 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_KERNEL); 5501 if (!dummy_updates) { 5502 drm_err(adev_to_drm(adev), "Failed to allocate memory for dummy_updates.\n"); 5503 continue; 5504 } 5505 for (j = 0; j < status->plane_count; j++) 5506 dummy_updates[j].surface = status->plane_states[j]; 5507 5508 sort(dummy_updates, status->plane_count, 5509 sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); 5510 5511 mutex_lock(&dm->dc_lock); 5512 dc_exit_ips_for_hw_access(dm->dc); 5513 dc_update_planes_and_stream(dm->dc, 5514 dummy_updates, 5515 status->plane_count, 5516 dm_new_crtc_state->stream, 5517 &stream_update); 5518 mutex_unlock(&dm->dc_lock); 5519 kfree(dummy_updates); 5520 5521 drm_connector_update_privacy_screen(new_con_state); 5522 } 5523 5524 /** 5525 * Enable interrupts for CRTCs that are newly enabled or went through 5526 * a modeset. It was intentionally deferred until after the front end 5527 * state was modified to wait until the OTG was on and so the IRQ 5528 * handlers didn't access stale or invalid state. 5529 */ 5530 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 5531 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 5532 #ifdef CONFIG_DEBUG_FS 5533 enum amdgpu_dm_pipe_crc_source cur_crc_src; 5534 #endif 5535 /* Count number of newly disabled CRTCs for dropping PM refs later. */ 5536 if (old_crtc_state->active && !new_crtc_state->active) 5537 crtc_disable_count++; 5538 5539 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5540 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5541 5542 /* For freesync config update on crtc state and params for irq */ 5543 update_stream_irq_parameters(dm, dm_new_crtc_state); 5544 5545 #ifdef CONFIG_DEBUG_FS 5546 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5547 cur_crc_src = acrtc->dm_irq_params.crc_src; 5548 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5549 #endif 5550 5551 if (new_crtc_state->active && 5552 (!old_crtc_state->active || 5553 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5554 dc_stream_retain(dm_new_crtc_state->stream); 5555 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; 5556 manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); 5557 } 5558 /* Handle vrr on->off / off->on transitions */ 5559 amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state); 5560 5561 #ifdef CONFIG_DEBUG_FS 5562 if (new_crtc_state->active && 5563 (!old_crtc_state->active || 5564 drm_atomic_crtc_needs_modeset(new_crtc_state))) { 5565 /** 5566 * Frontend may have changed so reapply the CRC capture 5567 * settings for the stream. 5568 */ 5569 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) { 5570 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 5571 if (amdgpu_dm_crc_window_is_activated(crtc)) { 5572 uint8_t cnt; 5573 5574 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5575 for (cnt = 0; cnt < MAX_CRC_WINDOW_NUM; cnt++) { 5576 if (acrtc->dm_irq_params.window_param[cnt].enable) { 5577 acrtc->dm_irq_params.window_param[cnt].update_win = true; 5578 5579 /** 5580 * It takes 2 frames for HW to stably generate CRC when 5581 * resuming from suspend, so we set skip_frame_cnt 2. 5582 */ 5583 acrtc->dm_irq_params.window_param[cnt].skip_frame_cnt = 2; 5584 } 5585 } 5586 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5587 } 5588 #endif 5589 if (amdgpu_dm_crtc_configure_crc_source( 5590 crtc, dm_new_crtc_state, cur_crc_src)) 5591 drm_dbg_atomic(dev, "Failed to configure crc source"); 5592 } 5593 } 5594 #endif 5595 } 5596 5597 amdgpu_dm_mod_power_setup_streams(state, dm); 5598 5599 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) 5600 if (new_crtc_state->async_flip) 5601 wait_for_vblank = false; 5602 5603 /* update planes when needed per crtc*/ 5604 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { 5605 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5606 5607 if (dm_new_crtc_state->stream) 5608 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank); 5609 } 5610 5611 /* Enable writeback */ 5612 for_each_new_connector_in_state(state, connector, new_con_state, i) { 5613 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 5614 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 5615 5616 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 5617 continue; 5618 5619 if (!new_con_state->writeback_job) 5620 continue; 5621 5622 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); 5623 5624 if (!new_crtc_state) 5625 continue; 5626 5627 if (acrtc->wb_enabled) 5628 continue; 5629 5630 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5631 5632 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state); 5633 acrtc->wb_enabled = true; 5634 } 5635 5636 /* Update audio instances for each connector. */ 5637 amdgpu_dm_commit_audio(dev, state); 5638 5639 /* restore the backlight level */ 5640 for (i = 0; i < dm->num_of_edps; i++) { 5641 if (dm->backlight_dev[i] && 5642 (dm->actual_brightness[i] != dm->brightness[i])) 5643 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]); 5644 } 5645 5646 /* 5647 * send vblank event on all events not handled in flip and 5648 * mark consumed event for drm_atomic_helper_commit_hw_done 5649 */ 5650 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 5651 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 5652 5653 if (new_crtc_state->event) 5654 drm_send_event_locked(dev, &new_crtc_state->event->base); 5655 5656 new_crtc_state->event = NULL; 5657 } 5658 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 5659 5660 /* Signal HW programming completion */ 5661 drm_atomic_helper_commit_hw_done(state); 5662 5663 if (wait_for_vblank) 5664 drm_atomic_helper_wait_for_flip_done(dev, state); 5665 5666 drm_atomic_helper_cleanup_planes(dev, state); 5667 5668 /* Don't free the memory if we are hitting this as part of suspend. 5669 * This way we don't free any memory during suspend; see 5670 * amdgpu_bo_free_kernel(). The memory will be freed in the first 5671 * non-suspend modeset or when the driver is torn down. 5672 */ 5673 if (!adev->in_suspend) { 5674 /* return the stolen vga memory back to VRAM */ 5675 if (!adev->mman.keep_stolen_vga_memory) 5676 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_VGA); 5677 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_STOLEN_EXTENDED); 5678 } 5679 5680 /* 5681 * Finally, drop a runtime PM reference for each newly disabled CRTC, 5682 * so we can put the GPU into runtime suspend if we're not driving any 5683 * displays anymore 5684 */ 5685 for (i = 0; i < crtc_disable_count; i++) 5686 pm_runtime_put_autosuspend(dev->dev); 5687 pm_runtime_mark_last_busy(dev->dev); 5688 5689 trace_amdgpu_dm_atomic_commit_tail_finish(state); 5690 } 5691 5692 /* 5693 * Grabs all modesetting locks to serialize against any blocking commits, 5694 * Waits for completion of all non blocking commits. 5695 */ 5696 static int do_aquire_global_lock(struct drm_device *dev, 5697 struct drm_atomic_commit *state) 5698 { 5699 struct drm_crtc *crtc; 5700 struct drm_crtc_commit *commit; 5701 long ret; 5702 5703 /* 5704 * Adding all modeset locks to aquire_ctx will 5705 * ensure that when the framework release it the 5706 * extra locks we are locking here will get released to 5707 */ 5708 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); 5709 if (ret) 5710 return ret; 5711 5712 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5713 spin_lock(&crtc->commit_lock); 5714 commit = list_first_entry_or_null(&crtc->commit_list, 5715 struct drm_crtc_commit, commit_entry); 5716 if (commit) 5717 drm_crtc_commit_get(commit); 5718 spin_unlock(&crtc->commit_lock); 5719 5720 if (!commit) 5721 continue; 5722 5723 /* 5724 * Make sure all pending HW programming completed and 5725 * page flips done 5726 */ 5727 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); 5728 5729 if (ret > 0) 5730 ret = wait_for_completion_interruptible_timeout( 5731 &commit->flip_done, 10*HZ); 5732 5733 if (ret == 0) 5734 drm_err(dev, "[CRTC:%d:%s] hw_done or flip_done timed out\n", 5735 crtc->base.id, crtc->name); 5736 5737 drm_crtc_commit_put(commit); 5738 } 5739 5740 return ret < 0 ? ret : 0; 5741 } 5742 5743 STATIC_IFN_KUNIT void get_freesync_config_for_crtc( 5744 struct dm_crtc_state *new_crtc_state, 5745 struct dm_connector_state *new_con_state) 5746 { 5747 struct mod_freesync_config config = {0}; 5748 struct amdgpu_dm_connector *aconnector; 5749 struct drm_display_mode *mode = &new_crtc_state->base.mode; 5750 int vrefresh = drm_mode_vrefresh(mode); 5751 bool fs_vid_mode = false; 5752 5753 if (new_con_state->base.connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 5754 return; 5755 5756 aconnector = to_amdgpu_dm_connector(new_con_state->base.connector); 5757 5758 new_crtc_state->vrr_supported = new_con_state->freesync_capable && 5759 vrefresh >= aconnector->min_vfreq && 5760 vrefresh <= aconnector->max_vfreq; 5761 5762 if (new_crtc_state->vrr_supported) { 5763 new_crtc_state->stream->ignore_msa_timing_param = true; 5764 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED; 5765 5766 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000; 5767 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000; 5768 config.vsif_supported = true; 5769 config.btr = true; 5770 5771 if (fs_vid_mode) { 5772 config.state = VRR_STATE_ACTIVE_FIXED; 5773 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz; 5774 goto out; 5775 } else if (new_crtc_state->base.vrr_enabled) { 5776 config.state = VRR_STATE_ACTIVE_VARIABLE; 5777 } else { 5778 config.state = VRR_STATE_INACTIVE; 5779 } 5780 } else { 5781 config.state = VRR_STATE_UNSUPPORTED; 5782 } 5783 out: 5784 new_crtc_state->freesync_config = config; 5785 } 5786 EXPORT_IF_KUNIT(get_freesync_config_for_crtc); 5787 5788 STATIC_IFN_KUNIT void reset_freesync_config_for_crtc( 5789 struct dm_crtc_state *new_crtc_state) 5790 { 5791 new_crtc_state->vrr_supported = false; 5792 5793 memset(&new_crtc_state->vrr_infopacket, 0, 5794 sizeof(new_crtc_state->vrr_infopacket)); 5795 } 5796 EXPORT_IF_KUNIT(reset_freesync_config_for_crtc); 5797 5798 STATIC_IFN_KUNIT bool 5799 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 5800 struct drm_crtc_state *new_crtc_state) 5801 { 5802 const struct drm_display_mode *old_mode, *new_mode; 5803 5804 if (!old_crtc_state || !new_crtc_state) 5805 return false; 5806 5807 old_mode = &old_crtc_state->mode; 5808 new_mode = &new_crtc_state->mode; 5809 5810 if (old_mode->clock == new_mode->clock && 5811 old_mode->hdisplay == new_mode->hdisplay && 5812 old_mode->vdisplay == new_mode->vdisplay && 5813 old_mode->htotal == new_mode->htotal && 5814 old_mode->vtotal != new_mode->vtotal && 5815 old_mode->hsync_start == new_mode->hsync_start && 5816 old_mode->vsync_start != new_mode->vsync_start && 5817 old_mode->hsync_end == new_mode->hsync_end && 5818 old_mode->vsync_end != new_mode->vsync_end && 5819 old_mode->hskew == new_mode->hskew && 5820 old_mode->vscan == new_mode->vscan && 5821 (old_mode->vsync_end - old_mode->vsync_start) == 5822 (new_mode->vsync_end - new_mode->vsync_start)) 5823 return true; 5824 5825 return false; 5826 } 5827 EXPORT_IF_KUNIT(is_timing_unchanged_for_freesync); 5828 5829 STATIC_IFN_KUNIT void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) 5830 { 5831 u64 num, den, res; 5832 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base; 5833 5834 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED; 5835 5836 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000; 5837 den = (unsigned long long)new_crtc_state->mode.htotal * 5838 (unsigned long long)new_crtc_state->mode.vtotal; 5839 5840 res = div_u64(num, den); 5841 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res; 5842 } 5843 EXPORT_IF_KUNIT(set_freesync_fixed_config); 5844 5845 static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 5846 struct drm_atomic_commit *state, 5847 struct drm_crtc *crtc, 5848 struct drm_crtc_state *old_crtc_state, 5849 struct drm_crtc_state *new_crtc_state, 5850 bool enable, 5851 bool *lock_and_validation_needed) 5852 { 5853 struct dm_atomic_state *dm_state = NULL; 5854 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 5855 struct dc_stream_state *new_stream; 5856 struct amdgpu_device *adev = dm->adev; 5857 int ret = 0; 5858 5859 /* 5860 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set 5861 * update changed items 5862 */ 5863 struct amdgpu_crtc *acrtc = NULL; 5864 struct drm_connector *connector = NULL; 5865 struct amdgpu_dm_connector *aconnector = NULL; 5866 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL; 5867 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL; 5868 5869 new_stream = NULL; 5870 5871 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 5872 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 5873 acrtc = to_amdgpu_crtc(crtc); 5874 connector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); 5875 if (connector) 5876 aconnector = to_amdgpu_dm_connector(connector); 5877 5878 /* TODO This hack should go away */ 5879 if (connector && enable) { 5880 /* Make sure fake sink is created in plug-in scenario */ 5881 drm_new_conn_state = drm_atomic_get_new_connector_state(state, 5882 connector); 5883 drm_old_conn_state = drm_atomic_get_old_connector_state(state, 5884 connector); 5885 5886 if (WARN_ON(!drm_new_conn_state)) { 5887 ret = -EINVAL; 5888 goto fail; 5889 } 5890 5891 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state); 5892 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state); 5893 5894 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5895 goto skip_modeset; 5896 5897 new_stream = amdgpu_dm_create_validate_stream_for_sink(connector, 5898 &new_crtc_state->mode, 5899 dm_new_conn_state, 5900 dm_old_crtc_state->stream); 5901 5902 /* 5903 * we can have no stream on ACTION_SET if a display 5904 * was disconnected during S3, in this case it is not an 5905 * error, the OS will be updated after detection, and 5906 * will do the right thing on next atomic commit 5907 */ 5908 5909 if (!new_stream) { 5910 drm_dbg_driver(adev_to_drm(adev), "%s: Failed to create new stream for crtc %d\n", 5911 __func__, acrtc->base.base.id); 5912 ret = -ENOMEM; 5913 goto fail; 5914 } 5915 5916 /* 5917 * TODO: Check VSDB bits to decide whether this should 5918 * be enabled or not. 5919 */ 5920 new_stream->triggered_crtc_reset.enabled = 5921 dm->force_timing_sync; 5922 5923 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 5924 5925 ret = amdgpu_dm_fill_hdr_info_packet(drm_new_conn_state, 5926 &new_stream->hdr_static_metadata); 5927 if (ret) 5928 goto fail; 5929 5930 /* 5931 * If we already removed the old stream from the context 5932 * (and set the new stream to NULL) then we can't reuse 5933 * the old stream even if the stream and scaling are unchanged. 5934 * We'll hit the BUG_ON and black screen. 5935 * 5936 * TODO: Refactor this function to allow this check to work 5937 * in all conditions. 5938 */ 5939 if (amdgpu_freesync_vid_mode && 5940 dm_new_crtc_state->stream && 5941 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state)) 5942 goto skip_modeset; 5943 5944 if (dm_new_crtc_state->stream && 5945 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5946 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { 5947 new_crtc_state->mode_changed = false; 5948 drm_dbg_driver(adev_to_drm(adev), "Mode change not required, setting mode_changed to %d", 5949 new_crtc_state->mode_changed); 5950 } 5951 } 5952 5953 /* mode_changed flag may get updated above, need to check again */ 5954 if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) 5955 goto skip_modeset; 5956 5957 drm_dbg_state(state->dev, 5958 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n", 5959 acrtc->crtc_id, 5960 new_crtc_state->enable, 5961 new_crtc_state->active, 5962 new_crtc_state->planes_changed, 5963 new_crtc_state->mode_changed, 5964 new_crtc_state->active_changed, 5965 new_crtc_state->connectors_changed); 5966 5967 /* Remove stream for any changed/disabled CRTC */ 5968 if (!enable) { 5969 5970 if (!dm_old_crtc_state->stream) 5971 goto skip_modeset; 5972 5973 /* Unset freesync video if it was active before */ 5974 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) { 5975 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE; 5976 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0; 5977 } 5978 5979 /* Now check if we should set freesync video mode */ 5980 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream && 5981 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && 5982 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) && 5983 is_timing_unchanged_for_freesync(new_crtc_state, 5984 old_crtc_state)) { 5985 new_crtc_state->mode_changed = false; 5986 drm_dbg_driver(adev_to_drm(adev), 5987 "Mode change not required for front porch change, setting mode_changed to %d", 5988 new_crtc_state->mode_changed); 5989 5990 set_freesync_fixed_config(dm_new_crtc_state); 5991 5992 goto skip_modeset; 5993 } else if (amdgpu_freesync_vid_mode && aconnector && 5994 amdgpu_dm_is_freesync_video_mode(&new_crtc_state->mode, 5995 aconnector)) { 5996 struct drm_display_mode *high_mode; 5997 5998 high_mode = amdgpu_dm_get_highest_refresh_rate_mode(aconnector, false); 5999 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) 6000 set_freesync_fixed_config(dm_new_crtc_state); 6001 } 6002 6003 ret = dm_atomic_get_state(state, &dm_state); 6004 if (ret) 6005 goto fail; 6006 6007 drm_dbg_driver(adev_to_drm(adev), "Disabling DRM crtc: %d\n", 6008 crtc->base.id); 6009 6010 /* i.e. reset mode */ 6011 if (dc_state_remove_stream( 6012 dm->dc, 6013 dm_state->context, 6014 dm_old_crtc_state->stream) != DC_OK) { 6015 ret = -EINVAL; 6016 goto fail; 6017 } 6018 6019 dc_stream_release(dm_old_crtc_state->stream); 6020 dm_new_crtc_state->stream = NULL; 6021 6022 reset_freesync_config_for_crtc(dm_new_crtc_state); 6023 6024 *lock_and_validation_needed = true; 6025 6026 } else {/* Add stream for any updated/enabled CRTC */ 6027 /* 6028 * Quick fix to prevent NULL pointer on new_stream when 6029 * added MST connectors not found in existing crtc_state in the chained mode 6030 * TODO: need to dig out the root cause of that 6031 */ 6032 if (!connector) 6033 goto skip_modeset; 6034 6035 if (modereset_required(new_crtc_state)) 6036 goto skip_modeset; 6037 6038 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream, 6039 dm_old_crtc_state->stream)) { 6040 6041 WARN_ON(dm_new_crtc_state->stream); 6042 6043 ret = dm_atomic_get_state(state, &dm_state); 6044 if (ret) 6045 goto fail; 6046 6047 dm_new_crtc_state->stream = new_stream; 6048 6049 dc_stream_retain(new_stream); 6050 6051 drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", 6052 crtc->base.id); 6053 6054 if (dc_state_add_stream( 6055 dm->dc, 6056 dm_state->context, 6057 dm_new_crtc_state->stream) != DC_OK) { 6058 ret = -EINVAL; 6059 goto fail; 6060 } 6061 6062 *lock_and_validation_needed = true; 6063 } 6064 } 6065 6066 skip_modeset: 6067 /* Release extra reference */ 6068 if (new_stream) 6069 dc_stream_release(new_stream); 6070 new_stream = NULL; 6071 6072 /* 6073 * We want to do dc stream updates that do not require a 6074 * full modeset below. 6075 */ 6076 if (!(enable && connector && new_crtc_state->active)) 6077 return 0; 6078 /* 6079 * Given above conditions, the dc state cannot be NULL because: 6080 * 1. We're in the process of enabling CRTCs (just been added 6081 * to the dc context, or already is on the context) 6082 * 2. Has a valid connector attached, and 6083 * 3. Is currently active and enabled. 6084 * => The dc stream state currently exists. 6085 */ 6086 BUG_ON(dm_new_crtc_state->stream == NULL); 6087 6088 /* Scaling or underscan settings */ 6089 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || 6090 drm_atomic_crtc_needs_modeset(new_crtc_state)) 6091 amdgpu_dm_update_stream_scaling_settings(adev_to_drm(adev), 6092 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); 6093 6094 /* ABM settings */ 6095 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; 6096 6097 /* 6098 * Color management settings. We also update color properties 6099 * when a modeset is needed, to ensure it gets reprogrammed. 6100 */ 6101 if (dm_new_crtc_state->base.color_mgmt_changed || 6102 dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || 6103 drm_atomic_crtc_needs_modeset(new_crtc_state)) { 6104 ret = amdgpu_dm_check_crtc_color_mgmt(dm_new_crtc_state, true); 6105 if (ret) 6106 goto fail; 6107 } 6108 6109 /* Update Freesync settings. */ 6110 get_freesync_config_for_crtc(dm_new_crtc_state, 6111 dm_new_conn_state); 6112 6113 return ret; 6114 6115 fail: 6116 if (new_stream) 6117 dc_stream_release(new_stream); 6118 return ret; 6119 } 6120 6121 static bool should_reset_plane(struct drm_atomic_commit *state, 6122 struct drm_plane *plane, 6123 struct drm_plane_state *old_plane_state, 6124 struct drm_plane_state *new_plane_state) 6125 { 6126 struct drm_plane *other; 6127 struct drm_plane_state *old_other_state, *new_other_state; 6128 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6129 struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; 6130 struct amdgpu_device *adev = drm_to_adev(plane->dev); 6131 struct drm_connector_state *new_con_state; 6132 struct drm_connector *connector; 6133 int i; 6134 6135 /* 6136 * TODO: Remove this hack for all asics once it proves that the 6137 * fast updates works fine on DCN3.2+. 6138 */ 6139 if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 2, 0) && 6140 state->allow_modeset) 6141 return true; 6142 6143 /* Check for writeback commit */ 6144 for_each_new_connector_in_state(state, connector, new_con_state, i) { 6145 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) 6146 continue; 6147 6148 if (new_con_state->writeback_job) 6149 return true; 6150 } 6151 6152 if (amdgpu_in_reset(adev) && state->allow_modeset) 6153 return true; 6154 6155 /* Exit early if we know that we're adding or removing the plane. */ 6156 if (old_plane_state->crtc != new_plane_state->crtc) 6157 return true; 6158 6159 /* old crtc == new_crtc == NULL, plane not in context. */ 6160 if (!new_plane_state->crtc) 6161 return false; 6162 6163 new_crtc_state = 6164 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); 6165 old_crtc_state = 6166 drm_atomic_get_old_crtc_state(state, old_plane_state->crtc); 6167 6168 if (!new_crtc_state) 6169 return true; 6170 6171 /* 6172 * A change in cursor mode means a new dc pipe needs to be acquired or 6173 * released from the state 6174 */ 6175 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state); 6176 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); 6177 if (plane->type == DRM_PLANE_TYPE_CURSOR && 6178 old_dm_crtc_state != NULL && 6179 old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) { 6180 return true; 6181 } 6182 6183 /* CRTC Degamma changes currently require us to recreate planes. */ 6184 if (new_crtc_state->color_mgmt_changed) 6185 return true; 6186 6187 /* 6188 * On zpos change, planes need to be reordered by removing and re-adding 6189 * them one by one to the dc state, in order of descending zpos. 6190 * 6191 * TODO: We can likely skip bandwidth validation if the only thing that 6192 * changed about the plane was it'z z-ordering. 6193 */ 6194 if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) 6195 return true; 6196 6197 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) 6198 return true; 6199 6200 /* 6201 * If there are any new primary or overlay planes being added or 6202 * removed then the z-order can potentially change. To ensure 6203 * correct z-order and pipe acquisition the current DC architecture 6204 * requires us to remove and recreate all existing planes. 6205 * 6206 * TODO: Come up with a more elegant solution for this. 6207 */ 6208 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { 6209 struct amdgpu_framebuffer *old_afb, *new_afb; 6210 struct dm_plane_state *dm_new_other_state, *dm_old_other_state; 6211 6212 dm_new_other_state = to_dm_plane_state(new_other_state); 6213 dm_old_other_state = to_dm_plane_state(old_other_state); 6214 6215 if (other->type == DRM_PLANE_TYPE_CURSOR) 6216 continue; 6217 6218 if (old_other_state->crtc != new_plane_state->crtc && 6219 new_other_state->crtc != new_plane_state->crtc) 6220 continue; 6221 6222 if (old_other_state->crtc != new_other_state->crtc) 6223 return true; 6224 6225 /* Src/dst size and scaling updates. */ 6226 if (old_other_state->src_w != new_other_state->src_w || 6227 old_other_state->src_h != new_other_state->src_h || 6228 old_other_state->crtc_w != new_other_state->crtc_w || 6229 old_other_state->crtc_h != new_other_state->crtc_h) 6230 return true; 6231 6232 /* Rotation / mirroring updates. */ 6233 if (old_other_state->rotation != new_other_state->rotation) 6234 return true; 6235 6236 /* Blending updates. */ 6237 if (old_other_state->pixel_blend_mode != 6238 new_other_state->pixel_blend_mode) 6239 return true; 6240 6241 /* Alpha updates. */ 6242 if (old_other_state->alpha != new_other_state->alpha) 6243 return true; 6244 6245 /* Colorspace changes. */ 6246 if (old_other_state->color_range != new_other_state->color_range || 6247 old_other_state->color_encoding != new_other_state->color_encoding) 6248 return true; 6249 6250 /* HDR/Transfer Function changes. */ 6251 if (dm_old_other_state->degamma_tf != dm_new_other_state->degamma_tf || 6252 dm_old_other_state->degamma_lut != dm_new_other_state->degamma_lut || 6253 dm_old_other_state->hdr_mult != dm_new_other_state->hdr_mult || 6254 dm_old_other_state->ctm != dm_new_other_state->ctm || 6255 dm_old_other_state->shaper_lut != dm_new_other_state->shaper_lut || 6256 dm_old_other_state->shaper_tf != dm_new_other_state->shaper_tf || 6257 dm_old_other_state->lut3d != dm_new_other_state->lut3d || 6258 dm_old_other_state->blend_lut != dm_new_other_state->blend_lut || 6259 dm_old_other_state->blend_tf != dm_new_other_state->blend_tf) 6260 return true; 6261 6262 /* Framebuffer checks fall at the end. */ 6263 if (!old_other_state->fb || !new_other_state->fb) 6264 continue; 6265 6266 /* Pixel format changes can require bandwidth updates. */ 6267 if (old_other_state->fb->format != new_other_state->fb->format) 6268 return true; 6269 6270 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; 6271 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb; 6272 6273 /* Tiling and DCC changes also require bandwidth updates. */ 6274 if (old_afb->tiling_flags != new_afb->tiling_flags || 6275 old_afb->base.modifier != new_afb->base.modifier) 6276 return true; 6277 } 6278 6279 return false; 6280 } 6281 6282 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 6283 struct drm_plane_state *new_plane_state, 6284 struct drm_framebuffer *fb) 6285 { 6286 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev); 6287 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); 6288 unsigned int pitch; 6289 bool linear; 6290 6291 if (fb->width > new_acrtc->max_cursor_width || 6292 fb->height > new_acrtc->max_cursor_height) { 6293 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB size %dx%d\n", 6294 new_plane_state->fb->width, 6295 new_plane_state->fb->height); 6296 return -EINVAL; 6297 } 6298 if (new_plane_state->src_w != fb->width << 16 || 6299 new_plane_state->src_h != fb->height << 16) { 6300 drm_dbg_atomic(adev_to_drm(adev), "Cropping not supported for cursor plane\n"); 6301 return -EINVAL; 6302 } 6303 6304 /* Pitch in pixels */ 6305 pitch = fb->pitches[0] / fb->format->cpp[0]; 6306 6307 if (fb->width != pitch) { 6308 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB width %d doesn't match pitch %d", 6309 fb->width, pitch); 6310 return -EINVAL; 6311 } 6312 6313 switch (pitch) { 6314 case 64: 6315 case 128: 6316 case 256: 6317 /* FB pitch is supported by cursor plane */ 6318 break; 6319 default: 6320 drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB pitch %d px\n", pitch); 6321 return -EINVAL; 6322 } 6323 6324 /* Core DRM takes care of checking FB modifiers, so we only need to 6325 * check tiling flags when the FB doesn't have a modifier. 6326 */ 6327 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { 6328 if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { 6329 linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; 6330 } else if (adev->family >= AMDGPU_FAMILY_AI) { 6331 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; 6332 } else { 6333 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 6334 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 6335 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 6336 } 6337 if (!linear) { 6338 drm_dbg_atomic(adev_to_drm(adev), "Cursor FB not linear"); 6339 return -EINVAL; 6340 } 6341 } 6342 6343 return 0; 6344 } 6345 6346 /* 6347 * Helper function for checking the cursor in native mode 6348 */ 6349 static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, 6350 struct drm_plane *plane, 6351 struct drm_plane_state *new_plane_state, 6352 bool enable) 6353 { 6354 6355 struct amdgpu_crtc *new_acrtc; 6356 int ret; 6357 6358 if (!enable || !new_plane_crtc || 6359 drm_atomic_plane_disabling(plane->state, new_plane_state)) 6360 return 0; 6361 6362 new_acrtc = to_amdgpu_crtc(new_plane_crtc); 6363 6364 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { 6365 drm_dbg_atomic(new_plane_crtc->dev, "Cropping not supported for cursor plane\n"); 6366 return -EINVAL; 6367 } 6368 6369 if (new_plane_state->fb) { 6370 ret = dm_check_cursor_fb(new_acrtc, new_plane_state, 6371 new_plane_state->fb); 6372 if (ret) 6373 return ret; 6374 } 6375 6376 return 0; 6377 } 6378 6379 STATIC_IFN_KUNIT bool dm_should_update_native_cursor(struct drm_atomic_commit *state, 6380 struct drm_crtc *old_plane_crtc, 6381 struct drm_crtc *new_plane_crtc, 6382 bool enable) 6383 { 6384 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6385 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 6386 6387 if (!enable) { 6388 if (old_plane_crtc == NULL) 6389 return true; 6390 6391 old_crtc_state = drm_atomic_get_old_crtc_state( 6392 state, old_plane_crtc); 6393 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6394 6395 return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6396 } else { 6397 if (new_plane_crtc == NULL) 6398 return true; 6399 6400 new_crtc_state = drm_atomic_get_new_crtc_state( 6401 state, new_plane_crtc); 6402 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6403 6404 return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE; 6405 } 6406 } 6407 EXPORT_IF_KUNIT(dm_should_update_native_cursor); 6408 6409 static int dm_update_plane_state(struct dc *dc, 6410 struct drm_atomic_commit *state, 6411 struct drm_plane *plane, 6412 struct drm_plane_state *old_plane_state, 6413 struct drm_plane_state *new_plane_state, 6414 bool enable, 6415 bool *lock_and_validation_needed, 6416 bool *is_top_most_overlay) 6417 { 6418 6419 struct dm_atomic_state *dm_state = NULL; 6420 struct drm_crtc *new_plane_crtc, *old_plane_crtc; 6421 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6422 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; 6423 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; 6424 bool needs_reset, update_native_cursor; 6425 int ret = 0; 6426 6427 6428 new_plane_crtc = new_plane_state->crtc; 6429 old_plane_crtc = old_plane_state->crtc; 6430 dm_new_plane_state = to_dm_plane_state(new_plane_state); 6431 dm_old_plane_state = to_dm_plane_state(old_plane_state); 6432 6433 update_native_cursor = dm_should_update_native_cursor(state, 6434 old_plane_crtc, 6435 new_plane_crtc, 6436 enable); 6437 6438 if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) { 6439 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6440 new_plane_state, enable); 6441 if (ret) 6442 return ret; 6443 6444 return 0; 6445 } 6446 6447 needs_reset = should_reset_plane(state, plane, old_plane_state, 6448 new_plane_state); 6449 6450 /* Remove any changed/removed planes */ 6451 if (!enable) { 6452 if (!needs_reset) 6453 return 0; 6454 6455 if (!old_plane_crtc) 6456 return 0; 6457 6458 old_crtc_state = drm_atomic_get_old_crtc_state( 6459 state, old_plane_crtc); 6460 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 6461 6462 if (!dm_old_crtc_state->stream) 6463 return 0; 6464 6465 drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", 6466 plane->base.id, old_plane_crtc->base.id); 6467 6468 ret = dm_atomic_get_state(state, &dm_state); 6469 if (ret) 6470 return ret; 6471 6472 if (!dc_state_remove_plane( 6473 dc, 6474 dm_old_crtc_state->stream, 6475 dm_old_plane_state->dc_state, 6476 dm_state->context)) { 6477 6478 return -EINVAL; 6479 } 6480 6481 if (dm_old_plane_state->dc_state) 6482 dc_plane_state_release(dm_old_plane_state->dc_state); 6483 6484 dm_new_plane_state->dc_state = NULL; 6485 6486 *lock_and_validation_needed = true; 6487 6488 } else { /* Add new planes */ 6489 struct dc_plane_state *dc_new_plane_state; 6490 6491 if (drm_atomic_plane_disabling(plane->state, new_plane_state)) 6492 return 0; 6493 6494 if (!new_plane_crtc) 6495 return 0; 6496 6497 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); 6498 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 6499 6500 if (!dm_new_crtc_state->stream) 6501 return 0; 6502 6503 if (!needs_reset) 6504 return 0; 6505 6506 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state); 6507 if (ret) 6508 goto out; 6509 6510 WARN_ON(dm_new_plane_state->dc_state); 6511 6512 dc_new_plane_state = dc_create_plane_state(dc); 6513 if (!dc_new_plane_state) { 6514 ret = -ENOMEM; 6515 goto out; 6516 } 6517 6518 drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", 6519 plane->base.id, new_plane_crtc->base.id); 6520 6521 ret = fill_dc_plane_attributes( 6522 drm_to_adev(new_plane_crtc->dev), 6523 dc_new_plane_state, 6524 new_plane_state, 6525 new_crtc_state); 6526 if (ret) { 6527 dc_plane_state_release(dc_new_plane_state); 6528 goto out; 6529 } 6530 6531 ret = dm_atomic_get_state(state, &dm_state); 6532 if (ret) { 6533 dc_plane_state_release(dc_new_plane_state); 6534 goto out; 6535 } 6536 6537 /* 6538 * Any atomic check errors that occur after this will 6539 * not need a release. The plane state will be attached 6540 * to the stream, and therefore part of the atomic 6541 * state. It'll be released when the atomic state is 6542 * cleaned. 6543 */ 6544 if (!dc_state_add_plane( 6545 dc, 6546 dm_new_crtc_state->stream, 6547 dc_new_plane_state, 6548 dm_state->context)) { 6549 6550 dc_plane_state_release(dc_new_plane_state); 6551 ret = -EINVAL; 6552 goto out; 6553 } 6554 6555 dm_new_plane_state->dc_state = dc_new_plane_state; 6556 6557 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY); 6558 6559 /* Tell DC to do a full surface update every time there 6560 * is a plane change. Inefficient, but works for now. 6561 */ 6562 dm_new_plane_state->dc_state->update_bits.full_update = 1; 6563 6564 *lock_and_validation_needed = true; 6565 } 6566 6567 out: 6568 /* If enabling cursor overlay failed, attempt fallback to native mode */ 6569 if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) { 6570 ret = dm_check_native_cursor_state(new_plane_crtc, plane, 6571 new_plane_state, enable); 6572 if (ret) 6573 return ret; 6574 6575 dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE; 6576 } 6577 6578 return ret; 6579 } 6580 6581 STATIC_IFN_KUNIT void dm_get_oriented_plane_size(struct drm_plane_state *plane_state, 6582 int *src_w, int *src_h) 6583 { 6584 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) { 6585 case DRM_MODE_ROTATE_90: 6586 case DRM_MODE_ROTATE_270: 6587 *src_w = plane_state->src_h >> 16; 6588 *src_h = plane_state->src_w >> 16; 6589 break; 6590 case DRM_MODE_ROTATE_0: 6591 case DRM_MODE_ROTATE_180: 6592 default: 6593 *src_w = plane_state->src_w >> 16; 6594 *src_h = plane_state->src_h >> 16; 6595 break; 6596 } 6597 } 6598 EXPORT_IF_KUNIT(dm_get_oriented_plane_size); 6599 6600 STATIC_IFN_KUNIT void 6601 dm_get_plane_scale(struct drm_plane_state *plane_state, 6602 int *out_plane_scale_w, int *out_plane_scale_h) 6603 { 6604 int plane_src_w, plane_src_h; 6605 6606 dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h); 6607 *out_plane_scale_w = plane_src_w ? plane_state->crtc_w * 1000 / plane_src_w : 0; 6608 *out_plane_scale_h = plane_src_h ? plane_state->crtc_h * 1000 / plane_src_h : 0; 6609 } 6610 EXPORT_IF_KUNIT(dm_get_plane_scale); 6611 6612 /* 6613 * The normalized_zpos value cannot be used by this iterator directly. It's only 6614 * calculated for enabled planes, potentially causing normalized_zpos collisions 6615 * between enabled/disabled planes in the atomic state. We need a unique value 6616 * so that the iterator will not generate the same object twice, or loop 6617 * indefinitely. 6618 */ 6619 static inline struct __drm_planes_state *__get_next_zpos( 6620 struct drm_atomic_commit *state, 6621 struct __drm_planes_state *prev) 6622 { 6623 unsigned int highest_zpos = 0, prev_zpos = 256; 6624 uint32_t highest_id = 0, prev_id = UINT_MAX; 6625 struct drm_plane_state *new_plane_state; 6626 struct drm_plane *plane; 6627 int i, highest_i = -1; 6628 6629 if (prev != NULL) { 6630 prev_zpos = prev->new_state->zpos; 6631 prev_id = prev->ptr->base.id; 6632 } 6633 6634 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 6635 /* Skip planes with higher zpos than the previously returned */ 6636 if (new_plane_state->zpos > prev_zpos || 6637 (new_plane_state->zpos == prev_zpos && 6638 plane->base.id >= prev_id)) 6639 continue; 6640 6641 /* Save the index of the plane with highest zpos */ 6642 if (new_plane_state->zpos > highest_zpos || 6643 (new_plane_state->zpos == highest_zpos && 6644 plane->base.id > highest_id)) { 6645 highest_zpos = new_plane_state->zpos; 6646 highest_id = plane->base.id; 6647 highest_i = i; 6648 } 6649 } 6650 6651 if (highest_i < 0) 6652 return NULL; 6653 6654 return &state->planes[highest_i]; 6655 } 6656 6657 /* 6658 * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate 6659 * by descending zpos, as read from the new plane state. This is the same 6660 * ordering as defined by drm_atomic_normalize_zpos(). 6661 */ 6662 #define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \ 6663 for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \ 6664 __i != NULL; __i = __get_next_zpos((__state), __i)) \ 6665 for_each_if(((plane) = __i->ptr, \ 6666 (void)(plane) /* Only to avoid unused-but-set-variable warning */, \ 6667 (old_plane_state) = __i->old_state, \ 6668 (new_plane_state) = __i->new_state, 1)) 6669 6670 static int add_affected_mst_dsc_crtcs(struct drm_atomic_commit *state, struct drm_crtc *crtc) 6671 { 6672 struct drm_connector *connector; 6673 struct drm_connector_state *conn_state, *old_conn_state; 6674 struct amdgpu_dm_connector *aconnector = NULL; 6675 int i; 6676 6677 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) { 6678 if (!conn_state->crtc) 6679 conn_state = old_conn_state; 6680 6681 if (conn_state->crtc != crtc) 6682 continue; 6683 6684 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) 6685 continue; 6686 6687 aconnector = to_amdgpu_dm_connector(connector); 6688 if (!aconnector->mst_output_port || !aconnector->mst_root) 6689 aconnector = NULL; 6690 else 6691 break; 6692 } 6693 6694 if (!aconnector) 6695 return 0; 6696 6697 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); 6698 } 6699 6700 /** 6701 * DOC: Cursor Modes - Native vs Overlay 6702 * 6703 * In native mode, the cursor uses a integrated cursor pipe within each DCN hw 6704 * plane. It does not require a dedicated hw plane to enable, but it is 6705 * subjected to the same z-order and scaling as the hw plane. It also has format 6706 * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB 6707 * hw plane. 6708 * 6709 * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its 6710 * own scaling and z-pos. It also has no blending restrictions. It lends to a 6711 * cursor behavior more akin to a DRM client's expectations. However, it does 6712 * occupy an extra DCN plane, and therefore will only be used if a DCN plane is 6713 * available. 6714 */ 6715 6716 /** 6717 * dm_plane_color_pipeline_active() - Check if a plane's color pipeline active. 6718 * @state: DRM atomic state 6719 * @plane: DRM plane to check 6720 * @use_old: if true, inspect the old colorop states; otherwise the new ones 6721 * 6722 * A color pipeline may be selected (color_pipeline != NULL) but still is 6723 * inactive if every colorop in the chain is bypassed. Only return 6724 * true when at least one colorop has bypass == false, meaning the cursor 6725 * would be subjected to the transformation in native mode. 6726 * 6727 * Return: true if the pipeline modifies pixels, false otherwise. 6728 */ 6729 static bool dm_plane_color_pipeline_active(struct drm_atomic_commit *state, 6730 struct drm_plane *plane, 6731 bool use_old) 6732 { 6733 struct drm_colorop *colorop; 6734 struct drm_colorop_state *old_colorop_state, *new_colorop_state; 6735 int i; 6736 6737 for_each_oldnew_colorop_in_state(state, colorop, old_colorop_state, new_colorop_state, i) { 6738 struct drm_colorop_state *cstate = use_old ? old_colorop_state : new_colorop_state; 6739 6740 if (cstate->colorop->plane != plane) 6741 continue; 6742 if (!cstate->bypass) 6743 return true; 6744 } 6745 return false; 6746 } 6747 6748 /** 6749 * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc 6750 * @adev: amdgpu device 6751 * @state: DRM atomic state 6752 * @dm_crtc_state: amdgpu state for the CRTC containing the cursor 6753 * @cursor_mode: Returns the required cursor mode on dm_crtc_state 6754 * 6755 * Get whether the cursor should be enabled in native mode, or overlay mode, on 6756 * the dm_crtc_state. 6757 * 6758 * The cursor should be enabled in overlay mode if there exists an underlying 6759 * plane - on which the cursor may be blended - that is either YUV formatted, 6760 * scaled differently from the cursor, or has a color pipeline active. 6761 * 6762 * Since zpos info is required, drm_atomic_normalize_zpos must be called before 6763 * calling this function. 6764 * 6765 * Return: 0 on success, or an error code if getting the cursor plane state 6766 * failed. 6767 */ 6768 static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 6769 struct drm_atomic_commit *state, 6770 struct dm_crtc_state *dm_crtc_state, 6771 enum amdgpu_dm_cursor_mode *cursor_mode) 6772 { 6773 struct drm_plane_state *old_plane_state, *plane_state, *cursor_state; 6774 struct drm_crtc_state *crtc_state = &dm_crtc_state->base; 6775 struct drm_plane *plane; 6776 bool consider_mode_change = false; 6777 bool entire_crtc_covered = false; 6778 bool cursor_changed = false; 6779 int underlying_scale_w, underlying_scale_h; 6780 int cursor_scale_w, cursor_scale_h; 6781 int i; 6782 6783 /* Overlay cursor not supported on HW before DCN 6784 * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions 6785 * as previous DCN generations, so enable native mode on DCN401/420 6786 * 6787 * Always set native cursor mode when the CRTC is disabled, 6788 * to make sure it doesn't cause atomic commits to fail when 6789 * they are trying to disable the CRTC. 6790 */ 6791 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || 6792 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 6793 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1) || 6794 !dm_crtc_state->base.enable) { 6795 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6796 return 0; 6797 } 6798 6799 /* Init cursor_mode to be the same as current */ 6800 *cursor_mode = dm_crtc_state->cursor_mode; 6801 6802 /* 6803 * Cursor mode can change if a plane's format changes, scale changes, is 6804 * enabled/disabled, z-order changes, or color management properties change. 6805 */ 6806 for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) { 6807 int new_scale_w, new_scale_h, old_scale_w, old_scale_h; 6808 6809 /* Only care about planes on this CRTC */ 6810 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0) 6811 continue; 6812 6813 if (plane->type == DRM_PLANE_TYPE_CURSOR) 6814 cursor_changed = true; 6815 6816 if (drm_atomic_plane_enabling(old_plane_state, plane_state) || 6817 drm_atomic_plane_disabling(old_plane_state, plane_state) || 6818 old_plane_state->fb->format != plane_state->fb->format) { 6819 consider_mode_change = true; 6820 break; 6821 } 6822 6823 dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h); 6824 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h); 6825 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) { 6826 consider_mode_change = true; 6827 break; 6828 } 6829 6830 /* 6831 * A non-cursor plane moving or resizing (without a scale change) 6832 * changes how much of the CRTC it covers. This can create or 6833 * remove a hole under the cursor and thus flip the required 6834 * cursor mode (native vs overlay), so its destination rect must 6835 * be re-evaluated too. 6836 * 6837 * The cursor plane itself is deliberately excluded: the cursor 6838 * mode depends on the underlying planes' coverage, not on the 6839 * cursor's position (see the entire_crtc_covered logic below). 6840 * Triggering on cursor movement would force every legacy cursor 6841 * update off its fast path, and in a cursor-only commit - where 6842 * the underlying planes are not part of the state - the coverage 6843 * loop would see no covering plane and misevaluate the mode as 6844 * overlay, regressing flip-vs-cursor-legacy. 6845 */ 6846 if (plane->type != DRM_PLANE_TYPE_CURSOR && 6847 (old_plane_state->crtc_x != plane_state->crtc_x || 6848 old_plane_state->crtc_y != plane_state->crtc_y || 6849 old_plane_state->crtc_w != plane_state->crtc_w || 6850 old_plane_state->crtc_h != plane_state->crtc_h)) { 6851 consider_mode_change = true; 6852 break; 6853 } 6854 6855 if (dm_plane_color_pipeline_active(state, plane, true) != 6856 dm_plane_color_pipeline_active(state, plane, false)) { 6857 consider_mode_change = true; 6858 break; 6859 } 6860 } 6861 6862 if (!consider_mode_change && !crtc_state->zpos_changed) 6863 return 0; 6864 6865 /* 6866 * If no cursor change on this CRTC, and not enabled on this CRTC, then 6867 * no need to set cursor mode. This avoids needlessly locking the cursor 6868 * state. 6869 */ 6870 if (!cursor_changed && 6871 !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) { 6872 return 0; 6873 } 6874 6875 cursor_state = drm_atomic_get_plane_state(state, 6876 crtc_state->crtc->cursor); 6877 if (IS_ERR(cursor_state)) 6878 return PTR_ERR(cursor_state); 6879 6880 /* Cursor is disabled */ 6881 if (!cursor_state->fb) 6882 return 0; 6883 6884 /* For all planes in descending z-order (all of which are below cursor 6885 * as per zpos definitions), check their scaling and format 6886 */ 6887 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) { 6888 6889 /* Only care about non-cursor planes on this CRTC */ 6890 if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 || 6891 plane->type == DRM_PLANE_TYPE_CURSOR) 6892 continue; 6893 6894 /* Underlying plane is YUV format - use overlay cursor */ 6895 if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) { 6896 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6897 return 0; 6898 } 6899 6900 /* Underlying plane has an active color pipeline - cursor would be transformed */ 6901 if (dm_plane_color_pipeline_active(state, plane, false)) { 6902 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6903 return 0; 6904 } 6905 6906 dm_get_plane_scale(plane_state, 6907 &underlying_scale_w, &underlying_scale_h); 6908 dm_get_plane_scale(cursor_state, 6909 &cursor_scale_w, &cursor_scale_h); 6910 6911 /* Underlying plane has different scale - use overlay cursor */ 6912 if (cursor_scale_w != underlying_scale_w && 6913 cursor_scale_h != underlying_scale_h) { 6914 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6915 return 0; 6916 } 6917 6918 /* If this plane covers the whole CRTC, no need to check planes underneath */ 6919 if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 && 6920 plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay && 6921 plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) { 6922 entire_crtc_covered = true; 6923 break; 6924 } 6925 } 6926 6927 /* If planes do not cover the entire CRTC, use overlay mode to enable 6928 * cursor over holes 6929 */ 6930 if (entire_crtc_covered) 6931 *cursor_mode = DM_CURSOR_NATIVE_MODE; 6932 else 6933 *cursor_mode = DM_CURSOR_OVERLAY_MODE; 6934 6935 return 0; 6936 } 6937 6938 static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev, 6939 struct drm_atomic_commit *state, 6940 struct drm_crtc_state *crtc_state) 6941 { 6942 struct drm_plane *plane; 6943 struct drm_plane_state *new_plane_state, *old_plane_state; 6944 6945 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { 6946 new_plane_state = drm_atomic_get_new_plane_state(state, plane); 6947 old_plane_state = drm_atomic_get_old_plane_state(state, plane); 6948 6949 if (!old_plane_state || !new_plane_state) 6950 continue; 6951 6952 if (old_plane_state->fb && new_plane_state->fb && 6953 get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb)) 6954 return true; 6955 } 6956 6957 return false; 6958 } 6959 6960 /** 6961 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM. 6962 * 6963 * @dev: The DRM device 6964 * @state: The atomic state to commit 6965 * 6966 * Validate that the given atomic state is programmable by DC into hardware. 6967 * This involves constructing a &struct dc_state reflecting the new hardware 6968 * state we wish to commit, then querying DC to see if it is programmable. It's 6969 * important not to modify the existing DC state. Otherwise, atomic_check 6970 * may unexpectedly commit hardware changes. 6971 * 6972 * When validating the DC state, it's important that the right locks are 6973 * acquired. For full updates case which removes/adds/updates streams on one 6974 * CRTC while flipping on another CRTC, acquiring global lock will guarantee 6975 * that any such full update commit will wait for completion of any outstanding 6976 * flip using DRMs synchronization events. 6977 * 6978 * Note that DM adds the affected connectors for all CRTCs in state, when that 6979 * might not seem necessary. This is because DC stream creation requires the 6980 * DC sink, which is tied to the DRM connector state. Cleaning this up should 6981 * be possible but non-trivial - a possible TODO item. 6982 * 6983 * Return: -Error code if validation failed. 6984 */ 6985 static int amdgpu_dm_atomic_check(struct drm_device *dev, 6986 struct drm_atomic_commit *state) 6987 { 6988 struct amdgpu_device *adev = drm_to_adev(dev); 6989 struct dm_atomic_state *dm_state = NULL; 6990 struct dc *dc = adev->dm.dc; 6991 struct drm_connector *connector; 6992 struct drm_connector_state *old_con_state, *new_con_state; 6993 struct drm_crtc *crtc; 6994 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 6995 struct drm_plane *plane; 6996 struct drm_plane_state *old_plane_state, *new_plane_state, *new_cursor_state; 6997 enum dc_status status; 6998 int ret, i; 6999 bool lock_and_validation_needed = false; 7000 bool is_top_most_overlay = true; 7001 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 7002 struct drm_dp_mst_topology_mgr *mgr; 7003 struct drm_dp_mst_topology_state *mst_state; 7004 struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; 7005 7006 trace_amdgpu_dm_atomic_check_begin(state); 7007 7008 ret = drm_atomic_helper_check_modeset(dev, state); 7009 if (ret) { 7010 drm_dbg_atomic(dev, "drm_atomic_helper_check_modeset() failed: %pe\n", ERR_PTR(ret)); 7011 goto fail; 7012 } 7013 7014 /* Check connector changes */ 7015 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7016 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7017 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7018 7019 /* Skip connectors that are disabled or part of modeset already. */ 7020 if (!new_con_state->crtc) 7021 continue; 7022 7023 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc); 7024 if (IS_ERR(new_crtc_state)) { 7025 drm_dbg_atomic(dev, "drm_atomic_get_crtc_state() failed: %pe\n", new_crtc_state); 7026 ret = PTR_ERR(new_crtc_state); 7027 goto fail; 7028 } 7029 7030 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level || 7031 dm_old_con_state->scaling != dm_new_con_state->scaling) 7032 new_crtc_state->connectors_changed = true; 7033 } 7034 7035 if (dc_resource_is_dsc_encoding_supported(dc)) { 7036 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7037 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7038 dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; 7039 } 7040 7041 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7042 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { 7043 ret = add_affected_mst_dsc_crtcs(state, crtc); 7044 if (ret) { 7045 drm_dbg_atomic(dev, "add_affected_mst_dsc_crtcs() failed: %pe\n", ERR_PTR(ret)); 7046 goto fail; 7047 } 7048 } 7049 } 7050 } 7051 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7052 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); 7053 7054 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && 7055 !new_crtc_state->color_mgmt_changed && 7056 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && 7057 dm_old_crtc_state->dsc_force_changed == false) 7058 continue; 7059 7060 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state); 7061 if (ret) { 7062 drm_dbg_atomic(dev, "amdgpu_dm_verify_lut_sizes() failed: %pe\n", ERR_PTR(ret)); 7063 goto fail; 7064 } 7065 7066 if (!new_crtc_state->enable) 7067 continue; 7068 7069 ret = drm_atomic_add_affected_connectors(state, crtc); 7070 if (ret) { 7071 drm_dbg_atomic(dev, "drm_atomic_add_affected_connectors() failed: %pe\n", ERR_PTR(ret)); 7072 goto fail; 7073 } 7074 7075 ret = drm_atomic_add_affected_planes(state, crtc); 7076 if (ret) { 7077 drm_dbg_atomic(dev, "drm_atomic_add_affected_planes() failed: %pe\n", ERR_PTR(ret)); 7078 goto fail; 7079 } 7080 7081 if (dm_old_crtc_state->dsc_force_changed) 7082 new_crtc_state->mode_changed = true; 7083 } 7084 7085 /* 7086 * Add all primary and overlay planes on the CRTC to the state 7087 * whenever a plane is enabled to maintain correct z-ordering 7088 * and to enable fast surface updates. 7089 */ 7090 drm_for_each_crtc(crtc, dev) { 7091 bool modified = false; 7092 7093 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { 7094 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7095 continue; 7096 7097 if (new_plane_state->crtc == crtc || 7098 old_plane_state->crtc == crtc) { 7099 modified = true; 7100 break; 7101 } 7102 } 7103 7104 if (!modified) 7105 continue; 7106 7107 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) { 7108 if (plane->type == DRM_PLANE_TYPE_CURSOR) 7109 continue; 7110 7111 new_plane_state = 7112 drm_atomic_get_plane_state(state, plane); 7113 7114 if (IS_ERR(new_plane_state)) { 7115 ret = PTR_ERR(new_plane_state); 7116 drm_dbg_atomic(dev, "new_plane_state is BAD: %pe\n", new_plane_state); 7117 goto fail; 7118 } 7119 } 7120 } 7121 7122 /* 7123 * DC consults the zpos (layer_index in DC terminology) to determine the 7124 * hw plane on which to enable the hw cursor (see 7125 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in 7126 * atomic state, so call drm helper to normalize zpos. 7127 */ 7128 ret = drm_atomic_normalize_zpos(dev, state); 7129 if (ret) { 7130 drm_dbg(dev, "drm_atomic_normalize_zpos() failed: %pe\n", ERR_PTR(ret)); 7131 goto fail; 7132 } 7133 7134 /* 7135 * Determine whether cursors on each CRTC should be enabled in native or 7136 * overlay mode. 7137 */ 7138 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7139 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7140 7141 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 7142 &dm_new_crtc_state->cursor_mode); 7143 if (ret) { 7144 drm_dbg(dev, "Failed to determine cursor mode: %pe\n", ERR_PTR(ret)); 7145 goto fail; 7146 } 7147 7148 /* 7149 * If overlay cursor is needed, DC cannot go through the 7150 * native cursor update path. All enabled planes on the CRTC 7151 * need to be added for DC to not disable a plane by mistake 7152 */ 7153 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { 7154 if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { 7155 drm_dbg(dev, "Overlay cursor not supported on DCE\n"); 7156 ret = -EINVAL; 7157 goto fail; 7158 } 7159 7160 ret = drm_atomic_add_affected_planes(state, crtc); 7161 if (ret) 7162 goto fail; 7163 } 7164 } 7165 7166 /* Remove exiting planes if they are modified */ 7167 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 7168 7169 ret = dm_update_plane_state(dc, state, plane, 7170 old_plane_state, 7171 new_plane_state, 7172 false, 7173 &lock_and_validation_needed, 7174 &is_top_most_overlay); 7175 if (ret) { 7176 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 7177 goto fail; 7178 } 7179 } 7180 7181 /* Disable all crtcs which require disable */ 7182 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7183 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7184 old_crtc_state, 7185 new_crtc_state, 7186 false, 7187 &lock_and_validation_needed); 7188 if (ret) { 7189 drm_dbg_atomic(dev, "DISABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 7190 goto fail; 7191 } 7192 } 7193 7194 /* Enable all crtcs which require enable */ 7195 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7196 ret = dm_update_crtc_state(&adev->dm, state, crtc, 7197 old_crtc_state, 7198 new_crtc_state, 7199 true, 7200 &lock_and_validation_needed); 7201 if (ret) { 7202 drm_dbg_atomic(dev, "ENABLE: dm_update_crtc_state() failed: %pe\n", ERR_PTR(ret)); 7203 goto fail; 7204 } 7205 } 7206 7207 /* Add new/modified planes */ 7208 for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) { 7209 ret = dm_update_plane_state(dc, state, plane, 7210 old_plane_state, 7211 new_plane_state, 7212 true, 7213 &lock_and_validation_needed, 7214 &is_top_most_overlay); 7215 if (ret) { 7216 drm_dbg_atomic(dev, "dm_update_plane_state() failed: %pe\n", ERR_PTR(ret)); 7217 goto fail; 7218 } 7219 } 7220 7221 #if defined(CONFIG_DRM_AMD_DC_FP) 7222 if (dc_resource_is_dsc_encoding_supported(dc)) { 7223 ret = pre_validate_dsc(state, &dm_state, vars); 7224 if (ret != 0) 7225 goto fail; 7226 } 7227 #endif 7228 7229 /* Run this here since we want to validate the streams we created */ 7230 ret = drm_atomic_helper_check_planes(dev, state); 7231 if (ret) { 7232 drm_dbg_atomic(dev, "drm_atomic_helper_check_planes() failed: %pe\n", ERR_PTR(ret)); 7233 goto fail; 7234 } 7235 7236 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7237 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7238 if (dm_new_crtc_state->mpo_requested) 7239 drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); 7240 } 7241 7242 /* Check cursor restrictions */ 7243 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7244 enum amdgpu_dm_cursor_mode required_cursor_mode; 7245 int is_rotated, is_scaled; 7246 7247 /* Overlay cusor not subject to native cursor restrictions */ 7248 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); 7249 if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) 7250 continue; 7251 7252 /* Check if rotation or scaling is enabled on DCN401 */ 7253 if ((drm_plane_mask(crtc->cursor) & 7254 new_crtc_state->plane_mask) && 7255 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 1) || 7256 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || 7257 amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { 7258 new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); 7259 7260 is_rotated = new_cursor_state && 7261 ((new_cursor_state->rotation & DRM_MODE_ROTATE_MASK) != DRM_MODE_ROTATE_0); 7262 is_scaled = new_cursor_state && ((new_cursor_state->src_w >> 16 != new_cursor_state->crtc_w) || 7263 (new_cursor_state->src_h >> 16 != new_cursor_state->crtc_h)); 7264 7265 if (is_rotated || is_scaled) { 7266 drm_dbg_driver( 7267 crtc->dev, 7268 "[CRTC:%d:%s] cannot enable hardware cursor due to rotation/scaling\n", 7269 crtc->base.id, crtc->name); 7270 ret = -EINVAL; 7271 goto fail; 7272 } 7273 } 7274 7275 /* If HW can only do native cursor, check restrictions again */ 7276 ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state, 7277 &required_cursor_mode); 7278 if (ret) { 7279 drm_dbg_driver(crtc->dev, 7280 "[CRTC:%d:%s] Checking cursor mode failed\n", 7281 crtc->base.id, crtc->name); 7282 goto fail; 7283 } else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) { 7284 drm_dbg_driver(crtc->dev, 7285 "[CRTC:%d:%s] Cannot enable native cursor due to scaling, YUV, or color pipeline restrictions\n", 7286 crtc->base.id, crtc->name); 7287 ret = -EINVAL; 7288 goto fail; 7289 } 7290 } 7291 7292 if (state->legacy_cursor_update) { 7293 /* 7294 * This is a fast cursor update coming from the plane update 7295 * helper, check if it can be done asynchronously for better 7296 * performance. 7297 */ 7298 state->async_update = 7299 !drm_atomic_helper_async_check(dev, state); 7300 7301 /* 7302 * Skip the remaining global validation if this is an async 7303 * update. Cursor updates can be done without affecting 7304 * state or bandwidth calcs and this avoids the performance 7305 * penalty of locking the private state object and 7306 * allocating a new dc_state. 7307 */ 7308 if (state->async_update) 7309 return 0; 7310 } 7311 7312 /* Check scaling and underscan changes*/ 7313 /* TODO Removed scaling changes validation due to inability to commit 7314 * new stream into context w\o causing full reset. Need to 7315 * decide how to handle. 7316 */ 7317 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { 7318 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); 7319 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); 7320 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); 7321 7322 /* Skip any modesets/resets */ 7323 if (!acrtc || drm_atomic_crtc_needs_modeset( 7324 drm_atomic_get_new_crtc_state(state, &acrtc->base))) 7325 continue; 7326 7327 /* Skip any thing not scale or underscan changes */ 7328 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) 7329 continue; 7330 7331 lock_and_validation_needed = true; 7332 } 7333 7334 /* set the slot info for each mst_state based on the link encoding format */ 7335 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 7336 struct amdgpu_dm_connector *aconnector; 7337 struct drm_connector *connector; 7338 struct drm_connector_list_iter iter; 7339 u8 link_coding_cap; 7340 7341 drm_connector_list_iter_begin(dev, &iter); 7342 drm_for_each_connector_iter(connector, &iter) { 7343 if (connector->index == mst_state->mgr->conn_base_id) { 7344 aconnector = to_amdgpu_dm_connector(connector); 7345 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); 7346 drm_dp_mst_update_slots(mst_state, link_coding_cap); 7347 7348 break; 7349 } 7350 } 7351 drm_connector_list_iter_end(&iter); 7352 } 7353 7354 /** 7355 * Streams and planes are reset when there are changes that affect 7356 * bandwidth. Anything that affects bandwidth needs to go through 7357 * DC global validation to ensure that the configuration can be applied 7358 * to hardware. 7359 * 7360 * We have to currently stall out here in atomic_check for outstanding 7361 * commits to finish in this case because our IRQ handlers reference 7362 * DRM state directly - we can end up disabling interrupts too early 7363 * if we don't. 7364 * 7365 * TODO: Remove this stall and drop DM state private objects. 7366 */ 7367 if (lock_and_validation_needed) { 7368 ret = dm_atomic_get_state(state, &dm_state); 7369 if (ret) { 7370 drm_dbg_atomic(dev, "dm_atomic_get_state() failed: %pe\n", ERR_PTR(ret)); 7371 goto fail; 7372 } 7373 7374 ret = do_aquire_global_lock(dev, state); 7375 if (ret) { 7376 drm_dbg_atomic(dev, "do_aquire_global_lock() failed: %pe\n", ERR_PTR(ret)); 7377 goto fail; 7378 } 7379 7380 #if defined(CONFIG_DRM_AMD_DC_FP) 7381 if (dc_resource_is_dsc_encoding_supported(dc)) { 7382 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); 7383 if (ret) { 7384 drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed: %pe\n", ERR_PTR(ret)); 7385 ret = -EINVAL; 7386 goto fail; 7387 } 7388 } 7389 #endif 7390 7391 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); 7392 if (ret) { 7393 drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed: %pe\n", ERR_PTR(ret)); 7394 goto fail; 7395 } 7396 7397 /* 7398 * Perform validation of MST topology in the state: 7399 * We need to perform MST atomic check before calling 7400 * dc_validate_global_state(), or there is a chance 7401 * to get stuck in an infinite loop and hang eventually. 7402 */ 7403 ret = drm_dp_mst_atomic_check(state); 7404 if (ret) { 7405 drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed: %pe\n", ERR_PTR(ret)); 7406 goto fail; 7407 } 7408 status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); 7409 if (status != DC_OK) { 7410 drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", 7411 dc_status_to_str(status), status); 7412 ret = -EINVAL; 7413 goto fail; 7414 } 7415 } else { 7416 /* 7417 * The commit is a fast update. Fast updates shouldn't change 7418 * the DC context, affect global validation, and can have their 7419 * commit work done in parallel with other commits not touching 7420 * the same resource. If we have a new DC context as part of 7421 * the DM atomic state from validation we need to free it and 7422 * retain the existing one instead. 7423 * 7424 * Furthermore, since the DM atomic state only contains the DC 7425 * context and can safely be annulled, we can free the state 7426 * and clear the associated private object now to free 7427 * some memory and avoid a possible use-after-free later. 7428 */ 7429 7430 for (i = 0; i < state->num_private_objs; i++) { 7431 struct drm_private_obj *obj = state->private_objs[i].ptr; 7432 7433 if (obj->funcs == adev->dm.atomic_obj.funcs) { 7434 int j = state->num_private_objs-1; 7435 7436 dm_atomic_destroy_state(obj, 7437 state->private_objs[i].state_to_destroy); 7438 7439 /* If i is not at the end of the array then the 7440 * last element needs to be moved to where i was 7441 * before the array can safely be truncated. 7442 */ 7443 if (i != j) 7444 state->private_objs[i] = 7445 state->private_objs[j]; 7446 7447 state->private_objs[j].ptr = NULL; 7448 state->private_objs[j].state_to_destroy = NULL; 7449 state->private_objs[j].old_state = NULL; 7450 state->private_objs[j].new_state = NULL; 7451 7452 state->num_private_objs = j; 7453 break; 7454 } 7455 } 7456 } 7457 7458 /* Store the overall update type for use later in atomic check. */ 7459 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 7460 struct dm_crtc_state *dm_new_crtc_state = 7461 to_dm_crtc_state(new_crtc_state); 7462 7463 /* 7464 * Only allow async flips for fast updates that don't change 7465 * the FB pitch, the DCC state, rotation, mem_type, etc. 7466 */ 7467 if (new_crtc_state->async_flip && 7468 (lock_and_validation_needed || 7469 amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { 7470 drm_dbg_atomic(crtc->dev, 7471 "[CRTC:%d:%s] async flips are only supported for fast updates\n", 7472 crtc->base.id, crtc->name); 7473 ret = -EINVAL; 7474 goto fail; 7475 } 7476 7477 dm_new_crtc_state->update_type = lock_and_validation_needed ? 7478 UPDATE_TYPE_FULL : UPDATE_TYPE_FAST; 7479 } 7480 7481 /* Must be success */ 7482 WARN_ON(ret); 7483 7484 trace_amdgpu_dm_atomic_check_finish(state, ret); 7485 7486 return ret; 7487 7488 fail: 7489 if (ret == -EDEADLK) 7490 drm_dbg_atomic(dev, "Atomic check stopped to avoid deadlock.\n"); 7491 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) 7492 drm_dbg_atomic(dev, "Atomic check stopped due to signal.\n"); 7493 else 7494 drm_dbg_atomic(dev, "Atomic check failed: %pe\n", ERR_PTR(ret)); 7495 7496 trace_amdgpu_dm_atomic_check_finish(state, ret); 7497 7498 return ret; 7499 } 7500 7501 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev) 7502 { 7503 struct amdgpu_device *adev = drm_to_adev(dev); 7504 struct dc *dc = adev->dm.dc; 7505 int i; 7506 7507 mutex_lock(&adev->dm.dc_lock); 7508 if (dc->current_state) { 7509 for (i = 0; i < dc->current_state->stream_count; ++i) 7510 dc->current_state->streams[i] 7511 ->triggered_crtc_reset.enabled = 7512 adev->dm.force_timing_sync; 7513 7514 dm_enable_per_frame_crtc_master_sync(dc->current_state); 7515 dc_trigger_sync(dc, dc->current_state); 7516 } 7517 mutex_unlock(&adev->dm.dc_lock); 7518 } 7519 7520 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address, 7521 u32 value, const char *func_name) 7522 { 7523 #ifdef DM_CHECK_ADDR_0 7524 if (address == 0) { 7525 drm_err(adev_to_drm(ctx->driver_context), 7526 "invalid register write. address = 0"); 7527 return; 7528 } 7529 #endif 7530 7531 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7532 cgs_write_register(ctx->cgs_device, address, value); 7533 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value); 7534 } 7535 7536 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address, 7537 const char *func_name) 7538 { 7539 u32 value; 7540 #ifdef DM_CHECK_ADDR_0 7541 if (address == 0) { 7542 drm_err(adev_to_drm(ctx->driver_context), 7543 "invalid register read; address = 0\n"); 7544 return 0; 7545 } 7546 #endif 7547 7548 amdgpu_dm_exit_ips_for_hw_access(ctx->dc); 7549 7550 value = cgs_read_register(ctx->cgs_device, address); 7551 7552 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value); 7553 7554 return value; 7555 } 7556 7557 void dm_acpi_process_phy_transition_interlock( 7558 const struct dc_context *ctx, 7559 struct dm_process_phy_transition_init_params process_phy_transition_init_params) 7560 { 7561 // Not yet implemented 7562 } 7563