1ad808910SAlex Deucher# SPDX-License-Identifier: MIT 2*f5d75327SLeo Ma# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved. 3*f5d75327SLeo Ma 44562236bSHarry Wentlandmenu "Display Engine Configuration" 54562236bSHarry Wentland depends on DRM && DRM_AMDGPU 64562236bSHarry Wentland 74562236bSHarry Wentlandconfig DRM_AMD_DC 84562236bSHarry Wentland bool "AMD DC - Enable new display engine" 94562236bSHarry Wentland default y 106f7cd037SSamuel Holland depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64 116ce8f316SNicholas Kazlauskas select SND_HDA_COMPONENT if SND_HDA_CORE 1279b72db6SAo Zhong # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 13901bdf5eSDave Airlie select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) 144562236bSHarry Wentland help 154562236bSHarry Wentland Choose this option if you want to use the new display engine 164562236bSHarry Wentland support for AMDGPU. This adds required support for Vega and 174562236bSHarry Wentland Raven ASICs. 184562236bSHarry Wentland 196f6cb171SLee Jones calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64) 206f6cb171SLee Jones architectures built with Clang (all released versions), whereby the stack 216f6cb171SLee Jones frame gets blown up to well over 5k. This would cause an immediate kernel 226f6cb171SLee Jones panic on most architectures. We'll revert this when the following bug report 236f6cb171SLee Jones has been resolved: https://github.com/llvm/llvm-project/issues/41896. 246f6cb171SLee Jones 254652ae7aSHarry Wentlandconfig DRM_AMD_DC_FP 269d1d02ffSLeo (Sunpeng) Li def_bool n 27dc37a9a0SLeo (Sunpeng) Li help 284652ae7aSHarry Wentland Floating point support, required for DCN-based SoCs 2936d26912SBhawanpreet Lakha 305963cddeSMauro Rossiconfig DRM_AMD_DC_SI 315963cddeSMauro Rossi bool "AMD DC support for Southern Islands ASICs" 32c2c15410SAlex Deucher depends on DRM_AMDGPU_SI 33c2c15410SAlex Deucher depends on DRM_AMD_DC 345963cddeSMauro Rossi help 355963cddeSMauro Rossi Choose this option to enable new AMD DC support for SI asics 365963cddeSMauro Rossi by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. 375963cddeSMauro Rossi Hainan is not supported by AMD DC and it has no physical DCE6. 385963cddeSMauro Rossi 394562236bSHarry Wentlandconfig DEBUG_KERNEL_DC 404562236bSHarry Wentland bool "Enable kgdb break in DC" 414562236bSHarry Wentland depends on DRM_AMD_DC 42c5ff0c19STakashi Iwai depends on KGDB 434562236bSHarry Wentland help 4417fd4fe9SRandy Dunlap Choose this option if you want to hit kdgb_break in assert. 454562236bSHarry Wentland 4686bc2219SWayne Linconfig DRM_AMD_SECURE_DISPLAY 4786bc2219SWayne Lin bool "Enable secure display support" 4886bc2219SWayne Lin depends on DEBUG_FS 494652ae7aSHarry Wentland depends on DRM_AMD_DC_FP 5086bc2219SWayne Lin help 51d155cfffSSui Jingfeng Choose this option if you want to support secure display 5286bc2219SWayne Lin 53d155cfffSSui Jingfeng This option enables the calculation of crc of specific region via 54d155cfffSSui Jingfeng debugfs. Cooperate with specific DMCU FW. 5586bc2219SWayne Lin 564562236bSHarry Wentlandendmenu 57