1ad808910SAlex Deucher# SPDX-License-Identifier: MIT 2f5d75327SLeo Ma# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved. 3f5d75327SLeo Ma 44562236bSHarry Wentlandmenu "Display Engine Configuration" 54562236bSHarry Wentland depends on DRM && DRM_AMDGPU 64562236bSHarry Wentland 74562236bSHarry Wentlandconfig DRM_AMD_DC 84562236bSHarry Wentland bool "AMD DC - Enable new display engine" 94562236bSHarry Wentland default y 10*4217ef9aSHuacai Chen depends on BROKEN || !CC_IS_CLANG || ARM64 || LOONGARCH || RISCV || SPARC64 || X86_64 116ce8f316SNicholas Kazlauskas select SND_HDA_COMPONENT if SND_HDA_CORE 1279b72db6SAo Zhong # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 13*4217ef9aSHuacai Chen select DRM_AMD_DC_FP if ARCH_HAS_KERNEL_FPU_SUPPORT && !(CC_IS_CLANG && (ARM64 || LOONGARCH || RISCV)) 144562236bSHarry Wentland help 154562236bSHarry Wentland Choose this option if you want to use the new display engine 164562236bSHarry Wentland support for AMDGPU. This adds required support for Vega and 174562236bSHarry Wentland Raven ASICs. 184562236bSHarry Wentland 19*4217ef9aSHuacai Chen calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || 20*4217ef9aSHuacai Chen ARM64 || LOONGARCH || RISCV) architectures built with Clang (all released 21*4217ef9aSHuacai Chen versions), whereby the stack frame gets blown up to well over 5k. This 22*4217ef9aSHuacai Chen would cause an immediate kernel panic on most architectures. We'll revert 23*4217ef9aSHuacai Chen this when the following bug report has been resolved: 24*4217ef9aSHuacai Chen https://github.com/llvm/llvm-project/issues/41896. 256f6cb171SLee Jones 264652ae7aSHarry Wentlandconfig DRM_AMD_DC_FP 279d1d02ffSLeo (Sunpeng) Li def_bool n 28dc37a9a0SLeo (Sunpeng) Li help 294652ae7aSHarry Wentland Floating point support, required for DCN-based SoCs 3036d26912SBhawanpreet Lakha 315963cddeSMauro Rossiconfig DRM_AMD_DC_SI 325963cddeSMauro Rossi bool "AMD DC support for Southern Islands ASICs" 33c2c15410SAlex Deucher depends on DRM_AMDGPU_SI 34c2c15410SAlex Deucher depends on DRM_AMD_DC 355963cddeSMauro Rossi help 365963cddeSMauro Rossi Choose this option to enable new AMD DC support for SI asics 375963cddeSMauro Rossi by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. 385963cddeSMauro Rossi Hainan is not supported by AMD DC and it has no physical DCE6. 395963cddeSMauro Rossi 404562236bSHarry Wentlandconfig DEBUG_KERNEL_DC 414562236bSHarry Wentland bool "Enable kgdb break in DC" 424562236bSHarry Wentland depends on DRM_AMD_DC 43c5ff0c19STakashi Iwai depends on KGDB 444562236bSHarry Wentland help 4517fd4fe9SRandy Dunlap Choose this option if you want to hit kdgb_break in assert. 464562236bSHarry Wentland 4786bc2219SWayne Linconfig DRM_AMD_SECURE_DISPLAY 4886bc2219SWayne Lin bool "Enable secure display support" 4986bc2219SWayne Lin depends on DEBUG_FS 504652ae7aSHarry Wentland depends on DRM_AMD_DC_FP 5186bc2219SWayne Lin help 52d155cfffSSui Jingfeng Choose this option if you want to support secure display 5386bc2219SWayne Lin 54d155cfffSSui Jingfeng This option enables the calculation of crc of specific region via 55d155cfffSSui Jingfeng debugfs. Cooperate with specific DMCU FW. 5686bc2219SWayne Lin 574562236bSHarry Wentlandendmenu 58