xref: /linux/drivers/gpu/drm/amd/amdkfd/kfd_topology.h (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02)
1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3  * Copyright 2014-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef __KFD_TOPOLOGY_H__
25 #define __KFD_TOPOLOGY_H__
26 
27 #include <linux/types.h>
28 #include <linux/list.h>
29 #include <linux/kfd_sysfs.h>
30 #include "kfd_crat.h"
31 
32 #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
33 
34 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9	6
35 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 7
36 #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10	7
37 #define HSA_DBG_WATCH_ADDR_MASK_HI_BIT  \
38 			(29 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)
39 #define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3 \
40 			(30 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)
41 
42 struct kfd_node_properties {
43 	uint64_t hive_id;
44 	uint32_t cpu_cores_count;
45 	uint32_t simd_count;
46 	uint32_t mem_banks_count;
47 	uint32_t caches_count;
48 	uint32_t io_links_count;
49 	uint32_t p2p_links_count;
50 	uint32_t cpu_core_id_base;
51 	uint32_t simd_id_base;
52 	uint32_t capability;
53 	uint64_t debug_prop;
54 	uint32_t max_waves_per_simd;
55 	uint32_t lds_size_in_kb;
56 	uint32_t gds_size_in_kb;
57 	uint32_t num_gws;
58 	uint32_t wave_front_size;
59 	uint32_t array_count;
60 	uint32_t simd_arrays_per_engine;
61 	uint32_t cu_per_simd_array;
62 	uint32_t simd_per_cu;
63 	uint32_t max_slots_scratch_cu;
64 	uint32_t engine_id;
65 	uint32_t gfx_target_version;
66 	uint32_t vendor_id;
67 	uint32_t device_id;
68 	uint32_t location_id;
69 	uint32_t domain;
70 	uint32_t max_engine_clk_fcompute;
71 	uint32_t max_engine_clk_ccompute;
72 	int32_t  drm_render_minor;
73 	uint32_t num_sdma_engines;
74 	uint32_t num_sdma_xgmi_engines;
75 	uint32_t num_sdma_queues_per_engine;
76 	uint32_t num_cp_queues;
77 	char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
78 };
79 
80 struct kfd_mem_properties {
81 	struct list_head	list;
82 	uint32_t		heap_type;
83 	uint64_t		size_in_bytes;
84 	uint32_t		flags;
85 	uint32_t		width;
86 	uint32_t		mem_clk_max;
87 	struct kfd_node		*gpu;
88 	struct kobject		*kobj;
89 	struct attribute	attr;
90 };
91 
92 #define CACHE_SIBLINGMAP_SIZE 128
93 
94 struct kfd_cache_properties {
95 	struct list_head	list;
96 	uint32_t		processor_id_low;
97 	uint32_t		cache_level;
98 	uint32_t		cache_size;
99 	uint32_t		cacheline_size;
100 	uint32_t		cachelines_per_tag;
101 	uint32_t		cache_assoc;
102 	uint32_t		cache_latency;
103 	uint32_t		cache_type;
104 	uint8_t			sibling_map[CACHE_SIBLINGMAP_SIZE];
105 	struct kfd_node		*gpu;
106 	struct kobject		*kobj;
107 	struct attribute	attr;
108 	uint32_t		sibling_map_size;
109 };
110 
111 struct kfd_iolink_properties {
112 	struct list_head	list;
113 	uint32_t		iolink_type;
114 	uint32_t		ver_maj;
115 	uint32_t		ver_min;
116 	uint32_t		node_from;
117 	uint32_t		node_to;
118 	uint32_t		weight;
119 	uint32_t		min_latency;
120 	uint32_t		max_latency;
121 	uint32_t		min_bandwidth;
122 	uint32_t		max_bandwidth;
123 	uint32_t		rec_transfer_size;
124 	uint32_t		flags;
125 	struct kfd_node		*gpu;
126 	struct kobject		*kobj;
127 	struct attribute	attr;
128 };
129 
130 struct kfd_perf_properties {
131 	struct list_head	list;
132 	char			block_name[16];
133 	uint32_t		max_concurrent;
134 	struct attribute_group	*attr_group;
135 };
136 
137 struct kfd_topology_device {
138 	struct list_head		list;
139 	uint32_t			gpu_id;
140 	uint32_t			proximity_domain;
141 	struct kfd_node_properties	node_props;
142 	struct list_head		mem_props;
143 	struct list_head		cache_props;
144 	struct list_head		io_link_props;
145 	struct list_head		p2p_link_props;
146 	struct list_head		perf_props;
147 	struct kfd_node			*gpu;
148 	struct kobject			*kobj_node;
149 	struct kobject			*kobj_mem;
150 	struct kobject			*kobj_cache;
151 	struct kobject			*kobj_iolink;
152 	struct kobject			*kobj_p2plink;
153 	struct kobject			*kobj_perf;
154 	struct attribute		attr_gpuid;
155 	struct attribute		attr_name;
156 	struct attribute		attr_props;
157 	union {
158 		uint8_t				oem_id[CRAT_OEMID_LENGTH];
159 		uint64_t			oem_id64;
160 	};
161 	uint8_t				oem_table_id[CRAT_OEMTABLEID_LENGTH];
162 	uint32_t			oem_revision;
163 };
164 
165 struct kfd_system_properties {
166 	uint32_t		num_devices;     /* Number of H-NUMA nodes */
167 	uint32_t		generation_count;
168 	uint64_t		platform_oem;
169 	uint64_t		platform_id;
170 	uint64_t		platform_rev;
171 	struct kobject		*kobj_topology;
172 	struct kobject		*kobj_nodes;
173 	struct attribute	attr_genid;
174 	struct attribute	attr_props;
175 };
176 
177 struct kfd_topology_device *kfd_create_topology_device(
178 		struct list_head *device_list);
179 void kfd_release_topology_device_list(struct list_head *device_list);
180 
181 #endif /* __KFD_TOPOLOGY_H__ */
182