1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2020-2021 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef KFD_SVM_H_ 26 #define KFD_SVM_H_ 27 28 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 29 30 #include <linux/rwsem.h> 31 #include <linux/list.h> 32 #include <linux/mutex.h> 33 #include <linux/sched/mm.h> 34 #include "amdgpu.h" 35 #include "kfd_priv.h" 36 37 #define SVM_RANGE_VRAM_DOMAIN (1UL << 0) 38 #define SVM_ADEV_PGMAP_OWNER(adev)\ 39 ((adev)->hive ? (void *)(adev)->hive : (void *)(adev)) 40 41 struct svm_range_bo { 42 struct amdgpu_bo bo; 43 struct kref kref; 44 struct list_head range_list; /* all svm ranges shared this bo */ 45 spinlock_t list_lock; 46 struct mm_struct *mm; 47 uint32_t evicting; 48 struct work_struct release_work; 49 struct kfd_node *node; 50 }; 51 52 enum svm_work_list_ops { 53 SVM_OP_NULL, 54 SVM_OP_UNMAP_RANGE, 55 SVM_OP_UPDATE_RANGE_NOTIFIER, 56 SVM_OP_UPDATE_RANGE_NOTIFIER_AND_MAP, 57 SVM_OP_ADD_RANGE, 58 SVM_OP_ADD_RANGE_AND_MAP 59 }; 60 61 struct svm_work_list_item { 62 enum svm_work_list_ops op; 63 struct mm_struct *mm; 64 }; 65 66 /** 67 * struct svm_range - shared virtual memory range 68 * 69 * @svms: list of svm ranges, structure defined in kfd_process 70 * @migrate_mutex: to serialize range migration, validation and mapping update 71 * @start: range start address in pages 72 * @last: range last address in pages 73 * @it_node: node [start, last] stored in interval tree, start, last are page 74 * aligned, page size is (last - start + 1) 75 * @list: link list node, used to scan all ranges of svms 76 * @update_list:link list node used to add to update_list 77 * @mapping: bo_va mapping structure to create and update GPU page table 78 * @npages: number of pages 79 * @vram_pages: vram pages number in this svm_range 80 * @dma_addr: dma mapping address on each GPU for system memory physical page 81 * @ttm_res: vram ttm resource map 82 * @offset: range start offset within mm_nodes 83 * @svm_bo: struct to manage splited amdgpu_bo 84 * @svm_bo_list:link list node, to scan all ranges which share same svm_bo 85 * @lock: protect prange start, last, child_list, svm_bo_list 86 * @saved_flags:save/restore current PF_MEMALLOC flags 87 * @flags: flags defined as KFD_IOCTL_SVM_FLAG_* 88 * @perferred_loc: perferred location, 0 for CPU, or GPU id 89 * @perfetch_loc: last prefetch location, 0 for CPU, or GPU id 90 * @actual_loc: this svm_range location. 0: all pages are from sys ram; 91 * GPU id: this svm_range may include vram pages from GPU with 92 * id actual_loc. 93 * @granularity:migration granularity, log2 num pages 94 * @invalid: not 0 means cpu page table is invalidated 95 * @validate_timestamp: system timestamp when range is validated 96 * @notifier: register mmu interval notifier 97 * @work_item: deferred work item information 98 * @deferred_list: list header used to add range to deferred list 99 * @child_list: list header for split ranges which are not added to svms yet 100 * @bitmap_access: index bitmap of GPUs which can access the range 101 * @bitmap_aip: index bitmap of GPUs which can access the range in place 102 * @bitmap_needs_unmap: index bitmap of GPUs which currently set NO_ACCESS 103 * @bitmap_mapped: index bitmap of GPUs which currently have the range mapped 104 * @mapping_done: true if range_validate_and_map complete successfully 105 * 106 * Data structure for virtual memory range shared by CPU and GPUs, it can be 107 * allocated from system memory ram or device vram, and migrate from ram to vram 108 * or from vram to ram. 109 */ 110 struct svm_range { 111 struct svm_range_list *svms; 112 struct mutex migrate_mutex; 113 unsigned long start; 114 unsigned long last; 115 struct interval_tree_node it_node; 116 struct list_head list; 117 struct list_head update_list; 118 uint64_t npages; 119 uint64_t vram_pages; 120 dma_addr_t *dma_addr[MAX_GPU_INSTANCE]; 121 struct ttm_resource *ttm_res; 122 uint64_t offset; 123 struct svm_range_bo *svm_bo; 124 struct list_head svm_bo_list; 125 struct mutex lock; 126 unsigned int saved_flags; 127 uint32_t flags; 128 uint32_t preferred_loc; 129 uint32_t prefetch_loc; 130 uint32_t actual_loc; 131 uint8_t granularity; 132 atomic_t invalid; 133 ktime_t validate_timestamp; 134 struct mmu_interval_notifier notifier; 135 struct svm_work_list_item work_item; 136 struct list_head deferred_list; 137 struct list_head child_list; 138 DECLARE_BITMAP(bitmap_access, MAX_GPU_INSTANCE); 139 DECLARE_BITMAP(bitmap_aip, MAX_GPU_INSTANCE); 140 DECLARE_BITMAP(bitmap_needs_unmap, MAX_GPU_INSTANCE); 141 DECLARE_BITMAP(bitmap_mapped, MAX_GPU_INSTANCE); 142 bool mapping_done; 143 atomic_t queue_refcount; 144 }; 145 146 static inline void svm_range_lock(struct svm_range *prange) 147 { 148 mutex_lock(&prange->lock); 149 prange->saved_flags = memalloc_noreclaim_save(); 150 151 } 152 static inline void svm_range_unlock(struct svm_range *prange) 153 { 154 memalloc_noreclaim_restore(prange->saved_flags); 155 mutex_unlock(&prange->lock); 156 } 157 158 static inline struct svm_range_bo *svm_range_bo_ref(struct svm_range_bo *svm_bo) 159 { 160 if (svm_bo) 161 kref_get(&svm_bo->kref); 162 163 return svm_bo; 164 } 165 166 int svm_range_list_init(struct kfd_process *p); 167 void svm_range_list_fini(struct kfd_process *p); 168 int svm_ioctl(struct kfd_process *p, enum kfd_ioctl_svm_op op, uint64_t start, 169 uint64_t size, uint32_t nattrs, 170 struct kfd_ioctl_svm_attribute *attrs); 171 struct svm_range *svm_range_from_addr(struct svm_range_list *svms, 172 unsigned long addr, 173 struct svm_range **parent); 174 struct kfd_node *svm_range_get_node_by_id(struct svm_range *prange, 175 uint32_t gpu_id); 176 void svm_range_bo_destroy(struct ttm_buffer_object *tbo); 177 int svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, 178 bool clear); 179 void svm_range_vram_node_free(struct svm_range *prange); 180 int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, 181 uint32_t vmid, uint32_t node_id, uint64_t addr, uint64_t ts, 182 bool write_fault); 183 int svm_range_evict_svm_bo(struct amdgpu_bo *bo); 184 185 void svm_range_add_list_work(struct svm_range_list *svms, 186 struct svm_range *prange, struct mm_struct *mm, 187 enum svm_work_list_ops op); 188 void schedule_deferred_list_work(struct svm_range_list *svms); 189 void svm_range_dma_unmap_dev(struct device *dev, dma_addr_t *dma_addr, 190 unsigned long offset, unsigned long npages); 191 void svm_range_dma_unmap(struct svm_range *prange); 192 void svm_range_get_info(struct kfd_process *p, uint32_t *num_svm_ranges, 193 uint64_t *svm_priv_data_size); 194 int kfd_criu_checkpoint_svm(struct kfd_process *p, 195 uint8_t __user *user_priv_data, 196 uint64_t *priv_offset); 197 int kfd_criu_restore_svm(struct kfd_process *p, 198 uint8_t __user *user_priv_ptr, 199 uint64_t *priv_data_offset, 200 uint64_t max_priv_data_size); 201 int kfd_criu_resume_svm(struct kfd_process *p); 202 struct kfd_process_device * 203 svm_range_get_pdd_by_node(struct svm_range *prange, struct kfd_node *node); 204 void svm_range_list_lock_and_flush_work(struct svm_range_list *svms, struct mm_struct *mm); 205 206 /* SVM API and HMM page migration work together, device memory type 207 * is initialized to not 0 when page migration register device memory. 208 */ 209 #define KFD_IS_SVM_API_SUPPORTED(adev) ((adev)->kfd.pgmap.type != 0 ||\ 210 ((adev)->apu_prefer_gtt)) 211 212 void svm_range_bo_unref_async(struct svm_range_bo *svm_bo); 213 214 void svm_range_set_max_pages(struct amdgpu_device *adev); 215 int svm_range_switch_xnack_reserve_mem(struct kfd_process *p, bool xnack_enabled); 216 217 #else 218 219 struct kfd_process; 220 221 static inline int svm_range_list_init(struct kfd_process *p) 222 { 223 return 0; 224 } 225 static inline void svm_range_list_fini(struct kfd_process *p) 226 { 227 /* empty */ 228 } 229 230 static inline int svm_range_restore_pages(struct amdgpu_device *adev, 231 unsigned int pasid, 232 uint32_t client_id, uint32_t node_id, 233 uint64_t addr, uint64_t ts, bool write_fault) 234 { 235 return -EFAULT; 236 } 237 238 static inline void svm_range_bo_destroy(struct ttm_buffer_object *tbo) 239 { 240 } 241 242 static inline int svm_range_evict_svm_bo(struct amdgpu_bo *bo) 243 { 244 return 0; 245 } 246 247 static inline void svm_range_get_info(struct kfd_process *p, 248 uint32_t *num_svm_ranges, 249 uint64_t *svm_priv_data_size) 250 { 251 *num_svm_ranges = 0; 252 *svm_priv_data_size = 0; 253 } 254 255 static inline int kfd_criu_checkpoint_svm(struct kfd_process *p, 256 uint8_t __user *user_priv_data, 257 uint64_t *priv_offset) 258 { 259 return 0; 260 } 261 262 static inline int kfd_criu_restore_svm(struct kfd_process *p, 263 uint8_t __user *user_priv_ptr, 264 uint64_t *priv_data_offset, 265 uint64_t max_priv_data_size) 266 { 267 return -EINVAL; 268 } 269 270 static inline int kfd_criu_resume_svm(struct kfd_process *p) 271 { 272 return 0; 273 } 274 275 static inline void svm_range_set_max_pages(struct amdgpu_device *adev) 276 { 277 } 278 279 #define KFD_IS_SVM_API_SUPPORTED(dev) false 280 281 #endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */ 282 283 #endif /* KFD_SVM_H_ */ 284