1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pid %d\n", 73 pqm->process->lead_thread->pid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 /* The MES context flush needs to filter out the case which the 90 * KFD process is created without setting up the MES context and 91 * queue for creating a compute queue. 92 */ 93 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && 95 down_read_trylock(&dev->adev->reset_domain->sem)) { 96 amdgpu_mes_flush_shader_debugger(dev->adev, 97 pdd->proc_ctx_gpu_addr); 98 up_read(&dev->adev->reset_domain->sem); 99 } 100 pdd->already_dequeued = true; 101 } 102 103 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 104 void *gws) 105 { 106 struct mqd_update_info minfo = {0}; 107 struct kfd_node *dev = NULL; 108 struct process_queue_node *pqn; 109 struct kfd_process_device *pdd; 110 struct kgd_mem *mem = NULL; 111 int ret; 112 113 pqn = get_queue_by_qid(pqm, qid); 114 if (!pqn) { 115 pr_err("Queue id does not match any known queue\n"); 116 return -EINVAL; 117 } 118 119 if (pqn->q) 120 dev = pqn->q->device; 121 if (WARN_ON(!dev)) 122 return -ENODEV; 123 124 pdd = kfd_get_process_device_data(dev, pqm->process); 125 if (!pdd) { 126 pr_err("Process device data doesn't exist\n"); 127 return -EINVAL; 128 } 129 130 /* Only allow one queue per process can have GWS assigned */ 131 if (gws && pdd->qpd.num_gws) 132 return -EBUSY; 133 134 if (!gws && pdd->qpd.num_gws == 0) 135 return -EINVAL; 136 137 if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 138 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 139 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && 140 !dev->kfd->shared_resources.enable_mes) { 141 if (gws) 142 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 143 gws, &mem); 144 else 145 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 146 pqn->q->gws); 147 if (unlikely(ret)) 148 return ret; 149 pqn->q->gws = mem; 150 } else { 151 /* 152 * Intentionally set GWS to a non-NULL value 153 * for devices that do not use GWS for global wave 154 * synchronization but require the formality 155 * of setting GWS for cooperative groups. 156 */ 157 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 158 } 159 160 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 161 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 162 163 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 164 pqn->q, &minfo); 165 } 166 167 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 168 { 169 int i; 170 171 for (i = 0; i < p->n_pdds; i++) 172 kfd_process_dequeue_from_device(p->pdds[i]); 173 } 174 175 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 176 { 177 INIT_LIST_HEAD(&pqm->queues); 178 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 179 GFP_KERNEL); 180 if (!pqm->queue_slot_bitmap) 181 return -ENOMEM; 182 pqm->process = p; 183 184 return 0; 185 } 186 187 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 188 struct process_queue_node *pqn) 189 { 190 struct kfd_node *dev; 191 struct kfd_process_device *pdd; 192 193 dev = pqn->q->device; 194 195 pdd = kfd_get_process_device_data(dev, pqm->process); 196 if (!pdd) { 197 pr_err("Process device data doesn't exist\n"); 198 return; 199 } 200 201 if (pqn->q->gws) { 202 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 203 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 204 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && 205 !dev->kfd->shared_resources.enable_mes) 206 amdgpu_amdkfd_remove_gws_from_process( 207 pqm->process->kgd_process_info, pqn->q->gws); 208 pdd->qpd.num_gws = 0; 209 } 210 211 if (dev->kfd->shared_resources.enable_mes) { 212 amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); 213 amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 214 } 215 } 216 217 void pqm_uninit(struct process_queue_manager *pqm) 218 { 219 struct process_queue_node *pqn, *next; 220 221 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 222 if (pqn->q) { 223 struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, 224 pqm->process); 225 if (pdd) { 226 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 227 kfd_queue_release_buffers(pdd, &pqn->q->properties); 228 } else { 229 WARN_ON(!pdd); 230 } 231 pqm_clean_queue_resource(pqm, pqn); 232 } 233 234 kfd_procfs_del_queue(pqn->q); 235 uninit_queue(pqn->q); 236 list_del(&pqn->process_queue_list); 237 kfree(pqn); 238 } 239 240 bitmap_free(pqm->queue_slot_bitmap); 241 pqm->queue_slot_bitmap = NULL; 242 } 243 244 static int init_user_queue(struct process_queue_manager *pqm, 245 struct kfd_node *dev, struct queue **q, 246 struct queue_properties *q_properties, 247 unsigned int qid) 248 { 249 int retval; 250 251 /* Doorbell initialized in user space*/ 252 q_properties->doorbell_ptr = NULL; 253 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 254 255 /* let DQM handle it*/ 256 q_properties->vmid = 0; 257 q_properties->queue_id = qid; 258 259 retval = init_queue(q, q_properties); 260 if (retval != 0) 261 return retval; 262 263 (*q)->device = dev; 264 (*q)->process = pqm->process; 265 266 if (dev->kfd->shared_resources.enable_mes) { 267 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 268 AMDGPU_MES_GANG_CTX_SIZE, 269 &(*q)->gang_ctx_bo, 270 &(*q)->gang_ctx_gpu_addr, 271 &(*q)->gang_ctx_cpu_ptr, 272 false); 273 if (retval) { 274 pr_err("failed to allocate gang context bo\n"); 275 goto cleanup; 276 } 277 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 278 279 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 280 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 281 */ 282 if (((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) 283 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { 284 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 285 pr_err("Queue memory allocated to wrong device\n"); 286 retval = -EINVAL; 287 goto free_gang_ctx_bo; 288 } 289 290 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 291 &(*q)->wptr_bo_gart); 292 if (retval) { 293 pr_err("Failed to map wptr bo to GART\n"); 294 goto free_gang_ctx_bo; 295 } 296 } 297 } 298 299 pr_debug("PQM After init queue"); 300 return 0; 301 302 free_gang_ctx_bo: 303 amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo); 304 cleanup: 305 uninit_queue(*q); 306 *q = NULL; 307 return retval; 308 } 309 310 int pqm_create_queue(struct process_queue_manager *pqm, 311 struct kfd_node *dev, 312 struct queue_properties *properties, 313 unsigned int *qid, 314 const struct kfd_criu_queue_priv_data *q_data, 315 const void *restore_mqd, 316 const void *restore_ctl_stack, 317 uint32_t *p_doorbell_offset_in_process) 318 { 319 int retval; 320 struct kfd_process_device *pdd; 321 struct queue *q; 322 struct process_queue_node *pqn; 323 struct kernel_queue *kq; 324 enum kfd_queue_type type = properties->type; 325 unsigned int max_queues = 127; /* HWS limit */ 326 327 /* 328 * On GFX 9.4.3/9.5.0, increase the number of queues that 329 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0. 330 */ 331 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 332 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 333 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) 334 max_queues = 255; 335 336 q = NULL; 337 kq = NULL; 338 339 pdd = kfd_get_process_device_data(dev, pqm->process); 340 if (!pdd) { 341 pr_err("Process device data doesn't exist\n"); 342 return -1; 343 } 344 345 /* 346 * for debug process, verify that it is within the static queues limit 347 * currently limit is set to half of the total avail HQD slots 348 * If we are just about to create DIQ, the is_debug flag is not set yet 349 * Hence we also check the type as well 350 */ 351 if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ)) 352 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 353 354 if (pdd->qpd.queue_count >= max_queues) 355 return -ENOSPC; 356 357 if (q_data) { 358 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 359 *qid = q_data->q_id; 360 } else 361 retval = find_available_queue_slot(pqm, qid); 362 363 if (retval != 0) 364 return retval; 365 366 /* Register process if this is the first queue */ 367 if (list_empty(&pdd->qpd.queues_list) && 368 list_empty(&pdd->qpd.priv_queue_list)) 369 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 370 371 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ 372 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { 373 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 374 AMDGPU_MES_PROC_CTX_SIZE, 375 &pdd->proc_ctx_bo, 376 &pdd->proc_ctx_gpu_addr, 377 &pdd->proc_ctx_cpu_ptr, 378 false); 379 if (retval) { 380 dev_err(dev->adev->dev, "failed to allocate process context bo\n"); 381 return retval; 382 } 383 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); 384 } 385 386 pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); 387 if (!pqn) { 388 retval = -ENOMEM; 389 goto err_allocate_pqn; 390 } 391 392 switch (type) { 393 case KFD_QUEUE_TYPE_SDMA: 394 case KFD_QUEUE_TYPE_SDMA_XGMI: 395 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 396 /* SDMA queues are always allocated statically no matter 397 * which scheduler mode is used. We also do not need to 398 * check whether a SDMA queue can be allocated here, because 399 * allocate_sdma_queue() in create_queue() has the 400 * corresponding check logic. 401 */ 402 retval = init_user_queue(pqm, dev, &q, properties, *qid); 403 if (retval != 0) 404 goto err_create_queue; 405 pqn->q = q; 406 pqn->kq = NULL; 407 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 408 restore_mqd, restore_ctl_stack); 409 print_queue(q); 410 break; 411 412 case KFD_QUEUE_TYPE_COMPUTE: 413 /* check if there is over subscription */ 414 if ((dev->dqm->sched_policy == 415 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 416 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 417 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 418 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 419 retval = -EPERM; 420 goto err_create_queue; 421 } 422 423 retval = init_user_queue(pqm, dev, &q, properties, *qid); 424 if (retval != 0) 425 goto err_create_queue; 426 pqn->q = q; 427 pqn->kq = NULL; 428 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 429 restore_mqd, restore_ctl_stack); 430 print_queue(q); 431 break; 432 case KFD_QUEUE_TYPE_DIQ: 433 kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ); 434 if (!kq) { 435 retval = -ENOMEM; 436 goto err_create_queue; 437 } 438 kq->queue->properties.queue_id = *qid; 439 pqn->kq = kq; 440 pqn->q = NULL; 441 retval = kfd_process_drain_interrupts(pdd); 442 if (retval) 443 break; 444 445 retval = dev->dqm->ops.create_kernel_queue(dev->dqm, 446 kq, &pdd->qpd); 447 break; 448 default: 449 WARN(1, "Invalid queue type %d", type); 450 retval = -EINVAL; 451 } 452 453 if (retval != 0) { 454 if ((type == KFD_QUEUE_TYPE_SDMA || 455 type == KFD_QUEUE_TYPE_SDMA_XGMI || 456 type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && 457 retval == -ENOMEM) 458 pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", 459 pqm->process->lead_thread->pid, type, retval); 460 else 461 pr_err("process pid %d DQM create queue type %d failed. ret %d\n", 462 pqm->process->lead_thread->pid, type, retval); 463 goto err_create_queue; 464 } 465 466 if (q && p_doorbell_offset_in_process) { 467 /* Return the doorbell offset within the doorbell page 468 * to the caller so it can be passed up to user mode 469 * (in bytes). 470 * relative doorbell index = Absolute doorbell index - 471 * absolute index of first doorbell in the page. 472 */ 473 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 474 pdd->qpd.proc_doorbells, 475 0, 476 pdd->dev->kfd->device_info.doorbell_size); 477 478 *p_doorbell_offset_in_process = (q->properties.doorbell_off 479 - first_db_index) * sizeof(uint32_t); 480 } 481 482 pr_debug("PQM After DQM create queue\n"); 483 484 list_add(&pqn->process_queue_list, &pqm->queues); 485 486 if (q) { 487 pr_debug("PQM done creating queue\n"); 488 kfd_procfs_add_queue(q); 489 print_queue_properties(&q->properties); 490 } 491 492 return retval; 493 494 err_create_queue: 495 uninit_queue(q); 496 if (kq) 497 kernel_queue_uninit(kq); 498 kfree(pqn); 499 err_allocate_pqn: 500 /* check if queues list is empty unregister process from device */ 501 clear_bit(*qid, pqm->queue_slot_bitmap); 502 if (list_empty(&pdd->qpd.queues_list) && 503 list_empty(&pdd->qpd.priv_queue_list)) 504 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 505 return retval; 506 } 507 508 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 509 { 510 struct process_queue_node *pqn; 511 struct kfd_process_device *pdd; 512 struct device_queue_manager *dqm; 513 struct kfd_node *dev; 514 int retval; 515 516 dqm = NULL; 517 518 retval = 0; 519 520 pqn = get_queue_by_qid(pqm, qid); 521 if (!pqn) { 522 pr_err("Queue id does not match any known queue\n"); 523 return -EINVAL; 524 } 525 526 dev = NULL; 527 if (pqn->kq) 528 dev = pqn->kq->dev; 529 if (pqn->q) 530 dev = pqn->q->device; 531 if (WARN_ON(!dev)) 532 return -ENODEV; 533 534 pdd = kfd_get_process_device_data(dev, pqm->process); 535 if (!pdd) { 536 pr_err("Process device data doesn't exist\n"); 537 return -1; 538 } 539 540 if (pqn->kq) { 541 /* destroy kernel queue (DIQ) */ 542 dqm = pqn->kq->dev->dqm; 543 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 544 kernel_queue_uninit(pqn->kq); 545 } 546 547 if (pqn->q) { 548 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 549 if (retval) 550 goto err_destroy_queue; 551 552 dqm = pqn->q->device->dqm; 553 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 554 if (retval) { 555 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 556 pdd->pasid, 557 pqn->q->properties.queue_id, retval); 558 if (retval != -ETIME && retval != -EIO) 559 goto err_destroy_queue; 560 } 561 kfd_procfs_del_queue(pqn->q); 562 kfd_queue_release_buffers(pdd, &pqn->q->properties); 563 pqm_clean_queue_resource(pqm, pqn); 564 uninit_queue(pqn->q); 565 } 566 567 list_del(&pqn->process_queue_list); 568 kfree(pqn); 569 clear_bit(qid, pqm->queue_slot_bitmap); 570 571 if (list_empty(&pdd->qpd.queues_list) && 572 list_empty(&pdd->qpd.priv_queue_list)) 573 dqm->ops.unregister_process(dqm, &pdd->qpd); 574 575 err_destroy_queue: 576 return retval; 577 } 578 579 int pqm_update_queue_properties(struct process_queue_manager *pqm, 580 unsigned int qid, struct queue_properties *p) 581 { 582 int retval; 583 struct process_queue_node *pqn; 584 585 pqn = get_queue_by_qid(pqm, qid); 586 if (!pqn || !pqn->q) { 587 pr_debug("No queue %d exists for update operation\n", qid); 588 return -EFAULT; 589 } 590 591 /* 592 * Update with NULL ring address is used to disable the queue 593 */ 594 if (p->queue_address && p->queue_size) { 595 struct kfd_process_device *pdd; 596 struct amdgpu_vm *vm; 597 struct queue *q = pqn->q; 598 int err; 599 600 pdd = kfd_get_process_device_data(q->device, q->process); 601 if (!pdd) 602 return -ENODEV; 603 vm = drm_priv_to_vm(pdd->drm_priv); 604 err = amdgpu_bo_reserve(vm->root.bo, false); 605 if (err) 606 return err; 607 608 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 609 p->queue_size)) { 610 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 611 p->queue_address, p->queue_size); 612 return -EFAULT; 613 } 614 615 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo); 616 kfd_queue_buffer_put(&pqn->q->properties.ring_bo); 617 amdgpu_bo_unreserve(vm->root.bo); 618 619 pqn->q->properties.ring_bo = p->ring_bo; 620 } 621 622 pqn->q->properties.queue_address = p->queue_address; 623 pqn->q->properties.queue_size = p->queue_size; 624 pqn->q->properties.queue_percent = p->queue_percent; 625 pqn->q->properties.priority = p->priority; 626 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 627 628 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 629 pqn->q, NULL); 630 if (retval != 0) 631 return retval; 632 633 return 0; 634 } 635 636 int pqm_update_mqd(struct process_queue_manager *pqm, 637 unsigned int qid, struct mqd_update_info *minfo) 638 { 639 int retval; 640 struct process_queue_node *pqn; 641 642 pqn = get_queue_by_qid(pqm, qid); 643 if (!pqn) { 644 pr_debug("No queue %d exists for update operation\n", qid); 645 return -EFAULT; 646 } 647 648 /* CUs are masked for debugger requirements so deny user mask */ 649 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 650 return -EBUSY; 651 652 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 653 if (minfo && minfo->cu_mask.ptr && 654 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { 655 int i; 656 657 for (i = 0; i < minfo->cu_mask.count; i += 2) { 658 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 659 660 if (cu_pair && cu_pair != 0x3) { 661 pr_debug("CUs must be adjacent pairwise enabled.\n"); 662 return -EINVAL; 663 } 664 } 665 } 666 667 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 668 pqn->q, minfo); 669 if (retval != 0) 670 return retval; 671 672 if (minfo && minfo->cu_mask.ptr) 673 pqn->q->properties.is_user_cu_masked = true; 674 675 return 0; 676 } 677 678 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 679 unsigned int qid) 680 { 681 struct process_queue_node *pqn; 682 683 pqn = get_queue_by_qid(pqm, qid); 684 return pqn ? pqn->q : NULL; 685 } 686 687 int pqm_get_wave_state(struct process_queue_manager *pqm, 688 unsigned int qid, 689 void __user *ctl_stack, 690 u32 *ctl_stack_used_size, 691 u32 *save_area_used_size) 692 { 693 struct process_queue_node *pqn; 694 695 pqn = get_queue_by_qid(pqm, qid); 696 if (!pqn) { 697 pr_debug("amdkfd: No queue %d exists for operation\n", 698 qid); 699 return -EFAULT; 700 } 701 702 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 703 pqn->q, 704 ctl_stack, 705 ctl_stack_used_size, 706 save_area_used_size); 707 } 708 709 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 710 uint64_t exception_clear_mask, 711 void __user *buf, 712 int *num_qss_entries, 713 uint32_t *entry_size) 714 { 715 struct process_queue_node *pqn; 716 struct kfd_queue_snapshot_entry src; 717 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 718 int r = 0; 719 720 *num_qss_entries = 0; 721 if (!(*entry_size)) 722 return -EINVAL; 723 724 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 725 mutex_lock(&pqm->process->event_mutex); 726 727 memset(&src, 0, sizeof(src)); 728 729 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 730 if (!pqn->q) 731 continue; 732 733 if (*num_qss_entries < tmp_qss_entries) { 734 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 735 736 if (copy_to_user(buf, &src, *entry_size)) { 737 r = -EFAULT; 738 break; 739 } 740 buf += tmp_entry_size; 741 } 742 *num_qss_entries += 1; 743 } 744 745 mutex_unlock(&pqm->process->event_mutex); 746 return r; 747 } 748 749 static int get_queue_data_sizes(struct kfd_process_device *pdd, 750 struct queue *q, 751 uint32_t *mqd_size, 752 uint32_t *ctl_stack_size) 753 { 754 int ret; 755 756 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 757 q->properties.queue_id, 758 mqd_size, 759 ctl_stack_size); 760 if (ret) 761 pr_err("Failed to get queue dump info (%d)\n", ret); 762 763 return ret; 764 } 765 766 int kfd_process_get_queue_info(struct kfd_process *p, 767 uint32_t *num_queues, 768 uint64_t *priv_data_sizes) 769 { 770 uint32_t extra_data_sizes = 0; 771 struct queue *q; 772 int i; 773 int ret; 774 775 *num_queues = 0; 776 777 /* Run over all PDDs of the process */ 778 for (i = 0; i < p->n_pdds; i++) { 779 struct kfd_process_device *pdd = p->pdds[i]; 780 781 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 782 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 783 q->properties.type == KFD_QUEUE_TYPE_SDMA || 784 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 785 uint32_t mqd_size, ctl_stack_size; 786 787 *num_queues = *num_queues + 1; 788 789 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 790 if (ret) 791 return ret; 792 793 extra_data_sizes += mqd_size + ctl_stack_size; 794 } else { 795 pr_err("Unsupported queue type (%d)\n", q->properties.type); 796 return -EOPNOTSUPP; 797 } 798 } 799 } 800 *priv_data_sizes = extra_data_sizes + 801 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 802 803 return 0; 804 } 805 806 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 807 unsigned int qid, 808 void *mqd, 809 void *ctl_stack) 810 { 811 struct process_queue_node *pqn; 812 813 pqn = get_queue_by_qid(pqm, qid); 814 if (!pqn) { 815 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 816 return -EFAULT; 817 } 818 819 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 820 pr_err("amdkfd: queue dumping not supported on this device\n"); 821 return -EOPNOTSUPP; 822 } 823 824 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 825 pqn->q, mqd, ctl_stack); 826 } 827 828 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 829 struct queue *q, 830 struct kfd_criu_queue_priv_data *q_data) 831 { 832 uint8_t *mqd, *ctl_stack; 833 int ret; 834 835 mqd = (void *)(q_data + 1); 836 ctl_stack = mqd + q_data->mqd_size; 837 838 q_data->gpu_id = pdd->user_gpu_id; 839 q_data->type = q->properties.type; 840 q_data->format = q->properties.format; 841 q_data->q_id = q->properties.queue_id; 842 q_data->q_address = q->properties.queue_address; 843 q_data->q_size = q->properties.queue_size; 844 q_data->priority = q->properties.priority; 845 q_data->q_percent = q->properties.queue_percent; 846 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 847 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 848 q_data->doorbell_id = q->doorbell_id; 849 850 q_data->sdma_id = q->sdma_id; 851 852 q_data->eop_ring_buffer_address = 853 q->properties.eop_ring_buffer_address; 854 855 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 856 857 q_data->ctx_save_restore_area_address = 858 q->properties.ctx_save_restore_area_address; 859 860 q_data->ctx_save_restore_area_size = 861 q->properties.ctx_save_restore_area_size; 862 863 q_data->gws = !!q->gws; 864 865 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 866 if (ret) { 867 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 868 return ret; 869 } 870 871 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 872 return ret; 873 } 874 875 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 876 uint8_t __user *user_priv, 877 unsigned int *q_index, 878 uint64_t *queues_priv_data_offset) 879 { 880 unsigned int q_private_data_size = 0; 881 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 882 struct queue *q; 883 int ret = 0; 884 885 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 886 struct kfd_criu_queue_priv_data *q_data; 887 uint64_t q_data_size; 888 uint32_t mqd_size; 889 uint32_t ctl_stack_size; 890 891 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 892 q->properties.type != KFD_QUEUE_TYPE_SDMA && 893 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 894 895 pr_err("Unsupported queue type (%d)\n", q->properties.type); 896 ret = -EOPNOTSUPP; 897 break; 898 } 899 900 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 901 if (ret) 902 break; 903 904 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 905 906 /* Increase local buffer space if needed */ 907 if (q_private_data_size < q_data_size) { 908 kfree(q_private_data); 909 910 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 911 if (!q_private_data) { 912 ret = -ENOMEM; 913 break; 914 } 915 q_private_data_size = q_data_size; 916 } 917 918 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 919 920 /* data stored in this order: priv_data, mqd, ctl_stack */ 921 q_data->mqd_size = mqd_size; 922 q_data->ctl_stack_size = ctl_stack_size; 923 924 ret = criu_checkpoint_queue(pdd, q, q_data); 925 if (ret) 926 break; 927 928 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 929 930 ret = copy_to_user(user_priv + *queues_priv_data_offset, 931 q_data, q_data_size); 932 if (ret) { 933 ret = -EFAULT; 934 break; 935 } 936 *queues_priv_data_offset += q_data_size; 937 *q_index = *q_index + 1; 938 } 939 940 kfree(q_private_data); 941 942 return ret; 943 } 944 945 int kfd_criu_checkpoint_queues(struct kfd_process *p, 946 uint8_t __user *user_priv_data, 947 uint64_t *priv_data_offset) 948 { 949 int ret = 0, pdd_index, q_index = 0; 950 951 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 952 struct kfd_process_device *pdd = p->pdds[pdd_index]; 953 954 /* 955 * criu_checkpoint_queues_device will copy data to user and update q_index and 956 * queues_priv_data_offset 957 */ 958 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 959 priv_data_offset); 960 961 if (ret) 962 break; 963 } 964 965 return ret; 966 } 967 968 static void set_queue_properties_from_criu(struct queue_properties *qp, 969 struct kfd_criu_queue_priv_data *q_data) 970 { 971 qp->is_interop = false; 972 qp->queue_percent = q_data->q_percent; 973 qp->priority = q_data->priority; 974 qp->queue_address = q_data->q_address; 975 qp->queue_size = q_data->q_size; 976 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr; 977 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr; 978 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 979 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 980 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 981 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 982 qp->ctl_stack_size = q_data->ctl_stack_size; 983 qp->type = q_data->type; 984 qp->format = q_data->format; 985 } 986 987 int kfd_criu_restore_queue(struct kfd_process *p, 988 uint8_t __user *user_priv_ptr, 989 uint64_t *priv_data_offset, 990 uint64_t max_priv_data_size) 991 { 992 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 993 struct kfd_criu_queue_priv_data *q_data; 994 struct kfd_process_device *pdd; 995 uint64_t q_extra_data_size; 996 struct queue_properties qp; 997 unsigned int queue_id; 998 int ret = 0; 999 1000 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 1001 return -EINVAL; 1002 1003 q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); 1004 if (!q_data) 1005 return -ENOMEM; 1006 1007 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 1008 if (ret) { 1009 ret = -EFAULT; 1010 goto exit; 1011 } 1012 1013 *priv_data_offset += sizeof(*q_data); 1014 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 1015 1016 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 1017 ret = -EINVAL; 1018 goto exit; 1019 } 1020 1021 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1022 if (!q_extra_data) { 1023 ret = -ENOMEM; 1024 goto exit; 1025 } 1026 1027 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1028 if (ret) { 1029 ret = -EFAULT; 1030 goto exit; 1031 } 1032 1033 *priv_data_offset += q_extra_data_size; 1034 1035 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1036 if (!pdd) { 1037 pr_err("Failed to get pdd\n"); 1038 ret = -EINVAL; 1039 goto exit; 1040 } 1041 1042 /* data stored in this order: mqd, ctl_stack */ 1043 mqd = q_extra_data; 1044 ctl_stack = mqd + q_data->mqd_size; 1045 1046 memset(&qp, 0, sizeof(qp)); 1047 set_queue_properties_from_criu(&qp, q_data); 1048 1049 print_queue_properties(&qp); 1050 1051 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); 1052 if (ret) { 1053 pr_err("Failed to create new queue err:%d\n", ret); 1054 goto exit; 1055 } 1056 1057 if (q_data->gws) 1058 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1059 1060 exit: 1061 if (ret) 1062 pr_err("Failed to restore queue (%d)\n", ret); 1063 else 1064 pr_debug("Queue id %d was restored successfully\n", queue_id); 1065 1066 kfree(q_data); 1067 kfree(q_extra_data); 1068 1069 return ret; 1070 } 1071 1072 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1073 unsigned int qid, 1074 uint32_t *mqd_size, 1075 uint32_t *ctl_stack_size) 1076 { 1077 struct process_queue_node *pqn; 1078 1079 pqn = get_queue_by_qid(pqm, qid); 1080 if (!pqn) { 1081 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1082 return -EFAULT; 1083 } 1084 1085 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1086 pr_err("amdkfd: queue dumping not supported on this device\n"); 1087 return -EOPNOTSUPP; 1088 } 1089 1090 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1091 pqn->q, mqd_size, 1092 ctl_stack_size); 1093 return 0; 1094 } 1095 1096 #if defined(CONFIG_DEBUG_FS) 1097 1098 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1099 { 1100 struct process_queue_manager *pqm = data; 1101 struct process_queue_node *pqn; 1102 struct queue *q; 1103 enum KFD_MQD_TYPE mqd_type; 1104 struct mqd_manager *mqd_mgr; 1105 int r = 0, xcc, num_xccs = 1; 1106 void *mqd; 1107 uint64_t size = 0; 1108 1109 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1110 if (pqn->q) { 1111 q = pqn->q; 1112 switch (q->properties.type) { 1113 case KFD_QUEUE_TYPE_SDMA: 1114 case KFD_QUEUE_TYPE_SDMA_XGMI: 1115 seq_printf(m, " SDMA queue on device %x\n", 1116 q->device->id); 1117 mqd_type = KFD_MQD_TYPE_SDMA; 1118 break; 1119 case KFD_QUEUE_TYPE_COMPUTE: 1120 seq_printf(m, " Compute queue on device %x\n", 1121 q->device->id); 1122 mqd_type = KFD_MQD_TYPE_CP; 1123 num_xccs = NUM_XCC(q->device->xcc_mask); 1124 break; 1125 default: 1126 seq_printf(m, 1127 " Bad user queue type %d on device %x\n", 1128 q->properties.type, q->device->id); 1129 continue; 1130 } 1131 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1132 size = mqd_mgr->mqd_stride(mqd_mgr, 1133 &q->properties); 1134 } else if (pqn->kq) { 1135 q = pqn->kq->queue; 1136 mqd_mgr = pqn->kq->mqd_mgr; 1137 switch (q->properties.type) { 1138 case KFD_QUEUE_TYPE_DIQ: 1139 seq_printf(m, " DIQ on device %x\n", 1140 pqn->kq->dev->id); 1141 break; 1142 default: 1143 seq_printf(m, 1144 " Bad kernel queue type %d on device %x\n", 1145 q->properties.type, 1146 pqn->kq->dev->id); 1147 continue; 1148 } 1149 } else { 1150 seq_printf(m, 1151 " Weird: Queue node with neither kernel nor user queue\n"); 1152 continue; 1153 } 1154 1155 for (xcc = 0; xcc < num_xccs; xcc++) { 1156 mqd = q->mqd + size * xcc; 1157 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1158 if (r != 0) 1159 break; 1160 } 1161 } 1162 1163 return r; 1164 } 1165 1166 #endif 1167