1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pasid 0x%x\n", 73 pqm->process->pasid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 90 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 91 if (dev->kfd->shared_resources.enable_mes && 92 down_read_trylock(&dev->adev->reset_domain->sem)) { 93 amdgpu_mes_flush_shader_debugger(dev->adev, 94 pdd->proc_ctx_gpu_addr); 95 up_read(&dev->adev->reset_domain->sem); 96 } 97 pdd->already_dequeued = true; 98 } 99 100 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 101 void *gws) 102 { 103 struct mqd_update_info minfo = {0}; 104 struct kfd_node *dev = NULL; 105 struct process_queue_node *pqn; 106 struct kfd_process_device *pdd; 107 struct kgd_mem *mem = NULL; 108 int ret; 109 110 pqn = get_queue_by_qid(pqm, qid); 111 if (!pqn) { 112 pr_err("Queue id does not match any known queue\n"); 113 return -EINVAL; 114 } 115 116 if (pqn->q) 117 dev = pqn->q->device; 118 if (WARN_ON(!dev)) 119 return -ENODEV; 120 121 pdd = kfd_get_process_device_data(dev, pqm->process); 122 if (!pdd) { 123 pr_err("Process device data doesn't exist\n"); 124 return -EINVAL; 125 } 126 127 /* Only allow one queue per process can have GWS assigned */ 128 if (gws && pdd->qpd.num_gws) 129 return -EBUSY; 130 131 if (!gws && pdd->qpd.num_gws == 0) 132 return -EINVAL; 133 134 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 135 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 136 !dev->kfd->shared_resources.enable_mes) { 137 if (gws) 138 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 139 gws, &mem); 140 else 141 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 142 pqn->q->gws); 143 if (unlikely(ret)) 144 return ret; 145 pqn->q->gws = mem; 146 } else { 147 /* 148 * Intentionally set GWS to a non-NULL value 149 * for devices that do not use GWS for global wave 150 * synchronization but require the formality 151 * of setting GWS for cooperative groups. 152 */ 153 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 154 } 155 156 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 157 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 158 159 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 160 pqn->q, &minfo); 161 } 162 163 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 164 { 165 int i; 166 167 for (i = 0; i < p->n_pdds; i++) 168 kfd_process_dequeue_from_device(p->pdds[i]); 169 } 170 171 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 172 { 173 INIT_LIST_HEAD(&pqm->queues); 174 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 175 GFP_KERNEL); 176 if (!pqm->queue_slot_bitmap) 177 return -ENOMEM; 178 pqm->process = p; 179 180 return 0; 181 } 182 183 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 184 struct process_queue_node *pqn) 185 { 186 struct kfd_node *dev; 187 struct kfd_process_device *pdd; 188 189 dev = pqn->q->device; 190 191 pdd = kfd_get_process_device_data(dev, pqm->process); 192 if (!pdd) { 193 pr_err("Process device data doesn't exist\n"); 194 return; 195 } 196 197 if (pqn->q->gws) { 198 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 199 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 200 !dev->kfd->shared_resources.enable_mes) 201 amdgpu_amdkfd_remove_gws_from_process( 202 pqm->process->kgd_process_info, pqn->q->gws); 203 pdd->qpd.num_gws = 0; 204 } 205 206 if (dev->kfd->shared_resources.enable_mes) { 207 amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); 208 amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 209 } 210 } 211 212 void pqm_uninit(struct process_queue_manager *pqm) 213 { 214 struct process_queue_node *pqn, *next; 215 struct kfd_process_device *pdd; 216 217 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 218 if (pqn->q) { 219 pdd = kfd_get_process_device_data(pqn->q->device, pqm->process); 220 kfd_queue_release_buffers(pdd, &pqn->q->properties); 221 pqm_clean_queue_resource(pqm, pqn); 222 } 223 224 kfd_procfs_del_queue(pqn->q); 225 uninit_queue(pqn->q); 226 list_del(&pqn->process_queue_list); 227 kfree(pqn); 228 } 229 230 bitmap_free(pqm->queue_slot_bitmap); 231 pqm->queue_slot_bitmap = NULL; 232 } 233 234 static int init_user_queue(struct process_queue_manager *pqm, 235 struct kfd_node *dev, struct queue **q, 236 struct queue_properties *q_properties, 237 struct file *f, unsigned int qid) 238 { 239 int retval; 240 241 /* Doorbell initialized in user space*/ 242 q_properties->doorbell_ptr = NULL; 243 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 244 245 /* let DQM handle it*/ 246 q_properties->vmid = 0; 247 q_properties->queue_id = qid; 248 249 retval = init_queue(q, q_properties); 250 if (retval != 0) 251 return retval; 252 253 (*q)->device = dev; 254 (*q)->process = pqm->process; 255 256 if (dev->kfd->shared_resources.enable_mes) { 257 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 258 AMDGPU_MES_GANG_CTX_SIZE, 259 &(*q)->gang_ctx_bo, 260 &(*q)->gang_ctx_gpu_addr, 261 &(*q)->gang_ctx_cpu_ptr, 262 false); 263 if (retval) { 264 pr_err("failed to allocate gang context bo\n"); 265 goto cleanup; 266 } 267 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 268 269 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 270 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 271 */ 272 if (((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) 273 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { 274 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 275 pr_err("Queue memory allocated to wrong device\n"); 276 retval = -EINVAL; 277 goto free_gang_ctx_bo; 278 } 279 280 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 281 &(*q)->wptr_bo_gart); 282 if (retval) { 283 pr_err("Failed to map wptr bo to GART\n"); 284 goto free_gang_ctx_bo; 285 } 286 } 287 } 288 289 pr_debug("PQM After init queue"); 290 return 0; 291 292 free_gang_ctx_bo: 293 amdgpu_amdkfd_free_gtt_mem(dev->adev, (*q)->gang_ctx_bo); 294 cleanup: 295 uninit_queue(*q); 296 *q = NULL; 297 return retval; 298 } 299 300 int pqm_create_queue(struct process_queue_manager *pqm, 301 struct kfd_node *dev, 302 struct file *f, 303 struct queue_properties *properties, 304 unsigned int *qid, 305 const struct kfd_criu_queue_priv_data *q_data, 306 const void *restore_mqd, 307 const void *restore_ctl_stack, 308 uint32_t *p_doorbell_offset_in_process) 309 { 310 int retval; 311 struct kfd_process_device *pdd; 312 struct queue *q; 313 struct process_queue_node *pqn; 314 struct kernel_queue *kq; 315 enum kfd_queue_type type = properties->type; 316 unsigned int max_queues = 127; /* HWS limit */ 317 318 /* 319 * On GFX 9.4.3, increase the number of queues that 320 * can be created to 255. No HWS limit on GFX 9.4.3. 321 */ 322 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 323 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) 324 max_queues = 255; 325 326 q = NULL; 327 kq = NULL; 328 329 pdd = kfd_get_process_device_data(dev, pqm->process); 330 if (!pdd) { 331 pr_err("Process device data doesn't exist\n"); 332 return -1; 333 } 334 335 /* 336 * for debug process, verify that it is within the static queues limit 337 * currently limit is set to half of the total avail HQD slots 338 * If we are just about to create DIQ, the is_debug flag is not set yet 339 * Hence we also check the type as well 340 */ 341 if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ)) 342 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 343 344 if (pdd->qpd.queue_count >= max_queues) 345 return -ENOSPC; 346 347 if (q_data) { 348 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 349 *qid = q_data->q_id; 350 } else 351 retval = find_available_queue_slot(pqm, qid); 352 353 if (retval != 0) 354 return retval; 355 356 if (list_empty(&pdd->qpd.queues_list) && 357 list_empty(&pdd->qpd.priv_queue_list)) 358 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 359 360 pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); 361 if (!pqn) { 362 retval = -ENOMEM; 363 goto err_allocate_pqn; 364 } 365 366 switch (type) { 367 case KFD_QUEUE_TYPE_SDMA: 368 case KFD_QUEUE_TYPE_SDMA_XGMI: 369 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 370 /* SDMA queues are always allocated statically no matter 371 * which scheduler mode is used. We also do not need to 372 * check whether a SDMA queue can be allocated here, because 373 * allocate_sdma_queue() in create_queue() has the 374 * corresponding check logic. 375 */ 376 retval = init_user_queue(pqm, dev, &q, properties, f, *qid); 377 if (retval != 0) 378 goto err_create_queue; 379 pqn->q = q; 380 pqn->kq = NULL; 381 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 382 restore_mqd, restore_ctl_stack); 383 print_queue(q); 384 break; 385 386 case KFD_QUEUE_TYPE_COMPUTE: 387 /* check if there is over subscription */ 388 if ((dev->dqm->sched_policy == 389 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 390 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 391 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 392 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 393 retval = -EPERM; 394 goto err_create_queue; 395 } 396 397 retval = init_user_queue(pqm, dev, &q, properties, f, *qid); 398 if (retval != 0) 399 goto err_create_queue; 400 pqn->q = q; 401 pqn->kq = NULL; 402 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 403 restore_mqd, restore_ctl_stack); 404 print_queue(q); 405 break; 406 case KFD_QUEUE_TYPE_DIQ: 407 kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ); 408 if (!kq) { 409 retval = -ENOMEM; 410 goto err_create_queue; 411 } 412 kq->queue->properties.queue_id = *qid; 413 pqn->kq = kq; 414 pqn->q = NULL; 415 retval = kfd_process_drain_interrupts(pdd); 416 if (retval) 417 break; 418 419 retval = dev->dqm->ops.create_kernel_queue(dev->dqm, 420 kq, &pdd->qpd); 421 break; 422 default: 423 WARN(1, "Invalid queue type %d", type); 424 retval = -EINVAL; 425 } 426 427 if (retval != 0) { 428 pr_err("Pasid 0x%x DQM create queue type %d failed. ret %d\n", 429 pqm->process->pasid, type, retval); 430 goto err_create_queue; 431 } 432 433 if (q && p_doorbell_offset_in_process) { 434 /* Return the doorbell offset within the doorbell page 435 * to the caller so it can be passed up to user mode 436 * (in bytes). 437 * relative doorbell index = Absolute doorbell index - 438 * absolute index of first doorbell in the page. 439 */ 440 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 441 pdd->qpd.proc_doorbells, 442 0, 443 pdd->dev->kfd->device_info.doorbell_size); 444 445 *p_doorbell_offset_in_process = (q->properties.doorbell_off 446 - first_db_index) * sizeof(uint32_t); 447 } 448 449 pr_debug("PQM After DQM create queue\n"); 450 451 list_add(&pqn->process_queue_list, &pqm->queues); 452 453 if (q) { 454 pr_debug("PQM done creating queue\n"); 455 kfd_procfs_add_queue(q); 456 print_queue_properties(&q->properties); 457 } 458 459 return retval; 460 461 err_create_queue: 462 uninit_queue(q); 463 if (kq) 464 kernel_queue_uninit(kq); 465 kfree(pqn); 466 err_allocate_pqn: 467 /* check if queues list is empty unregister process from device */ 468 clear_bit(*qid, pqm->queue_slot_bitmap); 469 if (list_empty(&pdd->qpd.queues_list) && 470 list_empty(&pdd->qpd.priv_queue_list)) 471 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 472 return retval; 473 } 474 475 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 476 { 477 struct process_queue_node *pqn; 478 struct kfd_process_device *pdd; 479 struct device_queue_manager *dqm; 480 struct kfd_node *dev; 481 int retval; 482 483 dqm = NULL; 484 485 retval = 0; 486 487 pqn = get_queue_by_qid(pqm, qid); 488 if (!pqn) { 489 pr_err("Queue id does not match any known queue\n"); 490 return -EINVAL; 491 } 492 493 dev = NULL; 494 if (pqn->kq) 495 dev = pqn->kq->dev; 496 if (pqn->q) 497 dev = pqn->q->device; 498 if (WARN_ON(!dev)) 499 return -ENODEV; 500 501 pdd = kfd_get_process_device_data(dev, pqm->process); 502 if (!pdd) { 503 pr_err("Process device data doesn't exist\n"); 504 return -1; 505 } 506 507 if (pqn->kq) { 508 /* destroy kernel queue (DIQ) */ 509 dqm = pqn->kq->dev->dqm; 510 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 511 kernel_queue_uninit(pqn->kq); 512 } 513 514 if (pqn->q) { 515 retval = kfd_queue_release_buffers(pdd, &pqn->q->properties); 516 if (retval) 517 goto err_destroy_queue; 518 519 kfd_procfs_del_queue(pqn->q); 520 dqm = pqn->q->device->dqm; 521 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 522 if (retval) { 523 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 524 pqm->process->pasid, 525 pqn->q->properties.queue_id, retval); 526 if (retval != -ETIME) 527 goto err_destroy_queue; 528 } 529 530 pqm_clean_queue_resource(pqm, pqn); 531 uninit_queue(pqn->q); 532 } 533 534 list_del(&pqn->process_queue_list); 535 kfree(pqn); 536 clear_bit(qid, pqm->queue_slot_bitmap); 537 538 if (list_empty(&pdd->qpd.queues_list) && 539 list_empty(&pdd->qpd.priv_queue_list)) 540 dqm->ops.unregister_process(dqm, &pdd->qpd); 541 542 err_destroy_queue: 543 return retval; 544 } 545 546 int pqm_update_queue_properties(struct process_queue_manager *pqm, 547 unsigned int qid, struct queue_properties *p) 548 { 549 int retval; 550 struct process_queue_node *pqn; 551 552 pqn = get_queue_by_qid(pqm, qid); 553 if (!pqn || !pqn->q) { 554 pr_debug("No queue %d exists for update operation\n", qid); 555 return -EFAULT; 556 } 557 558 /* 559 * Update with NULL ring address is used to disable the queue 560 */ 561 if (p->queue_address && p->queue_size) { 562 struct kfd_process_device *pdd; 563 struct amdgpu_vm *vm; 564 struct queue *q = pqn->q; 565 int err; 566 567 pdd = kfd_get_process_device_data(q->device, q->process); 568 if (!pdd) 569 return -ENODEV; 570 vm = drm_priv_to_vm(pdd->drm_priv); 571 err = amdgpu_bo_reserve(vm->root.bo, false); 572 if (err) 573 return err; 574 575 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 576 p->queue_size)) { 577 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 578 p->queue_address, p->queue_size); 579 return -EFAULT; 580 } 581 582 kfd_queue_buffer_put(vm, &pqn->q->properties.ring_bo); 583 amdgpu_bo_unreserve(vm->root.bo); 584 585 pqn->q->properties.ring_bo = p->ring_bo; 586 } 587 588 pqn->q->properties.queue_address = p->queue_address; 589 pqn->q->properties.queue_size = p->queue_size; 590 pqn->q->properties.queue_percent = p->queue_percent; 591 pqn->q->properties.priority = p->priority; 592 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 593 594 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 595 pqn->q, NULL); 596 if (retval != 0) 597 return retval; 598 599 return 0; 600 } 601 602 int pqm_update_mqd(struct process_queue_manager *pqm, 603 unsigned int qid, struct mqd_update_info *minfo) 604 { 605 int retval; 606 struct process_queue_node *pqn; 607 608 pqn = get_queue_by_qid(pqm, qid); 609 if (!pqn) { 610 pr_debug("No queue %d exists for update operation\n", qid); 611 return -EFAULT; 612 } 613 614 /* CUs are masked for debugger requirements so deny user mask */ 615 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 616 return -EBUSY; 617 618 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 619 if (minfo && minfo->cu_mask.ptr && 620 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { 621 int i; 622 623 for (i = 0; i < minfo->cu_mask.count; i += 2) { 624 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 625 626 if (cu_pair && cu_pair != 0x3) { 627 pr_debug("CUs must be adjacent pairwise enabled.\n"); 628 return -EINVAL; 629 } 630 } 631 } 632 633 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 634 pqn->q, minfo); 635 if (retval != 0) 636 return retval; 637 638 if (minfo && minfo->cu_mask.ptr) 639 pqn->q->properties.is_user_cu_masked = true; 640 641 return 0; 642 } 643 644 struct kernel_queue *pqm_get_kernel_queue( 645 struct process_queue_manager *pqm, 646 unsigned int qid) 647 { 648 struct process_queue_node *pqn; 649 650 pqn = get_queue_by_qid(pqm, qid); 651 if (pqn && pqn->kq) 652 return pqn->kq; 653 654 return NULL; 655 } 656 657 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 658 unsigned int qid) 659 { 660 struct process_queue_node *pqn; 661 662 pqn = get_queue_by_qid(pqm, qid); 663 return pqn ? pqn->q : NULL; 664 } 665 666 int pqm_get_wave_state(struct process_queue_manager *pqm, 667 unsigned int qid, 668 void __user *ctl_stack, 669 u32 *ctl_stack_used_size, 670 u32 *save_area_used_size) 671 { 672 struct process_queue_node *pqn; 673 674 pqn = get_queue_by_qid(pqm, qid); 675 if (!pqn) { 676 pr_debug("amdkfd: No queue %d exists for operation\n", 677 qid); 678 return -EFAULT; 679 } 680 681 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 682 pqn->q, 683 ctl_stack, 684 ctl_stack_used_size, 685 save_area_used_size); 686 } 687 688 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 689 uint64_t exception_clear_mask, 690 void __user *buf, 691 int *num_qss_entries, 692 uint32_t *entry_size) 693 { 694 struct process_queue_node *pqn; 695 struct kfd_queue_snapshot_entry src; 696 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 697 int r = 0; 698 699 *num_qss_entries = 0; 700 if (!(*entry_size)) 701 return -EINVAL; 702 703 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 704 mutex_lock(&pqm->process->event_mutex); 705 706 memset(&src, 0, sizeof(src)); 707 708 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 709 if (!pqn->q) 710 continue; 711 712 if (*num_qss_entries < tmp_qss_entries) { 713 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 714 715 if (copy_to_user(buf, &src, *entry_size)) { 716 r = -EFAULT; 717 break; 718 } 719 buf += tmp_entry_size; 720 } 721 *num_qss_entries += 1; 722 } 723 724 mutex_unlock(&pqm->process->event_mutex); 725 return r; 726 } 727 728 static int get_queue_data_sizes(struct kfd_process_device *pdd, 729 struct queue *q, 730 uint32_t *mqd_size, 731 uint32_t *ctl_stack_size) 732 { 733 int ret; 734 735 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 736 q->properties.queue_id, 737 mqd_size, 738 ctl_stack_size); 739 if (ret) 740 pr_err("Failed to get queue dump info (%d)\n", ret); 741 742 return ret; 743 } 744 745 int kfd_process_get_queue_info(struct kfd_process *p, 746 uint32_t *num_queues, 747 uint64_t *priv_data_sizes) 748 { 749 uint32_t extra_data_sizes = 0; 750 struct queue *q; 751 int i; 752 int ret; 753 754 *num_queues = 0; 755 756 /* Run over all PDDs of the process */ 757 for (i = 0; i < p->n_pdds; i++) { 758 struct kfd_process_device *pdd = p->pdds[i]; 759 760 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 761 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 762 q->properties.type == KFD_QUEUE_TYPE_SDMA || 763 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 764 uint32_t mqd_size, ctl_stack_size; 765 766 *num_queues = *num_queues + 1; 767 768 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 769 if (ret) 770 return ret; 771 772 extra_data_sizes += mqd_size + ctl_stack_size; 773 } else { 774 pr_err("Unsupported queue type (%d)\n", q->properties.type); 775 return -EOPNOTSUPP; 776 } 777 } 778 } 779 *priv_data_sizes = extra_data_sizes + 780 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 781 782 return 0; 783 } 784 785 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 786 unsigned int qid, 787 void *mqd, 788 void *ctl_stack) 789 { 790 struct process_queue_node *pqn; 791 792 pqn = get_queue_by_qid(pqm, qid); 793 if (!pqn) { 794 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 795 return -EFAULT; 796 } 797 798 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 799 pr_err("amdkfd: queue dumping not supported on this device\n"); 800 return -EOPNOTSUPP; 801 } 802 803 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 804 pqn->q, mqd, ctl_stack); 805 } 806 807 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 808 struct queue *q, 809 struct kfd_criu_queue_priv_data *q_data) 810 { 811 uint8_t *mqd, *ctl_stack; 812 int ret; 813 814 mqd = (void *)(q_data + 1); 815 ctl_stack = mqd + q_data->mqd_size; 816 817 q_data->gpu_id = pdd->user_gpu_id; 818 q_data->type = q->properties.type; 819 q_data->format = q->properties.format; 820 q_data->q_id = q->properties.queue_id; 821 q_data->q_address = q->properties.queue_address; 822 q_data->q_size = q->properties.queue_size; 823 q_data->priority = q->properties.priority; 824 q_data->q_percent = q->properties.queue_percent; 825 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 826 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 827 q_data->doorbell_id = q->doorbell_id; 828 829 q_data->sdma_id = q->sdma_id; 830 831 q_data->eop_ring_buffer_address = 832 q->properties.eop_ring_buffer_address; 833 834 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 835 836 q_data->ctx_save_restore_area_address = 837 q->properties.ctx_save_restore_area_address; 838 839 q_data->ctx_save_restore_area_size = 840 q->properties.ctx_save_restore_area_size; 841 842 q_data->gws = !!q->gws; 843 844 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 845 if (ret) { 846 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 847 return ret; 848 } 849 850 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 851 return ret; 852 } 853 854 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 855 uint8_t __user *user_priv, 856 unsigned int *q_index, 857 uint64_t *queues_priv_data_offset) 858 { 859 unsigned int q_private_data_size = 0; 860 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 861 struct queue *q; 862 int ret = 0; 863 864 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 865 struct kfd_criu_queue_priv_data *q_data; 866 uint64_t q_data_size; 867 uint32_t mqd_size; 868 uint32_t ctl_stack_size; 869 870 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 871 q->properties.type != KFD_QUEUE_TYPE_SDMA && 872 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 873 874 pr_err("Unsupported queue type (%d)\n", q->properties.type); 875 ret = -EOPNOTSUPP; 876 break; 877 } 878 879 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 880 if (ret) 881 break; 882 883 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 884 885 /* Increase local buffer space if needed */ 886 if (q_private_data_size < q_data_size) { 887 kfree(q_private_data); 888 889 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 890 if (!q_private_data) { 891 ret = -ENOMEM; 892 break; 893 } 894 q_private_data_size = q_data_size; 895 } 896 897 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 898 899 /* data stored in this order: priv_data, mqd, ctl_stack */ 900 q_data->mqd_size = mqd_size; 901 q_data->ctl_stack_size = ctl_stack_size; 902 903 ret = criu_checkpoint_queue(pdd, q, q_data); 904 if (ret) 905 break; 906 907 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 908 909 ret = copy_to_user(user_priv + *queues_priv_data_offset, 910 q_data, q_data_size); 911 if (ret) { 912 ret = -EFAULT; 913 break; 914 } 915 *queues_priv_data_offset += q_data_size; 916 *q_index = *q_index + 1; 917 } 918 919 kfree(q_private_data); 920 921 return ret; 922 } 923 924 int kfd_criu_checkpoint_queues(struct kfd_process *p, 925 uint8_t __user *user_priv_data, 926 uint64_t *priv_data_offset) 927 { 928 int ret = 0, pdd_index, q_index = 0; 929 930 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 931 struct kfd_process_device *pdd = p->pdds[pdd_index]; 932 933 /* 934 * criu_checkpoint_queues_device will copy data to user and update q_index and 935 * queues_priv_data_offset 936 */ 937 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 938 priv_data_offset); 939 940 if (ret) 941 break; 942 } 943 944 return ret; 945 } 946 947 static void set_queue_properties_from_criu(struct queue_properties *qp, 948 struct kfd_criu_queue_priv_data *q_data) 949 { 950 qp->is_interop = false; 951 qp->queue_percent = q_data->q_percent; 952 qp->priority = q_data->priority; 953 qp->queue_address = q_data->q_address; 954 qp->queue_size = q_data->q_size; 955 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr; 956 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr; 957 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 958 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 959 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 960 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 961 qp->ctl_stack_size = q_data->ctl_stack_size; 962 qp->type = q_data->type; 963 qp->format = q_data->format; 964 } 965 966 int kfd_criu_restore_queue(struct kfd_process *p, 967 uint8_t __user *user_priv_ptr, 968 uint64_t *priv_data_offset, 969 uint64_t max_priv_data_size) 970 { 971 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 972 struct kfd_criu_queue_priv_data *q_data; 973 struct kfd_process_device *pdd; 974 uint64_t q_extra_data_size; 975 struct queue_properties qp; 976 unsigned int queue_id; 977 int ret = 0; 978 979 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 980 return -EINVAL; 981 982 q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); 983 if (!q_data) 984 return -ENOMEM; 985 986 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 987 if (ret) { 988 ret = -EFAULT; 989 goto exit; 990 } 991 992 *priv_data_offset += sizeof(*q_data); 993 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 994 995 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 996 ret = -EINVAL; 997 goto exit; 998 } 999 1000 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1001 if (!q_extra_data) { 1002 ret = -ENOMEM; 1003 goto exit; 1004 } 1005 1006 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1007 if (ret) { 1008 ret = -EFAULT; 1009 goto exit; 1010 } 1011 1012 *priv_data_offset += q_extra_data_size; 1013 1014 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1015 if (!pdd) { 1016 pr_err("Failed to get pdd\n"); 1017 ret = -EINVAL; 1018 goto exit; 1019 } 1020 1021 /* data stored in this order: mqd, ctl_stack */ 1022 mqd = q_extra_data; 1023 ctl_stack = mqd + q_data->mqd_size; 1024 1025 memset(&qp, 0, sizeof(qp)); 1026 set_queue_properties_from_criu(&qp, q_data); 1027 1028 print_queue_properties(&qp); 1029 1030 ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, q_data, mqd, ctl_stack, 1031 NULL); 1032 if (ret) { 1033 pr_err("Failed to create new queue err:%d\n", ret); 1034 goto exit; 1035 } 1036 1037 if (q_data->gws) 1038 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1039 1040 exit: 1041 if (ret) 1042 pr_err("Failed to restore queue (%d)\n", ret); 1043 else 1044 pr_debug("Queue id %d was restored successfully\n", queue_id); 1045 1046 kfree(q_data); 1047 1048 return ret; 1049 } 1050 1051 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1052 unsigned int qid, 1053 uint32_t *mqd_size, 1054 uint32_t *ctl_stack_size) 1055 { 1056 struct process_queue_node *pqn; 1057 1058 pqn = get_queue_by_qid(pqm, qid); 1059 if (!pqn) { 1060 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1061 return -EFAULT; 1062 } 1063 1064 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1065 pr_err("amdkfd: queue dumping not supported on this device\n"); 1066 return -EOPNOTSUPP; 1067 } 1068 1069 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1070 pqn->q, mqd_size, 1071 ctl_stack_size); 1072 return 0; 1073 } 1074 1075 #if defined(CONFIG_DEBUG_FS) 1076 1077 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1078 { 1079 struct process_queue_manager *pqm = data; 1080 struct process_queue_node *pqn; 1081 struct queue *q; 1082 enum KFD_MQD_TYPE mqd_type; 1083 struct mqd_manager *mqd_mgr; 1084 int r = 0, xcc, num_xccs = 1; 1085 void *mqd; 1086 uint64_t size = 0; 1087 1088 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1089 if (pqn->q) { 1090 q = pqn->q; 1091 switch (q->properties.type) { 1092 case KFD_QUEUE_TYPE_SDMA: 1093 case KFD_QUEUE_TYPE_SDMA_XGMI: 1094 seq_printf(m, " SDMA queue on device %x\n", 1095 q->device->id); 1096 mqd_type = KFD_MQD_TYPE_SDMA; 1097 break; 1098 case KFD_QUEUE_TYPE_COMPUTE: 1099 seq_printf(m, " Compute queue on device %x\n", 1100 q->device->id); 1101 mqd_type = KFD_MQD_TYPE_CP; 1102 num_xccs = NUM_XCC(q->device->xcc_mask); 1103 break; 1104 default: 1105 seq_printf(m, 1106 " Bad user queue type %d on device %x\n", 1107 q->properties.type, q->device->id); 1108 continue; 1109 } 1110 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1111 size = mqd_mgr->mqd_stride(mqd_mgr, 1112 &q->properties); 1113 } else if (pqn->kq) { 1114 q = pqn->kq->queue; 1115 mqd_mgr = pqn->kq->mqd_mgr; 1116 switch (q->properties.type) { 1117 case KFD_QUEUE_TYPE_DIQ: 1118 seq_printf(m, " DIQ on device %x\n", 1119 pqn->kq->dev->id); 1120 break; 1121 default: 1122 seq_printf(m, 1123 " Bad kernel queue type %d on device %x\n", 1124 q->properties.type, 1125 pqn->kq->dev->id); 1126 continue; 1127 } 1128 } else { 1129 seq_printf(m, 1130 " Weird: Queue node with neither kernel nor user queue\n"); 1131 continue; 1132 } 1133 1134 for (xcc = 0; xcc < num_xccs; xcc++) { 1135 mqd = q->mqd + size * xcc; 1136 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1137 if (r != 0) 1138 break; 1139 } 1140 } 1141 1142 return r; 1143 } 1144 1145 #endif 1146