1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pasid 0x%x\n", 73 pqm->process->pasid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 90 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 91 if (dev->kfd->shared_resources.enable_mes && 92 down_read_trylock(&dev->adev->reset_domain->sem)) { 93 amdgpu_mes_flush_shader_debugger(dev->adev, 94 pdd->proc_ctx_gpu_addr); 95 up_read(&dev->adev->reset_domain->sem); 96 } 97 pdd->already_dequeued = true; 98 } 99 100 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 101 void *gws) 102 { 103 struct mqd_update_info minfo = {0}; 104 struct kfd_node *dev = NULL; 105 struct process_queue_node *pqn; 106 struct kfd_process_device *pdd; 107 struct kgd_mem *mem = NULL; 108 int ret; 109 110 pqn = get_queue_by_qid(pqm, qid); 111 if (!pqn) { 112 pr_err("Queue id does not match any known queue\n"); 113 return -EINVAL; 114 } 115 116 if (pqn->q) 117 dev = pqn->q->device; 118 if (WARN_ON(!dev)) 119 return -ENODEV; 120 121 pdd = kfd_get_process_device_data(dev, pqm->process); 122 if (!pdd) { 123 pr_err("Process device data doesn't exist\n"); 124 return -EINVAL; 125 } 126 127 /* Only allow one queue per process can have GWS assigned */ 128 if (gws && pdd->qpd.num_gws) 129 return -EBUSY; 130 131 if (!gws && pdd->qpd.num_gws == 0) 132 return -EINVAL; 133 134 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 135 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 136 !dev->kfd->shared_resources.enable_mes) { 137 if (gws) 138 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 139 gws, &mem); 140 else 141 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 142 pqn->q->gws); 143 if (unlikely(ret)) 144 return ret; 145 pqn->q->gws = mem; 146 } else { 147 /* 148 * Intentionally set GWS to a non-NULL value 149 * for devices that do not use GWS for global wave 150 * synchronization but require the formality 151 * of setting GWS for cooperative groups. 152 */ 153 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 154 } 155 156 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 157 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 158 159 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 160 pqn->q, &minfo); 161 } 162 163 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 164 { 165 int i; 166 167 for (i = 0; i < p->n_pdds; i++) 168 kfd_process_dequeue_from_device(p->pdds[i]); 169 } 170 171 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 172 { 173 INIT_LIST_HEAD(&pqm->queues); 174 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 175 GFP_KERNEL); 176 if (!pqm->queue_slot_bitmap) 177 return -ENOMEM; 178 pqm->process = p; 179 180 return 0; 181 } 182 183 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 184 struct process_queue_node *pqn) 185 { 186 struct kfd_node *dev; 187 struct kfd_process_device *pdd; 188 189 dev = pqn->q->device; 190 191 pdd = kfd_get_process_device_data(dev, pqm->process); 192 if (!pdd) { 193 pr_err("Process device data doesn't exist\n"); 194 return; 195 } 196 197 if (pqn->q->gws) { 198 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 199 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 200 !dev->kfd->shared_resources.enable_mes) 201 amdgpu_amdkfd_remove_gws_from_process( 202 pqm->process->kgd_process_info, pqn->q->gws); 203 pdd->qpd.num_gws = 0; 204 } 205 206 if (dev->kfd->shared_resources.enable_mes) { 207 amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); 208 amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 209 } 210 } 211 212 void pqm_uninit(struct process_queue_manager *pqm) 213 { 214 struct process_queue_node *pqn, *next; 215 struct kfd_process_device *pdd; 216 217 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 218 if (pqn->q) { 219 pdd = kfd_get_process_device_data(pqn->q->device, pqm->process); 220 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 221 kfd_queue_release_buffers(pdd, &pqn->q->properties); 222 pqm_clean_queue_resource(pqm, pqn); 223 } 224 225 kfd_procfs_del_queue(pqn->q); 226 uninit_queue(pqn->q); 227 list_del(&pqn->process_queue_list); 228 kfree(pqn); 229 } 230 231 bitmap_free(pqm->queue_slot_bitmap); 232 pqm->queue_slot_bitmap = NULL; 233 } 234 235 static int init_user_queue(struct process_queue_manager *pqm, 236 struct kfd_node *dev, struct queue **q, 237 struct queue_properties *q_properties, 238 unsigned int qid) 239 { 240 int retval; 241 242 /* Doorbell initialized in user space*/ 243 q_properties->doorbell_ptr = NULL; 244 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 245 246 /* let DQM handle it*/ 247 q_properties->vmid = 0; 248 q_properties->queue_id = qid; 249 250 retval = init_queue(q, q_properties); 251 if (retval != 0) 252 return retval; 253 254 (*q)->device = dev; 255 (*q)->process = pqm->process; 256 257 if (dev->kfd->shared_resources.enable_mes) { 258 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 259 AMDGPU_MES_GANG_CTX_SIZE, 260 &(*q)->gang_ctx_bo, 261 &(*q)->gang_ctx_gpu_addr, 262 &(*q)->gang_ctx_cpu_ptr, 263 false); 264 if (retval) { 265 pr_err("failed to allocate gang context bo\n"); 266 goto cleanup; 267 } 268 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 269 270 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 271 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 272 */ 273 if (((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) 274 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) { 275 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 276 pr_err("Queue memory allocated to wrong device\n"); 277 retval = -EINVAL; 278 goto free_gang_ctx_bo; 279 } 280 281 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 282 &(*q)->wptr_bo_gart); 283 if (retval) { 284 pr_err("Failed to map wptr bo to GART\n"); 285 goto free_gang_ctx_bo; 286 } 287 } 288 } 289 290 pr_debug("PQM After init queue"); 291 return 0; 292 293 free_gang_ctx_bo: 294 amdgpu_amdkfd_free_gtt_mem(dev->adev, (*q)->gang_ctx_bo); 295 cleanup: 296 uninit_queue(*q); 297 *q = NULL; 298 return retval; 299 } 300 301 int pqm_create_queue(struct process_queue_manager *pqm, 302 struct kfd_node *dev, 303 struct queue_properties *properties, 304 unsigned int *qid, 305 const struct kfd_criu_queue_priv_data *q_data, 306 const void *restore_mqd, 307 const void *restore_ctl_stack, 308 uint32_t *p_doorbell_offset_in_process) 309 { 310 int retval; 311 struct kfd_process_device *pdd; 312 struct queue *q; 313 struct process_queue_node *pqn; 314 struct kernel_queue *kq; 315 enum kfd_queue_type type = properties->type; 316 unsigned int max_queues = 127; /* HWS limit */ 317 318 /* 319 * On GFX 9.4.3, increase the number of queues that 320 * can be created to 255. No HWS limit on GFX 9.4.3. 321 */ 322 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 323 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) 324 max_queues = 255; 325 326 q = NULL; 327 kq = NULL; 328 329 pdd = kfd_get_process_device_data(dev, pqm->process); 330 if (!pdd) { 331 pr_err("Process device data doesn't exist\n"); 332 return -1; 333 } 334 335 /* 336 * for debug process, verify that it is within the static queues limit 337 * currently limit is set to half of the total avail HQD slots 338 * If we are just about to create DIQ, the is_debug flag is not set yet 339 * Hence we also check the type as well 340 */ 341 if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ)) 342 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 343 344 if (pdd->qpd.queue_count >= max_queues) 345 return -ENOSPC; 346 347 if (q_data) { 348 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 349 *qid = q_data->q_id; 350 } else 351 retval = find_available_queue_slot(pqm, qid); 352 353 if (retval != 0) 354 return retval; 355 356 if (list_empty(&pdd->qpd.queues_list) && 357 list_empty(&pdd->qpd.priv_queue_list)) 358 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 359 360 pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); 361 if (!pqn) { 362 retval = -ENOMEM; 363 goto err_allocate_pqn; 364 } 365 366 switch (type) { 367 case KFD_QUEUE_TYPE_SDMA: 368 case KFD_QUEUE_TYPE_SDMA_XGMI: 369 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 370 /* SDMA queues are always allocated statically no matter 371 * which scheduler mode is used. We also do not need to 372 * check whether a SDMA queue can be allocated here, because 373 * allocate_sdma_queue() in create_queue() has the 374 * corresponding check logic. 375 */ 376 retval = init_user_queue(pqm, dev, &q, properties, *qid); 377 if (retval != 0) 378 goto err_create_queue; 379 pqn->q = q; 380 pqn->kq = NULL; 381 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 382 restore_mqd, restore_ctl_stack); 383 print_queue(q); 384 break; 385 386 case KFD_QUEUE_TYPE_COMPUTE: 387 /* check if there is over subscription */ 388 if ((dev->dqm->sched_policy == 389 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 390 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 391 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 392 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 393 retval = -EPERM; 394 goto err_create_queue; 395 } 396 397 retval = init_user_queue(pqm, dev, &q, properties, *qid); 398 if (retval != 0) 399 goto err_create_queue; 400 pqn->q = q; 401 pqn->kq = NULL; 402 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 403 restore_mqd, restore_ctl_stack); 404 print_queue(q); 405 break; 406 case KFD_QUEUE_TYPE_DIQ: 407 kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ); 408 if (!kq) { 409 retval = -ENOMEM; 410 goto err_create_queue; 411 } 412 kq->queue->properties.queue_id = *qid; 413 pqn->kq = kq; 414 pqn->q = NULL; 415 retval = kfd_process_drain_interrupts(pdd); 416 if (retval) 417 break; 418 419 retval = dev->dqm->ops.create_kernel_queue(dev->dqm, 420 kq, &pdd->qpd); 421 break; 422 default: 423 WARN(1, "Invalid queue type %d", type); 424 retval = -EINVAL; 425 } 426 427 if (retval != 0) { 428 pr_err("Pasid 0x%x DQM create queue type %d failed. ret %d\n", 429 pqm->process->pasid, type, retval); 430 goto err_create_queue; 431 } 432 433 if (q && p_doorbell_offset_in_process) { 434 /* Return the doorbell offset within the doorbell page 435 * to the caller so it can be passed up to user mode 436 * (in bytes). 437 * relative doorbell index = Absolute doorbell index - 438 * absolute index of first doorbell in the page. 439 */ 440 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 441 pdd->qpd.proc_doorbells, 442 0, 443 pdd->dev->kfd->device_info.doorbell_size); 444 445 *p_doorbell_offset_in_process = (q->properties.doorbell_off 446 - first_db_index) * sizeof(uint32_t); 447 } 448 449 pr_debug("PQM After DQM create queue\n"); 450 451 list_add(&pqn->process_queue_list, &pqm->queues); 452 453 if (q) { 454 pr_debug("PQM done creating queue\n"); 455 kfd_procfs_add_queue(q); 456 print_queue_properties(&q->properties); 457 } 458 459 return retval; 460 461 err_create_queue: 462 uninit_queue(q); 463 if (kq) 464 kernel_queue_uninit(kq); 465 kfree(pqn); 466 err_allocate_pqn: 467 /* check if queues list is empty unregister process from device */ 468 clear_bit(*qid, pqm->queue_slot_bitmap); 469 if (list_empty(&pdd->qpd.queues_list) && 470 list_empty(&pdd->qpd.priv_queue_list)) 471 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 472 return retval; 473 } 474 475 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 476 { 477 struct process_queue_node *pqn; 478 struct kfd_process_device *pdd; 479 struct device_queue_manager *dqm; 480 struct kfd_node *dev; 481 int retval; 482 483 dqm = NULL; 484 485 retval = 0; 486 487 pqn = get_queue_by_qid(pqm, qid); 488 if (!pqn) { 489 pr_err("Queue id does not match any known queue\n"); 490 return -EINVAL; 491 } 492 493 dev = NULL; 494 if (pqn->kq) 495 dev = pqn->kq->dev; 496 if (pqn->q) 497 dev = pqn->q->device; 498 if (WARN_ON(!dev)) 499 return -ENODEV; 500 501 pdd = kfd_get_process_device_data(dev, pqm->process); 502 if (!pdd) { 503 pr_err("Process device data doesn't exist\n"); 504 return -1; 505 } 506 507 if (pqn->kq) { 508 /* destroy kernel queue (DIQ) */ 509 dqm = pqn->kq->dev->dqm; 510 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 511 kernel_queue_uninit(pqn->kq); 512 } 513 514 if (pqn->q) { 515 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 516 if (retval) 517 goto err_destroy_queue; 518 519 dqm = pqn->q->device->dqm; 520 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 521 if (retval) { 522 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 523 pqm->process->pasid, 524 pqn->q->properties.queue_id, retval); 525 if (retval != -ETIME) 526 goto err_destroy_queue; 527 } 528 kfd_procfs_del_queue(pqn->q); 529 kfd_queue_release_buffers(pdd, &pqn->q->properties); 530 pqm_clean_queue_resource(pqm, pqn); 531 uninit_queue(pqn->q); 532 } 533 534 list_del(&pqn->process_queue_list); 535 kfree(pqn); 536 clear_bit(qid, pqm->queue_slot_bitmap); 537 538 if (list_empty(&pdd->qpd.queues_list) && 539 list_empty(&pdd->qpd.priv_queue_list)) 540 dqm->ops.unregister_process(dqm, &pdd->qpd); 541 542 err_destroy_queue: 543 return retval; 544 } 545 546 int pqm_update_queue_properties(struct process_queue_manager *pqm, 547 unsigned int qid, struct queue_properties *p) 548 { 549 int retval; 550 struct process_queue_node *pqn; 551 552 pqn = get_queue_by_qid(pqm, qid); 553 if (!pqn || !pqn->q) { 554 pr_debug("No queue %d exists for update operation\n", qid); 555 return -EFAULT; 556 } 557 558 /* 559 * Update with NULL ring address is used to disable the queue 560 */ 561 if (p->queue_address && p->queue_size) { 562 struct kfd_process_device *pdd; 563 struct amdgpu_vm *vm; 564 struct queue *q = pqn->q; 565 int err; 566 567 pdd = kfd_get_process_device_data(q->device, q->process); 568 if (!pdd) 569 return -ENODEV; 570 vm = drm_priv_to_vm(pdd->drm_priv); 571 err = amdgpu_bo_reserve(vm->root.bo, false); 572 if (err) 573 return err; 574 575 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 576 p->queue_size)) { 577 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 578 p->queue_address, p->queue_size); 579 return -EFAULT; 580 } 581 582 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo); 583 kfd_queue_buffer_put(&pqn->q->properties.ring_bo); 584 amdgpu_bo_unreserve(vm->root.bo); 585 586 pqn->q->properties.ring_bo = p->ring_bo; 587 } 588 589 pqn->q->properties.queue_address = p->queue_address; 590 pqn->q->properties.queue_size = p->queue_size; 591 pqn->q->properties.queue_percent = p->queue_percent; 592 pqn->q->properties.priority = p->priority; 593 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 594 595 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 596 pqn->q, NULL); 597 if (retval != 0) 598 return retval; 599 600 return 0; 601 } 602 603 int pqm_update_mqd(struct process_queue_manager *pqm, 604 unsigned int qid, struct mqd_update_info *minfo) 605 { 606 int retval; 607 struct process_queue_node *pqn; 608 609 pqn = get_queue_by_qid(pqm, qid); 610 if (!pqn) { 611 pr_debug("No queue %d exists for update operation\n", qid); 612 return -EFAULT; 613 } 614 615 /* CUs are masked for debugger requirements so deny user mask */ 616 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 617 return -EBUSY; 618 619 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 620 if (minfo && minfo->cu_mask.ptr && 621 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { 622 int i; 623 624 for (i = 0; i < minfo->cu_mask.count; i += 2) { 625 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 626 627 if (cu_pair && cu_pair != 0x3) { 628 pr_debug("CUs must be adjacent pairwise enabled.\n"); 629 return -EINVAL; 630 } 631 } 632 } 633 634 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 635 pqn->q, minfo); 636 if (retval != 0) 637 return retval; 638 639 if (minfo && minfo->cu_mask.ptr) 640 pqn->q->properties.is_user_cu_masked = true; 641 642 return 0; 643 } 644 645 struct kernel_queue *pqm_get_kernel_queue( 646 struct process_queue_manager *pqm, 647 unsigned int qid) 648 { 649 struct process_queue_node *pqn; 650 651 pqn = get_queue_by_qid(pqm, qid); 652 if (pqn && pqn->kq) 653 return pqn->kq; 654 655 return NULL; 656 } 657 658 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 659 unsigned int qid) 660 { 661 struct process_queue_node *pqn; 662 663 pqn = get_queue_by_qid(pqm, qid); 664 return pqn ? pqn->q : NULL; 665 } 666 667 int pqm_get_wave_state(struct process_queue_manager *pqm, 668 unsigned int qid, 669 void __user *ctl_stack, 670 u32 *ctl_stack_used_size, 671 u32 *save_area_used_size) 672 { 673 struct process_queue_node *pqn; 674 675 pqn = get_queue_by_qid(pqm, qid); 676 if (!pqn) { 677 pr_debug("amdkfd: No queue %d exists for operation\n", 678 qid); 679 return -EFAULT; 680 } 681 682 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 683 pqn->q, 684 ctl_stack, 685 ctl_stack_used_size, 686 save_area_used_size); 687 } 688 689 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 690 uint64_t exception_clear_mask, 691 void __user *buf, 692 int *num_qss_entries, 693 uint32_t *entry_size) 694 { 695 struct process_queue_node *pqn; 696 struct kfd_queue_snapshot_entry src; 697 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 698 int r = 0; 699 700 *num_qss_entries = 0; 701 if (!(*entry_size)) 702 return -EINVAL; 703 704 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 705 mutex_lock(&pqm->process->event_mutex); 706 707 memset(&src, 0, sizeof(src)); 708 709 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 710 if (!pqn->q) 711 continue; 712 713 if (*num_qss_entries < tmp_qss_entries) { 714 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 715 716 if (copy_to_user(buf, &src, *entry_size)) { 717 r = -EFAULT; 718 break; 719 } 720 buf += tmp_entry_size; 721 } 722 *num_qss_entries += 1; 723 } 724 725 mutex_unlock(&pqm->process->event_mutex); 726 return r; 727 } 728 729 static int get_queue_data_sizes(struct kfd_process_device *pdd, 730 struct queue *q, 731 uint32_t *mqd_size, 732 uint32_t *ctl_stack_size) 733 { 734 int ret; 735 736 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 737 q->properties.queue_id, 738 mqd_size, 739 ctl_stack_size); 740 if (ret) 741 pr_err("Failed to get queue dump info (%d)\n", ret); 742 743 return ret; 744 } 745 746 int kfd_process_get_queue_info(struct kfd_process *p, 747 uint32_t *num_queues, 748 uint64_t *priv_data_sizes) 749 { 750 uint32_t extra_data_sizes = 0; 751 struct queue *q; 752 int i; 753 int ret; 754 755 *num_queues = 0; 756 757 /* Run over all PDDs of the process */ 758 for (i = 0; i < p->n_pdds; i++) { 759 struct kfd_process_device *pdd = p->pdds[i]; 760 761 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 762 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 763 q->properties.type == KFD_QUEUE_TYPE_SDMA || 764 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 765 uint32_t mqd_size, ctl_stack_size; 766 767 *num_queues = *num_queues + 1; 768 769 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 770 if (ret) 771 return ret; 772 773 extra_data_sizes += mqd_size + ctl_stack_size; 774 } else { 775 pr_err("Unsupported queue type (%d)\n", q->properties.type); 776 return -EOPNOTSUPP; 777 } 778 } 779 } 780 *priv_data_sizes = extra_data_sizes + 781 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 782 783 return 0; 784 } 785 786 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 787 unsigned int qid, 788 void *mqd, 789 void *ctl_stack) 790 { 791 struct process_queue_node *pqn; 792 793 pqn = get_queue_by_qid(pqm, qid); 794 if (!pqn) { 795 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 796 return -EFAULT; 797 } 798 799 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 800 pr_err("amdkfd: queue dumping not supported on this device\n"); 801 return -EOPNOTSUPP; 802 } 803 804 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 805 pqn->q, mqd, ctl_stack); 806 } 807 808 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 809 struct queue *q, 810 struct kfd_criu_queue_priv_data *q_data) 811 { 812 uint8_t *mqd, *ctl_stack; 813 int ret; 814 815 mqd = (void *)(q_data + 1); 816 ctl_stack = mqd + q_data->mqd_size; 817 818 q_data->gpu_id = pdd->user_gpu_id; 819 q_data->type = q->properties.type; 820 q_data->format = q->properties.format; 821 q_data->q_id = q->properties.queue_id; 822 q_data->q_address = q->properties.queue_address; 823 q_data->q_size = q->properties.queue_size; 824 q_data->priority = q->properties.priority; 825 q_data->q_percent = q->properties.queue_percent; 826 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 827 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 828 q_data->doorbell_id = q->doorbell_id; 829 830 q_data->sdma_id = q->sdma_id; 831 832 q_data->eop_ring_buffer_address = 833 q->properties.eop_ring_buffer_address; 834 835 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 836 837 q_data->ctx_save_restore_area_address = 838 q->properties.ctx_save_restore_area_address; 839 840 q_data->ctx_save_restore_area_size = 841 q->properties.ctx_save_restore_area_size; 842 843 q_data->gws = !!q->gws; 844 845 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 846 if (ret) { 847 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 848 return ret; 849 } 850 851 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 852 return ret; 853 } 854 855 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 856 uint8_t __user *user_priv, 857 unsigned int *q_index, 858 uint64_t *queues_priv_data_offset) 859 { 860 unsigned int q_private_data_size = 0; 861 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 862 struct queue *q; 863 int ret = 0; 864 865 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 866 struct kfd_criu_queue_priv_data *q_data; 867 uint64_t q_data_size; 868 uint32_t mqd_size; 869 uint32_t ctl_stack_size; 870 871 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 872 q->properties.type != KFD_QUEUE_TYPE_SDMA && 873 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 874 875 pr_err("Unsupported queue type (%d)\n", q->properties.type); 876 ret = -EOPNOTSUPP; 877 break; 878 } 879 880 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 881 if (ret) 882 break; 883 884 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 885 886 /* Increase local buffer space if needed */ 887 if (q_private_data_size < q_data_size) { 888 kfree(q_private_data); 889 890 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 891 if (!q_private_data) { 892 ret = -ENOMEM; 893 break; 894 } 895 q_private_data_size = q_data_size; 896 } 897 898 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 899 900 /* data stored in this order: priv_data, mqd, ctl_stack */ 901 q_data->mqd_size = mqd_size; 902 q_data->ctl_stack_size = ctl_stack_size; 903 904 ret = criu_checkpoint_queue(pdd, q, q_data); 905 if (ret) 906 break; 907 908 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 909 910 ret = copy_to_user(user_priv + *queues_priv_data_offset, 911 q_data, q_data_size); 912 if (ret) { 913 ret = -EFAULT; 914 break; 915 } 916 *queues_priv_data_offset += q_data_size; 917 *q_index = *q_index + 1; 918 } 919 920 kfree(q_private_data); 921 922 return ret; 923 } 924 925 int kfd_criu_checkpoint_queues(struct kfd_process *p, 926 uint8_t __user *user_priv_data, 927 uint64_t *priv_data_offset) 928 { 929 int ret = 0, pdd_index, q_index = 0; 930 931 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 932 struct kfd_process_device *pdd = p->pdds[pdd_index]; 933 934 /* 935 * criu_checkpoint_queues_device will copy data to user and update q_index and 936 * queues_priv_data_offset 937 */ 938 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 939 priv_data_offset); 940 941 if (ret) 942 break; 943 } 944 945 return ret; 946 } 947 948 static void set_queue_properties_from_criu(struct queue_properties *qp, 949 struct kfd_criu_queue_priv_data *q_data) 950 { 951 qp->is_interop = false; 952 qp->queue_percent = q_data->q_percent; 953 qp->priority = q_data->priority; 954 qp->queue_address = q_data->q_address; 955 qp->queue_size = q_data->q_size; 956 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr; 957 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr; 958 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 959 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 960 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 961 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 962 qp->ctl_stack_size = q_data->ctl_stack_size; 963 qp->type = q_data->type; 964 qp->format = q_data->format; 965 } 966 967 int kfd_criu_restore_queue(struct kfd_process *p, 968 uint8_t __user *user_priv_ptr, 969 uint64_t *priv_data_offset, 970 uint64_t max_priv_data_size) 971 { 972 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 973 struct kfd_criu_queue_priv_data *q_data; 974 struct kfd_process_device *pdd; 975 uint64_t q_extra_data_size; 976 struct queue_properties qp; 977 unsigned int queue_id; 978 int ret = 0; 979 980 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 981 return -EINVAL; 982 983 q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); 984 if (!q_data) 985 return -ENOMEM; 986 987 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 988 if (ret) { 989 ret = -EFAULT; 990 goto exit; 991 } 992 993 *priv_data_offset += sizeof(*q_data); 994 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 995 996 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 997 ret = -EINVAL; 998 goto exit; 999 } 1000 1001 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1002 if (!q_extra_data) { 1003 ret = -ENOMEM; 1004 goto exit; 1005 } 1006 1007 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1008 if (ret) { 1009 ret = -EFAULT; 1010 goto exit; 1011 } 1012 1013 *priv_data_offset += q_extra_data_size; 1014 1015 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1016 if (!pdd) { 1017 pr_err("Failed to get pdd\n"); 1018 ret = -EINVAL; 1019 goto exit; 1020 } 1021 1022 /* data stored in this order: mqd, ctl_stack */ 1023 mqd = q_extra_data; 1024 ctl_stack = mqd + q_data->mqd_size; 1025 1026 memset(&qp, 0, sizeof(qp)); 1027 set_queue_properties_from_criu(&qp, q_data); 1028 1029 print_queue_properties(&qp); 1030 1031 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); 1032 if (ret) { 1033 pr_err("Failed to create new queue err:%d\n", ret); 1034 goto exit; 1035 } 1036 1037 if (q_data->gws) 1038 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1039 1040 exit: 1041 if (ret) 1042 pr_err("Failed to restore queue (%d)\n", ret); 1043 else 1044 pr_debug("Queue id %d was restored successfully\n", queue_id); 1045 1046 kfree(q_data); 1047 kfree(q_extra_data); 1048 1049 return ret; 1050 } 1051 1052 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1053 unsigned int qid, 1054 uint32_t *mqd_size, 1055 uint32_t *ctl_stack_size) 1056 { 1057 struct process_queue_node *pqn; 1058 1059 pqn = get_queue_by_qid(pqm, qid); 1060 if (!pqn) { 1061 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1062 return -EFAULT; 1063 } 1064 1065 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1066 pr_err("amdkfd: queue dumping not supported on this device\n"); 1067 return -EOPNOTSUPP; 1068 } 1069 1070 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1071 pqn->q, mqd_size, 1072 ctl_stack_size); 1073 return 0; 1074 } 1075 1076 #if defined(CONFIG_DEBUG_FS) 1077 1078 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1079 { 1080 struct process_queue_manager *pqm = data; 1081 struct process_queue_node *pqn; 1082 struct queue *q; 1083 enum KFD_MQD_TYPE mqd_type; 1084 struct mqd_manager *mqd_mgr; 1085 int r = 0, xcc, num_xccs = 1; 1086 void *mqd; 1087 uint64_t size = 0; 1088 1089 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1090 if (pqn->q) { 1091 q = pqn->q; 1092 switch (q->properties.type) { 1093 case KFD_QUEUE_TYPE_SDMA: 1094 case KFD_QUEUE_TYPE_SDMA_XGMI: 1095 seq_printf(m, " SDMA queue on device %x\n", 1096 q->device->id); 1097 mqd_type = KFD_MQD_TYPE_SDMA; 1098 break; 1099 case KFD_QUEUE_TYPE_COMPUTE: 1100 seq_printf(m, " Compute queue on device %x\n", 1101 q->device->id); 1102 mqd_type = KFD_MQD_TYPE_CP; 1103 num_xccs = NUM_XCC(q->device->xcc_mask); 1104 break; 1105 default: 1106 seq_printf(m, 1107 " Bad user queue type %d on device %x\n", 1108 q->properties.type, q->device->id); 1109 continue; 1110 } 1111 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1112 size = mqd_mgr->mqd_stride(mqd_mgr, 1113 &q->properties); 1114 } else if (pqn->kq) { 1115 q = pqn->kq->queue; 1116 mqd_mgr = pqn->kq->mqd_mgr; 1117 switch (q->properties.type) { 1118 case KFD_QUEUE_TYPE_DIQ: 1119 seq_printf(m, " DIQ on device %x\n", 1120 pqn->kq->dev->id); 1121 break; 1122 default: 1123 seq_printf(m, 1124 " Bad kernel queue type %d on device %x\n", 1125 q->properties.type, 1126 pqn->kq->dev->id); 1127 continue; 1128 } 1129 } else { 1130 seq_printf(m, 1131 " Weird: Queue node with neither kernel nor user queue\n"); 1132 continue; 1133 } 1134 1135 for (xcc = 0; xcc < num_xccs; xcc++) { 1136 mqd = q->mqd + size * xcc; 1137 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1138 if (r != 0) 1139 break; 1140 } 1141 } 1142 1143 return r; 1144 } 1145 1146 #endif 1147