1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pid %d\n", 73 pqm->process->lead_thread->pid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 /* The MES context flush needs to filter out the case which the 90 * KFD process is created without setting up the MES context and 91 * queue for creating a compute queue. 92 */ 93 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && 95 down_read_trylock(&dev->adev->reset_domain->sem)) { 96 amdgpu_mes_flush_shader_debugger(dev->adev, 97 pdd->proc_ctx_gpu_addr, 98 ffs(pdd->dev->xcc_mask) - 1); 99 up_read(&dev->adev->reset_domain->sem); 100 } 101 pdd->already_dequeued = true; 102 } 103 104 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 105 void *gws) 106 { 107 struct mqd_update_info minfo = {0}; 108 struct kfd_node *dev = NULL; 109 struct process_queue_node *pqn; 110 struct kfd_process_device *pdd; 111 struct kgd_mem *mem = NULL; 112 int ret; 113 114 pqn = get_queue_by_qid(pqm, qid); 115 if (!pqn) { 116 pr_err("Queue id does not match any known queue\n"); 117 return -EINVAL; 118 } 119 120 if (pqn->q) 121 dev = pqn->q->device; 122 if (WARN_ON(!dev)) 123 return -ENODEV; 124 125 pdd = kfd_get_process_device_data(dev, pqm->process); 126 if (!pdd) { 127 pr_err("Process device data doesn't exist\n"); 128 return -EINVAL; 129 } 130 131 /* Only allow one queue per process can have GWS assigned */ 132 if (gws && pdd->qpd.num_gws) 133 return -EBUSY; 134 135 if (!gws && pdd->qpd.num_gws == 0) 136 return -EINVAL; 137 138 if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 139 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 140 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && 141 !dev->kfd->shared_resources.enable_mes) { 142 if (gws) 143 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 144 gws, &mem); 145 else 146 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 147 pqn->q->gws); 148 if (unlikely(ret)) 149 return ret; 150 pqn->q->gws = mem; 151 } else { 152 /* 153 * Intentionally set GWS to a non-NULL value 154 * for devices that do not use GWS for global wave 155 * synchronization but require the formality 156 * of setting GWS for cooperative groups. 157 */ 158 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 159 } 160 161 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 162 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 163 164 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 165 pqn->q, &minfo); 166 } 167 168 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 169 { 170 int i; 171 172 for (i = 0; i < p->n_pdds; i++) 173 kfd_process_dequeue_from_device(p->pdds[i]); 174 } 175 176 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 177 { 178 INIT_LIST_HEAD(&pqm->queues); 179 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 180 GFP_KERNEL); 181 if (!pqm->queue_slot_bitmap) 182 return -ENOMEM; 183 pqm->process = p; 184 185 return 0; 186 } 187 188 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 189 struct process_queue_node *pqn) 190 { 191 struct kfd_node *dev; 192 struct kfd_process_device *pdd; 193 194 dev = pqn->q->device; 195 196 pdd = kfd_get_process_device_data(dev, pqm->process); 197 if (!pdd) { 198 pr_err("Process device data doesn't exist\n"); 199 return; 200 } 201 202 if (pqn->q->gws) { 203 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 204 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 205 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && 206 !dev->kfd->shared_resources.enable_mes) 207 amdgpu_amdkfd_remove_gws_from_process( 208 pqm->process->kgd_process_info, pqn->q->gws); 209 pdd->qpd.num_gws = 0; 210 } 211 212 if (dev->kfd->shared_resources.enable_mes) { 213 amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, pqn->q->gang_ctx_array_index); 214 amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo); 215 amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 216 } 217 } 218 219 void pqm_uninit(struct process_queue_manager *pqm) 220 { 221 struct process_queue_node *pqn, *next; 222 223 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 224 if (pqn->q) { 225 struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, 226 pqm->process); 227 if (pdd) { 228 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 229 kfd_queue_release_buffers(pdd, &pqn->q->properties); 230 } else { 231 WARN_ON(!pdd); 232 } 233 pqm_clean_queue_resource(pqm, pqn); 234 } 235 236 kfd_procfs_del_queue(pqn->q); 237 uninit_queue(pqn->q); 238 list_del(&pqn->process_queue_list); 239 kfree(pqn); 240 } 241 242 bitmap_free(pqm->queue_slot_bitmap); 243 pqm->queue_slot_bitmap = NULL; 244 } 245 246 static int init_user_queue(struct process_queue_manager *pqm, 247 struct kfd_node *dev, struct queue **q, 248 struct queue_properties *q_properties, 249 unsigned int qid) 250 { 251 int retval; 252 253 /* Doorbell initialized in user space*/ 254 q_properties->doorbell_ptr = NULL; 255 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 256 257 /* let DQM handle it*/ 258 q_properties->vmid = 0; 259 q_properties->queue_id = qid; 260 261 retval = init_queue(q, q_properties); 262 if (retval != 0) 263 return retval; 264 265 (*q)->device = dev; 266 (*q)->process = pqm->process; 267 268 if (dev->kfd->shared_resources.enable_mes) { 269 if (!q_properties->wptr_bo) { 270 pr_debug("Queue initialization with shared MES requires queue buffers to be initialized\n"); 271 return -EINVAL; 272 } 273 274 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, 275 AMDGPU_MES_GANG_CTX_SIZE, 276 AMDGPU_GEM_DOMAIN_GTT, 277 &(*q)->gang_ctx_bo, 278 &(*q)->gang_ctx_gpu_addr, 279 &(*q)->gang_ctx_cpu_ptr, 280 false); 281 if (retval) { 282 pr_err("failed to allocate gang context bo\n"); 283 goto cleanup; 284 } 285 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 286 /* Bind one MES gang context slot per queue (gang). */ 287 if (dev->adev->mes.use_rs64mem) { 288 retval = amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes, 289 &(*q)->gang_ctx_array_index); 290 if (retval) { 291 pr_err("failed to allocate gang context index slot\n"); 292 goto cleanup; 293 } 294 } 295 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 296 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 297 */ 298 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 299 pr_err("Queue memory allocated to wrong device\n"); 300 retval = -EINVAL; 301 goto free_gang_ctx_bo; 302 } 303 304 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 305 &(*q)->wptr_bo_gart); 306 if (retval) { 307 pr_err("Failed to map wptr bo to GART\n"); 308 goto free_gang_ctx_bo; 309 } 310 } 311 312 pr_debug("PQM After init queue"); 313 return 0; 314 315 free_gang_ctx_bo: 316 amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, (*q)->gang_ctx_array_index); 317 amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo); 318 cleanup: 319 uninit_queue(*q); 320 *q = NULL; 321 return retval; 322 } 323 324 int pqm_create_queue(struct process_queue_manager *pqm, 325 struct kfd_node *dev, 326 struct queue_properties *properties, 327 unsigned int *qid, 328 const struct kfd_criu_queue_priv_data *q_data, 329 const void *restore_mqd, 330 const void *restore_ctl_stack, 331 uint32_t *p_doorbell_offset_in_process) 332 { 333 int retval; 334 struct kfd_process_device *pdd; 335 struct queue *q; 336 struct process_queue_node *pqn; 337 struct kernel_queue *kq; 338 enum kfd_queue_type type = properties->type; 339 unsigned int max_queues = 127; /* HWS limit */ 340 341 /* 342 * On GFX 9.4.3/9.5.0/12.1.0, increase the number of queues that 343 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0/12.1.0. 344 */ 345 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 346 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 347 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0) || 348 KFD_GC_VERSION(dev) == IP_VERSION(12, 1, 0)) 349 max_queues = 255; 350 351 q = NULL; 352 kq = NULL; 353 354 pdd = kfd_get_process_device_data(dev, pqm->process); 355 if (!pdd) { 356 pr_err("Process device data doesn't exist\n"); 357 return -1; 358 } 359 360 /* 361 * for debug process, verify that it is within the static queues limit 362 * currently limit is set to half of the total avail HQD slots 363 * If we are just about to create DIQ, the is_debug flag is not set yet 364 * Hence we also check the type as well 365 */ 366 if (pdd->qpd.is_debug) 367 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 368 369 if (pdd->qpd.queue_count >= max_queues) 370 return -ENOSPC; 371 372 if (q_data) { 373 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 374 *qid = q_data->q_id; 375 } else 376 retval = find_available_queue_slot(pqm, qid); 377 378 if (retval != 0) 379 return retval; 380 381 /* Register process if this is the first queue */ 382 if (list_empty(&pdd->qpd.queues_list) && 383 list_empty(&pdd->qpd.priv_queue_list)) 384 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 385 386 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ 387 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { 388 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, 389 AMDGPU_MES_PROC_CTX_SIZE, 390 AMDGPU_GEM_DOMAIN_GTT, 391 &pdd->proc_ctx_bo, 392 &pdd->proc_ctx_gpu_addr, 393 &pdd->proc_ctx_cpu_ptr, 394 false); 395 if (retval) { 396 dev_err(dev->adev->dev, "failed to allocate process context bo\n"); 397 goto err_allocate_pqn; 398 } 399 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); 400 /* Bind one MES process context slot to the whole process 401 * (per device); every queue of this process reuses it. 402 */ 403 if (dev->adev->mes.use_rs64mem) { 404 retval = amdgpu_mes_alloc_proc_ctx_index(&dev->adev->mes, 405 &pdd->proc_ctx_array_index); 406 if (retval) { 407 dev_err(dev->adev->dev, "failed to allocate process context index\n"); 408 goto err_allocate_pqn; 409 } 410 } 411 } 412 413 pqn = kzalloc_obj(*pqn); 414 if (!pqn) { 415 retval = -ENOMEM; 416 goto err_allocate_pqn; 417 } 418 419 switch (type) { 420 case KFD_QUEUE_TYPE_SDMA: 421 case KFD_QUEUE_TYPE_SDMA_XGMI: 422 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 423 /* SDMA queues are always allocated statically no matter 424 * which scheduler mode is used. We also do not need to 425 * check whether a SDMA queue can be allocated here, because 426 * allocate_sdma_queue() in create_queue() has the 427 * corresponding check logic. 428 */ 429 retval = init_user_queue(pqm, dev, &q, properties, *qid); 430 if (retval != 0) 431 goto err_create_queue; 432 pqn->q = q; 433 pqn->kq = NULL; 434 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 435 restore_mqd, restore_ctl_stack); 436 print_queue(q); 437 break; 438 439 case KFD_QUEUE_TYPE_COMPUTE: 440 /* check if there is over subscription */ 441 if ((dev->dqm->sched_policy == 442 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 443 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 444 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 445 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 446 retval = -EPERM; 447 goto err_create_queue; 448 } 449 450 retval = init_user_queue(pqm, dev, &q, properties, *qid); 451 if (retval != 0) 452 goto err_create_queue; 453 pqn->q = q; 454 pqn->kq = NULL; 455 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 456 restore_mqd, restore_ctl_stack); 457 print_queue(q); 458 break; 459 default: 460 WARN(1, "Invalid queue type %d", type); 461 retval = -EINVAL; 462 } 463 464 if (retval != 0) { 465 if ((type == KFD_QUEUE_TYPE_SDMA || 466 type == KFD_QUEUE_TYPE_SDMA_XGMI || 467 type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && 468 retval == -ENOMEM) 469 pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", 470 pqm->process->lead_thread->pid, type, retval); 471 else 472 pr_err("process pid %d DQM create queue type %d failed. ret %d\n", 473 pqm->process->lead_thread->pid, type, retval); 474 goto err_create_queue; 475 } 476 477 if (q && p_doorbell_offset_in_process) { 478 /* Return the doorbell offset within the doorbell page 479 * to the caller so it can be passed up to user mode 480 * (in bytes). 481 * relative doorbell index = Absolute doorbell index - 482 * absolute index of first doorbell in the page. 483 */ 484 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 485 pdd->qpd.proc_doorbells, 486 0, 487 pdd->dev->kfd->device_info.doorbell_size); 488 489 *p_doorbell_offset_in_process = (q->properties.doorbell_off 490 - first_db_index) * sizeof(uint32_t); 491 } 492 493 pr_debug("PQM After DQM create queue\n"); 494 495 list_add(&pqn->process_queue_list, &pqm->queues); 496 497 if (q) { 498 pr_debug("PQM done creating queue\n"); 499 kfd_procfs_add_queue(q); 500 print_queue_properties(&q->properties); 501 } 502 503 return retval; 504 505 err_create_queue: 506 uninit_queue(q); 507 if (kq) 508 kernel_queue_uninit(kq); 509 kfree(pqn); 510 err_allocate_pqn: 511 /* check if queues list is empty unregister process from device */ 512 clear_bit(*qid, pqm->queue_slot_bitmap); 513 if (list_empty(&pdd->qpd.queues_list) && 514 list_empty(&pdd->qpd.priv_queue_list)) 515 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 516 return retval; 517 } 518 519 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 520 { 521 struct process_queue_node *pqn; 522 struct kfd_process_device *pdd; 523 struct device_queue_manager *dqm; 524 struct kfd_node *dev; 525 int retval; 526 527 dqm = NULL; 528 529 retval = 0; 530 531 pqn = get_queue_by_qid(pqm, qid); 532 if (!pqn) { 533 pr_err("Queue id does not match any known queue\n"); 534 return -EINVAL; 535 } 536 537 dev = NULL; 538 if (pqn->kq) 539 dev = pqn->kq->dev; 540 if (pqn->q) 541 dev = pqn->q->device; 542 if (WARN_ON(!dev)) 543 return -ENODEV; 544 545 pdd = kfd_get_process_device_data(dev, pqm->process); 546 if (!pdd) { 547 pr_err("Process device data doesn't exist\n"); 548 return -1; 549 } 550 551 if (pqn->kq) { 552 /* destroy kernel queue (DIQ) */ 553 dqm = pqn->kq->dev->dqm; 554 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 555 kernel_queue_uninit(pqn->kq); 556 } 557 558 if (pqn->q) { 559 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 560 if (retval) 561 goto err_destroy_queue; 562 563 dqm = pqn->q->device->dqm; 564 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 565 if (retval) { 566 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 567 pdd->pasid, 568 pqn->q->properties.queue_id, retval); 569 if (retval != -ETIME && retval != -EIO) 570 goto err_destroy_queue; 571 } 572 kfd_procfs_del_queue(pqn->q); 573 kfd_queue_release_buffers(pdd, &pqn->q->properties); 574 pqm_clean_queue_resource(pqm, pqn); 575 uninit_queue(pqn->q); 576 } 577 578 list_del(&pqn->process_queue_list); 579 kfree(pqn); 580 clear_bit(qid, pqm->queue_slot_bitmap); 581 582 if (list_empty(&pdd->qpd.queues_list) && 583 list_empty(&pdd->qpd.priv_queue_list)) 584 dqm->ops.unregister_process(dqm, &pdd->qpd); 585 586 err_destroy_queue: 587 return retval; 588 } 589 590 int pqm_update_queue_properties(struct process_queue_manager *pqm, 591 unsigned int qid, struct queue_properties *p) 592 { 593 int retval; 594 struct process_queue_node *pqn; 595 596 pqn = get_queue_by_qid(pqm, qid); 597 if (!pqn || !pqn->q) { 598 pr_debug("No queue %d exists for update operation\n", qid); 599 return -EFAULT; 600 } 601 602 /* 603 * Update with NULL ring address is used to disable the queue 604 */ 605 if (p->queue_address && p->queue_size) { 606 struct kfd_process_device *pdd; 607 struct amdgpu_vm *vm; 608 struct queue *q = pqn->q; 609 int err; 610 611 pdd = kfd_get_process_device_data(q->device, q->process); 612 if (!pdd) 613 return -ENODEV; 614 vm = drm_priv_to_vm(pdd->drm_priv); 615 err = amdgpu_bo_reserve(vm->root.bo, false); 616 if (err) 617 return err; 618 619 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 620 p->queue_size + 621 pqn->q->properties.metadata_queue_size)) { 622 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 623 p->queue_address, p->queue_size); 624 amdgpu_bo_unreserve(vm->root.bo); 625 return -EFAULT; 626 } 627 628 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo); 629 kfd_queue_buffer_put(&pqn->q->properties.ring_bo); 630 amdgpu_bo_unreserve(vm->root.bo); 631 632 pqn->q->properties.ring_bo = p->ring_bo; 633 } 634 635 pqn->q->properties.queue_address = p->queue_address; 636 pqn->q->properties.queue_size = p->queue_size; 637 pqn->q->properties.queue_percent = p->queue_percent; 638 pqn->q->properties.priority = p->priority; 639 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 640 641 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 642 pqn->q, NULL); 643 if (retval != 0) 644 return retval; 645 646 return 0; 647 } 648 649 int pqm_update_mqd(struct process_queue_manager *pqm, 650 unsigned int qid, struct mqd_update_info *minfo) 651 { 652 int retval; 653 struct process_queue_node *pqn; 654 655 pqn = get_queue_by_qid(pqm, qid); 656 if (!pqn) { 657 pr_debug("No queue %d exists for update operation\n", qid); 658 return -EFAULT; 659 } 660 661 /* CUs are masked for debugger requirements so deny user mask */ 662 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 663 return -EBUSY; 664 665 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 666 if (minfo && minfo->cu_mask.ptr && 667 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0) && 668 KFD_GC_VERSION(pqn->q->device) < IP_VERSION(12, 1, 0)) { 669 int i; 670 671 for (i = 0; i < minfo->cu_mask.count; i += 2) { 672 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 673 674 if (cu_pair && cu_pair != 0x3) { 675 pr_debug("CUs must be adjacent pairwise enabled.\n"); 676 return -EINVAL; 677 } 678 } 679 } 680 681 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 682 pqn->q, minfo); 683 if (retval != 0) 684 return retval; 685 686 if (minfo && minfo->cu_mask.ptr) 687 pqn->q->properties.is_user_cu_masked = true; 688 689 return 0; 690 } 691 692 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 693 unsigned int qid) 694 { 695 struct process_queue_node *pqn; 696 697 pqn = get_queue_by_qid(pqm, qid); 698 return pqn ? pqn->q : NULL; 699 } 700 701 int pqm_get_wave_state(struct process_queue_manager *pqm, 702 unsigned int qid, 703 void __user *ctl_stack, 704 u32 *ctl_stack_used_size, 705 u32 *save_area_used_size) 706 { 707 struct process_queue_node *pqn; 708 709 pqn = get_queue_by_qid(pqm, qid); 710 if (!pqn) { 711 pr_debug("amdkfd: No queue %d exists for operation\n", 712 qid); 713 return -EFAULT; 714 } 715 716 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 717 pqn->q, 718 ctl_stack, 719 ctl_stack_used_size, 720 save_area_used_size); 721 } 722 723 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 724 uint64_t exception_clear_mask, 725 void __user *buf, 726 int *num_qss_entries, 727 uint32_t *entry_size) 728 { 729 struct process_queue_node *pqn; 730 struct kfd_queue_snapshot_entry src; 731 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 732 int r = 0; 733 734 *num_qss_entries = 0; 735 if (!(*entry_size)) 736 return -EINVAL; 737 738 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 739 mutex_lock(&pqm->process->event_mutex); 740 741 memset(&src, 0, sizeof(src)); 742 743 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 744 if (!pqn->q) 745 continue; 746 747 if (*num_qss_entries < tmp_qss_entries) { 748 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 749 750 if (copy_to_user(buf, &src, *entry_size)) { 751 r = -EFAULT; 752 break; 753 } 754 buf += tmp_entry_size; 755 } 756 *num_qss_entries += 1; 757 } 758 759 mutex_unlock(&pqm->process->event_mutex); 760 return r; 761 } 762 763 static int get_queue_data_sizes(struct kfd_process_device *pdd, 764 struct queue *q, 765 uint32_t *mqd_size, 766 uint32_t *ctl_stack_size) 767 { 768 int ret; 769 770 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 771 q->properties.queue_id, 772 mqd_size, 773 ctl_stack_size); 774 if (ret) 775 pr_err("Failed to get queue dump info (%d)\n", ret); 776 777 return ret; 778 } 779 780 int kfd_process_get_queue_info(struct kfd_process *p, 781 uint32_t *num_queues, 782 uint64_t *priv_data_sizes) 783 { 784 uint32_t extra_data_sizes = 0; 785 struct queue *q; 786 int i; 787 int ret; 788 789 *num_queues = 0; 790 791 /* Run over all PDDs of the process */ 792 for (i = 0; i < p->n_pdds; i++) { 793 struct kfd_process_device *pdd = p->pdds[i]; 794 795 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 796 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 797 q->properties.type == KFD_QUEUE_TYPE_SDMA || 798 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 799 uint32_t mqd_size, ctl_stack_size; 800 801 *num_queues = *num_queues + 1; 802 803 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 804 if (ret) 805 return ret; 806 807 extra_data_sizes += mqd_size + ctl_stack_size; 808 } else { 809 pr_err("Unsupported queue type (%d)\n", q->properties.type); 810 return -EOPNOTSUPP; 811 } 812 } 813 } 814 *priv_data_sizes = extra_data_sizes + 815 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 816 817 return 0; 818 } 819 820 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 821 unsigned int qid, 822 void *mqd, 823 void *ctl_stack) 824 { 825 struct process_queue_node *pqn; 826 827 pqn = get_queue_by_qid(pqm, qid); 828 if (!pqn) { 829 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 830 return -EFAULT; 831 } 832 833 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 834 pr_err("amdkfd: queue dumping not supported on this device\n"); 835 return -EOPNOTSUPP; 836 } 837 838 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 839 pqn->q, mqd, ctl_stack); 840 } 841 842 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 843 struct queue *q, 844 struct kfd_criu_queue_priv_data *q_data) 845 { 846 uint8_t *mqd, *ctl_stack; 847 int ret; 848 849 mqd = (void *)(q_data + 1); 850 ctl_stack = mqd + q_data->mqd_size; 851 852 q_data->gpu_id = pdd->user_gpu_id; 853 q_data->type = q->properties.type; 854 q_data->format = q->properties.format; 855 q_data->q_id = q->properties.queue_id; 856 q_data->q_address = q->properties.queue_address; 857 q_data->q_size = q->properties.queue_size; 858 q_data->priority = q->properties.priority; 859 q_data->q_percent = q->properties.queue_percent; 860 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 861 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 862 q_data->doorbell_id = q->doorbell_id; 863 864 q_data->sdma_id = q->sdma_id; 865 866 q_data->eop_ring_buffer_address = 867 q->properties.eop_ring_buffer_address; 868 869 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 870 871 q_data->ctx_save_restore_area_address = 872 q->properties.ctx_save_restore_area_address; 873 874 q_data->ctx_save_restore_area_size = 875 q->properties.ctx_save_restore_area_size; 876 877 q_data->gws = !!q->gws; 878 879 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 880 if (ret) { 881 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 882 return ret; 883 } 884 885 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 886 return ret; 887 } 888 889 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 890 uint8_t __user *user_priv, 891 unsigned int *q_index, 892 uint64_t *queues_priv_data_offset) 893 { 894 unsigned int q_private_data_size = 0; 895 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 896 struct queue *q; 897 int ret = 0; 898 899 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 900 struct kfd_criu_queue_priv_data *q_data; 901 uint64_t q_data_size; 902 uint32_t mqd_size; 903 uint32_t ctl_stack_size; 904 905 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 906 q->properties.type != KFD_QUEUE_TYPE_SDMA && 907 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 908 909 pr_err("Unsupported queue type (%d)\n", q->properties.type); 910 ret = -EOPNOTSUPP; 911 break; 912 } 913 914 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 915 if (ret) 916 break; 917 918 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 919 920 /* Increase local buffer space if needed */ 921 if (q_private_data_size < q_data_size) { 922 kfree(q_private_data); 923 924 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 925 if (!q_private_data) { 926 ret = -ENOMEM; 927 break; 928 } 929 q_private_data_size = q_data_size; 930 } 931 932 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 933 934 /* 935 * data stored in this order: 936 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 937 */ 938 q_data->mqd_size = mqd_size; 939 q_data->ctl_stack_size = ctl_stack_size; 940 941 ret = criu_checkpoint_queue(pdd, q, q_data); 942 if (ret) 943 break; 944 945 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 946 947 ret = copy_to_user(user_priv + *queues_priv_data_offset, 948 q_data, q_data_size); 949 if (ret) { 950 ret = -EFAULT; 951 break; 952 } 953 *queues_priv_data_offset += q_data_size; 954 *q_index = *q_index + 1; 955 } 956 957 kfree(q_private_data); 958 959 return ret; 960 } 961 962 int kfd_criu_checkpoint_queues(struct kfd_process *p, 963 uint8_t __user *user_priv_data, 964 uint64_t *priv_data_offset) 965 { 966 int ret = 0, pdd_index, q_index = 0; 967 968 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 969 struct kfd_process_device *pdd = p->pdds[pdd_index]; 970 971 /* 972 * criu_checkpoint_queues_device will copy data to user and update q_index and 973 * queues_priv_data_offset 974 */ 975 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 976 priv_data_offset); 977 978 if (ret) 979 break; 980 } 981 982 return ret; 983 } 984 985 static void set_queue_properties_from_criu(struct queue_properties *qp, 986 struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc) 987 { 988 qp->is_interop = false; 989 qp->queue_percent = q_data->q_percent; 990 qp->priority = q_data->priority; 991 qp->queue_address = q_data->q_address; 992 qp->queue_size = q_data->q_size; 993 qp->read_ptr = (void __user *)q_data->read_ptr_addr; 994 qp->write_ptr = (void __user *)q_data->write_ptr_addr; 995 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 996 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 997 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 998 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 999 if (q_data->type == KFD_QUEUE_TYPE_COMPUTE) 1000 qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc; 1001 else 1002 qp->ctl_stack_size = q_data->ctl_stack_size; 1003 1004 qp->type = q_data->type; 1005 qp->format = q_data->format; 1006 } 1007 1008 int kfd_criu_restore_queue(struct kfd_process *p, 1009 uint8_t __user *user_priv_ptr, 1010 uint64_t *priv_data_offset, 1011 uint64_t max_priv_data_size) 1012 { 1013 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 1014 struct kfd_criu_queue_priv_data *q_data; 1015 struct kfd_process_device *pdd; 1016 uint64_t q_extra_data_size; 1017 struct queue_properties qp; 1018 unsigned int queue_id; 1019 int ret = 0; 1020 1021 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 1022 return -EINVAL; 1023 1024 q_data = kmalloc_obj(*q_data); 1025 if (!q_data) 1026 return -ENOMEM; 1027 1028 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 1029 if (ret) { 1030 ret = -EFAULT; 1031 goto exit; 1032 } 1033 1034 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1035 if (!pdd) { 1036 pr_err("Failed to get pdd\n"); 1037 ret = -EINVAL; 1038 goto exit; 1039 } 1040 1041 if (q_data->type >= KFD_QUEUE_TYPE_MAX) { 1042 ret = -EINVAL; 1043 goto exit; 1044 } 1045 1046 if (q_data->mqd_size != mqd_size_from_queue_type(pdd->dev->dqm, q_data->type)) { 1047 ret = -EINVAL; 1048 goto exit; 1049 } 1050 1051 *priv_data_offset += sizeof(*q_data); 1052 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 1053 1054 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 1055 ret = -EINVAL; 1056 goto exit; 1057 } 1058 1059 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1060 if (!q_extra_data) { 1061 ret = -ENOMEM; 1062 goto exit; 1063 } 1064 1065 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1066 if (ret) { 1067 ret = -EFAULT; 1068 goto exit; 1069 } 1070 1071 *priv_data_offset += q_extra_data_size; 1072 1073 /* 1074 * data stored in this order: 1075 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 1076 */ 1077 mqd = q_extra_data; 1078 ctl_stack = mqd + q_data->mqd_size; 1079 1080 memset(&qp, 0, sizeof(qp)); 1081 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->xcc_mask)); 1082 1083 print_queue_properties(&qp); 1084 1085 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); 1086 if (ret) { 1087 pr_err("Failed to create new queue err:%d\n", ret); 1088 goto exit; 1089 } 1090 1091 if (q_data->gws) 1092 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1093 1094 exit: 1095 if (ret) 1096 pr_err("Failed to restore queue (%d)\n", ret); 1097 else 1098 pr_debug("Queue id %d was restored successfully\n", queue_id); 1099 1100 kfree(q_data); 1101 kfree(q_extra_data); 1102 1103 return ret; 1104 } 1105 1106 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1107 unsigned int qid, 1108 uint32_t *mqd_size, 1109 uint32_t *ctl_stack_size) 1110 { 1111 struct process_queue_node *pqn; 1112 int ret; 1113 1114 pqn = get_queue_by_qid(pqm, qid); 1115 if (!pqn) { 1116 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1117 return -EFAULT; 1118 } 1119 1120 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1121 pr_err("amdkfd: queue dumping not supported on this device\n"); 1122 return -EOPNOTSUPP; 1123 } 1124 1125 ret = pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1126 pqn->q, mqd_size, 1127 ctl_stack_size); 1128 if (ret) { 1129 pr_debug("amdkfd: Overflow while computing stack size for queue %d\n", qid); 1130 return ret; 1131 } 1132 1133 return 0; 1134 } 1135 1136 #if defined(CONFIG_DEBUG_FS) 1137 1138 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1139 { 1140 struct process_queue_manager *pqm = data; 1141 struct process_queue_node *pqn; 1142 struct queue *q; 1143 enum KFD_MQD_TYPE mqd_type; 1144 struct mqd_manager *mqd_mgr; 1145 int r = 0, xcc, num_xccs = 1; 1146 void *mqd; 1147 uint64_t size = 0; 1148 1149 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1150 if (pqn->q) { 1151 q = pqn->q; 1152 switch (q->properties.type) { 1153 case KFD_QUEUE_TYPE_SDMA: 1154 case KFD_QUEUE_TYPE_SDMA_XGMI: 1155 seq_printf(m, " SDMA queue on device %x\n", 1156 q->device->id); 1157 mqd_type = KFD_MQD_TYPE_SDMA; 1158 break; 1159 case KFD_QUEUE_TYPE_COMPUTE: 1160 seq_printf(m, " Compute queue on device %x\n", 1161 q->device->id); 1162 mqd_type = KFD_MQD_TYPE_CP; 1163 num_xccs = NUM_XCC(q->device->xcc_mask); 1164 break; 1165 default: 1166 seq_printf(m, 1167 " Queue node with bad user queue type %d on device %x\n", 1168 q->properties.type, q->device->id); 1169 continue; 1170 } 1171 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1172 size = mqd_mgr->mqd_stride(mqd_mgr, 1173 &q->properties); 1174 1175 for (xcc = 0; xcc < num_xccs; xcc++) { 1176 mqd = q->mqd + size * xcc; 1177 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1178 if (r != 0) 1179 break; 1180 } 1181 } 1182 } 1183 1184 return r; 1185 } 1186 1187 #endif 1188