1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pid %d\n", 73 pqm->process->lead_thread->pid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 /* The MES context flush needs to filter out the case which the 90 * KFD process is created without setting up the MES context and 91 * queue for creating a compute queue. 92 */ 93 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && 95 down_read_trylock(&dev->adev->reset_domain->sem)) { 96 amdgpu_mes_flush_shader_debugger(dev->adev, 97 pdd->proc_ctx_gpu_addr, 98 ffs(pdd->dev->xcc_mask) - 1); 99 up_read(&dev->adev->reset_domain->sem); 100 } 101 pdd->already_dequeued = true; 102 } 103 104 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 105 void *gws) 106 { 107 struct mqd_update_info minfo = {0}; 108 struct kfd_node *dev = NULL; 109 struct process_queue_node *pqn; 110 struct kfd_process_device *pdd; 111 struct kgd_mem *mem = NULL; 112 int ret; 113 114 pqn = get_queue_by_qid(pqm, qid); 115 if (!pqn) { 116 pr_err("Queue id does not match any known queue\n"); 117 return -EINVAL; 118 } 119 120 if (pqn->q) 121 dev = pqn->q->device; 122 if (WARN_ON(!dev)) 123 return -ENODEV; 124 125 pdd = kfd_get_process_device_data(dev, pqm->process); 126 if (!pdd) { 127 pr_err("Process device data doesn't exist\n"); 128 return -EINVAL; 129 } 130 131 /* Only allow one queue per process can have GWS assigned */ 132 if (gws && pdd->qpd.num_gws) 133 return -EBUSY; 134 135 if (!gws && pdd->qpd.num_gws == 0) 136 return -EINVAL; 137 138 if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 139 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 140 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && 141 !dev->kfd->shared_resources.enable_mes) { 142 if (gws) 143 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 144 gws, &mem); 145 else 146 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 147 pqn->q->gws); 148 if (unlikely(ret)) 149 return ret; 150 pqn->q->gws = mem; 151 } else { 152 /* 153 * Intentionally set GWS to a non-NULL value 154 * for devices that do not use GWS for global wave 155 * synchronization but require the formality 156 * of setting GWS for cooperative groups. 157 */ 158 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 159 } 160 161 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 162 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 163 164 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 165 pqn->q, &minfo); 166 } 167 168 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 169 { 170 int i; 171 172 for (i = 0; i < p->n_pdds; i++) 173 kfd_process_dequeue_from_device(p->pdds[i]); 174 } 175 176 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 177 { 178 INIT_LIST_HEAD(&pqm->queues); 179 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 180 GFP_KERNEL); 181 if (!pqm->queue_slot_bitmap) 182 return -ENOMEM; 183 pqm->process = p; 184 185 return 0; 186 } 187 188 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 189 struct process_queue_node *pqn) 190 { 191 struct kfd_node *dev; 192 struct kfd_process_device *pdd; 193 194 dev = pqn->q->device; 195 196 pdd = kfd_get_process_device_data(dev, pqm->process); 197 if (!pdd) { 198 pr_err("Process device data doesn't exist\n"); 199 return; 200 } 201 202 if (pqn->q->gws) { 203 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 204 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 205 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && 206 !dev->kfd->shared_resources.enable_mes) 207 amdgpu_amdkfd_remove_gws_from_process( 208 pqm->process->kgd_process_info, pqn->q->gws); 209 pdd->qpd.num_gws = 0; 210 } 211 212 if (dev->kfd->shared_resources.enable_mes) { 213 amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); 214 amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 215 } 216 } 217 218 void pqm_uninit(struct process_queue_manager *pqm) 219 { 220 struct process_queue_node *pqn, *next; 221 222 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 223 if (pqn->q) { 224 struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, 225 pqm->process); 226 if (pdd) { 227 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 228 kfd_queue_release_buffers(pdd, &pqn->q->properties); 229 } else { 230 WARN_ON(!pdd); 231 } 232 pqm_clean_queue_resource(pqm, pqn); 233 } 234 235 kfd_procfs_del_queue(pqn->q); 236 uninit_queue(pqn->q); 237 list_del(&pqn->process_queue_list); 238 kfree(pqn); 239 } 240 241 bitmap_free(pqm->queue_slot_bitmap); 242 pqm->queue_slot_bitmap = NULL; 243 } 244 245 static int init_user_queue(struct process_queue_manager *pqm, 246 struct kfd_node *dev, struct queue **q, 247 struct queue_properties *q_properties, 248 unsigned int qid) 249 { 250 int retval; 251 252 /* Doorbell initialized in user space*/ 253 q_properties->doorbell_ptr = NULL; 254 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 255 256 /* let DQM handle it*/ 257 q_properties->vmid = 0; 258 q_properties->queue_id = qid; 259 260 retval = init_queue(q, q_properties); 261 if (retval != 0) 262 return retval; 263 264 (*q)->device = dev; 265 (*q)->process = pqm->process; 266 267 if (dev->kfd->shared_resources.enable_mes) { 268 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 269 AMDGPU_MES_GANG_CTX_SIZE, 270 &(*q)->gang_ctx_bo, 271 &(*q)->gang_ctx_gpu_addr, 272 &(*q)->gang_ctx_cpu_ptr, 273 false); 274 if (retval) { 275 pr_err("failed to allocate gang context bo\n"); 276 goto cleanup; 277 } 278 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 279 280 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 281 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 282 */ 283 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 284 pr_err("Queue memory allocated to wrong device\n"); 285 retval = -EINVAL; 286 goto free_gang_ctx_bo; 287 } 288 289 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 290 &(*q)->wptr_bo_gart); 291 if (retval) { 292 pr_err("Failed to map wptr bo to GART\n"); 293 goto free_gang_ctx_bo; 294 } 295 } 296 297 pr_debug("PQM After init queue"); 298 return 0; 299 300 free_gang_ctx_bo: 301 amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo); 302 cleanup: 303 uninit_queue(*q); 304 *q = NULL; 305 return retval; 306 } 307 308 int pqm_create_queue(struct process_queue_manager *pqm, 309 struct kfd_node *dev, 310 struct queue_properties *properties, 311 unsigned int *qid, 312 const struct kfd_criu_queue_priv_data *q_data, 313 const void *restore_mqd, 314 const void *restore_ctl_stack, 315 uint32_t *p_doorbell_offset_in_process) 316 { 317 int retval; 318 struct kfd_process_device *pdd; 319 struct queue *q; 320 struct process_queue_node *pqn; 321 struct kernel_queue *kq; 322 enum kfd_queue_type type = properties->type; 323 unsigned int max_queues = 127; /* HWS limit */ 324 325 /* 326 * On GFX 9.4.3/9.5.0, increase the number of queues that 327 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0. 328 */ 329 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 330 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 331 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) 332 max_queues = 255; 333 334 q = NULL; 335 kq = NULL; 336 337 pdd = kfd_get_process_device_data(dev, pqm->process); 338 if (!pdd) { 339 pr_err("Process device data doesn't exist\n"); 340 return -1; 341 } 342 343 /* 344 * for debug process, verify that it is within the static queues limit 345 * currently limit is set to half of the total avail HQD slots 346 * If we are just about to create DIQ, the is_debug flag is not set yet 347 * Hence we also check the type as well 348 */ 349 if (pdd->qpd.is_debug) 350 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 351 352 if (pdd->qpd.queue_count >= max_queues) 353 return -ENOSPC; 354 355 if (q_data) { 356 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 357 *qid = q_data->q_id; 358 } else 359 retval = find_available_queue_slot(pqm, qid); 360 361 if (retval != 0) 362 return retval; 363 364 /* Register process if this is the first queue */ 365 if (list_empty(&pdd->qpd.queues_list) && 366 list_empty(&pdd->qpd.priv_queue_list)) 367 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 368 369 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ 370 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { 371 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 372 AMDGPU_MES_PROC_CTX_SIZE, 373 &pdd->proc_ctx_bo, 374 &pdd->proc_ctx_gpu_addr, 375 &pdd->proc_ctx_cpu_ptr, 376 false); 377 if (retval) { 378 dev_err(dev->adev->dev, "failed to allocate process context bo\n"); 379 return retval; 380 } 381 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); 382 } 383 384 pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); 385 if (!pqn) { 386 retval = -ENOMEM; 387 goto err_allocate_pqn; 388 } 389 390 switch (type) { 391 case KFD_QUEUE_TYPE_SDMA: 392 case KFD_QUEUE_TYPE_SDMA_XGMI: 393 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 394 /* SDMA queues are always allocated statically no matter 395 * which scheduler mode is used. We also do not need to 396 * check whether a SDMA queue can be allocated here, because 397 * allocate_sdma_queue() in create_queue() has the 398 * corresponding check logic. 399 */ 400 retval = init_user_queue(pqm, dev, &q, properties, *qid); 401 if (retval != 0) 402 goto err_create_queue; 403 pqn->q = q; 404 pqn->kq = NULL; 405 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 406 restore_mqd, restore_ctl_stack); 407 print_queue(q); 408 break; 409 410 case KFD_QUEUE_TYPE_COMPUTE: 411 /* check if there is over subscription */ 412 if ((dev->dqm->sched_policy == 413 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 414 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 415 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 416 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 417 retval = -EPERM; 418 goto err_create_queue; 419 } 420 421 retval = init_user_queue(pqm, dev, &q, properties, *qid); 422 if (retval != 0) 423 goto err_create_queue; 424 pqn->q = q; 425 pqn->kq = NULL; 426 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 427 restore_mqd, restore_ctl_stack); 428 print_queue(q); 429 break; 430 default: 431 WARN(1, "Invalid queue type %d", type); 432 retval = -EINVAL; 433 } 434 435 if (retval != 0) { 436 if ((type == KFD_QUEUE_TYPE_SDMA || 437 type == KFD_QUEUE_TYPE_SDMA_XGMI || 438 type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && 439 retval == -ENOMEM) 440 pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", 441 pqm->process->lead_thread->pid, type, retval); 442 else 443 pr_err("process pid %d DQM create queue type %d failed. ret %d\n", 444 pqm->process->lead_thread->pid, type, retval); 445 goto err_create_queue; 446 } 447 448 if (q && p_doorbell_offset_in_process) { 449 /* Return the doorbell offset within the doorbell page 450 * to the caller so it can be passed up to user mode 451 * (in bytes). 452 * relative doorbell index = Absolute doorbell index - 453 * absolute index of first doorbell in the page. 454 */ 455 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 456 pdd->qpd.proc_doorbells, 457 0, 458 pdd->dev->kfd->device_info.doorbell_size); 459 460 *p_doorbell_offset_in_process = (q->properties.doorbell_off 461 - first_db_index) * sizeof(uint32_t); 462 } 463 464 pr_debug("PQM After DQM create queue\n"); 465 466 list_add(&pqn->process_queue_list, &pqm->queues); 467 468 if (q) { 469 pr_debug("PQM done creating queue\n"); 470 kfd_procfs_add_queue(q); 471 print_queue_properties(&q->properties); 472 } 473 474 return retval; 475 476 err_create_queue: 477 uninit_queue(q); 478 if (kq) 479 kernel_queue_uninit(kq); 480 kfree(pqn); 481 err_allocate_pqn: 482 /* check if queues list is empty unregister process from device */ 483 clear_bit(*qid, pqm->queue_slot_bitmap); 484 if (list_empty(&pdd->qpd.queues_list) && 485 list_empty(&pdd->qpd.priv_queue_list)) 486 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 487 return retval; 488 } 489 490 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 491 { 492 struct process_queue_node *pqn; 493 struct kfd_process_device *pdd; 494 struct device_queue_manager *dqm; 495 struct kfd_node *dev; 496 int retval; 497 498 dqm = NULL; 499 500 retval = 0; 501 502 pqn = get_queue_by_qid(pqm, qid); 503 if (!pqn) { 504 pr_err("Queue id does not match any known queue\n"); 505 return -EINVAL; 506 } 507 508 dev = NULL; 509 if (pqn->kq) 510 dev = pqn->kq->dev; 511 if (pqn->q) 512 dev = pqn->q->device; 513 if (WARN_ON(!dev)) 514 return -ENODEV; 515 516 pdd = kfd_get_process_device_data(dev, pqm->process); 517 if (!pdd) { 518 pr_err("Process device data doesn't exist\n"); 519 return -1; 520 } 521 522 if (pqn->kq) { 523 /* destroy kernel queue (DIQ) */ 524 dqm = pqn->kq->dev->dqm; 525 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 526 kernel_queue_uninit(pqn->kq); 527 } 528 529 if (pqn->q) { 530 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 531 if (retval) 532 goto err_destroy_queue; 533 534 dqm = pqn->q->device->dqm; 535 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 536 if (retval) { 537 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 538 pdd->pasid, 539 pqn->q->properties.queue_id, retval); 540 if (retval != -ETIME && retval != -EIO) 541 goto err_destroy_queue; 542 } 543 kfd_procfs_del_queue(pqn->q); 544 kfd_queue_release_buffers(pdd, &pqn->q->properties); 545 pqm_clean_queue_resource(pqm, pqn); 546 uninit_queue(pqn->q); 547 } 548 549 list_del(&pqn->process_queue_list); 550 kfree(pqn); 551 clear_bit(qid, pqm->queue_slot_bitmap); 552 553 if (list_empty(&pdd->qpd.queues_list) && 554 list_empty(&pdd->qpd.priv_queue_list)) 555 dqm->ops.unregister_process(dqm, &pdd->qpd); 556 557 err_destroy_queue: 558 return retval; 559 } 560 561 int pqm_update_queue_properties(struct process_queue_manager *pqm, 562 unsigned int qid, struct queue_properties *p) 563 { 564 int retval; 565 struct process_queue_node *pqn; 566 567 pqn = get_queue_by_qid(pqm, qid); 568 if (!pqn || !pqn->q) { 569 pr_debug("No queue %d exists for update operation\n", qid); 570 return -EFAULT; 571 } 572 573 /* 574 * Update with NULL ring address is used to disable the queue 575 */ 576 if (p->queue_address && p->queue_size) { 577 struct kfd_process_device *pdd; 578 struct amdgpu_vm *vm; 579 struct queue *q = pqn->q; 580 int err; 581 582 pdd = kfd_get_process_device_data(q->device, q->process); 583 if (!pdd) 584 return -ENODEV; 585 vm = drm_priv_to_vm(pdd->drm_priv); 586 err = amdgpu_bo_reserve(vm->root.bo, false); 587 if (err) 588 return err; 589 590 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 591 p->queue_size)) { 592 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 593 p->queue_address, p->queue_size); 594 return -EFAULT; 595 } 596 597 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo); 598 kfd_queue_buffer_put(&pqn->q->properties.ring_bo); 599 amdgpu_bo_unreserve(vm->root.bo); 600 601 pqn->q->properties.ring_bo = p->ring_bo; 602 } 603 604 pqn->q->properties.queue_address = p->queue_address; 605 pqn->q->properties.queue_size = p->queue_size; 606 pqn->q->properties.queue_percent = p->queue_percent; 607 pqn->q->properties.priority = p->priority; 608 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 609 610 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 611 pqn->q, NULL); 612 if (retval != 0) 613 return retval; 614 615 return 0; 616 } 617 618 int pqm_update_mqd(struct process_queue_manager *pqm, 619 unsigned int qid, struct mqd_update_info *minfo) 620 { 621 int retval; 622 struct process_queue_node *pqn; 623 624 pqn = get_queue_by_qid(pqm, qid); 625 if (!pqn) { 626 pr_debug("No queue %d exists for update operation\n", qid); 627 return -EFAULT; 628 } 629 630 /* CUs are masked for debugger requirements so deny user mask */ 631 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 632 return -EBUSY; 633 634 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 635 if (minfo && minfo->cu_mask.ptr && 636 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { 637 int i; 638 639 for (i = 0; i < minfo->cu_mask.count; i += 2) { 640 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 641 642 if (cu_pair && cu_pair != 0x3) { 643 pr_debug("CUs must be adjacent pairwise enabled.\n"); 644 return -EINVAL; 645 } 646 } 647 } 648 649 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 650 pqn->q, minfo); 651 if (retval != 0) 652 return retval; 653 654 if (minfo && minfo->cu_mask.ptr) 655 pqn->q->properties.is_user_cu_masked = true; 656 657 return 0; 658 } 659 660 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 661 unsigned int qid) 662 { 663 struct process_queue_node *pqn; 664 665 pqn = get_queue_by_qid(pqm, qid); 666 return pqn ? pqn->q : NULL; 667 } 668 669 int pqm_get_wave_state(struct process_queue_manager *pqm, 670 unsigned int qid, 671 void __user *ctl_stack, 672 u32 *ctl_stack_used_size, 673 u32 *save_area_used_size) 674 { 675 struct process_queue_node *pqn; 676 677 pqn = get_queue_by_qid(pqm, qid); 678 if (!pqn) { 679 pr_debug("amdkfd: No queue %d exists for operation\n", 680 qid); 681 return -EFAULT; 682 } 683 684 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 685 pqn->q, 686 ctl_stack, 687 ctl_stack_used_size, 688 save_area_used_size); 689 } 690 691 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 692 uint64_t exception_clear_mask, 693 void __user *buf, 694 int *num_qss_entries, 695 uint32_t *entry_size) 696 { 697 struct process_queue_node *pqn; 698 struct kfd_queue_snapshot_entry src; 699 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 700 int r = 0; 701 702 *num_qss_entries = 0; 703 if (!(*entry_size)) 704 return -EINVAL; 705 706 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 707 mutex_lock(&pqm->process->event_mutex); 708 709 memset(&src, 0, sizeof(src)); 710 711 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 712 if (!pqn->q) 713 continue; 714 715 if (*num_qss_entries < tmp_qss_entries) { 716 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 717 718 if (copy_to_user(buf, &src, *entry_size)) { 719 r = -EFAULT; 720 break; 721 } 722 buf += tmp_entry_size; 723 } 724 *num_qss_entries += 1; 725 } 726 727 mutex_unlock(&pqm->process->event_mutex); 728 return r; 729 } 730 731 static int get_queue_data_sizes(struct kfd_process_device *pdd, 732 struct queue *q, 733 uint32_t *mqd_size, 734 uint32_t *ctl_stack_size) 735 { 736 int ret; 737 738 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 739 q->properties.queue_id, 740 mqd_size, 741 ctl_stack_size); 742 if (ret) 743 pr_err("Failed to get queue dump info (%d)\n", ret); 744 745 return ret; 746 } 747 748 int kfd_process_get_queue_info(struct kfd_process *p, 749 uint32_t *num_queues, 750 uint64_t *priv_data_sizes) 751 { 752 uint32_t extra_data_sizes = 0; 753 struct queue *q; 754 int i; 755 int ret; 756 757 *num_queues = 0; 758 759 /* Run over all PDDs of the process */ 760 for (i = 0; i < p->n_pdds; i++) { 761 struct kfd_process_device *pdd = p->pdds[i]; 762 763 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 764 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 765 q->properties.type == KFD_QUEUE_TYPE_SDMA || 766 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 767 uint32_t mqd_size, ctl_stack_size; 768 769 *num_queues = *num_queues + 1; 770 771 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 772 if (ret) 773 return ret; 774 775 extra_data_sizes += mqd_size + ctl_stack_size; 776 } else { 777 pr_err("Unsupported queue type (%d)\n", q->properties.type); 778 return -EOPNOTSUPP; 779 } 780 } 781 } 782 *priv_data_sizes = extra_data_sizes + 783 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 784 785 return 0; 786 } 787 788 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 789 unsigned int qid, 790 void *mqd, 791 void *ctl_stack) 792 { 793 struct process_queue_node *pqn; 794 795 pqn = get_queue_by_qid(pqm, qid); 796 if (!pqn) { 797 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 798 return -EFAULT; 799 } 800 801 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 802 pr_err("amdkfd: queue dumping not supported on this device\n"); 803 return -EOPNOTSUPP; 804 } 805 806 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 807 pqn->q, mqd, ctl_stack); 808 } 809 810 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 811 struct queue *q, 812 struct kfd_criu_queue_priv_data *q_data) 813 { 814 uint8_t *mqd, *ctl_stack; 815 int ret; 816 817 mqd = (void *)(q_data + 1); 818 ctl_stack = mqd + q_data->mqd_size; 819 820 q_data->gpu_id = pdd->user_gpu_id; 821 q_data->type = q->properties.type; 822 q_data->format = q->properties.format; 823 q_data->q_id = q->properties.queue_id; 824 q_data->q_address = q->properties.queue_address; 825 q_data->q_size = q->properties.queue_size; 826 q_data->priority = q->properties.priority; 827 q_data->q_percent = q->properties.queue_percent; 828 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 829 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 830 q_data->doorbell_id = q->doorbell_id; 831 832 q_data->sdma_id = q->sdma_id; 833 834 q_data->eop_ring_buffer_address = 835 q->properties.eop_ring_buffer_address; 836 837 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 838 839 q_data->ctx_save_restore_area_address = 840 q->properties.ctx_save_restore_area_address; 841 842 q_data->ctx_save_restore_area_size = 843 q->properties.ctx_save_restore_area_size; 844 845 q_data->gws = !!q->gws; 846 847 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 848 if (ret) { 849 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 850 return ret; 851 } 852 853 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 854 return ret; 855 } 856 857 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 858 uint8_t __user *user_priv, 859 unsigned int *q_index, 860 uint64_t *queues_priv_data_offset) 861 { 862 unsigned int q_private_data_size = 0; 863 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 864 struct queue *q; 865 int ret = 0; 866 867 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 868 struct kfd_criu_queue_priv_data *q_data; 869 uint64_t q_data_size; 870 uint32_t mqd_size; 871 uint32_t ctl_stack_size; 872 873 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 874 q->properties.type != KFD_QUEUE_TYPE_SDMA && 875 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 876 877 pr_err("Unsupported queue type (%d)\n", q->properties.type); 878 ret = -EOPNOTSUPP; 879 break; 880 } 881 882 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 883 if (ret) 884 break; 885 886 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 887 888 /* Increase local buffer space if needed */ 889 if (q_private_data_size < q_data_size) { 890 kfree(q_private_data); 891 892 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 893 if (!q_private_data) { 894 ret = -ENOMEM; 895 break; 896 } 897 q_private_data_size = q_data_size; 898 } 899 900 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 901 902 /* 903 * data stored in this order: 904 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 905 */ 906 q_data->mqd_size = mqd_size; 907 q_data->ctl_stack_size = ctl_stack_size; 908 909 ret = criu_checkpoint_queue(pdd, q, q_data); 910 if (ret) 911 break; 912 913 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 914 915 ret = copy_to_user(user_priv + *queues_priv_data_offset, 916 q_data, q_data_size); 917 if (ret) { 918 ret = -EFAULT; 919 break; 920 } 921 *queues_priv_data_offset += q_data_size; 922 *q_index = *q_index + 1; 923 } 924 925 kfree(q_private_data); 926 927 return ret; 928 } 929 930 int kfd_criu_checkpoint_queues(struct kfd_process *p, 931 uint8_t __user *user_priv_data, 932 uint64_t *priv_data_offset) 933 { 934 int ret = 0, pdd_index, q_index = 0; 935 936 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 937 struct kfd_process_device *pdd = p->pdds[pdd_index]; 938 939 /* 940 * criu_checkpoint_queues_device will copy data to user and update q_index and 941 * queues_priv_data_offset 942 */ 943 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 944 priv_data_offset); 945 946 if (ret) 947 break; 948 } 949 950 return ret; 951 } 952 953 static void set_queue_properties_from_criu(struct queue_properties *qp, 954 struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc) 955 { 956 qp->is_interop = false; 957 qp->queue_percent = q_data->q_percent; 958 qp->priority = q_data->priority; 959 qp->queue_address = q_data->q_address; 960 qp->queue_size = q_data->q_size; 961 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr; 962 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr; 963 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 964 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 965 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 966 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 967 if (q_data->type == KFD_QUEUE_TYPE_COMPUTE) 968 qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc; 969 else 970 qp->ctl_stack_size = q_data->ctl_stack_size; 971 972 qp->type = q_data->type; 973 qp->format = q_data->format; 974 } 975 976 int kfd_criu_restore_queue(struct kfd_process *p, 977 uint8_t __user *user_priv_ptr, 978 uint64_t *priv_data_offset, 979 uint64_t max_priv_data_size) 980 { 981 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 982 struct kfd_criu_queue_priv_data *q_data; 983 struct kfd_process_device *pdd; 984 uint64_t q_extra_data_size; 985 struct queue_properties qp; 986 unsigned int queue_id; 987 int ret = 0; 988 989 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 990 return -EINVAL; 991 992 q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); 993 if (!q_data) 994 return -ENOMEM; 995 996 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 997 if (ret) { 998 ret = -EFAULT; 999 goto exit; 1000 } 1001 1002 *priv_data_offset += sizeof(*q_data); 1003 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 1004 1005 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 1006 ret = -EINVAL; 1007 goto exit; 1008 } 1009 1010 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1011 if (!q_extra_data) { 1012 ret = -ENOMEM; 1013 goto exit; 1014 } 1015 1016 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1017 if (ret) { 1018 ret = -EFAULT; 1019 goto exit; 1020 } 1021 1022 *priv_data_offset += q_extra_data_size; 1023 1024 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1025 if (!pdd) { 1026 pr_err("Failed to get pdd\n"); 1027 ret = -EINVAL; 1028 goto exit; 1029 } 1030 1031 /* 1032 * data stored in this order: 1033 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 1034 */ 1035 mqd = q_extra_data; 1036 ctl_stack = mqd + q_data->mqd_size; 1037 1038 memset(&qp, 0, sizeof(qp)); 1039 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask)); 1040 1041 print_queue_properties(&qp); 1042 1043 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); 1044 if (ret) { 1045 pr_err("Failed to create new queue err:%d\n", ret); 1046 goto exit; 1047 } 1048 1049 if (q_data->gws) 1050 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1051 1052 exit: 1053 if (ret) 1054 pr_err("Failed to restore queue (%d)\n", ret); 1055 else 1056 pr_debug("Queue id %d was restored successfully\n", queue_id); 1057 1058 kfree(q_data); 1059 kfree(q_extra_data); 1060 1061 return ret; 1062 } 1063 1064 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1065 unsigned int qid, 1066 uint32_t *mqd_size, 1067 uint32_t *ctl_stack_size) 1068 { 1069 struct process_queue_node *pqn; 1070 1071 pqn = get_queue_by_qid(pqm, qid); 1072 if (!pqn) { 1073 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1074 return -EFAULT; 1075 } 1076 1077 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1078 pr_err("amdkfd: queue dumping not supported on this device\n"); 1079 return -EOPNOTSUPP; 1080 } 1081 1082 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1083 pqn->q, mqd_size, 1084 ctl_stack_size); 1085 return 0; 1086 } 1087 1088 #if defined(CONFIG_DEBUG_FS) 1089 1090 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1091 { 1092 struct process_queue_manager *pqm = data; 1093 struct process_queue_node *pqn; 1094 struct queue *q; 1095 enum KFD_MQD_TYPE mqd_type; 1096 struct mqd_manager *mqd_mgr; 1097 int r = 0, xcc, num_xccs = 1; 1098 void *mqd; 1099 uint64_t size = 0; 1100 1101 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1102 if (pqn->q) { 1103 q = pqn->q; 1104 switch (q->properties.type) { 1105 case KFD_QUEUE_TYPE_SDMA: 1106 case KFD_QUEUE_TYPE_SDMA_XGMI: 1107 seq_printf(m, " SDMA queue on device %x\n", 1108 q->device->id); 1109 mqd_type = KFD_MQD_TYPE_SDMA; 1110 break; 1111 case KFD_QUEUE_TYPE_COMPUTE: 1112 seq_printf(m, " Compute queue on device %x\n", 1113 q->device->id); 1114 mqd_type = KFD_MQD_TYPE_CP; 1115 num_xccs = NUM_XCC(q->device->xcc_mask); 1116 break; 1117 default: 1118 seq_printf(m, 1119 " Queue node with bad user queue type %d on device %x\n", 1120 q->properties.type, q->device->id); 1121 continue; 1122 } 1123 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1124 size = mqd_mgr->mqd_stride(mqd_mgr, 1125 &q->properties); 1126 } 1127 1128 for (xcc = 0; xcc < num_xccs; xcc++) { 1129 mqd = q->mqd + size * xcc; 1130 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1131 if (r != 0) 1132 break; 1133 } 1134 } 1135 1136 return r; 1137 } 1138 1139 #endif 1140