1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pid %d\n", 73 pqm->process->lead_thread->pid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 /* The MES context flush needs to filter out the case which the 90 * KFD process is created without setting up the MES context and 91 * queue for creating a compute queue. 92 */ 93 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && 95 down_read_trylock(&dev->adev->reset_domain->sem)) { 96 amdgpu_mes_flush_shader_debugger(dev->adev, 97 pdd->proc_ctx_gpu_addr, 98 ffs(pdd->dev->xcc_mask) - 1); 99 up_read(&dev->adev->reset_domain->sem); 100 } 101 pdd->already_dequeued = true; 102 } 103 104 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 105 void *gws) 106 { 107 struct mqd_update_info minfo = {0}; 108 struct kfd_node *dev = NULL; 109 struct process_queue_node *pqn; 110 struct kfd_process_device *pdd; 111 struct kgd_mem *mem = NULL; 112 int ret; 113 114 pqn = get_queue_by_qid(pqm, qid); 115 if (!pqn) { 116 pr_err("Queue id does not match any known queue\n"); 117 return -EINVAL; 118 } 119 120 if (pqn->q) 121 dev = pqn->q->device; 122 if (WARN_ON(!dev)) 123 return -ENODEV; 124 125 pdd = kfd_get_process_device_data(dev, pqm->process); 126 if (!pdd) { 127 pr_err("Process device data doesn't exist\n"); 128 return -EINVAL; 129 } 130 131 /* Only allow one queue per process can have GWS assigned */ 132 if (gws && pdd->qpd.num_gws) 133 return -EBUSY; 134 135 if (!gws && pdd->qpd.num_gws == 0) 136 return -EINVAL; 137 138 if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 139 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 140 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && 141 !dev->kfd->shared_resources.enable_mes) { 142 if (gws) 143 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 144 gws, &mem); 145 else 146 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 147 pqn->q->gws); 148 if (unlikely(ret)) 149 return ret; 150 pqn->q->gws = mem; 151 } else { 152 /* 153 * Intentionally set GWS to a non-NULL value 154 * for devices that do not use GWS for global wave 155 * synchronization but require the formality 156 * of setting GWS for cooperative groups. 157 */ 158 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 159 } 160 161 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 162 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 163 164 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 165 pqn->q, &minfo); 166 } 167 168 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 169 { 170 int i; 171 172 for (i = 0; i < p->n_pdds; i++) 173 kfd_process_dequeue_from_device(p->pdds[i]); 174 } 175 176 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 177 { 178 INIT_LIST_HEAD(&pqm->queues); 179 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 180 GFP_KERNEL); 181 if (!pqm->queue_slot_bitmap) 182 return -ENOMEM; 183 pqm->process = p; 184 185 return 0; 186 } 187 188 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 189 struct process_queue_node *pqn) 190 { 191 struct kfd_node *dev; 192 struct kfd_process_device *pdd; 193 194 dev = pqn->q->device; 195 196 pdd = kfd_get_process_device_data(dev, pqm->process); 197 if (!pdd) { 198 pr_err("Process device data doesn't exist\n"); 199 return; 200 } 201 202 if (pqn->q->gws) { 203 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 204 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 205 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && 206 !dev->kfd->shared_resources.enable_mes) 207 amdgpu_amdkfd_remove_gws_from_process( 208 pqm->process->kgd_process_info, pqn->q->gws); 209 pdd->qpd.num_gws = 0; 210 } 211 212 if (dev->kfd->shared_resources.enable_mes) { 213 amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo); 214 amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 215 } 216 } 217 218 void pqm_uninit(struct process_queue_manager *pqm) 219 { 220 struct process_queue_node *pqn, *next; 221 222 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 223 if (pqn->q) { 224 struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, 225 pqm->process); 226 if (pdd) { 227 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 228 kfd_queue_release_buffers(pdd, &pqn->q->properties); 229 } else { 230 WARN_ON(!pdd); 231 } 232 pqm_clean_queue_resource(pqm, pqn); 233 } 234 235 kfd_procfs_del_queue(pqn->q); 236 uninit_queue(pqn->q); 237 list_del(&pqn->process_queue_list); 238 kfree(pqn); 239 } 240 241 bitmap_free(pqm->queue_slot_bitmap); 242 pqm->queue_slot_bitmap = NULL; 243 } 244 245 static int init_user_queue(struct process_queue_manager *pqm, 246 struct kfd_node *dev, struct queue **q, 247 struct queue_properties *q_properties, 248 unsigned int qid) 249 { 250 int retval; 251 252 /* Doorbell initialized in user space*/ 253 q_properties->doorbell_ptr = NULL; 254 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 255 256 /* let DQM handle it*/ 257 q_properties->vmid = 0; 258 q_properties->queue_id = qid; 259 260 retval = init_queue(q, q_properties); 261 if (retval != 0) 262 return retval; 263 264 (*q)->device = dev; 265 (*q)->process = pqm->process; 266 267 if (dev->kfd->shared_resources.enable_mes) { 268 if (!q_properties->wptr_bo) { 269 pr_debug("Queue initialization with shared MES requires queue buffers to be initialized\n"); 270 return -EINVAL; 271 } 272 273 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, 274 AMDGPU_MES_GANG_CTX_SIZE, 275 AMDGPU_GEM_DOMAIN_GTT, 276 &(*q)->gang_ctx_bo, 277 &(*q)->gang_ctx_gpu_addr, 278 &(*q)->gang_ctx_cpu_ptr, 279 false); 280 if (retval) { 281 pr_err("failed to allocate gang context bo\n"); 282 goto cleanup; 283 } 284 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 285 286 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 287 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 288 */ 289 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 290 pr_err("Queue memory allocated to wrong device\n"); 291 retval = -EINVAL; 292 goto free_gang_ctx_bo; 293 } 294 295 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 296 &(*q)->wptr_bo_gart); 297 if (retval) { 298 pr_err("Failed to map wptr bo to GART\n"); 299 goto free_gang_ctx_bo; 300 } 301 } 302 303 pr_debug("PQM After init queue"); 304 return 0; 305 306 free_gang_ctx_bo: 307 amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo); 308 cleanup: 309 uninit_queue(*q); 310 *q = NULL; 311 return retval; 312 } 313 314 int pqm_create_queue(struct process_queue_manager *pqm, 315 struct kfd_node *dev, 316 struct queue_properties *properties, 317 unsigned int *qid, 318 const struct kfd_criu_queue_priv_data *q_data, 319 const void *restore_mqd, 320 const void *restore_ctl_stack, 321 uint32_t *p_doorbell_offset_in_process) 322 { 323 int retval; 324 struct kfd_process_device *pdd; 325 struct queue *q; 326 struct process_queue_node *pqn; 327 struct kernel_queue *kq; 328 enum kfd_queue_type type = properties->type; 329 unsigned int max_queues = 127; /* HWS limit */ 330 331 /* 332 * On GFX 9.4.3/9.5.0, increase the number of queues that 333 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0. 334 */ 335 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 336 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 337 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) 338 max_queues = 255; 339 340 q = NULL; 341 kq = NULL; 342 343 pdd = kfd_get_process_device_data(dev, pqm->process); 344 if (!pdd) { 345 pr_err("Process device data doesn't exist\n"); 346 return -1; 347 } 348 349 /* 350 * for debug process, verify that it is within the static queues limit 351 * currently limit is set to half of the total avail HQD slots 352 * If we are just about to create DIQ, the is_debug flag is not set yet 353 * Hence we also check the type as well 354 */ 355 if (pdd->qpd.is_debug) 356 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 357 358 if (pdd->qpd.queue_count >= max_queues) 359 return -ENOSPC; 360 361 if (q_data) { 362 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 363 *qid = q_data->q_id; 364 } else 365 retval = find_available_queue_slot(pqm, qid); 366 367 if (retval != 0) 368 return retval; 369 370 /* Register process if this is the first queue */ 371 if (list_empty(&pdd->qpd.queues_list) && 372 list_empty(&pdd->qpd.priv_queue_list)) 373 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 374 375 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ 376 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { 377 retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, 378 AMDGPU_MES_PROC_CTX_SIZE, 379 AMDGPU_GEM_DOMAIN_GTT, 380 &pdd->proc_ctx_bo, 381 &pdd->proc_ctx_gpu_addr, 382 &pdd->proc_ctx_cpu_ptr, 383 false); 384 if (retval) { 385 dev_err(dev->adev->dev, "failed to allocate process context bo\n"); 386 goto err_allocate_pqn; 387 } 388 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); 389 } 390 391 pqn = kzalloc_obj(*pqn); 392 if (!pqn) { 393 retval = -ENOMEM; 394 goto err_allocate_pqn; 395 } 396 397 switch (type) { 398 case KFD_QUEUE_TYPE_SDMA: 399 case KFD_QUEUE_TYPE_SDMA_XGMI: 400 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 401 /* SDMA queues are always allocated statically no matter 402 * which scheduler mode is used. We also do not need to 403 * check whether a SDMA queue can be allocated here, because 404 * allocate_sdma_queue() in create_queue() has the 405 * corresponding check logic. 406 */ 407 retval = init_user_queue(pqm, dev, &q, properties, *qid); 408 if (retval != 0) 409 goto err_create_queue; 410 pqn->q = q; 411 pqn->kq = NULL; 412 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 413 restore_mqd, restore_ctl_stack); 414 print_queue(q); 415 break; 416 417 case KFD_QUEUE_TYPE_COMPUTE: 418 /* check if there is over subscription */ 419 if ((dev->dqm->sched_policy == 420 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 421 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 422 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 423 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 424 retval = -EPERM; 425 goto err_create_queue; 426 } 427 428 retval = init_user_queue(pqm, dev, &q, properties, *qid); 429 if (retval != 0) 430 goto err_create_queue; 431 pqn->q = q; 432 pqn->kq = NULL; 433 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 434 restore_mqd, restore_ctl_stack); 435 print_queue(q); 436 break; 437 default: 438 WARN(1, "Invalid queue type %d", type); 439 retval = -EINVAL; 440 } 441 442 if (retval != 0) { 443 if ((type == KFD_QUEUE_TYPE_SDMA || 444 type == KFD_QUEUE_TYPE_SDMA_XGMI || 445 type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && 446 retval == -ENOMEM) 447 pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", 448 pqm->process->lead_thread->pid, type, retval); 449 else 450 pr_err("process pid %d DQM create queue type %d failed. ret %d\n", 451 pqm->process->lead_thread->pid, type, retval); 452 goto err_create_queue; 453 } 454 455 if (q && p_doorbell_offset_in_process) { 456 /* Return the doorbell offset within the doorbell page 457 * to the caller so it can be passed up to user mode 458 * (in bytes). 459 * relative doorbell index = Absolute doorbell index - 460 * absolute index of first doorbell in the page. 461 */ 462 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 463 pdd->qpd.proc_doorbells, 464 0, 465 pdd->dev->kfd->device_info.doorbell_size); 466 467 *p_doorbell_offset_in_process = (q->properties.doorbell_off 468 - first_db_index) * sizeof(uint32_t); 469 } 470 471 pr_debug("PQM After DQM create queue\n"); 472 473 list_add(&pqn->process_queue_list, &pqm->queues); 474 475 if (q) { 476 pr_debug("PQM done creating queue\n"); 477 kfd_procfs_add_queue(q); 478 print_queue_properties(&q->properties); 479 } 480 481 return retval; 482 483 err_create_queue: 484 uninit_queue(q); 485 if (kq) 486 kernel_queue_uninit(kq); 487 kfree(pqn); 488 err_allocate_pqn: 489 /* check if queues list is empty unregister process from device */ 490 clear_bit(*qid, pqm->queue_slot_bitmap); 491 if (list_empty(&pdd->qpd.queues_list) && 492 list_empty(&pdd->qpd.priv_queue_list)) 493 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 494 return retval; 495 } 496 497 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 498 { 499 struct process_queue_node *pqn; 500 struct kfd_process_device *pdd; 501 struct device_queue_manager *dqm; 502 struct kfd_node *dev; 503 int retval; 504 505 dqm = NULL; 506 507 retval = 0; 508 509 pqn = get_queue_by_qid(pqm, qid); 510 if (!pqn) { 511 pr_err("Queue id does not match any known queue\n"); 512 return -EINVAL; 513 } 514 515 dev = NULL; 516 if (pqn->kq) 517 dev = pqn->kq->dev; 518 if (pqn->q) 519 dev = pqn->q->device; 520 if (WARN_ON(!dev)) 521 return -ENODEV; 522 523 pdd = kfd_get_process_device_data(dev, pqm->process); 524 if (!pdd) { 525 pr_err("Process device data doesn't exist\n"); 526 return -1; 527 } 528 529 if (pqn->kq) { 530 /* destroy kernel queue (DIQ) */ 531 dqm = pqn->kq->dev->dqm; 532 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 533 kernel_queue_uninit(pqn->kq); 534 } 535 536 if (pqn->q) { 537 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 538 if (retval) 539 goto err_destroy_queue; 540 541 dqm = pqn->q->device->dqm; 542 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 543 if (retval) { 544 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 545 pdd->pasid, 546 pqn->q->properties.queue_id, retval); 547 if (retval != -ETIME && retval != -EIO) 548 goto err_destroy_queue; 549 } 550 kfd_procfs_del_queue(pqn->q); 551 kfd_queue_release_buffers(pdd, &pqn->q->properties); 552 pqm_clean_queue_resource(pqm, pqn); 553 uninit_queue(pqn->q); 554 } 555 556 list_del(&pqn->process_queue_list); 557 kfree(pqn); 558 clear_bit(qid, pqm->queue_slot_bitmap); 559 560 if (list_empty(&pdd->qpd.queues_list) && 561 list_empty(&pdd->qpd.priv_queue_list)) 562 dqm->ops.unregister_process(dqm, &pdd->qpd); 563 564 err_destroy_queue: 565 return retval; 566 } 567 568 int pqm_update_queue_properties(struct process_queue_manager *pqm, 569 unsigned int qid, struct queue_properties *p) 570 { 571 int retval; 572 struct process_queue_node *pqn; 573 574 pqn = get_queue_by_qid(pqm, qid); 575 if (!pqn || !pqn->q) { 576 pr_debug("No queue %d exists for update operation\n", qid); 577 return -EFAULT; 578 } 579 580 /* 581 * Update with NULL ring address is used to disable the queue 582 */ 583 if (p->queue_address && p->queue_size) { 584 struct kfd_process_device *pdd; 585 struct amdgpu_vm *vm; 586 struct queue *q = pqn->q; 587 int err; 588 589 pdd = kfd_get_process_device_data(q->device, q->process); 590 if (!pdd) 591 return -ENODEV; 592 vm = drm_priv_to_vm(pdd->drm_priv); 593 err = amdgpu_bo_reserve(vm->root.bo, false); 594 if (err) 595 return err; 596 597 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 598 p->queue_size + 599 pqn->q->properties.metadata_queue_size)) { 600 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 601 p->queue_address, p->queue_size); 602 amdgpu_bo_unreserve(vm->root.bo); 603 return -EFAULT; 604 } 605 606 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo); 607 kfd_queue_buffer_put(&pqn->q->properties.ring_bo); 608 amdgpu_bo_unreserve(vm->root.bo); 609 610 pqn->q->properties.ring_bo = p->ring_bo; 611 } 612 613 pqn->q->properties.queue_address = p->queue_address; 614 pqn->q->properties.queue_size = p->queue_size; 615 pqn->q->properties.queue_percent = p->queue_percent; 616 pqn->q->properties.priority = p->priority; 617 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 618 619 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 620 pqn->q, NULL); 621 if (retval != 0) 622 return retval; 623 624 return 0; 625 } 626 627 int pqm_update_mqd(struct process_queue_manager *pqm, 628 unsigned int qid, struct mqd_update_info *minfo) 629 { 630 int retval; 631 struct process_queue_node *pqn; 632 633 pqn = get_queue_by_qid(pqm, qid); 634 if (!pqn) { 635 pr_debug("No queue %d exists for update operation\n", qid); 636 return -EFAULT; 637 } 638 639 /* CUs are masked for debugger requirements so deny user mask */ 640 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 641 return -EBUSY; 642 643 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 644 if (minfo && minfo->cu_mask.ptr && 645 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { 646 int i; 647 648 for (i = 0; i < minfo->cu_mask.count; i += 2) { 649 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 650 651 if (cu_pair && cu_pair != 0x3) { 652 pr_debug("CUs must be adjacent pairwise enabled.\n"); 653 return -EINVAL; 654 } 655 } 656 } 657 658 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 659 pqn->q, minfo); 660 if (retval != 0) 661 return retval; 662 663 if (minfo && minfo->cu_mask.ptr) 664 pqn->q->properties.is_user_cu_masked = true; 665 666 return 0; 667 } 668 669 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 670 unsigned int qid) 671 { 672 struct process_queue_node *pqn; 673 674 pqn = get_queue_by_qid(pqm, qid); 675 return pqn ? pqn->q : NULL; 676 } 677 678 int pqm_get_wave_state(struct process_queue_manager *pqm, 679 unsigned int qid, 680 void __user *ctl_stack, 681 u32 *ctl_stack_used_size, 682 u32 *save_area_used_size) 683 { 684 struct process_queue_node *pqn; 685 686 pqn = get_queue_by_qid(pqm, qid); 687 if (!pqn) { 688 pr_debug("amdkfd: No queue %d exists for operation\n", 689 qid); 690 return -EFAULT; 691 } 692 693 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 694 pqn->q, 695 ctl_stack, 696 ctl_stack_used_size, 697 save_area_used_size); 698 } 699 700 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 701 uint64_t exception_clear_mask, 702 void __user *buf, 703 int *num_qss_entries, 704 uint32_t *entry_size) 705 { 706 struct process_queue_node *pqn; 707 struct kfd_queue_snapshot_entry src; 708 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 709 int r = 0; 710 711 *num_qss_entries = 0; 712 if (!(*entry_size)) 713 return -EINVAL; 714 715 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 716 mutex_lock(&pqm->process->event_mutex); 717 718 memset(&src, 0, sizeof(src)); 719 720 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 721 if (!pqn->q) 722 continue; 723 724 if (*num_qss_entries < tmp_qss_entries) { 725 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 726 727 if (copy_to_user(buf, &src, *entry_size)) { 728 r = -EFAULT; 729 break; 730 } 731 buf += tmp_entry_size; 732 } 733 *num_qss_entries += 1; 734 } 735 736 mutex_unlock(&pqm->process->event_mutex); 737 return r; 738 } 739 740 static int get_queue_data_sizes(struct kfd_process_device *pdd, 741 struct queue *q, 742 uint32_t *mqd_size, 743 uint32_t *ctl_stack_size) 744 { 745 int ret; 746 747 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 748 q->properties.queue_id, 749 mqd_size, 750 ctl_stack_size); 751 if (ret) 752 pr_err("Failed to get queue dump info (%d)\n", ret); 753 754 return ret; 755 } 756 757 int kfd_process_get_queue_info(struct kfd_process *p, 758 uint32_t *num_queues, 759 uint64_t *priv_data_sizes) 760 { 761 uint32_t extra_data_sizes = 0; 762 struct queue *q; 763 int i; 764 int ret; 765 766 *num_queues = 0; 767 768 /* Run over all PDDs of the process */ 769 for (i = 0; i < p->n_pdds; i++) { 770 struct kfd_process_device *pdd = p->pdds[i]; 771 772 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 773 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 774 q->properties.type == KFD_QUEUE_TYPE_SDMA || 775 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 776 uint32_t mqd_size, ctl_stack_size; 777 778 *num_queues = *num_queues + 1; 779 780 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 781 if (ret) 782 return ret; 783 784 extra_data_sizes += mqd_size + ctl_stack_size; 785 } else { 786 pr_err("Unsupported queue type (%d)\n", q->properties.type); 787 return -EOPNOTSUPP; 788 } 789 } 790 } 791 *priv_data_sizes = extra_data_sizes + 792 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 793 794 return 0; 795 } 796 797 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 798 unsigned int qid, 799 void *mqd, 800 void *ctl_stack) 801 { 802 struct process_queue_node *pqn; 803 804 pqn = get_queue_by_qid(pqm, qid); 805 if (!pqn) { 806 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 807 return -EFAULT; 808 } 809 810 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 811 pr_err("amdkfd: queue dumping not supported on this device\n"); 812 return -EOPNOTSUPP; 813 } 814 815 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 816 pqn->q, mqd, ctl_stack); 817 } 818 819 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 820 struct queue *q, 821 struct kfd_criu_queue_priv_data *q_data) 822 { 823 uint8_t *mqd, *ctl_stack; 824 int ret; 825 826 mqd = (void *)(q_data + 1); 827 ctl_stack = mqd + q_data->mqd_size; 828 829 q_data->gpu_id = pdd->user_gpu_id; 830 q_data->type = q->properties.type; 831 q_data->format = q->properties.format; 832 q_data->q_id = q->properties.queue_id; 833 q_data->q_address = q->properties.queue_address; 834 q_data->q_size = q->properties.queue_size; 835 q_data->priority = q->properties.priority; 836 q_data->q_percent = q->properties.queue_percent; 837 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 838 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 839 q_data->doorbell_id = q->doorbell_id; 840 841 q_data->sdma_id = q->sdma_id; 842 843 q_data->eop_ring_buffer_address = 844 q->properties.eop_ring_buffer_address; 845 846 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 847 848 q_data->ctx_save_restore_area_address = 849 q->properties.ctx_save_restore_area_address; 850 851 q_data->ctx_save_restore_area_size = 852 q->properties.ctx_save_restore_area_size; 853 854 q_data->gws = !!q->gws; 855 856 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 857 if (ret) { 858 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 859 return ret; 860 } 861 862 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 863 return ret; 864 } 865 866 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 867 uint8_t __user *user_priv, 868 unsigned int *q_index, 869 uint64_t *queues_priv_data_offset) 870 { 871 unsigned int q_private_data_size = 0; 872 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 873 struct queue *q; 874 int ret = 0; 875 876 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 877 struct kfd_criu_queue_priv_data *q_data; 878 uint64_t q_data_size; 879 uint32_t mqd_size; 880 uint32_t ctl_stack_size; 881 882 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 883 q->properties.type != KFD_QUEUE_TYPE_SDMA && 884 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 885 886 pr_err("Unsupported queue type (%d)\n", q->properties.type); 887 ret = -EOPNOTSUPP; 888 break; 889 } 890 891 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 892 if (ret) 893 break; 894 895 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 896 897 /* Increase local buffer space if needed */ 898 if (q_private_data_size < q_data_size) { 899 kfree(q_private_data); 900 901 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 902 if (!q_private_data) { 903 ret = -ENOMEM; 904 break; 905 } 906 q_private_data_size = q_data_size; 907 } 908 909 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 910 911 /* 912 * data stored in this order: 913 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 914 */ 915 q_data->mqd_size = mqd_size; 916 q_data->ctl_stack_size = ctl_stack_size; 917 918 ret = criu_checkpoint_queue(pdd, q, q_data); 919 if (ret) 920 break; 921 922 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 923 924 ret = copy_to_user(user_priv + *queues_priv_data_offset, 925 q_data, q_data_size); 926 if (ret) { 927 ret = -EFAULT; 928 break; 929 } 930 *queues_priv_data_offset += q_data_size; 931 *q_index = *q_index + 1; 932 } 933 934 kfree(q_private_data); 935 936 return ret; 937 } 938 939 int kfd_criu_checkpoint_queues(struct kfd_process *p, 940 uint8_t __user *user_priv_data, 941 uint64_t *priv_data_offset) 942 { 943 int ret = 0, pdd_index, q_index = 0; 944 945 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 946 struct kfd_process_device *pdd = p->pdds[pdd_index]; 947 948 /* 949 * criu_checkpoint_queues_device will copy data to user and update q_index and 950 * queues_priv_data_offset 951 */ 952 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 953 priv_data_offset); 954 955 if (ret) 956 break; 957 } 958 959 return ret; 960 } 961 962 static void set_queue_properties_from_criu(struct queue_properties *qp, 963 struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc) 964 { 965 qp->is_interop = false; 966 qp->queue_percent = q_data->q_percent; 967 qp->priority = q_data->priority; 968 qp->queue_address = q_data->q_address; 969 qp->queue_size = q_data->q_size; 970 qp->read_ptr = (void __user *)q_data->read_ptr_addr; 971 qp->write_ptr = (void __user *)q_data->write_ptr_addr; 972 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 973 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 974 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 975 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 976 if (q_data->type == KFD_QUEUE_TYPE_COMPUTE) 977 qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc; 978 else 979 qp->ctl_stack_size = q_data->ctl_stack_size; 980 981 qp->type = q_data->type; 982 qp->format = q_data->format; 983 } 984 985 int kfd_criu_restore_queue(struct kfd_process *p, 986 uint8_t __user *user_priv_ptr, 987 uint64_t *priv_data_offset, 988 uint64_t max_priv_data_size) 989 { 990 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 991 struct kfd_criu_queue_priv_data *q_data; 992 struct kfd_process_device *pdd; 993 uint64_t q_extra_data_size; 994 struct queue_properties qp; 995 unsigned int queue_id; 996 int ret = 0; 997 998 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 999 return -EINVAL; 1000 1001 q_data = kmalloc_obj(*q_data); 1002 if (!q_data) 1003 return -ENOMEM; 1004 1005 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 1006 if (ret) { 1007 ret = -EFAULT; 1008 goto exit; 1009 } 1010 1011 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1012 if (!pdd) { 1013 pr_err("Failed to get pdd\n"); 1014 ret = -EINVAL; 1015 goto exit; 1016 } 1017 1018 if (q_data->type >= KFD_QUEUE_TYPE_MAX) { 1019 ret = -EINVAL; 1020 goto exit; 1021 } 1022 1023 if (q_data->mqd_size != mqd_size_from_queue_type(pdd->dev->dqm, q_data->type)) { 1024 ret = -EINVAL; 1025 goto exit; 1026 } 1027 1028 *priv_data_offset += sizeof(*q_data); 1029 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 1030 1031 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 1032 ret = -EINVAL; 1033 goto exit; 1034 } 1035 1036 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1037 if (!q_extra_data) { 1038 ret = -ENOMEM; 1039 goto exit; 1040 } 1041 1042 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1043 if (ret) { 1044 ret = -EFAULT; 1045 goto exit; 1046 } 1047 1048 *priv_data_offset += q_extra_data_size; 1049 1050 /* 1051 * data stored in this order: 1052 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 1053 */ 1054 mqd = q_extra_data; 1055 ctl_stack = mqd + q_data->mqd_size; 1056 1057 memset(&qp, 0, sizeof(qp)); 1058 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask)); 1059 1060 print_queue_properties(&qp); 1061 1062 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); 1063 if (ret) { 1064 pr_err("Failed to create new queue err:%d\n", ret); 1065 goto exit; 1066 } 1067 1068 if (q_data->gws) 1069 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1070 1071 exit: 1072 if (ret) 1073 pr_err("Failed to restore queue (%d)\n", ret); 1074 else 1075 pr_debug("Queue id %d was restored successfully\n", queue_id); 1076 1077 kfree(q_data); 1078 kfree(q_extra_data); 1079 1080 return ret; 1081 } 1082 1083 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1084 unsigned int qid, 1085 uint32_t *mqd_size, 1086 uint32_t *ctl_stack_size) 1087 { 1088 struct process_queue_node *pqn; 1089 int ret; 1090 1091 pqn = get_queue_by_qid(pqm, qid); 1092 if (!pqn) { 1093 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1094 return -EFAULT; 1095 } 1096 1097 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1098 pr_err("amdkfd: queue dumping not supported on this device\n"); 1099 return -EOPNOTSUPP; 1100 } 1101 1102 ret = pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1103 pqn->q, mqd_size, 1104 ctl_stack_size); 1105 if (ret) { 1106 pr_debug("amdkfd: Overflow while computing stack size for queue %d\n", qid); 1107 return ret; 1108 } 1109 1110 return 0; 1111 } 1112 1113 #if defined(CONFIG_DEBUG_FS) 1114 1115 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1116 { 1117 struct process_queue_manager *pqm = data; 1118 struct process_queue_node *pqn; 1119 struct queue *q; 1120 enum KFD_MQD_TYPE mqd_type; 1121 struct mqd_manager *mqd_mgr; 1122 int r = 0, xcc, num_xccs = 1; 1123 void *mqd; 1124 uint64_t size = 0; 1125 1126 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1127 if (pqn->q) { 1128 q = pqn->q; 1129 switch (q->properties.type) { 1130 case KFD_QUEUE_TYPE_SDMA: 1131 case KFD_QUEUE_TYPE_SDMA_XGMI: 1132 seq_printf(m, " SDMA queue on device %x\n", 1133 q->device->id); 1134 mqd_type = KFD_MQD_TYPE_SDMA; 1135 break; 1136 case KFD_QUEUE_TYPE_COMPUTE: 1137 seq_printf(m, " Compute queue on device %x\n", 1138 q->device->id); 1139 mqd_type = KFD_MQD_TYPE_CP; 1140 num_xccs = NUM_XCC(q->device->xcc_mask); 1141 break; 1142 default: 1143 seq_printf(m, 1144 " Queue node with bad user queue type %d on device %x\n", 1145 q->properties.type, q->device->id); 1146 continue; 1147 } 1148 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1149 size = mqd_mgr->mqd_stride(mqd_mgr, 1150 &q->properties); 1151 } 1152 1153 for (xcc = 0; xcc < num_xccs; xcc++) { 1154 mqd = q->mqd + size * xcc; 1155 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1156 if (r != 0) 1157 break; 1158 } 1159 } 1160 1161 return r; 1162 } 1163 1164 #endif 1165