1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/slab.h> 26 #include <linux/list.h> 27 #include "kfd_device_queue_manager.h" 28 #include "kfd_priv.h" 29 #include "kfd_kernel_queue.h" 30 #include "amdgpu_amdkfd.h" 31 #include "amdgpu_reset.h" 32 33 static inline struct process_queue_node *get_queue_by_qid( 34 struct process_queue_manager *pqm, unsigned int qid) 35 { 36 struct process_queue_node *pqn; 37 38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 39 if ((pqn->q && pqn->q->properties.queue_id == qid) || 40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid)) 41 return pqn; 42 } 43 44 return NULL; 45 } 46 47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm, 48 unsigned int qid) 49 { 50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 51 return -EINVAL; 52 53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) { 54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid); 55 return -ENOSPC; 56 } 57 58 return 0; 59 } 60 61 static int find_available_queue_slot(struct process_queue_manager *pqm, 62 unsigned int *qid) 63 { 64 unsigned long found; 65 66 found = find_first_zero_bit(pqm->queue_slot_bitmap, 67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS); 68 69 pr_debug("The new slot id %lu\n", found); 70 71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) { 72 pr_info("Cannot open more queues for process with pid %d\n", 73 pqm->process->lead_thread->pid); 74 return -ENOMEM; 75 } 76 77 set_bit(found, pqm->queue_slot_bitmap); 78 *qid = found; 79 80 return 0; 81 } 82 83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) 84 { 85 struct kfd_node *dev = pdd->dev; 86 87 if (pdd->already_dequeued) 88 return; 89 /* The MES context flush needs to filter out the case which the 90 * KFD process is created without setting up the MES context and 91 * queue for creating a compute queue. 92 */ 93 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd); 94 if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && 95 down_read_trylock(&dev->adev->reset_domain->sem)) { 96 amdgpu_mes_flush_shader_debugger(dev->adev, 97 pdd->proc_ctx_gpu_addr, 0); 98 up_read(&dev->adev->reset_domain->sem); 99 } 100 pdd->already_dequeued = true; 101 } 102 103 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 104 void *gws) 105 { 106 struct mqd_update_info minfo = {0}; 107 struct kfd_node *dev = NULL; 108 struct process_queue_node *pqn; 109 struct kfd_process_device *pdd; 110 struct kgd_mem *mem = NULL; 111 int ret; 112 113 pqn = get_queue_by_qid(pqm, qid); 114 if (!pqn) { 115 pr_err("Queue id does not match any known queue\n"); 116 return -EINVAL; 117 } 118 119 if (pqn->q) 120 dev = pqn->q->device; 121 if (WARN_ON(!dev)) 122 return -ENODEV; 123 124 pdd = kfd_get_process_device_data(dev, pqm->process); 125 if (!pdd) { 126 pr_err("Process device data doesn't exist\n"); 127 return -EINVAL; 128 } 129 130 /* Only allow one queue per process can have GWS assigned */ 131 if (gws && pdd->qpd.num_gws) 132 return -EBUSY; 133 134 if (!gws && pdd->qpd.num_gws == 0) 135 return -EINVAL; 136 137 if ((KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 138 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 139 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) && 140 !dev->kfd->shared_resources.enable_mes) { 141 if (gws) 142 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info, 143 gws, &mem); 144 else 145 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info, 146 pqn->q->gws); 147 if (unlikely(ret)) 148 return ret; 149 pqn->q->gws = mem; 150 } else { 151 /* 152 * Intentionally set GWS to a non-NULL value 153 * for devices that do not use GWS for global wave 154 * synchronization but require the formality 155 * of setting GWS for cooperative groups. 156 */ 157 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL; 158 } 159 160 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0; 161 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0; 162 163 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 164 pqn->q, &minfo); 165 } 166 167 void kfd_process_dequeue_from_all_devices(struct kfd_process *p) 168 { 169 int i; 170 171 for (i = 0; i < p->n_pdds; i++) 172 kfd_process_dequeue_from_device(p->pdds[i]); 173 } 174 175 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) 176 { 177 INIT_LIST_HEAD(&pqm->queues); 178 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, 179 GFP_KERNEL); 180 if (!pqm->queue_slot_bitmap) 181 return -ENOMEM; 182 pqm->process = p; 183 184 return 0; 185 } 186 187 static void pqm_clean_queue_resource(struct process_queue_manager *pqm, 188 struct process_queue_node *pqn) 189 { 190 struct kfd_node *dev; 191 struct kfd_process_device *pdd; 192 193 dev = pqn->q->device; 194 195 pdd = kfd_get_process_device_data(dev, pqm->process); 196 if (!pdd) { 197 pr_err("Process device data doesn't exist\n"); 198 return; 199 } 200 201 if (pqn->q->gws) { 202 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) && 203 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) && 204 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 5, 0) && 205 !dev->kfd->shared_resources.enable_mes) 206 amdgpu_amdkfd_remove_gws_from_process( 207 pqm->process->kgd_process_info, pqn->q->gws); 208 pdd->qpd.num_gws = 0; 209 } 210 211 if (dev->kfd->shared_resources.enable_mes) { 212 amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); 213 amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); 214 } 215 } 216 217 void pqm_uninit(struct process_queue_manager *pqm) 218 { 219 struct process_queue_node *pqn, *next; 220 221 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) { 222 if (pqn->q) { 223 struct kfd_process_device *pdd = kfd_get_process_device_data(pqn->q->device, 224 pqm->process); 225 if (pdd) { 226 kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 227 kfd_queue_release_buffers(pdd, &pqn->q->properties); 228 } else { 229 WARN_ON(!pdd); 230 } 231 pqm_clean_queue_resource(pqm, pqn); 232 } 233 234 kfd_procfs_del_queue(pqn->q); 235 uninit_queue(pqn->q); 236 list_del(&pqn->process_queue_list); 237 kfree(pqn); 238 } 239 240 bitmap_free(pqm->queue_slot_bitmap); 241 pqm->queue_slot_bitmap = NULL; 242 } 243 244 static int init_user_queue(struct process_queue_manager *pqm, 245 struct kfd_node *dev, struct queue **q, 246 struct queue_properties *q_properties, 247 unsigned int qid) 248 { 249 int retval; 250 251 /* Doorbell initialized in user space*/ 252 q_properties->doorbell_ptr = NULL; 253 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW); 254 255 /* let DQM handle it*/ 256 q_properties->vmid = 0; 257 q_properties->queue_id = qid; 258 259 retval = init_queue(q, q_properties); 260 if (retval != 0) 261 return retval; 262 263 (*q)->device = dev; 264 (*q)->process = pqm->process; 265 266 if (dev->kfd->shared_resources.enable_mes) { 267 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 268 AMDGPU_MES_GANG_CTX_SIZE, 269 &(*q)->gang_ctx_bo, 270 &(*q)->gang_ctx_gpu_addr, 271 &(*q)->gang_ctx_cpu_ptr, 272 false); 273 if (retval) { 274 pr_err("failed to allocate gang context bo\n"); 275 goto cleanup; 276 } 277 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE); 278 279 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work 280 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell) 281 */ 282 if (dev->adev != amdgpu_ttm_adev(q_properties->wptr_bo->tbo.bdev)) { 283 pr_err("Queue memory allocated to wrong device\n"); 284 retval = -EINVAL; 285 goto free_gang_ctx_bo; 286 } 287 288 retval = amdgpu_amdkfd_map_gtt_bo_to_gart(q_properties->wptr_bo, 289 &(*q)->wptr_bo_gart); 290 if (retval) { 291 pr_err("Failed to map wptr bo to GART\n"); 292 goto free_gang_ctx_bo; 293 } 294 } 295 296 pr_debug("PQM After init queue"); 297 return 0; 298 299 free_gang_ctx_bo: 300 amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo); 301 cleanup: 302 uninit_queue(*q); 303 *q = NULL; 304 return retval; 305 } 306 307 int pqm_create_queue(struct process_queue_manager *pqm, 308 struct kfd_node *dev, 309 struct queue_properties *properties, 310 unsigned int *qid, 311 const struct kfd_criu_queue_priv_data *q_data, 312 const void *restore_mqd, 313 const void *restore_ctl_stack, 314 uint32_t *p_doorbell_offset_in_process) 315 { 316 int retval; 317 struct kfd_process_device *pdd; 318 struct queue *q; 319 struct process_queue_node *pqn; 320 struct kernel_queue *kq; 321 enum kfd_queue_type type = properties->type; 322 unsigned int max_queues = 127; /* HWS limit */ 323 324 /* 325 * On GFX 9.4.3/9.5.0, increase the number of queues that 326 * can be created to 255. No HWS limit on GFX 9.4.3/9.5.0. 327 */ 328 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 329 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 330 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) 331 max_queues = 255; 332 333 q = NULL; 334 kq = NULL; 335 336 pdd = kfd_get_process_device_data(dev, pqm->process); 337 if (!pdd) { 338 pr_err("Process device data doesn't exist\n"); 339 return -1; 340 } 341 342 /* 343 * for debug process, verify that it is within the static queues limit 344 * currently limit is set to half of the total avail HQD slots 345 * If we are just about to create DIQ, the is_debug flag is not set yet 346 * Hence we also check the type as well 347 */ 348 if (pdd->qpd.is_debug) 349 max_queues = dev->kfd->device_info.max_no_of_hqd/2; 350 351 if (pdd->qpd.queue_count >= max_queues) 352 return -ENOSPC; 353 354 if (q_data) { 355 retval = assign_queue_slot_by_qid(pqm, q_data->q_id); 356 *qid = q_data->q_id; 357 } else 358 retval = find_available_queue_slot(pqm, qid); 359 360 if (retval != 0) 361 return retval; 362 363 /* Register process if this is the first queue */ 364 if (list_empty(&pdd->qpd.queues_list) && 365 list_empty(&pdd->qpd.priv_queue_list)) 366 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd); 367 368 /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ 369 if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { 370 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, 371 AMDGPU_MES_PROC_CTX_SIZE, 372 &pdd->proc_ctx_bo, 373 &pdd->proc_ctx_gpu_addr, 374 &pdd->proc_ctx_cpu_ptr, 375 false); 376 if (retval) { 377 dev_err(dev->adev->dev, "failed to allocate process context bo\n"); 378 return retval; 379 } 380 memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); 381 } 382 383 pqn = kzalloc(sizeof(*pqn), GFP_KERNEL); 384 if (!pqn) { 385 retval = -ENOMEM; 386 goto err_allocate_pqn; 387 } 388 389 switch (type) { 390 case KFD_QUEUE_TYPE_SDMA: 391 case KFD_QUEUE_TYPE_SDMA_XGMI: 392 case KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: 393 /* SDMA queues are always allocated statically no matter 394 * which scheduler mode is used. We also do not need to 395 * check whether a SDMA queue can be allocated here, because 396 * allocate_sdma_queue() in create_queue() has the 397 * corresponding check logic. 398 */ 399 retval = init_user_queue(pqm, dev, &q, properties, *qid); 400 if (retval != 0) 401 goto err_create_queue; 402 pqn->q = q; 403 pqn->kq = NULL; 404 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 405 restore_mqd, restore_ctl_stack); 406 print_queue(q); 407 break; 408 409 case KFD_QUEUE_TYPE_COMPUTE: 410 /* check if there is over subscription */ 411 if ((dev->dqm->sched_policy == 412 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) && 413 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) || 414 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) { 415 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n"); 416 retval = -EPERM; 417 goto err_create_queue; 418 } 419 420 retval = init_user_queue(pqm, dev, &q, properties, *qid); 421 if (retval != 0) 422 goto err_create_queue; 423 pqn->q = q; 424 pqn->kq = NULL; 425 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data, 426 restore_mqd, restore_ctl_stack); 427 print_queue(q); 428 break; 429 default: 430 WARN(1, "Invalid queue type %d", type); 431 retval = -EINVAL; 432 } 433 434 if (retval != 0) { 435 if ((type == KFD_QUEUE_TYPE_SDMA || 436 type == KFD_QUEUE_TYPE_SDMA_XGMI || 437 type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) && 438 retval == -ENOMEM) 439 pr_warn("process pid %d DQM create queue type %d failed. ret %d\n", 440 pqm->process->lead_thread->pid, type, retval); 441 else 442 pr_err("process pid %d DQM create queue type %d failed. ret %d\n", 443 pqm->process->lead_thread->pid, type, retval); 444 goto err_create_queue; 445 } 446 447 if (q && p_doorbell_offset_in_process) { 448 /* Return the doorbell offset within the doorbell page 449 * to the caller so it can be passed up to user mode 450 * (in bytes). 451 * relative doorbell index = Absolute doorbell index - 452 * absolute index of first doorbell in the page. 453 */ 454 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev, 455 pdd->qpd.proc_doorbells, 456 0, 457 pdd->dev->kfd->device_info.doorbell_size); 458 459 *p_doorbell_offset_in_process = (q->properties.doorbell_off 460 - first_db_index) * sizeof(uint32_t); 461 } 462 463 pr_debug("PQM After DQM create queue\n"); 464 465 list_add(&pqn->process_queue_list, &pqm->queues); 466 467 if (q) { 468 pr_debug("PQM done creating queue\n"); 469 kfd_procfs_add_queue(q); 470 print_queue_properties(&q->properties); 471 } 472 473 return retval; 474 475 err_create_queue: 476 uninit_queue(q); 477 if (kq) 478 kernel_queue_uninit(kq); 479 kfree(pqn); 480 err_allocate_pqn: 481 /* check if queues list is empty unregister process from device */ 482 clear_bit(*qid, pqm->queue_slot_bitmap); 483 if (list_empty(&pdd->qpd.queues_list) && 484 list_empty(&pdd->qpd.priv_queue_list)) 485 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd); 486 return retval; 487 } 488 489 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) 490 { 491 struct process_queue_node *pqn; 492 struct kfd_process_device *pdd; 493 struct device_queue_manager *dqm; 494 struct kfd_node *dev; 495 int retval; 496 497 dqm = NULL; 498 499 retval = 0; 500 501 pqn = get_queue_by_qid(pqm, qid); 502 if (!pqn) { 503 pr_err("Queue id does not match any known queue\n"); 504 return -EINVAL; 505 } 506 507 dev = NULL; 508 if (pqn->kq) 509 dev = pqn->kq->dev; 510 if (pqn->q) 511 dev = pqn->q->device; 512 if (WARN_ON(!dev)) 513 return -ENODEV; 514 515 pdd = kfd_get_process_device_data(dev, pqm->process); 516 if (!pdd) { 517 pr_err("Process device data doesn't exist\n"); 518 return -1; 519 } 520 521 if (pqn->kq) { 522 /* destroy kernel queue (DIQ) */ 523 dqm = pqn->kq->dev->dqm; 524 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd); 525 kernel_queue_uninit(pqn->kq); 526 } 527 528 if (pqn->q) { 529 retval = kfd_queue_unref_bo_vas(pdd, &pqn->q->properties); 530 if (retval) 531 goto err_destroy_queue; 532 533 dqm = pqn->q->device->dqm; 534 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); 535 if (retval) { 536 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", 537 pdd->pasid, 538 pqn->q->properties.queue_id, retval); 539 if (retval != -ETIME && retval != -EIO) 540 goto err_destroy_queue; 541 } 542 kfd_procfs_del_queue(pqn->q); 543 kfd_queue_release_buffers(pdd, &pqn->q->properties); 544 pqm_clean_queue_resource(pqm, pqn); 545 uninit_queue(pqn->q); 546 } 547 548 list_del(&pqn->process_queue_list); 549 kfree(pqn); 550 clear_bit(qid, pqm->queue_slot_bitmap); 551 552 if (list_empty(&pdd->qpd.queues_list) && 553 list_empty(&pdd->qpd.priv_queue_list)) 554 dqm->ops.unregister_process(dqm, &pdd->qpd); 555 556 err_destroy_queue: 557 return retval; 558 } 559 560 int pqm_update_queue_properties(struct process_queue_manager *pqm, 561 unsigned int qid, struct queue_properties *p) 562 { 563 int retval; 564 struct process_queue_node *pqn; 565 566 pqn = get_queue_by_qid(pqm, qid); 567 if (!pqn || !pqn->q) { 568 pr_debug("No queue %d exists for update operation\n", qid); 569 return -EFAULT; 570 } 571 572 /* 573 * Update with NULL ring address is used to disable the queue 574 */ 575 if (p->queue_address && p->queue_size) { 576 struct kfd_process_device *pdd; 577 struct amdgpu_vm *vm; 578 struct queue *q = pqn->q; 579 int err; 580 581 pdd = kfd_get_process_device_data(q->device, q->process); 582 if (!pdd) 583 return -ENODEV; 584 vm = drm_priv_to_vm(pdd->drm_priv); 585 err = amdgpu_bo_reserve(vm->root.bo, false); 586 if (err) 587 return err; 588 589 if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, 590 p->queue_size)) { 591 pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", 592 p->queue_address, p->queue_size); 593 return -EFAULT; 594 } 595 596 kfd_queue_unref_bo_va(vm, &pqn->q->properties.ring_bo); 597 kfd_queue_buffer_put(&pqn->q->properties.ring_bo); 598 amdgpu_bo_unreserve(vm->root.bo); 599 600 pqn->q->properties.ring_bo = p->ring_bo; 601 } 602 603 pqn->q->properties.queue_address = p->queue_address; 604 pqn->q->properties.queue_size = p->queue_size; 605 pqn->q->properties.queue_percent = p->queue_percent; 606 pqn->q->properties.priority = p->priority; 607 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc; 608 609 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 610 pqn->q, NULL); 611 if (retval != 0) 612 return retval; 613 614 return 0; 615 } 616 617 int pqm_update_mqd(struct process_queue_manager *pqm, 618 unsigned int qid, struct mqd_update_info *minfo) 619 { 620 int retval; 621 struct process_queue_node *pqn; 622 623 pqn = get_queue_by_qid(pqm, qid); 624 if (!pqn) { 625 pr_debug("No queue %d exists for update operation\n", qid); 626 return -EFAULT; 627 } 628 629 /* CUs are masked for debugger requirements so deny user mask */ 630 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr) 631 return -EBUSY; 632 633 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */ 634 if (minfo && minfo->cu_mask.ptr && 635 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) { 636 int i; 637 638 for (i = 0; i < minfo->cu_mask.count; i += 2) { 639 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3; 640 641 if (cu_pair && cu_pair != 0x3) { 642 pr_debug("CUs must be adjacent pairwise enabled.\n"); 643 return -EINVAL; 644 } 645 } 646 } 647 648 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm, 649 pqn->q, minfo); 650 if (retval != 0) 651 return retval; 652 653 if (minfo && minfo->cu_mask.ptr) 654 pqn->q->properties.is_user_cu_masked = true; 655 656 return 0; 657 } 658 659 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 660 unsigned int qid) 661 { 662 struct process_queue_node *pqn; 663 664 pqn = get_queue_by_qid(pqm, qid); 665 return pqn ? pqn->q : NULL; 666 } 667 668 int pqm_get_wave_state(struct process_queue_manager *pqm, 669 unsigned int qid, 670 void __user *ctl_stack, 671 u32 *ctl_stack_used_size, 672 u32 *save_area_used_size) 673 { 674 struct process_queue_node *pqn; 675 676 pqn = get_queue_by_qid(pqm, qid); 677 if (!pqn) { 678 pr_debug("amdkfd: No queue %d exists for operation\n", 679 qid); 680 return -EFAULT; 681 } 682 683 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm, 684 pqn->q, 685 ctl_stack, 686 ctl_stack_used_size, 687 save_area_used_size); 688 } 689 690 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 691 uint64_t exception_clear_mask, 692 void __user *buf, 693 int *num_qss_entries, 694 uint32_t *entry_size) 695 { 696 struct process_queue_node *pqn; 697 struct kfd_queue_snapshot_entry src; 698 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries; 699 int r = 0; 700 701 *num_qss_entries = 0; 702 if (!(*entry_size)) 703 return -EINVAL; 704 705 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry)); 706 mutex_lock(&pqm->process->event_mutex); 707 708 memset(&src, 0, sizeof(src)); 709 710 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 711 if (!pqn->q) 712 continue; 713 714 if (*num_qss_entries < tmp_qss_entries) { 715 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src); 716 717 if (copy_to_user(buf, &src, *entry_size)) { 718 r = -EFAULT; 719 break; 720 } 721 buf += tmp_entry_size; 722 } 723 *num_qss_entries += 1; 724 } 725 726 mutex_unlock(&pqm->process->event_mutex); 727 return r; 728 } 729 730 static int get_queue_data_sizes(struct kfd_process_device *pdd, 731 struct queue *q, 732 uint32_t *mqd_size, 733 uint32_t *ctl_stack_size) 734 { 735 int ret; 736 737 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm, 738 q->properties.queue_id, 739 mqd_size, 740 ctl_stack_size); 741 if (ret) 742 pr_err("Failed to get queue dump info (%d)\n", ret); 743 744 return ret; 745 } 746 747 int kfd_process_get_queue_info(struct kfd_process *p, 748 uint32_t *num_queues, 749 uint64_t *priv_data_sizes) 750 { 751 uint32_t extra_data_sizes = 0; 752 struct queue *q; 753 int i; 754 int ret; 755 756 *num_queues = 0; 757 758 /* Run over all PDDs of the process */ 759 for (i = 0; i < p->n_pdds; i++) { 760 struct kfd_process_device *pdd = p->pdds[i]; 761 762 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 763 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || 764 q->properties.type == KFD_QUEUE_TYPE_SDMA || 765 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) { 766 uint32_t mqd_size, ctl_stack_size; 767 768 *num_queues = *num_queues + 1; 769 770 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 771 if (ret) 772 return ret; 773 774 extra_data_sizes += mqd_size + ctl_stack_size; 775 } else { 776 pr_err("Unsupported queue type (%d)\n", q->properties.type); 777 return -EOPNOTSUPP; 778 } 779 } 780 } 781 *priv_data_sizes = extra_data_sizes + 782 (*num_queues * sizeof(struct kfd_criu_queue_priv_data)); 783 784 return 0; 785 } 786 787 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm, 788 unsigned int qid, 789 void *mqd, 790 void *ctl_stack) 791 { 792 struct process_queue_node *pqn; 793 794 pqn = get_queue_by_qid(pqm, qid); 795 if (!pqn) { 796 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 797 return -EFAULT; 798 } 799 800 if (!pqn->q->device->dqm->ops.checkpoint_mqd) { 801 pr_err("amdkfd: queue dumping not supported on this device\n"); 802 return -EOPNOTSUPP; 803 } 804 805 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm, 806 pqn->q, mqd, ctl_stack); 807 } 808 809 static int criu_checkpoint_queue(struct kfd_process_device *pdd, 810 struct queue *q, 811 struct kfd_criu_queue_priv_data *q_data) 812 { 813 uint8_t *mqd, *ctl_stack; 814 int ret; 815 816 mqd = (void *)(q_data + 1); 817 ctl_stack = mqd + q_data->mqd_size; 818 819 q_data->gpu_id = pdd->user_gpu_id; 820 q_data->type = q->properties.type; 821 q_data->format = q->properties.format; 822 q_data->q_id = q->properties.queue_id; 823 q_data->q_address = q->properties.queue_address; 824 q_data->q_size = q->properties.queue_size; 825 q_data->priority = q->properties.priority; 826 q_data->q_percent = q->properties.queue_percent; 827 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr; 828 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr; 829 q_data->doorbell_id = q->doorbell_id; 830 831 q_data->sdma_id = q->sdma_id; 832 833 q_data->eop_ring_buffer_address = 834 q->properties.eop_ring_buffer_address; 835 836 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size; 837 838 q_data->ctx_save_restore_area_address = 839 q->properties.ctx_save_restore_area_address; 840 841 q_data->ctx_save_restore_area_size = 842 q->properties.ctx_save_restore_area_size; 843 844 q_data->gws = !!q->gws; 845 846 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack); 847 if (ret) { 848 pr_err("Failed checkpoint queue_mqd (%d)\n", ret); 849 return ret; 850 } 851 852 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id); 853 return ret; 854 } 855 856 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd, 857 uint8_t __user *user_priv, 858 unsigned int *q_index, 859 uint64_t *queues_priv_data_offset) 860 { 861 unsigned int q_private_data_size = 0; 862 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */ 863 struct queue *q; 864 int ret = 0; 865 866 list_for_each_entry(q, &pdd->qpd.queues_list, list) { 867 struct kfd_criu_queue_priv_data *q_data; 868 uint64_t q_data_size; 869 uint32_t mqd_size; 870 uint32_t ctl_stack_size; 871 872 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE && 873 q->properties.type != KFD_QUEUE_TYPE_SDMA && 874 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) { 875 876 pr_err("Unsupported queue type (%d)\n", q->properties.type); 877 ret = -EOPNOTSUPP; 878 break; 879 } 880 881 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size); 882 if (ret) 883 break; 884 885 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size; 886 887 /* Increase local buffer space if needed */ 888 if (q_private_data_size < q_data_size) { 889 kfree(q_private_data); 890 891 q_private_data = kzalloc(q_data_size, GFP_KERNEL); 892 if (!q_private_data) { 893 ret = -ENOMEM; 894 break; 895 } 896 q_private_data_size = q_data_size; 897 } 898 899 q_data = (struct kfd_criu_queue_priv_data *)q_private_data; 900 901 /* 902 * data stored in this order: 903 * priv_data, mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 904 */ 905 q_data->mqd_size = mqd_size; 906 q_data->ctl_stack_size = ctl_stack_size; 907 908 ret = criu_checkpoint_queue(pdd, q, q_data); 909 if (ret) 910 break; 911 912 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE; 913 914 ret = copy_to_user(user_priv + *queues_priv_data_offset, 915 q_data, q_data_size); 916 if (ret) { 917 ret = -EFAULT; 918 break; 919 } 920 *queues_priv_data_offset += q_data_size; 921 *q_index = *q_index + 1; 922 } 923 924 kfree(q_private_data); 925 926 return ret; 927 } 928 929 int kfd_criu_checkpoint_queues(struct kfd_process *p, 930 uint8_t __user *user_priv_data, 931 uint64_t *priv_data_offset) 932 { 933 int ret = 0, pdd_index, q_index = 0; 934 935 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 936 struct kfd_process_device *pdd = p->pdds[pdd_index]; 937 938 /* 939 * criu_checkpoint_queues_device will copy data to user and update q_index and 940 * queues_priv_data_offset 941 */ 942 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index, 943 priv_data_offset); 944 945 if (ret) 946 break; 947 } 948 949 return ret; 950 } 951 952 static void set_queue_properties_from_criu(struct queue_properties *qp, 953 struct kfd_criu_queue_priv_data *q_data, uint32_t num_xcc) 954 { 955 qp->is_interop = false; 956 qp->queue_percent = q_data->q_percent; 957 qp->priority = q_data->priority; 958 qp->queue_address = q_data->q_address; 959 qp->queue_size = q_data->q_size; 960 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr; 961 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr; 962 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address; 963 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size; 964 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address; 965 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size; 966 if (q_data->type == KFD_QUEUE_TYPE_COMPUTE) 967 qp->ctl_stack_size = q_data->ctl_stack_size / num_xcc; 968 else 969 qp->ctl_stack_size = q_data->ctl_stack_size; 970 971 qp->type = q_data->type; 972 qp->format = q_data->format; 973 } 974 975 int kfd_criu_restore_queue(struct kfd_process *p, 976 uint8_t __user *user_priv_ptr, 977 uint64_t *priv_data_offset, 978 uint64_t max_priv_data_size) 979 { 980 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL; 981 struct kfd_criu_queue_priv_data *q_data; 982 struct kfd_process_device *pdd; 983 uint64_t q_extra_data_size; 984 struct queue_properties qp; 985 unsigned int queue_id; 986 int ret = 0; 987 988 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size) 989 return -EINVAL; 990 991 q_data = kmalloc(sizeof(*q_data), GFP_KERNEL); 992 if (!q_data) 993 return -ENOMEM; 994 995 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data)); 996 if (ret) { 997 ret = -EFAULT; 998 goto exit; 999 } 1000 1001 *priv_data_offset += sizeof(*q_data); 1002 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size; 1003 1004 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) { 1005 ret = -EINVAL; 1006 goto exit; 1007 } 1008 1009 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL); 1010 if (!q_extra_data) { 1011 ret = -ENOMEM; 1012 goto exit; 1013 } 1014 1015 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size); 1016 if (ret) { 1017 ret = -EFAULT; 1018 goto exit; 1019 } 1020 1021 *priv_data_offset += q_extra_data_size; 1022 1023 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id); 1024 if (!pdd) { 1025 pr_err("Failed to get pdd\n"); 1026 ret = -EINVAL; 1027 goto exit; 1028 } 1029 1030 /* 1031 * data stored in this order: 1032 * mqd[xcc0], mqd[xcc1],..., ctl_stack[xcc0], ctl_stack[xcc1]... 1033 */ 1034 mqd = q_extra_data; 1035 ctl_stack = mqd + q_data->mqd_size; 1036 1037 memset(&qp, 0, sizeof(qp)); 1038 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask)); 1039 1040 print_queue_properties(&qp); 1041 1042 ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); 1043 if (ret) { 1044 pr_err("Failed to create new queue err:%d\n", ret); 1045 goto exit; 1046 } 1047 1048 if (q_data->gws) 1049 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws); 1050 1051 exit: 1052 if (ret) 1053 pr_err("Failed to restore queue (%d)\n", ret); 1054 else 1055 pr_debug("Queue id %d was restored successfully\n", queue_id); 1056 1057 kfree(q_data); 1058 kfree(q_extra_data); 1059 1060 return ret; 1061 } 1062 1063 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1064 unsigned int qid, 1065 uint32_t *mqd_size, 1066 uint32_t *ctl_stack_size) 1067 { 1068 struct process_queue_node *pqn; 1069 1070 pqn = get_queue_by_qid(pqm, qid); 1071 if (!pqn) { 1072 pr_debug("amdkfd: No queue %d exists for operation\n", qid); 1073 return -EFAULT; 1074 } 1075 1076 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) { 1077 pr_err("amdkfd: queue dumping not supported on this device\n"); 1078 return -EOPNOTSUPP; 1079 } 1080 1081 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, 1082 pqn->q, mqd_size, 1083 ctl_stack_size); 1084 return 0; 1085 } 1086 1087 #if defined(CONFIG_DEBUG_FS) 1088 1089 int pqm_debugfs_mqds(struct seq_file *m, void *data) 1090 { 1091 struct process_queue_manager *pqm = data; 1092 struct process_queue_node *pqn; 1093 struct queue *q; 1094 enum KFD_MQD_TYPE mqd_type; 1095 struct mqd_manager *mqd_mgr; 1096 int r = 0, xcc, num_xccs = 1; 1097 void *mqd; 1098 uint64_t size = 0; 1099 1100 list_for_each_entry(pqn, &pqm->queues, process_queue_list) { 1101 if (pqn->q) { 1102 q = pqn->q; 1103 switch (q->properties.type) { 1104 case KFD_QUEUE_TYPE_SDMA: 1105 case KFD_QUEUE_TYPE_SDMA_XGMI: 1106 seq_printf(m, " SDMA queue on device %x\n", 1107 q->device->id); 1108 mqd_type = KFD_MQD_TYPE_SDMA; 1109 break; 1110 case KFD_QUEUE_TYPE_COMPUTE: 1111 seq_printf(m, " Compute queue on device %x\n", 1112 q->device->id); 1113 mqd_type = KFD_MQD_TYPE_CP; 1114 num_xccs = NUM_XCC(q->device->xcc_mask); 1115 break; 1116 default: 1117 seq_printf(m, 1118 " Qeueu node with bad user queue type %d on device %x\n", 1119 q->properties.type, q->device->id); 1120 continue; 1121 } 1122 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; 1123 size = mqd_mgr->mqd_stride(mqd_mgr, 1124 &q->properties); 1125 } 1126 1127 for (xcc = 0; xcc < num_xccs; xcc++) { 1128 mqd = q->mqd + size * xcc; 1129 r = mqd_mgr->debugfs_show_mqd(m, mqd); 1130 if (r != 0) 1131 break; 1132 } 1133 } 1134 1135 return r; 1136 } 1137 1138 #endif 1139