1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <uapi/linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc_obj(*ptr_to_struct)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first chunk is the TBA used for the CWSR ISA code. The second 103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048) 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC 115 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time 116 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is 117 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload 118 * The format here makes CP workload 10% of total timeout 119 */ 120 #define KFD_UNMAP_LATENCY_MS \ 121 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) 122 123 #define KFD_MAX_SDMA_QUEUES 128 124 125 /* 126 * 512 = 0x200 127 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 128 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 129 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 130 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 131 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 132 */ 133 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 134 135 /** 136 * enum kfd_ioctl_flags - KFD ioctl flags 137 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 138 * userspace can use a given ioctl. 139 */ 140 enum kfd_ioctl_flags { 141 /* 142 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 143 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 144 * perform privileged operations and load arbitrary data into MQDs and 145 * eventually HQD registers when the queue is mapped by HWS. In order to 146 * prevent this we should perform additional security checks. 147 * 148 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 149 * 150 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 151 * we also allow ioctls with SYS_ADMIN capability. 152 */ 153 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 154 }; 155 /* 156 * Kernel module parameter to specify maximum number of supported queues per 157 * device 158 */ 159 extern int max_num_of_queues_per_device; 160 161 162 /* Kernel module parameter to specify the scheduling policy */ 163 extern int sched_policy; 164 165 /* 166 * Kernel module parameter to specify the maximum process 167 * number per HW scheduler 168 */ 169 extern int hws_max_conc_proc; 170 171 extern int cwsr_enable; 172 173 /* 174 * Kernel module parameter to specify whether to send sigterm to HSA process on 175 * unhandled exception 176 */ 177 extern int send_sigterm; 178 179 /* 180 * This kernel module is used to simulate large bar machine on non-large bar 181 * enabled machines. 182 */ 183 extern int debug_largebar; 184 185 /* Set sh_mem_config.retry_disable on GFX v9 */ 186 extern int amdgpu_noretry; 187 188 /* Halt if HWS hang is detected */ 189 extern int halt_if_hws_hang; 190 191 /* Whether MEC FW support GWS barriers */ 192 extern bool hws_gws_support; 193 194 /* Queue preemption timeout in ms */ 195 extern int queue_preemption_timeout_ms; 196 197 /* 198 * Don't evict process queues on vm fault 199 */ 200 extern int amdgpu_no_queue_eviction_on_vm_fault; 201 202 /* Enable eviction debug messages */ 203 extern bool debug_evictions; 204 205 extern struct mutex kfd_processes_mutex; 206 207 enum cache_policy { 208 cache_policy_coherent, 209 cache_policy_noncoherent 210 }; 211 212 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0)) 213 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 214 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 215 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 216 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ 217 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ 218 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) 219 220 struct kfd_node; 221 222 struct kfd_event_interrupt_class { 223 bool (*interrupt_isr)(struct kfd_node *dev, 224 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 225 bool *patched_flag); 226 void (*interrupt_wq)(struct kfd_node *dev, 227 const uint32_t *ih_ring_entry); 228 }; 229 230 struct kfd_device_info { 231 uint32_t gfx_target_version; 232 const struct kfd_event_interrupt_class *event_interrupt_class; 233 unsigned int max_pasid_bits; 234 unsigned int max_no_of_hqd; 235 unsigned int doorbell_size; 236 size_t ih_ring_entry_size; 237 uint8_t num_of_watch_points; 238 uint16_t mqd_size_aligned; 239 bool supports_cwsr; 240 bool needs_pci_atomics; 241 uint32_t no_atomic_fw_version; 242 unsigned int num_sdma_queues_per_engine; 243 unsigned int num_reserved_sdma_queues_per_engine; 244 }; 245 246 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 247 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 248 249 struct kfd_mem_obj { 250 uint32_t range_start; 251 uint32_t range_end; 252 uint64_t gpu_addr; 253 uint32_t *cpu_ptr; 254 void *mem; 255 }; 256 257 struct kfd_vmid_info { 258 uint32_t first_vmid_kfd; 259 uint32_t last_vmid_kfd; 260 uint32_t vmid_num_kfd; 261 }; 262 263 #define MAX_KFD_NODES 8 264 265 struct kfd_dev; 266 267 struct kfd_node { 268 unsigned int node_id; 269 struct amdgpu_device *adev; /* Duplicated here along with keeping 270 * a copy in kfd_dev to save a hop 271 */ 272 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 273 * keeping a copy in kfd_dev to 274 * save a hop 275 */ 276 struct kfd_vmid_info vm_info; 277 unsigned int id; /* topology stub index */ 278 uint32_t xcc_mask; /* Instance mask of XCCs present */ 279 struct amdgpu_xcp *xcp; 280 281 /* Interrupts */ 282 struct kfifo ih_fifo; 283 struct work_struct interrupt_work; 284 spinlock_t interrupt_lock; 285 286 /* 287 * Interrupts of interest to KFD are copied 288 * from the HW ring into a SW ring. 289 */ 290 bool interrupts_active; 291 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 292 293 /* QCM Device instance */ 294 struct device_queue_manager *dqm; 295 296 /* Global GWS resource shared between processes */ 297 void *gws; 298 299 /* Clients watching SMI events */ 300 struct list_head smi_clients; 301 spinlock_t smi_lock; 302 uint32_t reset_seq_num; 303 304 /* SRAM ECC flag */ 305 atomic_t sram_ecc_flag; 306 307 /*spm process id */ 308 unsigned int spm_pasid; 309 310 /* Maximum process number mapped to HW scheduler */ 311 unsigned int max_proc_per_quantum; 312 313 unsigned int compute_vmid_bitmap; 314 315 struct kfd_local_mem_info local_mem_info; 316 317 struct kfd_dev *kfd; 318 319 /* Track per device allocated watch points */ 320 uint32_t alloc_watch_ids; 321 spinlock_t watch_points_lock; 322 }; 323 324 struct kfd_dev { 325 struct amdgpu_device *adev; 326 327 struct kfd_device_info device_info; 328 329 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 330 * page used by kernel queue 331 */ 332 333 struct kgd2kfd_shared_resources shared_resources; 334 335 const struct kfd2kgd_calls *kfd2kgd; 336 struct mutex doorbell_mutex; 337 338 void *gtt_mem; 339 uint64_t gtt_start_gpu_addr; 340 void *gtt_start_cpu_ptr; 341 void *gtt_sa_bitmap; 342 struct mutex gtt_sa_lock; 343 unsigned int gtt_sa_chunk_size; 344 unsigned int gtt_sa_num_of_chunks; 345 346 bool init_complete; 347 348 /* Firmware versions */ 349 uint16_t mec_fw_version; 350 uint16_t mec2_fw_version; 351 uint16_t sdma_fw_version; 352 353 /* CWSR */ 354 bool cwsr_enabled; 355 const void *cwsr_isa; 356 unsigned int cwsr_isa_size; 357 358 /* xGMI */ 359 uint64_t hive_id; 360 361 bool pci_atomic_requested; 362 363 /* Compute Profile ref. count */ 364 atomic_t compute_profile; 365 366 struct ida doorbell_ida; 367 unsigned int max_doorbell_slices; 368 369 int noretry; 370 371 struct kfd_node *nodes[MAX_KFD_NODES]; 372 unsigned int num_nodes; 373 374 struct workqueue_struct *ih_wq; 375 376 /* Kernel doorbells for KFD device */ 377 struct amdgpu_bo *doorbells; 378 379 /* bitmap for dynamic doorbell allocation from doorbell object */ 380 unsigned long *doorbell_bitmap; 381 382 /* for dynamic partitioning */ 383 int kfd_dev_lock; 384 385 atomic_t kfd_processes_count; 386 387 /* Lock for profiler process */ 388 struct mutex profiler_lock; 389 /* Process currently holding the lock */ 390 struct kfd_process *profiler_process; 391 }; 392 393 enum kfd_mempool { 394 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 395 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 396 KFD_MEMPOOL_FRAMEBUFFER = 3, 397 }; 398 399 /* Character device interface */ 400 int kfd_chardev_init(void); 401 void kfd_chardev_exit(void); 402 403 /** 404 * enum kfd_unmap_queues_filter - Enum for queue filters. 405 * 406 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 407 * running queues list. 408 * 409 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 410 * in the run list. 411 * 412 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 413 * specific process. 414 * 415 */ 416 enum kfd_unmap_queues_filter { 417 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 418 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 419 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 420 }; 421 422 /** 423 * enum kfd_queue_type - Enum for various queue types. 424 * 425 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 426 * 427 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 428 * 429 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 430 * 431 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 432 * 433 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 434 * 435 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID. 436 */ 437 enum kfd_queue_type { 438 KFD_QUEUE_TYPE_COMPUTE, 439 KFD_QUEUE_TYPE_SDMA, 440 KFD_QUEUE_TYPE_HIQ, 441 KFD_QUEUE_TYPE_SDMA_XGMI, 442 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID 443 }; 444 445 enum kfd_queue_format { 446 KFD_QUEUE_FORMAT_PM4, 447 KFD_QUEUE_FORMAT_AQL 448 }; 449 450 enum KFD_QUEUE_PRIORITY { 451 KFD_QUEUE_PRIORITY_MINIMUM = 0, 452 KFD_QUEUE_PRIORITY_MAXIMUM = 15 453 }; 454 455 /** 456 * struct queue_properties 457 * 458 * @type: The queue type. 459 * 460 * @queue_id: Queue identifier. 461 * 462 * @queue_address: Queue ring buffer address. 463 * 464 * @queue_size: Queue ring buffer size. 465 * 466 * @priority: Defines the queue priority relative to other queues in the 467 * process. 468 * This is just an indication and HW scheduling may override the priority as 469 * necessary while keeping the relative prioritization. 470 * the priority granularity is from 0 to f which f is the highest priority. 471 * currently all queues are initialized with the highest priority. 472 * 473 * @queue_percent: This field is partially implemented and currently a zero in 474 * this field defines that the queue is non active. 475 * 476 * @read_ptr: User space address which points to the number of dwords the 477 * cp read from the ring buffer. This field updates automatically by the H/W. 478 * 479 * @write_ptr: Defines the number of dwords written to the ring buffer. 480 * 481 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 482 * buffer. This field should be similar to write_ptr and the user should 483 * update this field after updating the write_ptr. 484 * 485 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 486 * 487 * @is_interop: Defines if this is a interop queue. Interop queue means that 488 * the queue can access both graphics and compute resources. 489 * 490 * @is_evicted: Defines if the queue is evicted. Only active queues 491 * are evicted, rendering them inactive. 492 * 493 * @is_active: Defines if the queue is active or not. @is_active and 494 * @is_evicted are protected by the DQM lock. 495 * 496 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 497 * @is_gws should be protected by the DQM lock, since changing it can yield the 498 * possibility of updating DQM state on number of GWS queues. 499 * 500 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 501 * of the queue. 502 * 503 * This structure represents the queue properties for each queue no matter if 504 * it's user mode or kernel mode queue. 505 * 506 */ 507 508 struct queue_properties { 509 enum kfd_queue_type type; 510 enum kfd_queue_format format; 511 unsigned int queue_id; 512 uint64_t queue_address; 513 uint64_t queue_size; 514 uint64_t metadata_queue_size; 515 uint32_t priority; 516 uint32_t queue_percent; 517 void __user *read_ptr; 518 void __user *write_ptr; 519 void __iomem *doorbell_ptr; 520 uint32_t doorbell_off; 521 bool is_interop; 522 bool is_evicted; 523 bool is_suspended; 524 bool is_being_destroyed; 525 bool is_active; 526 bool is_gws; 527 uint32_t pm4_target_xcc; 528 bool is_dbg_wa; 529 bool is_user_cu_masked; 530 bool is_reset; 531 /* Not relevant for user mode queues in cp scheduling */ 532 unsigned int vmid; 533 /* Relevant only for sdma queues*/ 534 uint32_t sdma_engine_id; 535 uint32_t sdma_queue_id; 536 uint32_t sdma_vm_addr; 537 /* Relevant only for VI */ 538 uint64_t eop_ring_buffer_address; 539 uint32_t eop_ring_buffer_size; 540 uint64_t ctx_save_restore_area_address; 541 uint32_t ctx_save_restore_area_size; 542 uint32_t ctl_stack_size; 543 uint64_t tba_addr; 544 uint64_t tma_addr; 545 uint64_t exception_status; 546 547 struct amdgpu_bo *wptr_bo; 548 struct amdgpu_bo *rptr_bo; 549 struct amdgpu_bo *ring_bo; 550 struct amdgpu_bo *eop_buf_bo; 551 struct amdgpu_bo *cwsr_bo; 552 }; 553 554 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 555 (q).queue_address != 0 && \ 556 (q).queue_percent > 0 && \ 557 !(q).is_evicted && \ 558 !(q).is_suspended) 559 560 enum mqd_update_flag { 561 UPDATE_FLAG_DBG_WA_ENABLE = 1, 562 UPDATE_FLAG_DBG_WA_DISABLE = 2, 563 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 564 UPDATE_FLAG_PERFCOUNT_ENABLE = 5, 565 UPDATE_FLAG_PERFCOUNT_DISABLE = 6, 566 }; 567 568 struct mqd_update_info { 569 union { 570 struct { 571 uint32_t count; /* Must be a multiple of 32 */ 572 uint32_t *ptr; 573 } cu_mask; 574 }; 575 enum mqd_update_flag update_flag; 576 }; 577 578 /** 579 * struct queue 580 * 581 * @list: Queue linked list. 582 * 583 * @mqd: The queue MQD (memory queue descriptor). 584 * 585 * @mqd_mem_obj: The MQD local gpu memory object. 586 * 587 * @gart_mqd_addr: The MQD gart mc address. 588 * 589 * @properties: The queue properties. 590 * 591 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 592 * that the queue should be executed on. 593 * 594 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 595 * id. 596 * 597 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 598 * 599 * @process: The kfd process that created this queue. 600 * 601 * @device: The kfd device that created this queue. 602 * 603 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 604 * otherwise. 605 * 606 * This structure represents user mode compute queues. 607 * It contains all the necessary data to handle such queues. 608 * 609 */ 610 611 struct queue { 612 struct list_head list; 613 void *mqd; 614 struct kfd_mem_obj *mqd_mem_obj; 615 uint64_t gart_mqd_addr; 616 struct queue_properties properties; 617 618 uint32_t mec; 619 uint32_t pipe; 620 uint32_t queue; 621 622 unsigned int sdma_id; 623 unsigned int doorbell_id; 624 625 struct kfd_process *process; 626 struct kfd_node *device; 627 void *gws; 628 629 /* procfs */ 630 struct kobject kobj; 631 632 void *gang_ctx_bo; 633 uint64_t gang_ctx_gpu_addr; 634 void *gang_ctx_cpu_ptr; 635 636 struct amdgpu_bo *wptr_bo_gart; 637 }; 638 639 enum KFD_MQD_TYPE { 640 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 641 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 642 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 643 KFD_MQD_TYPE_DIQ, /* for diq */ 644 KFD_MQD_TYPE_MAX 645 }; 646 647 enum KFD_PIPE_PRIORITY { 648 KFD_PIPE_PRIORITY_CS_LOW = 0, 649 KFD_PIPE_PRIORITY_CS_MEDIUM, 650 KFD_PIPE_PRIORITY_CS_HIGH 651 }; 652 653 struct scheduling_resources { 654 unsigned int vmid_mask; 655 enum kfd_queue_type type; 656 uint64_t queue_mask; 657 uint64_t gws_mask; 658 uint32_t oac_mask; 659 uint32_t gds_heap_base; 660 uint32_t gds_heap_size; 661 }; 662 663 struct process_queue_manager { 664 /* data */ 665 struct kfd_process *process; 666 struct list_head queues; 667 unsigned long *queue_slot_bitmap; 668 }; 669 670 struct qcm_process_device { 671 /* The Device Queue Manager that owns this data */ 672 struct device_queue_manager *dqm; 673 struct process_queue_manager *pqm; 674 /* Queues list */ 675 struct list_head queues_list; 676 struct list_head priv_queue_list; 677 678 unsigned int queue_count; 679 unsigned int vmid; 680 bool is_debug; 681 unsigned int evicted; /* eviction counter, 0=active */ 682 683 /* This flag tells if we should reset all wavefronts on 684 * process termination 685 */ 686 bool reset_wavefronts; 687 688 /* This flag tells us if this process has a GWS-capable 689 * queue that will be mapped into the runlist. It's 690 * possible to request a GWS BO, but not have the queue 691 * currently mapped, and this changes how the MAP_PROCESS 692 * PM4 packet is configured. 693 */ 694 bool mapped_gws_queue; 695 696 /* All the memory management data should be here too */ 697 uint64_t gds_context_area; 698 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 699 uint64_t page_table_base; 700 uint32_t sh_mem_config; 701 uint32_t sh_mem_bases; 702 uint32_t sh_mem_ape1_base; 703 uint32_t sh_mem_ape1_limit; 704 uint32_t gds_size; 705 uint32_t num_gws; 706 uint32_t num_oac; 707 uint32_t sh_hidden_private_base; 708 uint32_t vm_cntx_cntl; 709 710 /* CWSR memory */ 711 struct kgd_mem *cwsr_mem; 712 void *cwsr_kaddr; 713 uint64_t cwsr_base; 714 uint64_t tba_addr; 715 uint64_t tma_addr; 716 717 /* IB memory */ 718 struct kgd_mem *ib_mem; 719 uint64_t ib_base; 720 void *ib_kaddr; 721 722 /* doorbells for kfd process */ 723 struct amdgpu_bo *proc_doorbells; 724 725 /* bitmap for dynamic doorbell allocation from the bo */ 726 unsigned long *doorbell_bitmap; 727 }; 728 729 /* KFD Memory Eviction */ 730 731 /* Approx. wait time before attempting to restore evicted BOs */ 732 #define PROCESS_RESTORE_TIME_MS 100 733 /* Approx. back off time if restore fails due to lack of memory */ 734 #define PROCESS_BACK_OFF_TIME_MS 100 735 /* Approx. time before evicting the process again */ 736 #define PROCESS_ACTIVE_TIME_MS 10 737 738 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 739 * idr_handle in the least significant 4 bytes 740 */ 741 #define MAKE_HANDLE(gpu_id, idr_handle) \ 742 (((uint64_t)(gpu_id) << 32) + idr_handle) 743 #define GET_GPU_ID(handle) (handle >> 32) 744 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 745 746 enum kfd_pdd_bound { 747 PDD_UNBOUND = 0, 748 PDD_BOUND, 749 PDD_BOUND_SUSPENDED, 750 }; 751 752 #define MAX_SYSFS_FILENAME_LEN 15 753 754 /* 755 * SDMA counter runs at 100MHz frequency. 756 * We display SDMA activity in microsecond granularity in sysfs. 757 * As a result, the divisor is 100. 758 */ 759 #define SDMA_ACTIVITY_DIVISOR 100 760 761 /* Data that is per-process-per device. */ 762 struct kfd_process_device { 763 /* The device that owns this data. */ 764 struct kfd_node *dev; 765 766 /* The process that owns this kfd_process_device. */ 767 struct kfd_process *process; 768 769 /* per-process-per device QCM data structure */ 770 struct qcm_process_device qpd; 771 772 /*Apertures*/ 773 uint64_t lds_base; 774 uint64_t lds_limit; 775 uint64_t gpuvm_base; 776 uint64_t gpuvm_limit; 777 uint64_t scratch_base; 778 uint64_t scratch_limit; 779 780 /* VM context for GPUVM allocations */ 781 struct file *drm_file; 782 void *drm_priv; 783 784 /* GPUVM allocations storage */ 785 struct idr alloc_idr; 786 787 /* Flag used to tell the pdd has dequeued from the dqm. 788 * This is used to prevent dev->dqm->ops.process_termination() from 789 * being called twice when it is already called in IOMMU callback 790 * function. 791 */ 792 bool already_dequeued; 793 bool runtime_inuse; 794 795 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 796 enum kfd_pdd_bound bound; 797 798 /* VRAM usage */ 799 atomic64_t vram_usage; 800 struct attribute attr_vram; 801 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 802 803 /* SDMA activity tracking */ 804 uint64_t sdma_past_activity_counter; 805 struct attribute attr_sdma; 806 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 807 808 /* Eviction activity tracking */ 809 uint64_t last_evict_timestamp; 810 atomic64_t evict_duration_counter; 811 struct attribute attr_evict; 812 813 struct kobject *kobj_stats; 814 815 /* 816 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 817 * that is associated with device encoded by "this" struct instance. The 818 * value reflects CU usage by all of the waves launched by this process 819 * on this device. A very important property of occupancy parameter is 820 * that its value is a snapshot of current use. 821 * 822 * Following is to be noted regarding how this parameter is reported: 823 * 824 * The number of waves that a CU can launch is limited by couple of 825 * parameters. These are encoded by struct amdgpu_cu_info instance 826 * that is part of every device definition. For GFX9 devices this 827 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 828 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 829 * when they do use scratch memory. This could change for future 830 * devices and therefore this example should be considered as a guide. 831 * 832 * All CU's of a device are available for the process. This may not be true 833 * under certain conditions - e.g. CU masking. 834 * 835 * Finally number of CU's that are occupied by a process is affected by both 836 * number of CU's a device has along with number of other competing processes 837 */ 838 struct attribute attr_cu_occupancy; 839 840 /* sysfs counters for GPU retry fault and page migration tracking */ 841 struct kobject *kobj_counters; 842 struct attribute attr_faults; 843 struct attribute attr_page_in; 844 struct attribute attr_page_out; 845 uint64_t faults; 846 uint64_t page_in; 847 uint64_t page_out; 848 849 /* Exception code status*/ 850 uint64_t exception_status; 851 void *vm_fault_exc_data; 852 size_t vm_fault_exc_data_size; 853 854 /* Tracks debug per-vmid request settings */ 855 uint32_t spi_dbg_override; 856 uint32_t spi_dbg_launch_mode; 857 uint32_t watch_points[4]; 858 uint32_t alloc_watch_ids; 859 860 /* 861 * If this process has been checkpointed before, then the user 862 * application will use the original gpu_id on the 863 * checkpointed node to refer to this device. 864 */ 865 uint32_t user_gpu_id; 866 867 void *proc_ctx_bo; 868 uint64_t proc_ctx_gpu_addr; 869 void *proc_ctx_cpu_ptr; 870 871 /* Tracks queue reset status */ 872 bool has_reset_queue; 873 874 u32 pasid; 875 /* Indicates this process has requested PTL stay disabled */ 876 bool ptl_disable_req; 877 }; 878 879 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 880 881 struct svm_range_list { 882 struct mutex lock; 883 struct rb_root_cached objects; 884 struct list_head list; 885 struct work_struct deferred_list_work; 886 struct list_head deferred_range_list; 887 struct list_head criu_svm_metadata_list; 888 spinlock_t deferred_list_lock; 889 atomic_t evicted_ranges; 890 atomic_t drain_pagefaults; 891 struct delayed_work restore_work; 892 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 893 struct task_struct *faulting_task; 894 /* check point ts decides if page fault recovery need be dropped */ 895 uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; 896 897 /* Default granularity to use in buffer migration 898 * and restoration of backing memory while handling 899 * recoverable page faults 900 */ 901 uint8_t default_granularity; 902 }; 903 904 /* Process data */ 905 struct kfd_process { 906 /* 907 * kfd_process are stored in an mm_struct*->kfd_process* 908 * hash table (kfd_processes in kfd_process.c) 909 */ 910 struct hlist_node kfd_processes; 911 912 /* 913 * Opaque pointer to mm_struct. We don't hold a reference to 914 * it so it should never be dereferenced from here. This is 915 * only used for looking up processes by their mm. 916 */ 917 void *mm; 918 919 struct kref ref; 920 struct work_struct release_work; 921 922 struct mutex mutex; 923 924 /* 925 * In any process, the thread that started main() is the lead 926 * thread and outlives the rest. 927 * It is here because amd_iommu_bind_pasid wants a task_struct. 928 * It can also be used for safely getting a reference to the 929 * mm_struct of the process. 930 */ 931 struct task_struct *lead_thread; 932 933 /* We want to receive a notification when the mm_struct is destroyed */ 934 struct mmu_notifier mmu_notifier; 935 936 /* 937 * Array of kfd_process_device pointers, 938 * one for each device the process is using. 939 */ 940 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 941 uint32_t n_pdds; 942 943 struct process_queue_manager pqm; 944 945 /*Is the user space process 32 bit?*/ 946 bool is_32bit_user_mode; 947 948 /* Event-related data */ 949 struct mutex event_mutex; 950 /* Event ID allocator and lookup */ 951 struct idr event_idr; 952 /* Event page */ 953 u64 signal_handle; 954 struct kfd_signal_page *signal_page; 955 size_t signal_mapped_size; 956 size_t signal_event_count; 957 bool signal_event_limit_reached; 958 959 /* Information used for memory eviction */ 960 void *kgd_process_info; 961 /* Eviction fence that is attached to all the BOs of this process. The 962 * fence will be triggered during eviction and new one will be created 963 * during restore 964 */ 965 struct dma_fence __rcu *ef; 966 967 /* Work items for evicting and restoring BOs */ 968 struct delayed_work eviction_work; 969 struct delayed_work restore_work; 970 /* seqno of the last scheduled eviction */ 971 unsigned int last_eviction_seqno; 972 /* Approx. the last timestamp (in jiffies) when the process was 973 * restored after an eviction 974 */ 975 unsigned long last_restore_timestamp; 976 977 /* Indicates device process is debug attached with reserved vmid. */ 978 bool debug_trap_enabled; 979 980 /* per-process-per device debug event fd file */ 981 struct file *dbg_ev_file; 982 983 /* If the process is a kfd debugger, we need to know so we can clean 984 * up at exit time. If a process enables debugging on itself, it does 985 * its own clean-up, so we don't set the flag here. We track this by 986 * counting the number of processes this process is debugging. 987 */ 988 atomic_t debugged_process_count; 989 990 /* If the process is a debugged, this is the debugger process */ 991 struct kfd_process *debugger_process; 992 993 /* Kobj for our procfs */ 994 struct kobject *kobj; 995 struct kobject *kobj_queues; 996 struct attribute attr_pasid; 997 998 /* Exception code enable mask and status */ 999 uint64_t exception_enable_mask; 1000 uint64_t exception_status; 1001 1002 /* Used to drain stale interrupts */ 1003 wait_queue_head_t wait_irq_drain; 1004 bool irq_drain_is_open; 1005 1006 /* shared virtual memory registered by this process */ 1007 struct svm_range_list svms; 1008 1009 bool xnack_enabled; 1010 1011 /* Work area for debugger event writer worker. */ 1012 struct work_struct debug_event_workarea; 1013 1014 /* Tracks debug per-vmid request for debug flags */ 1015 u32 dbg_flags; 1016 1017 atomic_t poison; 1018 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 1019 bool queues_paused; 1020 1021 /* Tracks runtime enable status */ 1022 struct semaphore runtime_enable_sema; 1023 bool is_runtime_retry; 1024 struct kfd_runtime_info runtime_info; 1025 1026 /* if gpu page fault sent to KFD */ 1027 bool gpu_page_fault; 1028 1029 /*kfd context id */ 1030 u16 context_id; 1031 1032 /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */ 1033 struct ida id_table; 1034 1035 }; 1036 1037 #define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */ 1038 #define KFD_CONTEXT_ID_PRIMARY 0xFFFF 1039 #define KFD_CONTEXT_ID_MIN 0 1040 1041 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 1042 extern struct srcu_struct kfd_processes_srcu; 1043 1044 /** 1045 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 1046 * 1047 * @filep: pointer to file structure. 1048 * @p: amdkfd process pointer. 1049 * @data: pointer to arg that was copied from user. 1050 * 1051 * Return: returns ioctl completion code. 1052 */ 1053 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 1054 void *data); 1055 1056 typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize); 1057 1058 struct amdkfd_ioctl_desc { 1059 unsigned int cmd; 1060 int flags; 1061 amdkfd_ioctl_t *func; 1062 amdkfd_ioctl_validate_t *validate; 1063 unsigned int cmd_drv; 1064 const char *name; 1065 }; 1066 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1067 1068 struct kfd_process *create_process(const struct task_struct *thread, bool primary); 1069 int kfd_process_create_wq(void); 1070 void kfd_process_destroy_wq(void); 1071 void kfd_cleanup_processes(void); 1072 struct kfd_process *kfd_create_process(struct task_struct *thread); 1073 int kfd_create_process_sysfs(struct kfd_process *process); 1074 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid, 1075 struct kfd_process_device **pdd); 1076 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1077 struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id); 1078 1079 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1080 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1081 uint32_t *gpuid, uint32_t *gpuidx); 1082 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1083 uint32_t gpuidx, uint32_t *gpuid) { 1084 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1085 } 1086 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1087 struct kfd_process *p, uint32_t gpuidx) { 1088 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1089 } 1090 1091 void kfd_unref_process(struct kfd_process *p); 1092 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1093 int kfd_process_restore_queues(struct kfd_process *p); 1094 void kfd_suspend_all_processes(void); 1095 int kfd_resume_all_processes(void); 1096 1097 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1098 uint32_t gpu_id); 1099 1100 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1101 1102 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1103 struct file *drm_file); 1104 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1105 struct kfd_process *p); 1106 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1107 struct kfd_process *p); 1108 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1109 struct kfd_process *p); 1110 1111 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1112 1113 void kfd_process_notifier_release_internal(struct kfd_process *p); 1114 1115 /* KFD process API for creating and translating handles */ 1116 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1117 void *mem); 1118 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1119 int handle); 1120 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1121 int handle); 1122 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1123 1124 /* PASIDs */ 1125 int kfd_pasid_init(void); 1126 void kfd_pasid_exit(void); 1127 u32 kfd_pasid_alloc(void); 1128 void kfd_pasid_free(u32 pasid); 1129 1130 /* Doorbells */ 1131 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1132 int kfd_doorbell_init(struct kfd_dev *kfd); 1133 void kfd_doorbell_fini(struct kfd_dev *kfd); 1134 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1135 struct vm_area_struct *vma); 1136 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1137 unsigned int *doorbell_off); 1138 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1139 u32 read_kernel_doorbell(u32 __iomem *db); 1140 void write_kernel_doorbell(void __iomem *db, u32 value); 1141 void write_kernel_doorbell64(void __iomem *db, u64 value); 1142 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1143 struct kfd_process_device *pdd, 1144 unsigned int doorbell_id); 1145 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1146 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1147 struct kfd_process_device *pdd); 1148 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1149 struct kfd_process_device *pdd); 1150 /* GTT Sub-Allocator */ 1151 1152 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1153 struct kfd_mem_obj **mem_obj); 1154 1155 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1156 1157 extern struct device *kfd_device; 1158 1159 /* KFD's procfs */ 1160 void kfd_procfs_init(void); 1161 void kfd_procfs_shutdown(void); 1162 int kfd_procfs_add_queue(struct queue *q); 1163 void kfd_procfs_del_queue(struct queue *q); 1164 1165 /* Topology */ 1166 int kfd_topology_init(void); 1167 void kfd_topology_shutdown(void); 1168 int kfd_topology_add_device(struct kfd_node *gpu); 1169 int kfd_topology_remove_device(struct kfd_node *gpu); 1170 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1171 uint32_t proximity_domain); 1172 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1173 uint32_t proximity_domain); 1174 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1175 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1176 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1177 uint32_t vmid) 1178 { 1179 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1180 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1181 } 1182 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1183 uint32_t node_id, uint32_t vmid) { 1184 struct kfd_dev *dev = adev->kfd.dev; 1185 uint32_t i; 1186 1187 /* 1188 * On multi-aid system, attempt per-node matching. Otherwise, 1189 * fall back to the first node. 1190 */ 1191 if (!amdgpu_is_multi_aid(adev)) 1192 return dev->nodes[0]; 1193 1194 for (i = 0; i < dev->num_nodes; i++) 1195 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1196 return dev->nodes[i]; 1197 1198 return NULL; 1199 } 1200 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1201 uint32_t kfd_topology_get_num_devices(void); 1202 int kfd_numa_node_to_apic_id(int numa_node_id); 1203 uint32_t kfd_gpu_node_num(void); 1204 1205 /* Interrupts */ 1206 #define KFD_IRQ_FENCE_CLIENTID 0xff 1207 #define KFD_IRQ_FENCE_SOURCEID 0xff 1208 #define KFD_IRQ_IS_FENCE(client, source) \ 1209 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1210 (source) == KFD_IRQ_FENCE_SOURCEID) 1211 int kfd_interrupt_init(struct kfd_node *dev); 1212 void kfd_interrupt_exit(struct kfd_node *dev); 1213 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1214 bool interrupt_is_wanted(struct kfd_node *dev, 1215 const uint32_t *ih_ring_entry, 1216 uint32_t *patched_ihre, bool *flag); 1217 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1218 void kfd_process_close_interrupt_drain(unsigned int pasid); 1219 1220 /* amdkfd Apertures */ 1221 int kfd_init_apertures(struct kfd_process *process); 1222 1223 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1224 uint64_t tba_addr, 1225 uint64_t tma_addr); 1226 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1227 bool enabled); 1228 1229 /* CRIU */ 1230 /* 1231 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1232 * structures: 1233 * kfd_criu_process_priv_data 1234 * kfd_criu_device_priv_data 1235 * kfd_criu_bo_priv_data 1236 * kfd_criu_queue_priv_data 1237 * kfd_criu_event_priv_data 1238 * kfd_criu_svm_range_priv_data 1239 */ 1240 1241 #define KFD_CRIU_PRIV_VERSION 1 1242 1243 struct kfd_criu_process_priv_data { 1244 uint32_t version; 1245 uint32_t xnack_mode; 1246 }; 1247 1248 struct kfd_criu_device_priv_data { 1249 /* For future use */ 1250 uint64_t reserved; 1251 }; 1252 1253 struct kfd_criu_bo_priv_data { 1254 uint64_t user_addr; 1255 uint32_t idr_handle; 1256 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1257 }; 1258 1259 /* 1260 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1261 * kfd_criu_svm_range_priv_data is the object type 1262 */ 1263 enum kfd_criu_object_type { 1264 KFD_CRIU_OBJECT_TYPE_QUEUE, 1265 KFD_CRIU_OBJECT_TYPE_EVENT, 1266 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1267 }; 1268 1269 struct kfd_criu_svm_range_priv_data { 1270 uint32_t object_type; 1271 uint64_t start_addr; 1272 uint64_t size; 1273 /* Variable length array of attributes */ 1274 struct kfd_ioctl_svm_attribute attrs[]; 1275 }; 1276 1277 struct kfd_criu_queue_priv_data { 1278 uint32_t object_type; 1279 uint64_t q_address; 1280 uint64_t q_size; 1281 uint64_t read_ptr_addr; 1282 uint64_t write_ptr_addr; 1283 uint64_t doorbell_off; 1284 uint64_t eop_ring_buffer_address; 1285 uint64_t ctx_save_restore_area_address; 1286 uint32_t gpu_id; 1287 uint32_t type; 1288 uint32_t format; 1289 uint32_t q_id; 1290 uint32_t priority; 1291 uint32_t q_percent; 1292 uint32_t doorbell_id; 1293 uint32_t gws; 1294 uint32_t sdma_id; 1295 uint32_t eop_ring_buffer_size; 1296 uint32_t ctx_save_restore_area_size; 1297 uint32_t ctl_stack_size; 1298 uint32_t mqd_size; 1299 }; 1300 1301 struct kfd_criu_event_priv_data { 1302 uint32_t object_type; 1303 uint64_t user_handle; 1304 uint32_t event_id; 1305 uint32_t auto_reset; 1306 uint32_t type; 1307 uint32_t signaled; 1308 1309 union { 1310 struct kfd_hsa_memory_exception_data memory_exception_data; 1311 struct kfd_hsa_hw_exception_data hw_exception_data; 1312 }; 1313 }; 1314 1315 int kfd_process_get_queue_info(struct kfd_process *p, 1316 uint32_t *num_queues, 1317 uint64_t *priv_data_sizes); 1318 1319 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1320 uint8_t __user *user_priv_data, 1321 uint64_t *priv_data_offset); 1322 1323 int kfd_criu_restore_queue(struct kfd_process *p, 1324 uint8_t __user *user_priv_data, 1325 uint64_t *priv_data_offset, 1326 uint64_t max_priv_data_size); 1327 1328 int kfd_criu_checkpoint_events(struct kfd_process *p, 1329 uint8_t __user *user_priv_data, 1330 uint64_t *priv_data_offset); 1331 1332 int kfd_criu_restore_event(struct file *devkfd, 1333 struct kfd_process *p, 1334 uint8_t __user *user_priv_data, 1335 uint64_t *priv_data_offset, 1336 uint64_t max_priv_data_size); 1337 /* CRIU - End */ 1338 1339 /* Queue Context Management */ 1340 int init_queue(struct queue **q, const struct queue_properties *properties); 1341 void uninit_queue(struct queue *q); 1342 void print_queue_properties(struct queue_properties *q); 1343 void print_queue(struct queue *q); 1344 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo, 1345 u64 expected_size); 1346 void kfd_queue_buffer_put(struct amdgpu_bo **bo); 1347 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1348 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1349 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo); 1350 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd, 1351 struct queue_properties *properties); 1352 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev); 1353 1354 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1355 struct kfd_node *dev); 1356 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1357 struct kfd_node *dev); 1358 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1359 struct kfd_node *dev); 1360 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1361 struct kfd_node *dev); 1362 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1363 struct kfd_node *dev); 1364 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 1365 struct kfd_node *dev); 1366 struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, 1367 struct kfd_node *dev); 1368 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1369 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1370 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1371 enum kfd_queue_type type); 1372 void kernel_queue_uninit(struct kernel_queue *kq); 1373 int kfd_evict_process_device(struct kfd_process_device *pdd); 1374 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id); 1375 1376 /* Process Queue Manager */ 1377 struct process_queue_node { 1378 struct queue *q; 1379 struct kernel_queue *kq; 1380 struct list_head process_queue_list; 1381 }; 1382 1383 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1384 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1385 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1386 void pqm_uninit(struct process_queue_manager *pqm); 1387 int pqm_create_queue(struct process_queue_manager *pqm, 1388 struct kfd_node *dev, 1389 struct queue_properties *properties, 1390 unsigned int *qid, 1391 const struct kfd_criu_queue_priv_data *q_data, 1392 const void *restore_mqd, 1393 const void *restore_ctl_stack, 1394 uint32_t *p_doorbell_offset_in_process); 1395 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1396 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1397 struct queue_properties *p); 1398 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1399 struct mqd_update_info *minfo); 1400 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1401 void *gws); 1402 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1403 unsigned int qid); 1404 int pqm_get_wave_state(struct process_queue_manager *pqm, 1405 unsigned int qid, 1406 void __user *ctl_stack, 1407 u32 *ctl_stack_used_size, 1408 u32 *save_area_used_size); 1409 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1410 uint64_t exception_clear_mask, 1411 void __user *buf, 1412 int *num_qss_entries, 1413 uint32_t *entry_size); 1414 1415 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1416 uint64_t fence_value, 1417 unsigned int timeout_ms); 1418 1419 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1420 unsigned int qid, 1421 u32 *mqd_size, 1422 u32 *ctl_stack_size); 1423 /* Packet Manager */ 1424 1425 #define KFD_FENCE_COMPLETED (100) 1426 #define KFD_FENCE_INIT (10) 1427 1428 /** 1429 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring 1430 * dequeue wait counts. 1431 * 1432 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a 1433 * certain ASICs. For these ASICs, this is default value used by RESET 1434 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value 1435 * for certain ASICs. For others set it to default hardware reset value 1436 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait 1437 * 1438 */ 1439 enum kfd_config_dequeue_wait_counts_cmd { 1440 KFD_DEQUEUE_WAIT_INIT = 1, 1441 KFD_DEQUEUE_WAIT_RESET = 2, 1442 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3 1443 }; 1444 1445 1446 struct packet_manager { 1447 struct device_queue_manager *dqm; 1448 struct kernel_queue *priv_queue; 1449 struct mutex lock; 1450 bool allocated; 1451 struct kfd_mem_obj *ib_buffer_obj; 1452 unsigned int ib_size_bytes; 1453 bool is_over_subscription; 1454 1455 const struct packet_manager_funcs *pmf; 1456 }; 1457 1458 struct packet_manager_funcs { 1459 /* Support ASIC-specific packet formats for PM4 packets */ 1460 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1461 struct qcm_process_device *qpd); 1462 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1463 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1464 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1465 struct scheduling_resources *res); 1466 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1467 struct queue *q, bool is_static); 1468 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1469 enum kfd_unmap_queues_filter mode, 1470 uint32_t filter_param, bool reset); 1471 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer, 1472 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value); 1473 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1474 uint64_t fence_address, uint64_t fence_value); 1475 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1476 1477 /* Packet sizes */ 1478 int map_process_size; 1479 int runlist_size; 1480 int set_resources_size; 1481 int map_queues_size; 1482 int unmap_queues_size; 1483 int config_dequeue_wait_counts_size; 1484 int query_status_size; 1485 int release_mem_size; 1486 }; 1487 1488 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1489 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1490 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1491 1492 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1493 void pm_uninit(struct packet_manager *pm); 1494 int pm_send_set_resources(struct packet_manager *pm, 1495 struct scheduling_resources *res); 1496 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1497 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1498 uint64_t fence_value); 1499 1500 int pm_send_unmap_queue(struct packet_manager *pm, 1501 enum kfd_unmap_queues_filter mode, 1502 uint32_t filter_param, bool reset); 1503 1504 void pm_release_ib(struct packet_manager *pm); 1505 1506 int pm_config_dequeue_wait_counts(struct packet_manager *pm, 1507 enum kfd_config_dequeue_wait_counts_cmd cmd, 1508 uint32_t wait_counts_config); 1509 1510 /* Following PM funcs can be shared among VI and AI */ 1511 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1512 1513 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1514 1515 /* Events */ 1516 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1517 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1518 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; 1519 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1520 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1521 extern const struct kfd_event_interrupt_class event_interrupt_class_v12_1; 1522 1523 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1524 1525 int kfd_event_init_process(struct kfd_process *p); 1526 void kfd_event_free_process(struct kfd_process *p); 1527 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); 1528 int kfd_wait_on_events(struct kfd_process *p, 1529 uint32_t num_events, void __user *data, 1530 bool all, uint32_t *user_timeout_ms, 1531 uint32_t *wait_result); 1532 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1533 uint32_t valid_id_bits, bool signal_mailbox_updated); 1534 void kfd_signal_hw_exception_event(u32 pasid); 1535 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1536 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1537 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1538 1539 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1540 uint32_t event_type, bool auto_reset, uint32_t node_id, 1541 uint32_t *event_id, uint32_t *event_trigger_data, 1542 uint64_t *event_page_offset, uint32_t *event_slot_index); 1543 1544 int kfd_get_num_events(struct kfd_process *p); 1545 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1546 1547 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va); 1548 1549 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, 1550 struct kfd_vm_fault_info *info, 1551 struct kfd_hsa_memory_exception_data *data); 1552 1553 void kfd_signal_reset_event(struct kfd_node *dev); 1554 1555 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1556 void kfd_signal_process_terminate_event(struct kfd_process *p); 1557 1558 static inline void kfd_flush_tlb(struct kfd_process_device *pdd) 1559 { 1560 struct amdgpu_device *adev = pdd->dev->adev; 1561 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); 1562 1563 amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT, 1564 pdd->dev->xcc_mask); 1565 } 1566 1567 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1568 { 1569 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) || 1570 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1571 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1572 } 1573 1574 int kfd_send_exception_to_runtime(struct kfd_process *p, 1575 unsigned int queue_id, 1576 uint64_t error_reason); 1577 bool kfd_is_locked(struct kfd_dev *kfd); 1578 1579 /* Compute profile */ 1580 void kfd_inc_compute_active(struct kfd_node *dev); 1581 void kfd_dec_compute_active(struct kfd_node *dev); 1582 1583 /* Cgroup Support */ 1584 /* Check with device cgroup if @kfd device is accessible */ 1585 static inline int kfd_devcgroup_check_permission(struct kfd_node *node) 1586 { 1587 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1588 struct drm_device *ddev; 1589 1590 if (node->xcp) 1591 ddev = node->xcp->ddev; 1592 else 1593 ddev = adev_to_drm(node->adev); 1594 1595 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1596 ddev->render->index, 1597 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1598 #else 1599 return 0; 1600 #endif 1601 } 1602 1603 static inline bool kfd_is_first_node(struct kfd_node *node) 1604 { 1605 return (node == node->kfd->nodes[0]); 1606 } 1607 1608 /* PTL support */ 1609 int kfd_ptl_disable_request(struct kfd_process_device *pdd, 1610 struct kfd_process *p); 1611 int kfd_ptl_disable_release(struct kfd_process_device *pdd, 1612 struct kfd_process *p); 1613 1614 /* Debugfs */ 1615 #if defined(CONFIG_DEBUG_FS) 1616 1617 void kfd_debugfs_init(void); 1618 void kfd_debugfs_fini(void); 1619 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1620 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1621 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1622 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1623 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1624 int pm_debugfs_runlist(struct seq_file *m, void *data); 1625 1626 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1627 int pm_debugfs_hang_hws(struct packet_manager *pm); 1628 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1629 1630 void kfd_debugfs_add_process(struct kfd_process *p); 1631 void kfd_debugfs_remove_process(struct kfd_process *p); 1632 1633 #else 1634 1635 static inline void kfd_debugfs_init(void) {} 1636 static inline void kfd_debugfs_fini(void) {} 1637 static inline void kfd_debugfs_add_process(struct kfd_process *p) {} 1638 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {} 1639 1640 #endif 1641 1642 #endif 1643