1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <uapi/linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc_obj(*ptr_to_struct)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first chunk is the TBA used for the CWSR ISA code. The second 103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048) 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC 115 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time 116 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is 117 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload 118 * The format here makes CP workload 10% of total timeout 119 */ 120 #define KFD_UNMAP_LATENCY_MS \ 121 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) 122 123 #define KFD_MAX_SDMA_QUEUES 128 124 125 /* 126 * 512 = 0x200 127 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 128 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 129 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 130 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 131 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 132 */ 133 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 134 135 /** 136 * enum kfd_ioctl_flags - KFD ioctl flags 137 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 138 * userspace can use a given ioctl. 139 */ 140 enum kfd_ioctl_flags { 141 /* 142 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 143 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 144 * perform privileged operations and load arbitrary data into MQDs and 145 * eventually HQD registers when the queue is mapped by HWS. In order to 146 * prevent this we should perform additional security checks. 147 * 148 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 149 * 150 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 151 * we also allow ioctls with SYS_ADMIN capability. 152 */ 153 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 154 }; 155 /* 156 * Kernel module parameter to specify maximum number of supported queues per 157 * device 158 */ 159 extern int max_num_of_queues_per_device; 160 161 162 /* Kernel module parameter to specify the scheduling policy */ 163 extern int sched_policy; 164 165 /* 166 * Kernel module parameter to specify the maximum process 167 * number per HW scheduler 168 */ 169 extern int hws_max_conc_proc; 170 171 extern int cwsr_enable; 172 173 /* 174 * Kernel module parameter to specify whether to send sigterm to HSA process on 175 * unhandled exception 176 */ 177 extern int send_sigterm; 178 179 /* 180 * This kernel module is used to simulate large bar machine on non-large bar 181 * enabled machines. 182 */ 183 extern int debug_largebar; 184 185 /* Set sh_mem_config.retry_disable on GFX v9 */ 186 extern int amdgpu_noretry; 187 188 /* Halt if HWS hang is detected */ 189 extern int halt_if_hws_hang; 190 191 /* Whether MEC FW support GWS barriers */ 192 extern bool hws_gws_support; 193 194 /* Queue preemption timeout in ms */ 195 extern int queue_preemption_timeout_ms; 196 197 /* 198 * Don't evict process queues on vm fault 199 */ 200 extern int amdgpu_no_queue_eviction_on_vm_fault; 201 202 /* Enable eviction debug messages */ 203 extern bool debug_evictions; 204 205 extern struct mutex kfd_processes_mutex; 206 207 enum cache_policy { 208 cache_policy_coherent, 209 cache_policy_noncoherent 210 }; 211 212 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0)) 213 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 214 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 215 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 216 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ 217 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ 218 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) 219 220 struct kfd_node; 221 222 struct kfd_event_interrupt_class { 223 bool (*interrupt_isr)(struct kfd_node *dev, 224 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 225 bool *patched_flag); 226 void (*interrupt_wq)(struct kfd_node *dev, 227 const uint32_t *ih_ring_entry); 228 }; 229 230 struct kfd_device_info { 231 uint32_t gfx_target_version; 232 const struct kfd_event_interrupt_class *event_interrupt_class; 233 unsigned int max_pasid_bits; 234 unsigned int max_no_of_hqd; 235 unsigned int doorbell_size; 236 size_t ih_ring_entry_size; 237 uint8_t num_of_watch_points; 238 uint16_t mqd_size_aligned; 239 bool supports_cwsr; 240 bool needs_pci_atomics; 241 uint32_t no_atomic_fw_version; 242 unsigned int num_sdma_queues_per_engine; 243 unsigned int num_reserved_sdma_queues_per_engine; 244 }; 245 246 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 247 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 248 249 struct kfd_mem_obj { 250 uint32_t range_start; 251 uint32_t range_end; 252 uint64_t gpu_addr; 253 uint32_t *cpu_ptr; 254 void *mem; 255 }; 256 257 struct kfd_vmid_info { 258 uint32_t first_vmid_kfd; 259 uint32_t last_vmid_kfd; 260 uint32_t vmid_num_kfd; 261 }; 262 263 #define MAX_KFD_NODES 8 264 265 struct kfd_dev; 266 267 struct kfd_node { 268 unsigned int node_id; 269 struct amdgpu_device *adev; /* Duplicated here along with keeping 270 * a copy in kfd_dev to save a hop 271 */ 272 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 273 * keeping a copy in kfd_dev to 274 * save a hop 275 */ 276 struct kfd_vmid_info vm_info; 277 unsigned int id; /* topology stub index */ 278 uint32_t xcc_mask; /* Instance mask of XCCs present */ 279 struct amdgpu_xcp *xcp; 280 281 /* Interrupts */ 282 struct kfifo ih_fifo; 283 struct work_struct interrupt_work; 284 spinlock_t interrupt_lock; 285 286 /* 287 * Interrupts of interest to KFD are copied 288 * from the HW ring into a SW ring. 289 */ 290 bool interrupts_active; 291 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 292 293 /* QCM Device instance */ 294 struct device_queue_manager *dqm; 295 296 /* Global GWS resource shared between processes */ 297 void *gws; 298 299 /* Clients watching SMI events */ 300 struct list_head smi_clients; 301 spinlock_t smi_lock; 302 uint32_t reset_seq_num; 303 304 /* SRAM ECC flag */ 305 atomic_t sram_ecc_flag; 306 307 /*spm process id */ 308 unsigned int spm_pasid; 309 310 /* Maximum process number mapped to HW scheduler */ 311 unsigned int max_proc_per_quantum; 312 313 unsigned int compute_vmid_bitmap; 314 315 struct kfd_local_mem_info local_mem_info; 316 317 struct kfd_dev *kfd; 318 319 /* Track per device allocated watch points */ 320 uint32_t alloc_watch_ids; 321 spinlock_t watch_points_lock; 322 }; 323 324 struct kfd_dev { 325 struct amdgpu_device *adev; 326 327 struct kfd_device_info device_info; 328 329 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 330 * page used by kernel queue 331 */ 332 333 struct kgd2kfd_shared_resources shared_resources; 334 335 const struct kfd2kgd_calls *kfd2kgd; 336 struct mutex doorbell_mutex; 337 338 void *gtt_mem; 339 uint64_t gtt_start_gpu_addr; 340 void *gtt_start_cpu_ptr; 341 void *gtt_sa_bitmap; 342 struct mutex gtt_sa_lock; 343 unsigned int gtt_sa_chunk_size; 344 unsigned int gtt_sa_num_of_chunks; 345 346 bool init_complete; 347 348 /* Firmware versions */ 349 uint16_t mec_fw_version; 350 uint16_t mec2_fw_version; 351 uint16_t sdma_fw_version; 352 353 /* CWSR */ 354 bool cwsr_enabled; 355 const void *cwsr_isa; 356 unsigned int cwsr_isa_size; 357 358 /* xGMI */ 359 uint64_t hive_id; 360 361 bool pci_atomic_requested; 362 363 /* Compute Profile ref. count */ 364 atomic_t compute_profile; 365 366 struct ida doorbell_ida; 367 unsigned int max_doorbell_slices; 368 369 int noretry; 370 371 struct kfd_node *nodes[MAX_KFD_NODES]; 372 unsigned int num_nodes; 373 374 struct workqueue_struct *ih_wq; 375 376 /* Kernel doorbells for KFD device */ 377 struct amdgpu_bo *doorbells; 378 379 /* bitmap for dynamic doorbell allocation from doorbell object */ 380 unsigned long *doorbell_bitmap; 381 382 /* for dynamic partitioning */ 383 int kfd_dev_lock; 384 385 atomic_t kfd_processes_count; 386 387 /* Lock for profiler process */ 388 struct mutex profiler_lock; 389 /* Process currently holding the lock */ 390 struct kfd_process *profiler_process; 391 }; 392 393 enum kfd_mempool { 394 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 395 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 396 KFD_MEMPOOL_FRAMEBUFFER = 3, 397 }; 398 399 /* Character device interface */ 400 int kfd_chardev_init(void); 401 void kfd_chardev_exit(void); 402 void kfd_dev_unmap_mapping_range(loff_t const holebegin, loff_t const holelen); 403 404 /** 405 * enum kfd_unmap_queues_filter - Enum for queue filters. 406 * 407 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 408 * running queues list. 409 * 410 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 411 * in the run list. 412 * 413 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 414 * specific process. 415 * 416 */ 417 enum kfd_unmap_queues_filter { 418 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 419 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 420 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 421 }; 422 423 /** 424 * enum kfd_queue_type - Enum for various queue types. 425 * 426 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 427 * 428 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 429 * 430 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 431 * 432 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 433 * 434 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 435 * 436 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID. 437 */ 438 enum kfd_queue_type { 439 KFD_QUEUE_TYPE_COMPUTE, 440 KFD_QUEUE_TYPE_SDMA, 441 KFD_QUEUE_TYPE_HIQ, 442 KFD_QUEUE_TYPE_SDMA_XGMI, 443 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID 444 }; 445 446 enum kfd_queue_format { 447 KFD_QUEUE_FORMAT_PM4, 448 KFD_QUEUE_FORMAT_AQL 449 }; 450 451 enum KFD_QUEUE_PRIORITY { 452 KFD_QUEUE_PRIORITY_MINIMUM = 0, 453 KFD_QUEUE_PRIORITY_MAXIMUM = 15 454 }; 455 456 /** 457 * struct queue_properties 458 * 459 * @type: The queue type. 460 * 461 * @queue_id: Queue identifier. 462 * 463 * @queue_address: Queue ring buffer address. 464 * 465 * @queue_size: Queue ring buffer size. 466 * 467 * @priority: Defines the queue priority relative to other queues in the 468 * process. 469 * This is just an indication and HW scheduling may override the priority as 470 * necessary while keeping the relative prioritization. 471 * the priority granularity is from 0 to f which f is the highest priority. 472 * currently all queues are initialized with the highest priority. 473 * 474 * @queue_percent: This field is partially implemented and currently a zero in 475 * this field defines that the queue is non active. 476 * 477 * @read_ptr: User space address which points to the number of dwords the 478 * cp read from the ring buffer. This field updates automatically by the H/W. 479 * 480 * @write_ptr: Defines the number of dwords written to the ring buffer. 481 * 482 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 483 * buffer. This field should be similar to write_ptr and the user should 484 * update this field after updating the write_ptr. 485 * 486 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 487 * 488 * @is_interop: Defines if this is a interop queue. Interop queue means that 489 * the queue can access both graphics and compute resources. 490 * 491 * @is_evicted: Defines if the queue is evicted. Only active queues 492 * are evicted, rendering them inactive. 493 * 494 * @is_active: Defines if the queue is active or not. @is_active and 495 * @is_evicted are protected by the DQM lock. 496 * 497 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 498 * @is_gws should be protected by the DQM lock, since changing it can yield the 499 * possibility of updating DQM state on number of GWS queues. 500 * 501 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 502 * of the queue. 503 * 504 * This structure represents the queue properties for each queue no matter if 505 * it's user mode or kernel mode queue. 506 * 507 */ 508 509 struct queue_properties { 510 enum kfd_queue_type type; 511 enum kfd_queue_format format; 512 unsigned int queue_id; 513 uint64_t queue_address; 514 uint64_t queue_size; 515 uint64_t metadata_queue_size; 516 uint32_t priority; 517 uint32_t queue_percent; 518 void __user *read_ptr; 519 void __user *write_ptr; 520 void __iomem *doorbell_ptr; 521 uint32_t doorbell_off; 522 bool is_interop; 523 bool is_evicted; 524 bool is_suspended; 525 bool is_being_destroyed; 526 bool is_active; 527 bool is_gws; 528 uint32_t pm4_target_xcc; 529 bool is_dbg_wa; 530 bool is_user_cu_masked; 531 bool is_reset; 532 /* Not relevant for user mode queues in cp scheduling */ 533 unsigned int vmid; 534 /* Relevant only for sdma queues*/ 535 uint32_t sdma_engine_id; 536 uint32_t sdma_queue_id; 537 uint32_t sdma_vm_addr; 538 /* Relevant only for VI */ 539 uint64_t eop_ring_buffer_address; 540 uint32_t eop_ring_buffer_size; 541 uint64_t ctx_save_restore_area_address; 542 uint32_t ctx_save_restore_area_size; 543 uint32_t ctl_stack_size; 544 uint64_t tba_addr; 545 uint64_t tma_addr; 546 uint64_t exception_status; 547 548 struct amdgpu_bo *wptr_bo; 549 struct amdgpu_bo *rptr_bo; 550 struct amdgpu_bo *ring_bo; 551 struct amdgpu_bo *eop_buf_bo; 552 struct amdgpu_bo *cwsr_bo; 553 }; 554 555 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 556 (q).queue_address != 0 && \ 557 (q).queue_percent > 0 && \ 558 !(q).is_evicted && \ 559 !(q).is_suspended) 560 561 enum mqd_update_flag { 562 UPDATE_FLAG_DBG_WA_ENABLE = 1, 563 UPDATE_FLAG_DBG_WA_DISABLE = 2, 564 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 565 UPDATE_FLAG_PERFCOUNT_ENABLE = 5, 566 UPDATE_FLAG_PERFCOUNT_DISABLE = 6, 567 }; 568 569 struct mqd_update_info { 570 union { 571 struct { 572 uint32_t count; /* Must be a multiple of 32 */ 573 uint32_t *ptr; 574 } cu_mask; 575 }; 576 enum mqd_update_flag update_flag; 577 }; 578 579 /** 580 * struct queue 581 * 582 * @list: Queue linked list. 583 * 584 * @mqd: The queue MQD (memory queue descriptor). 585 * 586 * @mqd_mem_obj: The MQD local gpu memory object. 587 * 588 * @gart_mqd_addr: The MQD gart mc address. 589 * 590 * @properties: The queue properties. 591 * 592 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 593 * that the queue should be executed on. 594 * 595 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 596 * id. 597 * 598 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 599 * 600 * @process: The kfd process that created this queue. 601 * 602 * @device: The kfd device that created this queue. 603 * 604 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 605 * otherwise. 606 * 607 * This structure represents user mode compute queues. 608 * It contains all the necessary data to handle such queues. 609 * 610 */ 611 612 struct queue { 613 struct list_head list; 614 void *mqd; 615 struct kfd_mem_obj *mqd_mem_obj; 616 uint64_t gart_mqd_addr; 617 struct queue_properties properties; 618 619 uint32_t mec; 620 uint32_t pipe; 621 uint32_t queue; 622 623 unsigned int sdma_id; 624 unsigned int doorbell_id; 625 626 struct kfd_process *process; 627 struct kfd_node *device; 628 void *gws; 629 630 /* procfs */ 631 struct kobject kobj; 632 633 void *gang_ctx_bo; 634 uint64_t gang_ctx_gpu_addr; 635 void *gang_ctx_cpu_ptr; 636 637 struct amdgpu_bo *wptr_bo_gart; 638 }; 639 640 enum KFD_MQD_TYPE { 641 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 642 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 643 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 644 KFD_MQD_TYPE_DIQ, /* for diq */ 645 KFD_MQD_TYPE_MAX 646 }; 647 648 enum KFD_PIPE_PRIORITY { 649 KFD_PIPE_PRIORITY_CS_LOW = 0, 650 KFD_PIPE_PRIORITY_CS_MEDIUM, 651 KFD_PIPE_PRIORITY_CS_HIGH 652 }; 653 654 struct scheduling_resources { 655 unsigned int vmid_mask; 656 enum kfd_queue_type type; 657 uint64_t queue_mask; 658 uint64_t gws_mask; 659 uint32_t oac_mask; 660 uint32_t gds_heap_base; 661 uint32_t gds_heap_size; 662 }; 663 664 struct process_queue_manager { 665 /* data */ 666 struct kfd_process *process; 667 struct list_head queues; 668 unsigned long *queue_slot_bitmap; 669 }; 670 671 struct qcm_process_device { 672 /* The Device Queue Manager that owns this data */ 673 struct device_queue_manager *dqm; 674 struct process_queue_manager *pqm; 675 /* Queues list */ 676 struct list_head queues_list; 677 struct list_head priv_queue_list; 678 679 unsigned int queue_count; 680 unsigned int vmid; 681 bool is_debug; 682 unsigned int evicted; /* eviction counter, 0=active */ 683 684 /* This flag tells if we should reset all wavefronts on 685 * process termination 686 */ 687 bool reset_wavefronts; 688 689 /* This flag tells us if this process has a GWS-capable 690 * queue that will be mapped into the runlist. It's 691 * possible to request a GWS BO, but not have the queue 692 * currently mapped, and this changes how the MAP_PROCESS 693 * PM4 packet is configured. 694 */ 695 bool mapped_gws_queue; 696 697 /* All the memory management data should be here too */ 698 uint64_t gds_context_area; 699 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 700 uint64_t page_table_base; 701 uint32_t sh_mem_config; 702 uint32_t sh_mem_bases; 703 uint32_t sh_mem_ape1_base; 704 uint32_t sh_mem_ape1_limit; 705 uint32_t gds_size; 706 uint32_t num_gws; 707 uint32_t num_oac; 708 uint32_t sh_hidden_private_base; 709 uint32_t vm_cntx_cntl; 710 711 /* CWSR memory */ 712 struct kgd_mem *cwsr_mem; 713 void *cwsr_kaddr; 714 uint64_t cwsr_base; 715 uint64_t tba_addr; 716 uint64_t tma_addr; 717 718 /* IB memory */ 719 struct kgd_mem *ib_mem; 720 uint64_t ib_base; 721 void *ib_kaddr; 722 723 /* doorbells for kfd process */ 724 struct amdgpu_bo *proc_doorbells; 725 726 /* bitmap for dynamic doorbell allocation from the bo */ 727 unsigned long *doorbell_bitmap; 728 }; 729 730 /* KFD Memory Eviction */ 731 732 /* Approx. wait time before attempting to restore evicted BOs */ 733 #define PROCESS_RESTORE_TIME_MS 100 734 /* Approx. back off time if restore fails due to lack of memory */ 735 #define PROCESS_BACK_OFF_TIME_MS 100 736 /* Approx. time before evicting the process again */ 737 #define PROCESS_ACTIVE_TIME_MS 10 738 739 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 740 * idr_handle in the least significant 4 bytes 741 */ 742 #define MAKE_HANDLE(gpu_id, idr_handle) \ 743 (((uint64_t)(gpu_id) << 32) + idr_handle) 744 #define GET_GPU_ID(handle) (handle >> 32) 745 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 746 747 enum kfd_pdd_bound { 748 PDD_UNBOUND = 0, 749 PDD_BOUND, 750 PDD_BOUND_SUSPENDED, 751 }; 752 753 #define MAX_SYSFS_FILENAME_LEN 15 754 755 /* 756 * SDMA counter runs at 100MHz frequency. 757 * We display SDMA activity in microsecond granularity in sysfs. 758 * As a result, the divisor is 100. 759 */ 760 #define SDMA_ACTIVITY_DIVISOR 100 761 762 /* Data that is per-process-per device. */ 763 struct kfd_process_device { 764 /* The device that owns this data. */ 765 struct kfd_node *dev; 766 767 /* The process that owns this kfd_process_device. */ 768 struct kfd_process *process; 769 770 /* per-process-per device QCM data structure */ 771 struct qcm_process_device qpd; 772 773 /*Apertures*/ 774 uint64_t lds_base; 775 uint64_t lds_limit; 776 uint64_t gpuvm_base; 777 uint64_t gpuvm_limit; 778 uint64_t scratch_base; 779 uint64_t scratch_limit; 780 781 /* VM context for GPUVM allocations */ 782 struct file *drm_file; 783 void *drm_priv; 784 785 /* GPUVM allocations storage */ 786 struct idr alloc_idr; 787 788 /* Flag used to tell the pdd has dequeued from the dqm. 789 * This is used to prevent dev->dqm->ops.process_termination() from 790 * being called twice when it is already called in IOMMU callback 791 * function. 792 */ 793 bool already_dequeued; 794 bool runtime_inuse; 795 796 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 797 enum kfd_pdd_bound bound; 798 799 /* VRAM usage */ 800 atomic64_t vram_usage; 801 struct attribute attr_vram; 802 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 803 804 /* SDMA activity tracking */ 805 uint64_t sdma_past_activity_counter; 806 struct attribute attr_sdma; 807 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 808 809 /* Eviction activity tracking */ 810 uint64_t last_evict_timestamp; 811 atomic64_t evict_duration_counter; 812 struct attribute attr_evict; 813 814 struct kobject *kobj_stats; 815 816 /* 817 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 818 * that is associated with device encoded by "this" struct instance. The 819 * value reflects CU usage by all of the waves launched by this process 820 * on this device. A very important property of occupancy parameter is 821 * that its value is a snapshot of current use. 822 * 823 * Following is to be noted regarding how this parameter is reported: 824 * 825 * The number of waves that a CU can launch is limited by couple of 826 * parameters. These are encoded by struct amdgpu_cu_info instance 827 * that is part of every device definition. For GFX9 devices this 828 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 829 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 830 * when they do use scratch memory. This could change for future 831 * devices and therefore this example should be considered as a guide. 832 * 833 * All CU's of a device are available for the process. This may not be true 834 * under certain conditions - e.g. CU masking. 835 * 836 * Finally number of CU's that are occupied by a process is affected by both 837 * number of CU's a device has along with number of other competing processes 838 */ 839 struct attribute attr_cu_occupancy; 840 841 /* sysfs counters for GPU retry fault and page migration tracking */ 842 struct kobject *kobj_counters; 843 struct attribute attr_faults; 844 struct attribute attr_page_in; 845 struct attribute attr_page_out; 846 uint64_t faults; 847 uint64_t page_in; 848 uint64_t page_out; 849 850 /* Exception code status*/ 851 uint64_t exception_status; 852 void *vm_fault_exc_data; 853 size_t vm_fault_exc_data_size; 854 855 /* Tracks debug per-vmid request settings */ 856 uint32_t spi_dbg_override; 857 uint32_t spi_dbg_launch_mode; 858 uint32_t watch_points[4]; 859 uint32_t alloc_watch_ids; 860 861 /* 862 * If this process has been checkpointed before, then the user 863 * application will use the original gpu_id on the 864 * checkpointed node to refer to this device. 865 */ 866 uint32_t user_gpu_id; 867 868 void *proc_ctx_bo; 869 uint64_t proc_ctx_gpu_addr; 870 void *proc_ctx_cpu_ptr; 871 872 /* Tracks queue reset status */ 873 bool has_reset_queue; 874 875 u32 pasid; 876 /* Indicates this process has requested PTL stay disabled */ 877 bool ptl_disable_req; 878 }; 879 880 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 881 882 struct svm_range_list { 883 struct mutex lock; 884 struct rb_root_cached objects; 885 struct list_head list; 886 struct work_struct deferred_list_work; 887 struct list_head deferred_range_list; 888 struct list_head criu_svm_metadata_list; 889 spinlock_t deferred_list_lock; 890 atomic_t evicted_ranges; 891 atomic_t drain_pagefaults; 892 struct delayed_work restore_work; 893 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 894 struct task_struct *faulting_task; 895 /* check point ts decides if page fault recovery need be dropped */ 896 uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; 897 898 /* Default granularity to use in buffer migration 899 * and restoration of backing memory while handling 900 * recoverable page faults 901 */ 902 uint8_t default_granularity; 903 }; 904 905 /* Process data */ 906 struct kfd_process { 907 /* 908 * kfd_process are stored in an mm_struct*->kfd_process* 909 * hash table (kfd_processes in kfd_process.c) 910 */ 911 struct hlist_node kfd_processes; 912 913 /* 914 * Opaque pointer to mm_struct. We don't hold a reference to 915 * it so it should never be dereferenced from here. This is 916 * only used for looking up processes by their mm. 917 */ 918 void *mm; 919 920 struct kref ref; 921 struct work_struct release_work; 922 923 struct mutex mutex; 924 925 /* 926 * In any process, the thread that started main() is the lead 927 * thread and outlives the rest. 928 * It is here because amd_iommu_bind_pasid wants a task_struct. 929 * It can also be used for safely getting a reference to the 930 * mm_struct of the process. 931 */ 932 struct task_struct *lead_thread; 933 934 /* We want to receive a notification when the mm_struct is destroyed */ 935 struct mmu_notifier mmu_notifier; 936 937 /* 938 * Array of kfd_process_device pointers, 939 * one for each device the process is using. 940 */ 941 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 942 uint32_t n_pdds; 943 944 struct process_queue_manager pqm; 945 946 /*Is the user space process 32 bit?*/ 947 bool is_32bit_user_mode; 948 949 /* Event-related data */ 950 struct mutex event_mutex; 951 /* Event ID allocator and lookup */ 952 struct idr event_idr; 953 /* Event page */ 954 u64 signal_handle; 955 /* 956 * Each signal event needs a 64-bit signal slot where the signaler will 957 * write a 1 before sending an interrupt. (This is needed because some 958 * interrupts do not contain enough spare data bits to identify an 959 * event.) The signal page is allocated in user mode and mapped to the 960 * kernel; individual signal events use their event_id as slot index. 961 */ 962 uint64_t *signal_page; 963 size_t signal_mapped_size; 964 size_t signal_event_count; 965 bool signal_event_limit_reached; 966 967 /** 968 * @kfd_sigbus_delay_ms: Per-process KFD SIGBUS delivery option for 969 * poison/RAS events (set via DRM_IOCTL_AMDGPU_PROC_OPTIONS / 970 * AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY). 971 * 972 * 0 - send SIGBUS immediately (default) 973 * 0xFFFFFFFF - suppress SIGBUS delivery 974 * other - delay SIGBUS delivery by this many milliseconds 975 */ 976 atomic_t kfd_sigbus_delay_ms; 977 978 /* Delayed signal delivery to user */ 979 struct delayed_work signal_work; 980 981 /* Information used for memory eviction */ 982 void *kgd_process_info; 983 /* Eviction fence that is attached to all the BOs of this process. The 984 * fence will be triggered during eviction and new one will be created 985 * during restore 986 */ 987 struct dma_fence __rcu *ef; 988 989 /* Work items for evicting and restoring BOs */ 990 struct delayed_work eviction_work; 991 struct delayed_work restore_work; 992 /* seqno of the last scheduled eviction */ 993 unsigned int last_eviction_seqno; 994 /* Approx. the last timestamp (in jiffies) when the process was 995 * restored after an eviction 996 */ 997 unsigned long last_restore_timestamp; 998 999 /* Indicates device process is debug attached with reserved vmid. */ 1000 bool debug_trap_enabled; 1001 1002 /* per-process-per device debug event fd file */ 1003 struct file *dbg_ev_file; 1004 1005 /* If the process is a kfd debugger, we need to know so we can clean 1006 * up at exit time. If a process enables debugging on itself, it does 1007 * its own clean-up, so we don't set the flag here. We track this by 1008 * counting the number of processes this process is debugging. 1009 */ 1010 atomic_t debugged_process_count; 1011 1012 /* If the process is a debugged, this is the debugger process */ 1013 struct kfd_process *debugger_process; 1014 1015 /* Kobj for our procfs */ 1016 struct kobject *kobj; 1017 struct kobject *kobj_queues; 1018 struct attribute attr_pasid; 1019 1020 /* Exception code enable mask and status */ 1021 uint64_t exception_enable_mask; 1022 uint64_t exception_status; 1023 1024 /* Used to drain stale interrupts */ 1025 wait_queue_head_t wait_irq_drain; 1026 bool irq_drain_is_open; 1027 1028 /* shared virtual memory registered by this process */ 1029 struct svm_range_list svms; 1030 1031 bool xnack_enabled; 1032 1033 /* Work area for debugger event writer worker. */ 1034 struct work_struct debug_event_workarea; 1035 1036 /* Tracks debug per-vmid request for debug flags */ 1037 u32 dbg_flags; 1038 1039 atomic_t poison; 1040 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 1041 bool queues_paused; 1042 1043 /* Tracks runtime enable status */ 1044 struct semaphore runtime_enable_sema; 1045 bool is_runtime_retry; 1046 struct kfd_runtime_info runtime_info; 1047 1048 /* if gpu page fault sent to KFD */ 1049 bool gpu_page_fault; 1050 1051 /*kfd context id */ 1052 u16 context_id; 1053 1054 /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */ 1055 struct ida id_table; 1056 1057 }; 1058 1059 #define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */ 1060 #define KFD_CONTEXT_ID_PRIMARY 0xFFFF 1061 #define KFD_CONTEXT_ID_MIN 0 1062 1063 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 1064 extern struct srcu_struct kfd_processes_srcu; 1065 1066 /** 1067 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 1068 * 1069 * @filep: pointer to file structure. 1070 * @p: amdkfd process pointer. 1071 * @data: pointer to arg that was copied from user. 1072 * 1073 * Return: returns ioctl completion code. 1074 */ 1075 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 1076 void *data); 1077 1078 typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize); 1079 1080 struct amdkfd_ioctl_desc { 1081 unsigned int cmd; 1082 int flags; 1083 amdkfd_ioctl_t *func; 1084 amdkfd_ioctl_validate_t *validate; 1085 unsigned int cmd_drv; 1086 const char *name; 1087 }; 1088 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1089 1090 struct kfd_process *create_process(const struct task_struct *thread, bool primary); 1091 int kfd_process_create_wq(void); 1092 void kfd_process_destroy_wq(void); 1093 void kfd_cleanup_processes(void); 1094 struct kfd_process *kfd_create_process(struct task_struct *thread); 1095 int kfd_create_process_sysfs(struct kfd_process *process); 1096 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid, 1097 struct kfd_process_device **pdd); 1098 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1099 struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id); 1100 1101 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1102 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1103 uint32_t *gpuid, uint32_t *gpuidx); 1104 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1105 uint32_t gpuidx, uint32_t *gpuid) { 1106 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1107 } 1108 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1109 struct kfd_process *p, uint32_t gpuidx) { 1110 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1111 } 1112 1113 void kfd_unref_process(struct kfd_process *p); 1114 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1115 int kfd_process_restore_queues(struct kfd_process *p); 1116 void kfd_suspend_all_processes(void); 1117 int kfd_resume_all_processes(void); 1118 1119 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1120 uint32_t gpu_id); 1121 1122 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1123 1124 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1125 struct file *drm_file); 1126 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1127 struct kfd_process *p); 1128 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1129 struct kfd_process *p); 1130 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1131 struct kfd_process *p); 1132 1133 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1134 1135 void kfd_process_notifier_release_internal(struct kfd_process *p); 1136 1137 /* KFD process API for creating and translating handles */ 1138 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1139 void *mem); 1140 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1141 int handle); 1142 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1143 int handle); 1144 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1145 1146 /* PASIDs */ 1147 int kfd_pasid_init(void); 1148 void kfd_pasid_exit(void); 1149 u32 kfd_pasid_alloc(void); 1150 void kfd_pasid_free(u32 pasid); 1151 1152 /* Doorbells */ 1153 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1154 int kfd_doorbell_init(struct kfd_dev *kfd); 1155 void kfd_doorbell_fini(struct kfd_dev *kfd); 1156 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1157 struct vm_area_struct *vma); 1158 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1159 unsigned int *doorbell_off); 1160 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1161 u32 read_kernel_doorbell(u32 __iomem *db); 1162 void write_kernel_doorbell(void __iomem *db, u32 value); 1163 void write_kernel_doorbell64(void __iomem *db, u64 value); 1164 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1165 struct kfd_process_device *pdd, 1166 unsigned int doorbell_id); 1167 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1168 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1169 struct kfd_process_device *pdd); 1170 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1171 struct kfd_process_device *pdd); 1172 /* GTT Sub-Allocator */ 1173 1174 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1175 struct kfd_mem_obj **mem_obj); 1176 1177 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1178 1179 extern struct device *kfd_device; 1180 1181 /* KFD's procfs */ 1182 void kfd_procfs_init(void); 1183 void kfd_procfs_shutdown(void); 1184 int kfd_procfs_add_queue(struct queue *q); 1185 void kfd_procfs_del_queue(struct queue *q); 1186 1187 /* Topology */ 1188 int kfd_topology_init(void); 1189 void kfd_topology_shutdown(void); 1190 int kfd_topology_add_device(struct kfd_node *gpu); 1191 int kfd_topology_remove_device(struct kfd_node *gpu); 1192 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1193 uint32_t proximity_domain); 1194 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1195 uint32_t proximity_domain); 1196 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1197 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1198 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1199 uint32_t vmid) 1200 { 1201 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1202 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1203 } 1204 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1205 uint32_t node_id, uint32_t vmid) { 1206 struct kfd_dev *dev = adev->kfd.dev; 1207 uint32_t i; 1208 1209 /* 1210 * On multi-aid system, attempt per-node matching. Otherwise, 1211 * fall back to the first node. 1212 */ 1213 if (!amdgpu_is_multi_aid(adev)) 1214 return dev->nodes[0]; 1215 1216 for (i = 0; i < dev->num_nodes; i++) 1217 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1218 return dev->nodes[i]; 1219 1220 return NULL; 1221 } 1222 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1223 uint32_t kfd_topology_get_num_devices(void); 1224 int kfd_numa_node_to_apic_id(int numa_node_id); 1225 uint32_t kfd_gpu_node_num(void); 1226 1227 /* Interrupts */ 1228 #define KFD_IRQ_FENCE_CLIENTID 0xff 1229 #define KFD_IRQ_FENCE_SOURCEID 0xff 1230 #define KFD_IRQ_IS_FENCE(client, source) \ 1231 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1232 (source) == KFD_IRQ_FENCE_SOURCEID) 1233 int kfd_interrupt_init(struct kfd_node *dev); 1234 void kfd_interrupt_exit(struct kfd_node *dev); 1235 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1236 bool interrupt_is_wanted(struct kfd_node *dev, 1237 const uint32_t *ih_ring_entry, 1238 uint32_t *patched_ihre, bool *flag); 1239 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1240 void kfd_process_close_interrupt_drain(unsigned int pasid); 1241 1242 /* amdkfd Apertures */ 1243 int kfd_init_apertures(struct kfd_process *process); 1244 1245 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1246 uint64_t tba_addr, 1247 uint64_t tma_addr); 1248 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1249 bool enabled); 1250 1251 /* CRIU */ 1252 /* 1253 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1254 * structures: 1255 * kfd_criu_process_priv_data 1256 * kfd_criu_device_priv_data 1257 * kfd_criu_bo_priv_data 1258 * kfd_criu_queue_priv_data 1259 * kfd_criu_event_priv_data 1260 * kfd_criu_svm_range_priv_data 1261 */ 1262 1263 #define KFD_CRIU_PRIV_VERSION 1 1264 1265 struct kfd_criu_process_priv_data { 1266 uint32_t version; 1267 uint32_t xnack_mode; 1268 }; 1269 1270 struct kfd_criu_device_priv_data { 1271 /* For future use */ 1272 uint64_t reserved; 1273 }; 1274 1275 struct kfd_criu_bo_priv_data { 1276 uint64_t user_addr; 1277 uint32_t idr_handle; 1278 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1279 }; 1280 1281 /* 1282 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1283 * kfd_criu_svm_range_priv_data is the object type 1284 */ 1285 enum kfd_criu_object_type { 1286 KFD_CRIU_OBJECT_TYPE_QUEUE, 1287 KFD_CRIU_OBJECT_TYPE_EVENT, 1288 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1289 }; 1290 1291 struct kfd_criu_svm_range_priv_data { 1292 uint32_t object_type; 1293 uint64_t start_addr; 1294 uint64_t size; 1295 /* Variable length array of attributes */ 1296 struct kfd_ioctl_svm_attribute attrs[]; 1297 }; 1298 1299 struct kfd_criu_queue_priv_data { 1300 uint32_t object_type; 1301 uint64_t q_address; 1302 uint64_t q_size; 1303 uint64_t read_ptr_addr; 1304 uint64_t write_ptr_addr; 1305 uint64_t doorbell_off; 1306 uint64_t eop_ring_buffer_address; 1307 uint64_t ctx_save_restore_area_address; 1308 uint32_t gpu_id; 1309 uint32_t type; 1310 uint32_t format; 1311 uint32_t q_id; 1312 uint32_t priority; 1313 uint32_t q_percent; 1314 uint32_t doorbell_id; 1315 uint32_t gws; 1316 uint32_t sdma_id; 1317 uint32_t eop_ring_buffer_size; 1318 uint32_t ctx_save_restore_area_size; 1319 uint32_t ctl_stack_size; 1320 uint32_t mqd_size; 1321 }; 1322 1323 struct kfd_criu_event_priv_data { 1324 uint32_t object_type; 1325 uint64_t user_handle; 1326 uint32_t event_id; 1327 uint32_t auto_reset; 1328 uint32_t type; 1329 uint32_t signaled; 1330 1331 union { 1332 struct kfd_hsa_memory_exception_data memory_exception_data; 1333 struct kfd_hsa_hw_exception_data hw_exception_data; 1334 }; 1335 }; 1336 1337 int kfd_process_get_queue_info(struct kfd_process *p, 1338 uint32_t *num_queues, 1339 uint64_t *priv_data_sizes); 1340 1341 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1342 uint8_t __user *user_priv_data, 1343 uint64_t *priv_data_offset); 1344 1345 int kfd_criu_restore_queue(struct kfd_process *p, 1346 uint8_t __user *user_priv_data, 1347 uint64_t *priv_data_offset, 1348 uint64_t max_priv_data_size); 1349 1350 int kfd_criu_checkpoint_events(struct kfd_process *p, 1351 uint8_t __user *user_priv_data, 1352 uint64_t *priv_data_offset); 1353 1354 int kfd_criu_restore_event(struct file *devkfd, 1355 struct kfd_process *p, 1356 uint8_t __user *user_priv_data, 1357 uint64_t *priv_data_offset, 1358 uint64_t max_priv_data_size); 1359 /* CRIU - End */ 1360 1361 /* Queue Context Management */ 1362 int init_queue(struct queue **q, const struct queue_properties *properties); 1363 void uninit_queue(struct queue *q); 1364 void print_queue_properties(struct queue_properties *q); 1365 void print_queue(struct queue *q); 1366 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo, 1367 u64 expected_size); 1368 void kfd_queue_buffer_put(struct amdgpu_bo **bo); 1369 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1370 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1371 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo); 1372 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd, 1373 struct queue_properties *properties); 1374 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev); 1375 1376 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1377 struct kfd_node *dev); 1378 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1379 struct kfd_node *dev); 1380 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1381 struct kfd_node *dev); 1382 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1383 struct kfd_node *dev); 1384 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1385 struct kfd_node *dev); 1386 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 1387 struct kfd_node *dev); 1388 struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, 1389 struct kfd_node *dev); 1390 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1391 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1392 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1393 enum kfd_queue_type type); 1394 void kernel_queue_uninit(struct kernel_queue *kq); 1395 int kfd_evict_process_device(struct kfd_process_device *pdd); 1396 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id); 1397 1398 /* Process Queue Manager */ 1399 struct process_queue_node { 1400 struct queue *q; 1401 struct kernel_queue *kq; 1402 struct list_head process_queue_list; 1403 }; 1404 1405 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1406 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1407 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1408 void pqm_uninit(struct process_queue_manager *pqm); 1409 int pqm_create_queue(struct process_queue_manager *pqm, 1410 struct kfd_node *dev, 1411 struct queue_properties *properties, 1412 unsigned int *qid, 1413 const struct kfd_criu_queue_priv_data *q_data, 1414 const void *restore_mqd, 1415 const void *restore_ctl_stack, 1416 uint32_t *p_doorbell_offset_in_process); 1417 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1418 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1419 struct queue_properties *p); 1420 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1421 struct mqd_update_info *minfo); 1422 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1423 void *gws); 1424 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1425 unsigned int qid); 1426 int pqm_get_wave_state(struct process_queue_manager *pqm, 1427 unsigned int qid, 1428 void __user *ctl_stack, 1429 u32 *ctl_stack_used_size, 1430 u32 *save_area_used_size); 1431 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1432 uint64_t exception_clear_mask, 1433 void __user *buf, 1434 int *num_qss_entries, 1435 uint32_t *entry_size); 1436 1437 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1438 uint64_t fence_value, 1439 unsigned int timeout_ms); 1440 1441 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1442 unsigned int qid, 1443 u32 *mqd_size, 1444 u32 *ctl_stack_size); 1445 /* Packet Manager */ 1446 1447 #define KFD_FENCE_COMPLETED (100) 1448 #define KFD_FENCE_INIT (10) 1449 1450 /** 1451 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring 1452 * dequeue wait counts. 1453 * 1454 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a 1455 * certain ASICs. For these ASICs, this is default value used by RESET 1456 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value 1457 * for certain ASICs. For others set it to default hardware reset value 1458 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait 1459 * 1460 */ 1461 enum kfd_config_dequeue_wait_counts_cmd { 1462 KFD_DEQUEUE_WAIT_INIT = 1, 1463 KFD_DEQUEUE_WAIT_RESET = 2, 1464 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3 1465 }; 1466 1467 1468 struct packet_manager { 1469 struct device_queue_manager *dqm; 1470 struct kernel_queue *priv_queue; 1471 struct mutex lock; 1472 bool allocated; 1473 struct kfd_mem_obj *ib_buffer_obj; 1474 unsigned int ib_size_bytes; 1475 bool is_over_subscription; 1476 1477 const struct packet_manager_funcs *pmf; 1478 }; 1479 1480 struct packet_manager_funcs { 1481 /* Support ASIC-specific packet formats for PM4 packets */ 1482 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1483 struct qcm_process_device *qpd); 1484 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1485 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1486 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1487 struct scheduling_resources *res); 1488 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1489 struct queue *q, bool is_static); 1490 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1491 enum kfd_unmap_queues_filter mode, 1492 uint32_t filter_param, bool reset); 1493 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer, 1494 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value); 1495 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1496 uint64_t fence_address, uint64_t fence_value); 1497 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1498 1499 /* Packet sizes */ 1500 int map_process_size; 1501 int runlist_size; 1502 int set_resources_size; 1503 int map_queues_size; 1504 int unmap_queues_size; 1505 int config_dequeue_wait_counts_size; 1506 int query_status_size; 1507 int release_mem_size; 1508 }; 1509 1510 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1511 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1512 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1513 1514 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1515 void pm_uninit(struct packet_manager *pm); 1516 int pm_send_set_resources(struct packet_manager *pm, 1517 struct scheduling_resources *res); 1518 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1519 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1520 uint64_t fence_value); 1521 1522 int pm_send_unmap_queue(struct packet_manager *pm, 1523 enum kfd_unmap_queues_filter mode, 1524 uint32_t filter_param, bool reset); 1525 1526 void pm_release_ib(struct packet_manager *pm); 1527 1528 int pm_config_dequeue_wait_counts(struct packet_manager *pm, 1529 enum kfd_config_dequeue_wait_counts_cmd cmd, 1530 uint32_t wait_counts_config); 1531 1532 /* Following PM funcs can be shared among VI and AI */ 1533 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1534 1535 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1536 1537 /* Events */ 1538 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1539 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1540 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; 1541 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1542 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1543 extern const struct kfd_event_interrupt_class event_interrupt_class_v12_1; 1544 1545 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1546 1547 int kfd_event_init_process(struct kfd_process *p); 1548 void kfd_event_free_process(struct kfd_process *p); 1549 int kfd_wait_on_events(struct kfd_process *p, 1550 uint32_t num_events, void __user *data, 1551 bool all, uint32_t *user_timeout_ms, 1552 uint32_t *wait_result); 1553 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1554 uint32_t valid_id_bits, bool signal_mailbox_updated); 1555 void kfd_signal_hw_exception_event(u32 pasid); 1556 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1557 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1558 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1559 1560 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1561 uint32_t event_type, bool auto_reset, uint32_t node_id, 1562 uint32_t *event_id, uint32_t *event_trigger_data, 1563 uint64_t *event_page_offset, uint32_t *event_slot_index); 1564 1565 int kfd_get_num_events(struct kfd_process *p); 1566 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1567 1568 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va); 1569 1570 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, 1571 struct kfd_vm_fault_info *info, 1572 struct kfd_hsa_memory_exception_data *data); 1573 1574 void kfd_signal_reset_event(struct kfd_node *dev); 1575 1576 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1577 void kfd_signal_sigbus_delayed_fn(struct work_struct *work); 1578 void kfd_signal_process_terminate_event(struct kfd_process *p); 1579 1580 static inline void kfd_flush_tlb(struct kfd_process_device *pdd) 1581 { 1582 struct amdgpu_device *adev = pdd->dev->adev; 1583 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); 1584 1585 amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT, 1586 pdd->dev->xcc_mask); 1587 } 1588 1589 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1590 { 1591 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) || 1592 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1593 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1594 } 1595 1596 int kfd_send_exception_to_runtime(struct kfd_process *p, 1597 unsigned int queue_id, 1598 uint64_t error_reason); 1599 bool kfd_is_locked(struct kfd_dev *kfd); 1600 1601 /* Compute profile */ 1602 void kfd_inc_compute_active(struct kfd_node *dev); 1603 void kfd_dec_compute_active(struct kfd_node *dev); 1604 1605 /* Cgroup Support */ 1606 /* Check with device cgroup if @kfd device is accessible */ 1607 static inline int kfd_devcgroup_check_permission(struct kfd_node *node) 1608 { 1609 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1610 struct drm_device *ddev; 1611 1612 if (node->xcp) 1613 ddev = node->xcp->ddev; 1614 else 1615 ddev = adev_to_drm(node->adev); 1616 1617 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1618 ddev->render->index, 1619 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1620 #else 1621 return 0; 1622 #endif 1623 } 1624 1625 static inline bool kfd_is_first_node(struct kfd_node *node) 1626 { 1627 return (node == node->kfd->nodes[0]); 1628 } 1629 1630 /* PTL support */ 1631 int kfd_ptl_disable_request(struct kfd_process_device *pdd, 1632 struct kfd_process *p); 1633 int kfd_ptl_disable_release(struct kfd_process_device *pdd, 1634 struct kfd_process *p); 1635 1636 /* Debugfs */ 1637 #if defined(CONFIG_DEBUG_FS) 1638 1639 void kfd_debugfs_init(void); 1640 void kfd_debugfs_fini(void); 1641 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1642 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1643 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1644 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1645 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1646 int pm_debugfs_runlist(struct seq_file *m, void *data); 1647 1648 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1649 int pm_debugfs_hang_hws(struct packet_manager *pm); 1650 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1651 1652 void kfd_debugfs_add_process(struct kfd_process *p); 1653 void kfd_debugfs_remove_process(struct kfd_process *p); 1654 1655 #else 1656 1657 static inline void kfd_debugfs_init(void) {} 1658 static inline void kfd_debugfs_fini(void) {} 1659 static inline void kfd_debugfs_add_process(struct kfd_process *p) {} 1660 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {} 1661 1662 #endif 1663 1664 #endif 1665