1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <uapi/linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first chunk is the TBA used for the CWSR ISA code. The second 103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET (PAGE_SIZE + 2048) 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC 115 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time 116 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is 117 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload 118 * The format here makes CP workload 10% of total timeout 119 */ 120 #define KFD_UNMAP_LATENCY_MS \ 121 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) 122 123 #define KFD_MAX_SDMA_QUEUES 128 124 125 /* 126 * 512 = 0x200 127 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 128 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 129 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 130 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 131 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 132 */ 133 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 134 135 /** 136 * enum kfd_ioctl_flags - KFD ioctl flags 137 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 138 * userspace can use a given ioctl. 139 */ 140 enum kfd_ioctl_flags { 141 /* 142 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 143 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 144 * perform privileged operations and load arbitrary data into MQDs and 145 * eventually HQD registers when the queue is mapped by HWS. In order to 146 * prevent this we should perform additional security checks. 147 * 148 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 149 * 150 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 151 * we also allow ioctls with SYS_ADMIN capability. 152 */ 153 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 154 }; 155 /* 156 * Kernel module parameter to specify maximum number of supported queues per 157 * device 158 */ 159 extern int max_num_of_queues_per_device; 160 161 162 /* Kernel module parameter to specify the scheduling policy */ 163 extern int sched_policy; 164 165 /* 166 * Kernel module parameter to specify the maximum process 167 * number per HW scheduler 168 */ 169 extern int hws_max_conc_proc; 170 171 extern int cwsr_enable; 172 173 /* 174 * Kernel module parameter to specify whether to send sigterm to HSA process on 175 * unhandled exception 176 */ 177 extern int send_sigterm; 178 179 /* 180 * This kernel module is used to simulate large bar machine on non-large bar 181 * enabled machines. 182 */ 183 extern int debug_largebar; 184 185 /* Set sh_mem_config.retry_disable on GFX v9 */ 186 extern int amdgpu_noretry; 187 188 /* Halt if HWS hang is detected */ 189 extern int halt_if_hws_hang; 190 191 /* Whether MEC FW support GWS barriers */ 192 extern bool hws_gws_support; 193 194 /* Queue preemption timeout in ms */ 195 extern int queue_preemption_timeout_ms; 196 197 /* 198 * Don't evict process queues on vm fault 199 */ 200 extern int amdgpu_no_queue_eviction_on_vm_fault; 201 202 /* Enable eviction debug messages */ 203 extern bool debug_evictions; 204 205 extern struct mutex kfd_processes_mutex; 206 207 enum cache_policy { 208 cache_policy_coherent, 209 cache_policy_noncoherent 210 }; 211 212 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0)) 213 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 214 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 215 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 216 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ 217 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ 218 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) 219 220 struct kfd_node; 221 222 struct kfd_event_interrupt_class { 223 bool (*interrupt_isr)(struct kfd_node *dev, 224 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 225 bool *patched_flag); 226 void (*interrupt_wq)(struct kfd_node *dev, 227 const uint32_t *ih_ring_entry); 228 }; 229 230 struct kfd_device_info { 231 uint32_t gfx_target_version; 232 const struct kfd_event_interrupt_class *event_interrupt_class; 233 unsigned int max_pasid_bits; 234 unsigned int max_no_of_hqd; 235 unsigned int doorbell_size; 236 size_t ih_ring_entry_size; 237 uint8_t num_of_watch_points; 238 uint16_t mqd_size_aligned; 239 bool supports_cwsr; 240 bool needs_pci_atomics; 241 uint32_t no_atomic_fw_version; 242 unsigned int num_sdma_queues_per_engine; 243 unsigned int num_reserved_sdma_queues_per_engine; 244 DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 245 }; 246 247 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 248 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 249 250 struct kfd_mem_obj { 251 uint32_t range_start; 252 uint32_t range_end; 253 uint64_t gpu_addr; 254 uint32_t *cpu_ptr; 255 void *gtt_mem; 256 }; 257 258 struct kfd_vmid_info { 259 uint32_t first_vmid_kfd; 260 uint32_t last_vmid_kfd; 261 uint32_t vmid_num_kfd; 262 }; 263 264 #define MAX_KFD_NODES 8 265 266 struct kfd_dev; 267 268 struct kfd_node { 269 unsigned int node_id; 270 struct amdgpu_device *adev; /* Duplicated here along with keeping 271 * a copy in kfd_dev to save a hop 272 */ 273 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 274 * keeping a copy in kfd_dev to 275 * save a hop 276 */ 277 struct kfd_vmid_info vm_info; 278 unsigned int id; /* topology stub index */ 279 uint32_t xcc_mask; /* Instance mask of XCCs present */ 280 struct amdgpu_xcp *xcp; 281 282 /* Interrupts */ 283 struct kfifo ih_fifo; 284 struct work_struct interrupt_work; 285 spinlock_t interrupt_lock; 286 287 /* 288 * Interrupts of interest to KFD are copied 289 * from the HW ring into a SW ring. 290 */ 291 bool interrupts_active; 292 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 293 294 /* QCM Device instance */ 295 struct device_queue_manager *dqm; 296 297 /* Global GWS resource shared between processes */ 298 void *gws; 299 300 /* Clients watching SMI events */ 301 struct list_head smi_clients; 302 spinlock_t smi_lock; 303 uint32_t reset_seq_num; 304 305 /* SRAM ECC flag */ 306 atomic_t sram_ecc_flag; 307 308 /*spm process id */ 309 unsigned int spm_pasid; 310 311 /* Maximum process number mapped to HW scheduler */ 312 unsigned int max_proc_per_quantum; 313 314 unsigned int compute_vmid_bitmap; 315 316 struct kfd_local_mem_info local_mem_info; 317 318 struct kfd_dev *kfd; 319 320 /* Track per device allocated watch points */ 321 uint32_t alloc_watch_ids; 322 spinlock_t watch_points_lock; 323 }; 324 325 struct kfd_dev { 326 struct amdgpu_device *adev; 327 328 struct kfd_device_info device_info; 329 330 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 331 * page used by kernel queue 332 */ 333 334 struct kgd2kfd_shared_resources shared_resources; 335 336 const struct kfd2kgd_calls *kfd2kgd; 337 struct mutex doorbell_mutex; 338 339 void *gtt_mem; 340 uint64_t gtt_start_gpu_addr; 341 void *gtt_start_cpu_ptr; 342 void *gtt_sa_bitmap; 343 struct mutex gtt_sa_lock; 344 unsigned int gtt_sa_chunk_size; 345 unsigned int gtt_sa_num_of_chunks; 346 347 bool init_complete; 348 349 /* Firmware versions */ 350 uint16_t mec_fw_version; 351 uint16_t mec2_fw_version; 352 uint16_t sdma_fw_version; 353 354 /* CWSR */ 355 bool cwsr_enabled; 356 const void *cwsr_isa; 357 unsigned int cwsr_isa_size; 358 359 /* xGMI */ 360 uint64_t hive_id; 361 362 bool pci_atomic_requested; 363 364 /* Compute Profile ref. count */ 365 atomic_t compute_profile; 366 367 struct ida doorbell_ida; 368 unsigned int max_doorbell_slices; 369 370 int noretry; 371 372 struct kfd_node *nodes[MAX_KFD_NODES]; 373 unsigned int num_nodes; 374 375 struct workqueue_struct *ih_wq; 376 377 /* Kernel doorbells for KFD device */ 378 struct amdgpu_bo *doorbells; 379 380 /* bitmap for dynamic doorbell allocation from doorbell object */ 381 unsigned long *doorbell_bitmap; 382 383 /* for dynamic partitioning */ 384 int kfd_dev_lock; 385 }; 386 387 enum kfd_mempool { 388 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 389 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 390 KFD_MEMPOOL_FRAMEBUFFER = 3, 391 }; 392 393 /* Character device interface */ 394 int kfd_chardev_init(void); 395 void kfd_chardev_exit(void); 396 397 /** 398 * enum kfd_unmap_queues_filter - Enum for queue filters. 399 * 400 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 401 * running queues list. 402 * 403 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 404 * in the run list. 405 * 406 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 407 * specific process. 408 * 409 */ 410 enum kfd_unmap_queues_filter { 411 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 412 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 413 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 414 }; 415 416 /** 417 * enum kfd_queue_type - Enum for various queue types. 418 * 419 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 420 * 421 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 422 * 423 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 424 * 425 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 426 * 427 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 428 * 429 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID. 430 */ 431 enum kfd_queue_type { 432 KFD_QUEUE_TYPE_COMPUTE, 433 KFD_QUEUE_TYPE_SDMA, 434 KFD_QUEUE_TYPE_HIQ, 435 KFD_QUEUE_TYPE_DIQ, 436 KFD_QUEUE_TYPE_SDMA_XGMI, 437 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID 438 }; 439 440 enum kfd_queue_format { 441 KFD_QUEUE_FORMAT_PM4, 442 KFD_QUEUE_FORMAT_AQL 443 }; 444 445 enum KFD_QUEUE_PRIORITY { 446 KFD_QUEUE_PRIORITY_MINIMUM = 0, 447 KFD_QUEUE_PRIORITY_MAXIMUM = 15 448 }; 449 450 /** 451 * struct queue_properties 452 * 453 * @type: The queue type. 454 * 455 * @queue_id: Queue identifier. 456 * 457 * @queue_address: Queue ring buffer address. 458 * 459 * @queue_size: Queue ring buffer size. 460 * 461 * @priority: Defines the queue priority relative to other queues in the 462 * process. 463 * This is just an indication and HW scheduling may override the priority as 464 * necessary while keeping the relative prioritization. 465 * the priority granularity is from 0 to f which f is the highest priority. 466 * currently all queues are initialized with the highest priority. 467 * 468 * @queue_percent: This field is partially implemented and currently a zero in 469 * this field defines that the queue is non active. 470 * 471 * @read_ptr: User space address which points to the number of dwords the 472 * cp read from the ring buffer. This field updates automatically by the H/W. 473 * 474 * @write_ptr: Defines the number of dwords written to the ring buffer. 475 * 476 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 477 * buffer. This field should be similar to write_ptr and the user should 478 * update this field after updating the write_ptr. 479 * 480 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 481 * 482 * @is_interop: Defines if this is a interop queue. Interop queue means that 483 * the queue can access both graphics and compute resources. 484 * 485 * @is_evicted: Defines if the queue is evicted. Only active queues 486 * are evicted, rendering them inactive. 487 * 488 * @is_active: Defines if the queue is active or not. @is_active and 489 * @is_evicted are protected by the DQM lock. 490 * 491 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 492 * @is_gws should be protected by the DQM lock, since changing it can yield the 493 * possibility of updating DQM state on number of GWS queues. 494 * 495 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 496 * of the queue. 497 * 498 * This structure represents the queue properties for each queue no matter if 499 * it's user mode or kernel mode queue. 500 * 501 */ 502 503 struct queue_properties { 504 enum kfd_queue_type type; 505 enum kfd_queue_format format; 506 unsigned int queue_id; 507 uint64_t queue_address; 508 uint64_t queue_size; 509 uint32_t priority; 510 uint32_t queue_percent; 511 void __user *read_ptr; 512 void __user *write_ptr; 513 void __iomem *doorbell_ptr; 514 uint32_t doorbell_off; 515 bool is_interop; 516 bool is_evicted; 517 bool is_suspended; 518 bool is_being_destroyed; 519 bool is_active; 520 bool is_gws; 521 uint32_t pm4_target_xcc; 522 bool is_dbg_wa; 523 bool is_user_cu_masked; 524 /* Not relevant for user mode queues in cp scheduling */ 525 unsigned int vmid; 526 /* Relevant only for sdma queues*/ 527 uint32_t sdma_engine_id; 528 uint32_t sdma_queue_id; 529 uint32_t sdma_vm_addr; 530 /* Relevant only for VI */ 531 uint64_t eop_ring_buffer_address; 532 uint32_t eop_ring_buffer_size; 533 uint64_t ctx_save_restore_area_address; 534 uint32_t ctx_save_restore_area_size; 535 uint32_t ctl_stack_size; 536 uint64_t tba_addr; 537 uint64_t tma_addr; 538 uint64_t exception_status; 539 540 struct amdgpu_bo *wptr_bo; 541 struct amdgpu_bo *rptr_bo; 542 struct amdgpu_bo *ring_bo; 543 struct amdgpu_bo *eop_buf_bo; 544 struct amdgpu_bo *cwsr_bo; 545 }; 546 547 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 548 (q).queue_address != 0 && \ 549 (q).queue_percent > 0 && \ 550 !(q).is_evicted && \ 551 !(q).is_suspended) 552 553 enum mqd_update_flag { 554 UPDATE_FLAG_DBG_WA_ENABLE = 1, 555 UPDATE_FLAG_DBG_WA_DISABLE = 2, 556 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 557 }; 558 559 struct mqd_update_info { 560 union { 561 struct { 562 uint32_t count; /* Must be a multiple of 32 */ 563 uint32_t *ptr; 564 } cu_mask; 565 }; 566 enum mqd_update_flag update_flag; 567 }; 568 569 /** 570 * struct queue 571 * 572 * @list: Queue linked list. 573 * 574 * @mqd: The queue MQD (memory queue descriptor). 575 * 576 * @mqd_mem_obj: The MQD local gpu memory object. 577 * 578 * @gart_mqd_addr: The MQD gart mc address. 579 * 580 * @properties: The queue properties. 581 * 582 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 583 * that the queue should be executed on. 584 * 585 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 586 * id. 587 * 588 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 589 * 590 * @process: The kfd process that created this queue. 591 * 592 * @device: The kfd device that created this queue. 593 * 594 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 595 * otherwise. 596 * 597 * This structure represents user mode compute queues. 598 * It contains all the necessary data to handle such queues. 599 * 600 */ 601 602 struct queue { 603 struct list_head list; 604 void *mqd; 605 struct kfd_mem_obj *mqd_mem_obj; 606 uint64_t gart_mqd_addr; 607 struct queue_properties properties; 608 609 uint32_t mec; 610 uint32_t pipe; 611 uint32_t queue; 612 613 unsigned int sdma_id; 614 unsigned int doorbell_id; 615 616 struct kfd_process *process; 617 struct kfd_node *device; 618 void *gws; 619 620 /* procfs */ 621 struct kobject kobj; 622 623 void *gang_ctx_bo; 624 uint64_t gang_ctx_gpu_addr; 625 void *gang_ctx_cpu_ptr; 626 627 struct amdgpu_bo *wptr_bo_gart; 628 }; 629 630 enum KFD_MQD_TYPE { 631 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 632 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 633 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 634 KFD_MQD_TYPE_DIQ, /* for diq */ 635 KFD_MQD_TYPE_MAX 636 }; 637 638 enum KFD_PIPE_PRIORITY { 639 KFD_PIPE_PRIORITY_CS_LOW = 0, 640 KFD_PIPE_PRIORITY_CS_MEDIUM, 641 KFD_PIPE_PRIORITY_CS_HIGH 642 }; 643 644 struct scheduling_resources { 645 unsigned int vmid_mask; 646 enum kfd_queue_type type; 647 uint64_t queue_mask; 648 uint64_t gws_mask; 649 uint32_t oac_mask; 650 uint32_t gds_heap_base; 651 uint32_t gds_heap_size; 652 }; 653 654 struct process_queue_manager { 655 /* data */ 656 struct kfd_process *process; 657 struct list_head queues; 658 unsigned long *queue_slot_bitmap; 659 }; 660 661 struct qcm_process_device { 662 /* The Device Queue Manager that owns this data */ 663 struct device_queue_manager *dqm; 664 struct process_queue_manager *pqm; 665 /* Queues list */ 666 struct list_head queues_list; 667 struct list_head priv_queue_list; 668 669 unsigned int queue_count; 670 unsigned int vmid; 671 bool is_debug; 672 unsigned int evicted; /* eviction counter, 0=active */ 673 674 /* This flag tells if we should reset all wavefronts on 675 * process termination 676 */ 677 bool reset_wavefronts; 678 679 /* This flag tells us if this process has a GWS-capable 680 * queue that will be mapped into the runlist. It's 681 * possible to request a GWS BO, but not have the queue 682 * currently mapped, and this changes how the MAP_PROCESS 683 * PM4 packet is configured. 684 */ 685 bool mapped_gws_queue; 686 687 /* All the memory management data should be here too */ 688 uint64_t gds_context_area; 689 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 690 uint64_t page_table_base; 691 uint32_t sh_mem_config; 692 uint32_t sh_mem_bases; 693 uint32_t sh_mem_ape1_base; 694 uint32_t sh_mem_ape1_limit; 695 uint32_t gds_size; 696 uint32_t num_gws; 697 uint32_t num_oac; 698 uint32_t sh_hidden_private_base; 699 700 /* CWSR memory */ 701 struct kgd_mem *cwsr_mem; 702 void *cwsr_kaddr; 703 uint64_t cwsr_base; 704 uint64_t tba_addr; 705 uint64_t tma_addr; 706 707 /* IB memory */ 708 struct kgd_mem *ib_mem; 709 uint64_t ib_base; 710 void *ib_kaddr; 711 712 /* doorbells for kfd process */ 713 struct amdgpu_bo *proc_doorbells; 714 715 /* bitmap for dynamic doorbell allocation from the bo */ 716 unsigned long *doorbell_bitmap; 717 }; 718 719 /* KFD Memory Eviction */ 720 721 /* Approx. wait time before attempting to restore evicted BOs */ 722 #define PROCESS_RESTORE_TIME_MS 100 723 /* Approx. back off time if restore fails due to lack of memory */ 724 #define PROCESS_BACK_OFF_TIME_MS 100 725 /* Approx. time before evicting the process again */ 726 #define PROCESS_ACTIVE_TIME_MS 10 727 728 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 729 * idr_handle in the least significant 4 bytes 730 */ 731 #define MAKE_HANDLE(gpu_id, idr_handle) \ 732 (((uint64_t)(gpu_id) << 32) + idr_handle) 733 #define GET_GPU_ID(handle) (handle >> 32) 734 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 735 736 enum kfd_pdd_bound { 737 PDD_UNBOUND = 0, 738 PDD_BOUND, 739 PDD_BOUND_SUSPENDED, 740 }; 741 742 #define MAX_SYSFS_FILENAME_LEN 15 743 744 /* 745 * SDMA counter runs at 100MHz frequency. 746 * We display SDMA activity in microsecond granularity in sysfs. 747 * As a result, the divisor is 100. 748 */ 749 #define SDMA_ACTIVITY_DIVISOR 100 750 751 /* Data that is per-process-per device. */ 752 struct kfd_process_device { 753 /* The device that owns this data. */ 754 struct kfd_node *dev; 755 756 /* The process that owns this kfd_process_device. */ 757 struct kfd_process *process; 758 759 /* per-process-per device QCM data structure */ 760 struct qcm_process_device qpd; 761 762 /*Apertures*/ 763 uint64_t lds_base; 764 uint64_t lds_limit; 765 uint64_t gpuvm_base; 766 uint64_t gpuvm_limit; 767 uint64_t scratch_base; 768 uint64_t scratch_limit; 769 770 /* VM context for GPUVM allocations */ 771 struct file *drm_file; 772 void *drm_priv; 773 774 /* GPUVM allocations storage */ 775 struct idr alloc_idr; 776 777 /* Flag used to tell the pdd has dequeued from the dqm. 778 * This is used to prevent dev->dqm->ops.process_termination() from 779 * being called twice when it is already called in IOMMU callback 780 * function. 781 */ 782 bool already_dequeued; 783 bool runtime_inuse; 784 785 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 786 enum kfd_pdd_bound bound; 787 788 /* VRAM usage */ 789 atomic64_t vram_usage; 790 struct attribute attr_vram; 791 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 792 793 /* SDMA activity tracking */ 794 uint64_t sdma_past_activity_counter; 795 struct attribute attr_sdma; 796 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 797 798 /* Eviction activity tracking */ 799 uint64_t last_evict_timestamp; 800 atomic64_t evict_duration_counter; 801 struct attribute attr_evict; 802 803 struct kobject *kobj_stats; 804 805 /* 806 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 807 * that is associated with device encoded by "this" struct instance. The 808 * value reflects CU usage by all of the waves launched by this process 809 * on this device. A very important property of occupancy parameter is 810 * that its value is a snapshot of current use. 811 * 812 * Following is to be noted regarding how this parameter is reported: 813 * 814 * The number of waves that a CU can launch is limited by couple of 815 * parameters. These are encoded by struct amdgpu_cu_info instance 816 * that is part of every device definition. For GFX9 devices this 817 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 818 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 819 * when they do use scratch memory. This could change for future 820 * devices and therefore this example should be considered as a guide. 821 * 822 * All CU's of a device are available for the process. This may not be true 823 * under certain conditions - e.g. CU masking. 824 * 825 * Finally number of CU's that are occupied by a process is affected by both 826 * number of CU's a device has along with number of other competing processes 827 */ 828 struct attribute attr_cu_occupancy; 829 830 /* sysfs counters for GPU retry fault and page migration tracking */ 831 struct kobject *kobj_counters; 832 struct attribute attr_faults; 833 struct attribute attr_page_in; 834 struct attribute attr_page_out; 835 uint64_t faults; 836 uint64_t page_in; 837 uint64_t page_out; 838 839 /* Exception code status*/ 840 uint64_t exception_status; 841 void *vm_fault_exc_data; 842 size_t vm_fault_exc_data_size; 843 844 /* Tracks debug per-vmid request settings */ 845 uint32_t spi_dbg_override; 846 uint32_t spi_dbg_launch_mode; 847 uint32_t watch_points[4]; 848 uint32_t alloc_watch_ids; 849 850 /* 851 * If this process has been checkpointed before, then the user 852 * application will use the original gpu_id on the 853 * checkpointed node to refer to this device. 854 */ 855 uint32_t user_gpu_id; 856 857 void *proc_ctx_bo; 858 uint64_t proc_ctx_gpu_addr; 859 void *proc_ctx_cpu_ptr; 860 861 /* Tracks queue reset status */ 862 bool has_reset_queue; 863 864 u32 pasid; 865 }; 866 867 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 868 869 struct svm_range_list { 870 struct mutex lock; 871 struct rb_root_cached objects; 872 struct list_head list; 873 struct work_struct deferred_list_work; 874 struct list_head deferred_range_list; 875 struct list_head criu_svm_metadata_list; 876 spinlock_t deferred_list_lock; 877 atomic_t evicted_ranges; 878 atomic_t drain_pagefaults; 879 struct delayed_work restore_work; 880 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 881 struct task_struct *faulting_task; 882 /* check point ts decides if page fault recovery need be dropped */ 883 uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; 884 885 /* Default granularity to use in buffer migration 886 * and restoration of backing memory while handling 887 * recoverable page faults 888 */ 889 uint8_t default_granularity; 890 }; 891 892 /* Process data */ 893 struct kfd_process { 894 /* 895 * kfd_process are stored in an mm_struct*->kfd_process* 896 * hash table (kfd_processes in kfd_process.c) 897 */ 898 struct hlist_node kfd_processes; 899 900 /* 901 * Opaque pointer to mm_struct. We don't hold a reference to 902 * it so it should never be dereferenced from here. This is 903 * only used for looking up processes by their mm. 904 */ 905 void *mm; 906 907 struct kref ref; 908 struct work_struct release_work; 909 910 struct mutex mutex; 911 912 /* 913 * In any process, the thread that started main() is the lead 914 * thread and outlives the rest. 915 * It is here because amd_iommu_bind_pasid wants a task_struct. 916 * It can also be used for safely getting a reference to the 917 * mm_struct of the process. 918 */ 919 struct task_struct *lead_thread; 920 921 /* We want to receive a notification when the mm_struct is destroyed */ 922 struct mmu_notifier mmu_notifier; 923 924 /* 925 * Array of kfd_process_device pointers, 926 * one for each device the process is using. 927 */ 928 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 929 uint32_t n_pdds; 930 931 struct process_queue_manager pqm; 932 933 /*Is the user space process 32 bit?*/ 934 bool is_32bit_user_mode; 935 936 /* Event-related data */ 937 struct mutex event_mutex; 938 /* Event ID allocator and lookup */ 939 struct idr event_idr; 940 /* Event page */ 941 u64 signal_handle; 942 struct kfd_signal_page *signal_page; 943 size_t signal_mapped_size; 944 size_t signal_event_count; 945 bool signal_event_limit_reached; 946 947 /* Information used for memory eviction */ 948 void *kgd_process_info; 949 /* Eviction fence that is attached to all the BOs of this process. The 950 * fence will be triggered during eviction and new one will be created 951 * during restore 952 */ 953 struct dma_fence __rcu *ef; 954 955 /* Work items for evicting and restoring BOs */ 956 struct delayed_work eviction_work; 957 struct delayed_work restore_work; 958 /* seqno of the last scheduled eviction */ 959 unsigned int last_eviction_seqno; 960 /* Approx. the last timestamp (in jiffies) when the process was 961 * restored after an eviction 962 */ 963 unsigned long last_restore_timestamp; 964 965 /* Indicates device process is debug attached with reserved vmid. */ 966 bool debug_trap_enabled; 967 968 /* per-process-per device debug event fd file */ 969 struct file *dbg_ev_file; 970 971 /* If the process is a kfd debugger, we need to know so we can clean 972 * up at exit time. If a process enables debugging on itself, it does 973 * its own clean-up, so we don't set the flag here. We track this by 974 * counting the number of processes this process is debugging. 975 */ 976 atomic_t debugged_process_count; 977 978 /* If the process is a debugged, this is the debugger process */ 979 struct kfd_process *debugger_process; 980 981 /* Kobj for our procfs */ 982 struct kobject *kobj; 983 struct kobject *kobj_queues; 984 struct attribute attr_pasid; 985 986 /* Keep track cwsr init */ 987 bool has_cwsr; 988 989 /* Exception code enable mask and status */ 990 uint64_t exception_enable_mask; 991 uint64_t exception_status; 992 993 /* Used to drain stale interrupts */ 994 wait_queue_head_t wait_irq_drain; 995 bool irq_drain_is_open; 996 997 /* shared virtual memory registered by this process */ 998 struct svm_range_list svms; 999 1000 bool xnack_enabled; 1001 1002 /* Work area for debugger event writer worker. */ 1003 struct work_struct debug_event_workarea; 1004 1005 /* Tracks debug per-vmid request for debug flags */ 1006 u32 dbg_flags; 1007 1008 atomic_t poison; 1009 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 1010 bool queues_paused; 1011 1012 /* Tracks runtime enable status */ 1013 struct semaphore runtime_enable_sema; 1014 bool is_runtime_retry; 1015 struct kfd_runtime_info runtime_info; 1016 1017 /* if gpu page fault sent to KFD */ 1018 bool gpu_page_fault; 1019 }; 1020 1021 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ 1022 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 1023 extern struct srcu_struct kfd_processes_srcu; 1024 1025 /** 1026 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 1027 * 1028 * @filep: pointer to file structure. 1029 * @p: amdkfd process pointer. 1030 * @data: pointer to arg that was copied from user. 1031 * 1032 * Return: returns ioctl completion code. 1033 */ 1034 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 1035 void *data); 1036 1037 struct amdkfd_ioctl_desc { 1038 unsigned int cmd; 1039 int flags; 1040 amdkfd_ioctl_t *func; 1041 unsigned int cmd_drv; 1042 const char *name; 1043 }; 1044 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1045 1046 int kfd_process_create_wq(void); 1047 void kfd_process_destroy_wq(void); 1048 void kfd_cleanup_processes(void); 1049 struct kfd_process *kfd_create_process(struct task_struct *thread); 1050 struct kfd_process *kfd_get_process(const struct task_struct *task); 1051 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid, 1052 struct kfd_process_device **pdd); 1053 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1054 1055 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1056 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1057 uint32_t *gpuid, uint32_t *gpuidx); 1058 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1059 uint32_t gpuidx, uint32_t *gpuid) { 1060 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1061 } 1062 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1063 struct kfd_process *p, uint32_t gpuidx) { 1064 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1065 } 1066 1067 void kfd_unref_process(struct kfd_process *p); 1068 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1069 int kfd_process_restore_queues(struct kfd_process *p); 1070 void kfd_suspend_all_processes(void); 1071 int kfd_resume_all_processes(void); 1072 1073 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1074 uint32_t gpu_id); 1075 1076 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1077 1078 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1079 struct file *drm_file); 1080 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1081 struct kfd_process *p); 1082 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1083 struct kfd_process *p); 1084 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1085 struct kfd_process *p); 1086 1087 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1088 1089 int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, 1090 struct vm_area_struct *vma); 1091 1092 /* KFD process API for creating and translating handles */ 1093 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1094 void *mem); 1095 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1096 int handle); 1097 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1098 int handle); 1099 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1100 1101 /* PASIDs */ 1102 int kfd_pasid_init(void); 1103 void kfd_pasid_exit(void); 1104 u32 kfd_pasid_alloc(void); 1105 void kfd_pasid_free(u32 pasid); 1106 1107 /* Doorbells */ 1108 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1109 int kfd_doorbell_init(struct kfd_dev *kfd); 1110 void kfd_doorbell_fini(struct kfd_dev *kfd); 1111 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1112 struct vm_area_struct *vma); 1113 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1114 unsigned int *doorbell_off); 1115 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1116 u32 read_kernel_doorbell(u32 __iomem *db); 1117 void write_kernel_doorbell(void __iomem *db, u32 value); 1118 void write_kernel_doorbell64(void __iomem *db, u64 value); 1119 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1120 struct kfd_process_device *pdd, 1121 unsigned int doorbell_id); 1122 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1123 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1124 struct kfd_process_device *pdd); 1125 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1126 struct kfd_process_device *pdd); 1127 /* GTT Sub-Allocator */ 1128 1129 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1130 struct kfd_mem_obj **mem_obj); 1131 1132 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1133 1134 extern struct device *kfd_device; 1135 1136 /* KFD's procfs */ 1137 void kfd_procfs_init(void); 1138 void kfd_procfs_shutdown(void); 1139 int kfd_procfs_add_queue(struct queue *q); 1140 void kfd_procfs_del_queue(struct queue *q); 1141 1142 /* Topology */ 1143 int kfd_topology_init(void); 1144 void kfd_topology_shutdown(void); 1145 int kfd_topology_add_device(struct kfd_node *gpu); 1146 int kfd_topology_remove_device(struct kfd_node *gpu); 1147 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1148 uint32_t proximity_domain); 1149 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1150 uint32_t proximity_domain); 1151 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1152 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1153 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1154 uint32_t vmid) 1155 { 1156 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1157 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1158 } 1159 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1160 uint32_t node_id, uint32_t vmid) { 1161 struct kfd_dev *dev = adev->kfd.dev; 1162 uint32_t i; 1163 1164 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 1165 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 1166 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) 1167 return dev->nodes[0]; 1168 1169 for (i = 0; i < dev->num_nodes; i++) 1170 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1171 return dev->nodes[i]; 1172 1173 return NULL; 1174 } 1175 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1176 int kfd_numa_node_to_apic_id(int numa_node_id); 1177 1178 /* Interrupts */ 1179 #define KFD_IRQ_FENCE_CLIENTID 0xff 1180 #define KFD_IRQ_FENCE_SOURCEID 0xff 1181 #define KFD_IRQ_IS_FENCE(client, source) \ 1182 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1183 (source) == KFD_IRQ_FENCE_SOURCEID) 1184 int kfd_interrupt_init(struct kfd_node *dev); 1185 void kfd_interrupt_exit(struct kfd_node *dev); 1186 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1187 bool interrupt_is_wanted(struct kfd_node *dev, 1188 const uint32_t *ih_ring_entry, 1189 uint32_t *patched_ihre, bool *flag); 1190 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1191 void kfd_process_close_interrupt_drain(unsigned int pasid); 1192 1193 /* amdkfd Apertures */ 1194 int kfd_init_apertures(struct kfd_process *process); 1195 1196 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1197 uint64_t tba_addr, 1198 uint64_t tma_addr); 1199 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1200 bool enabled); 1201 1202 /* CWSR initialization */ 1203 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); 1204 1205 /* CRIU */ 1206 /* 1207 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1208 * structures: 1209 * kfd_criu_process_priv_data 1210 * kfd_criu_device_priv_data 1211 * kfd_criu_bo_priv_data 1212 * kfd_criu_queue_priv_data 1213 * kfd_criu_event_priv_data 1214 * kfd_criu_svm_range_priv_data 1215 */ 1216 1217 #define KFD_CRIU_PRIV_VERSION 1 1218 1219 struct kfd_criu_process_priv_data { 1220 uint32_t version; 1221 uint32_t xnack_mode; 1222 }; 1223 1224 struct kfd_criu_device_priv_data { 1225 /* For future use */ 1226 uint64_t reserved; 1227 }; 1228 1229 struct kfd_criu_bo_priv_data { 1230 uint64_t user_addr; 1231 uint32_t idr_handle; 1232 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1233 }; 1234 1235 /* 1236 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1237 * kfd_criu_svm_range_priv_data is the object type 1238 */ 1239 enum kfd_criu_object_type { 1240 KFD_CRIU_OBJECT_TYPE_QUEUE, 1241 KFD_CRIU_OBJECT_TYPE_EVENT, 1242 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1243 }; 1244 1245 struct kfd_criu_svm_range_priv_data { 1246 uint32_t object_type; 1247 uint64_t start_addr; 1248 uint64_t size; 1249 /* Variable length array of attributes */ 1250 struct kfd_ioctl_svm_attribute attrs[]; 1251 }; 1252 1253 struct kfd_criu_queue_priv_data { 1254 uint32_t object_type; 1255 uint64_t q_address; 1256 uint64_t q_size; 1257 uint64_t read_ptr_addr; 1258 uint64_t write_ptr_addr; 1259 uint64_t doorbell_off; 1260 uint64_t eop_ring_buffer_address; 1261 uint64_t ctx_save_restore_area_address; 1262 uint32_t gpu_id; 1263 uint32_t type; 1264 uint32_t format; 1265 uint32_t q_id; 1266 uint32_t priority; 1267 uint32_t q_percent; 1268 uint32_t doorbell_id; 1269 uint32_t gws; 1270 uint32_t sdma_id; 1271 uint32_t eop_ring_buffer_size; 1272 uint32_t ctx_save_restore_area_size; 1273 uint32_t ctl_stack_size; 1274 uint32_t mqd_size; 1275 }; 1276 1277 struct kfd_criu_event_priv_data { 1278 uint32_t object_type; 1279 uint64_t user_handle; 1280 uint32_t event_id; 1281 uint32_t auto_reset; 1282 uint32_t type; 1283 uint32_t signaled; 1284 1285 union { 1286 struct kfd_hsa_memory_exception_data memory_exception_data; 1287 struct kfd_hsa_hw_exception_data hw_exception_data; 1288 }; 1289 }; 1290 1291 int kfd_process_get_queue_info(struct kfd_process *p, 1292 uint32_t *num_queues, 1293 uint64_t *priv_data_sizes); 1294 1295 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1296 uint8_t __user *user_priv_data, 1297 uint64_t *priv_data_offset); 1298 1299 int kfd_criu_restore_queue(struct kfd_process *p, 1300 uint8_t __user *user_priv_data, 1301 uint64_t *priv_data_offset, 1302 uint64_t max_priv_data_size); 1303 1304 int kfd_criu_checkpoint_events(struct kfd_process *p, 1305 uint8_t __user *user_priv_data, 1306 uint64_t *priv_data_offset); 1307 1308 int kfd_criu_restore_event(struct file *devkfd, 1309 struct kfd_process *p, 1310 uint8_t __user *user_priv_data, 1311 uint64_t *priv_data_offset, 1312 uint64_t max_priv_data_size); 1313 /* CRIU - End */ 1314 1315 /* Queue Context Management */ 1316 int init_queue(struct queue **q, const struct queue_properties *properties); 1317 void uninit_queue(struct queue *q); 1318 void print_queue_properties(struct queue_properties *q); 1319 void print_queue(struct queue *q); 1320 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo, 1321 u64 expected_size); 1322 void kfd_queue_buffer_put(struct amdgpu_bo **bo); 1323 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1324 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1325 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo); 1326 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd, 1327 struct queue_properties *properties); 1328 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev); 1329 1330 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1331 struct kfd_node *dev); 1332 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1333 struct kfd_node *dev); 1334 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1335 struct kfd_node *dev); 1336 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1337 struct kfd_node *dev); 1338 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1339 struct kfd_node *dev); 1340 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 1341 struct kfd_node *dev); 1342 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1343 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1344 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1345 enum kfd_queue_type type); 1346 void kernel_queue_uninit(struct kernel_queue *kq); 1347 int kfd_evict_process_device(struct kfd_process_device *pdd); 1348 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id); 1349 1350 /* Process Queue Manager */ 1351 struct process_queue_node { 1352 struct queue *q; 1353 struct kernel_queue *kq; 1354 struct list_head process_queue_list; 1355 }; 1356 1357 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1358 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1359 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1360 void pqm_uninit(struct process_queue_manager *pqm); 1361 int pqm_create_queue(struct process_queue_manager *pqm, 1362 struct kfd_node *dev, 1363 struct queue_properties *properties, 1364 unsigned int *qid, 1365 const struct kfd_criu_queue_priv_data *q_data, 1366 const void *restore_mqd, 1367 const void *restore_ctl_stack, 1368 uint32_t *p_doorbell_offset_in_process); 1369 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1370 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1371 struct queue_properties *p); 1372 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1373 struct mqd_update_info *minfo); 1374 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1375 void *gws); 1376 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1377 unsigned int qid); 1378 int pqm_get_wave_state(struct process_queue_manager *pqm, 1379 unsigned int qid, 1380 void __user *ctl_stack, 1381 u32 *ctl_stack_used_size, 1382 u32 *save_area_used_size); 1383 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1384 uint64_t exception_clear_mask, 1385 void __user *buf, 1386 int *num_qss_entries, 1387 uint32_t *entry_size); 1388 1389 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1390 uint64_t fence_value, 1391 unsigned int timeout_ms); 1392 1393 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1394 unsigned int qid, 1395 u32 *mqd_size, 1396 u32 *ctl_stack_size); 1397 /* Packet Manager */ 1398 1399 #define KFD_FENCE_COMPLETED (100) 1400 #define KFD_FENCE_INIT (10) 1401 1402 /** 1403 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring 1404 * dequeue wait counts. 1405 * 1406 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a 1407 * certain ASICs. For these ASICs, this is default value used by RESET 1408 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value 1409 * for certain ASICs. For others set it to default hardware reset value 1410 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait 1411 * 1412 */ 1413 enum kfd_config_dequeue_wait_counts_cmd { 1414 KFD_DEQUEUE_WAIT_INIT = 1, 1415 KFD_DEQUEUE_WAIT_RESET = 2, 1416 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3 1417 }; 1418 1419 1420 struct packet_manager { 1421 struct device_queue_manager *dqm; 1422 struct kernel_queue *priv_queue; 1423 struct mutex lock; 1424 bool allocated; 1425 struct kfd_mem_obj *ib_buffer_obj; 1426 unsigned int ib_size_bytes; 1427 bool is_over_subscription; 1428 1429 const struct packet_manager_funcs *pmf; 1430 }; 1431 1432 struct packet_manager_funcs { 1433 /* Support ASIC-specific packet formats for PM4 packets */ 1434 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1435 struct qcm_process_device *qpd); 1436 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1437 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1438 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1439 struct scheduling_resources *res); 1440 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1441 struct queue *q, bool is_static); 1442 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1443 enum kfd_unmap_queues_filter mode, 1444 uint32_t filter_param, bool reset); 1445 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer, 1446 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value); 1447 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1448 uint64_t fence_address, uint64_t fence_value); 1449 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1450 1451 /* Packet sizes */ 1452 int map_process_size; 1453 int runlist_size; 1454 int set_resources_size; 1455 int map_queues_size; 1456 int unmap_queues_size; 1457 int config_dequeue_wait_counts_size; 1458 int query_status_size; 1459 int release_mem_size; 1460 }; 1461 1462 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1463 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1464 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1465 1466 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1467 void pm_uninit(struct packet_manager *pm); 1468 int pm_send_set_resources(struct packet_manager *pm, 1469 struct scheduling_resources *res); 1470 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1471 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1472 uint64_t fence_value); 1473 1474 int pm_send_unmap_queue(struct packet_manager *pm, 1475 enum kfd_unmap_queues_filter mode, 1476 uint32_t filter_param, bool reset); 1477 1478 void pm_release_ib(struct packet_manager *pm); 1479 1480 int pm_config_dequeue_wait_counts(struct packet_manager *pm, 1481 enum kfd_config_dequeue_wait_counts_cmd cmd, 1482 uint32_t wait_counts_config); 1483 1484 /* Following PM funcs can be shared among VI and AI */ 1485 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1486 1487 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1488 1489 /* Events */ 1490 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1491 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1492 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; 1493 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1494 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1495 1496 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1497 1498 int kfd_event_init_process(struct kfd_process *p); 1499 void kfd_event_free_process(struct kfd_process *p); 1500 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); 1501 int kfd_wait_on_events(struct kfd_process *p, 1502 uint32_t num_events, void __user *data, 1503 bool all, uint32_t *user_timeout_ms, 1504 uint32_t *wait_result); 1505 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1506 uint32_t valid_id_bits); 1507 void kfd_signal_hw_exception_event(u32 pasid); 1508 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1509 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1510 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1511 1512 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1513 uint32_t event_type, bool auto_reset, uint32_t node_id, 1514 uint32_t *event_id, uint32_t *event_trigger_data, 1515 uint64_t *event_page_offset, uint32_t *event_slot_index); 1516 1517 int kfd_get_num_events(struct kfd_process *p); 1518 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1519 1520 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va); 1521 1522 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, 1523 struct kfd_vm_fault_info *info, 1524 struct kfd_hsa_memory_exception_data *data); 1525 1526 void kfd_signal_reset_event(struct kfd_node *dev); 1527 1528 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1529 1530 static inline void kfd_flush_tlb(struct kfd_process_device *pdd, 1531 enum TLB_FLUSH_TYPE type) 1532 { 1533 struct amdgpu_device *adev = pdd->dev->adev; 1534 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); 1535 1536 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); 1537 } 1538 1539 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1540 { 1541 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) || 1542 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1543 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1544 } 1545 1546 int kfd_send_exception_to_runtime(struct kfd_process *p, 1547 unsigned int queue_id, 1548 uint64_t error_reason); 1549 bool kfd_is_locked(struct kfd_dev *kfd); 1550 1551 /* Compute profile */ 1552 void kfd_inc_compute_active(struct kfd_node *dev); 1553 void kfd_dec_compute_active(struct kfd_node *dev); 1554 1555 /* Cgroup Support */ 1556 /* Check with device cgroup if @kfd device is accessible */ 1557 static inline int kfd_devcgroup_check_permission(struct kfd_node *node) 1558 { 1559 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1560 struct drm_device *ddev; 1561 1562 if (node->xcp) 1563 ddev = node->xcp->ddev; 1564 else 1565 ddev = adev_to_drm(node->adev); 1566 1567 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1568 ddev->render->index, 1569 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1570 #else 1571 return 0; 1572 #endif 1573 } 1574 1575 static inline bool kfd_is_first_node(struct kfd_node *node) 1576 { 1577 return (node == node->kfd->nodes[0]); 1578 } 1579 1580 /* Debugfs */ 1581 #if defined(CONFIG_DEBUG_FS) 1582 1583 void kfd_debugfs_init(void); 1584 void kfd_debugfs_fini(void); 1585 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1586 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1587 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1588 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1589 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1590 int pm_debugfs_runlist(struct seq_file *m, void *data); 1591 1592 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1593 int pm_debugfs_hang_hws(struct packet_manager *pm); 1594 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1595 1596 void kfd_debugfs_add_process(struct kfd_process *p); 1597 void kfd_debugfs_remove_process(struct kfd_process *p); 1598 1599 #else 1600 1601 static inline void kfd_debugfs_init(void) {} 1602 static inline void kfd_debugfs_fini(void) {} 1603 static inline void kfd_debugfs_add_process(struct kfd_process *p) {} 1604 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {} 1605 1606 #endif 1607 1608 #endif 1609