1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <uapi/linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc(sizeof(*ptr_to_struct), GFP_KERNEL)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first chunk is the TBA used for the CWSR ISA code. The second 103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET (PAGE_SIZE + 2048) 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC 115 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time 116 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is 117 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload 118 * The format here makes CP workload 10% of total timeout 119 */ 120 #define KFD_UNMAP_LATENCY_MS \ 121 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) 122 123 #define KFD_MAX_SDMA_QUEUES 128 124 125 /* 126 * 512 = 0x200 127 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 128 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 129 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 130 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 131 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 132 */ 133 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 134 135 /** 136 * enum kfd_ioctl_flags - KFD ioctl flags 137 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 138 * userspace can use a given ioctl. 139 */ 140 enum kfd_ioctl_flags { 141 /* 142 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 143 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 144 * perform privileged operations and load arbitrary data into MQDs and 145 * eventually HQD registers when the queue is mapped by HWS. In order to 146 * prevent this we should perform additional security checks. 147 * 148 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 149 * 150 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 151 * we also allow ioctls with SYS_ADMIN capability. 152 */ 153 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 154 }; 155 /* 156 * Kernel module parameter to specify maximum number of supported queues per 157 * device 158 */ 159 extern int max_num_of_queues_per_device; 160 161 162 /* Kernel module parameter to specify the scheduling policy */ 163 extern int sched_policy; 164 165 /* 166 * Kernel module parameter to specify the maximum process 167 * number per HW scheduler 168 */ 169 extern int hws_max_conc_proc; 170 171 extern int cwsr_enable; 172 173 /* 174 * Kernel module parameter to specify whether to send sigterm to HSA process on 175 * unhandled exception 176 */ 177 extern int send_sigterm; 178 179 /* 180 * This kernel module is used to simulate large bar machine on non-large bar 181 * enabled machines. 182 */ 183 extern int debug_largebar; 184 185 /* Set sh_mem_config.retry_disable on GFX v9 */ 186 extern int amdgpu_noretry; 187 188 /* Halt if HWS hang is detected */ 189 extern int halt_if_hws_hang; 190 191 /* Whether MEC FW support GWS barriers */ 192 extern bool hws_gws_support; 193 194 /* Queue preemption timeout in ms */ 195 extern int queue_preemption_timeout_ms; 196 197 /* 198 * Don't evict process queues on vm fault 199 */ 200 extern int amdgpu_no_queue_eviction_on_vm_fault; 201 202 /* Enable eviction debug messages */ 203 extern bool debug_evictions; 204 205 extern struct mutex kfd_processes_mutex; 206 207 enum cache_policy { 208 cache_policy_coherent, 209 cache_policy_noncoherent 210 }; 211 212 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0)) 213 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 214 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 215 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 216 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ 217 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ 218 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) 219 220 struct kfd_node; 221 222 struct kfd_event_interrupt_class { 223 bool (*interrupt_isr)(struct kfd_node *dev, 224 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 225 bool *patched_flag); 226 void (*interrupt_wq)(struct kfd_node *dev, 227 const uint32_t *ih_ring_entry); 228 }; 229 230 struct kfd_device_info { 231 uint32_t gfx_target_version; 232 const struct kfd_event_interrupt_class *event_interrupt_class; 233 unsigned int max_pasid_bits; 234 unsigned int max_no_of_hqd; 235 unsigned int doorbell_size; 236 size_t ih_ring_entry_size; 237 uint8_t num_of_watch_points; 238 uint16_t mqd_size_aligned; 239 bool supports_cwsr; 240 bool needs_pci_atomics; 241 uint32_t no_atomic_fw_version; 242 unsigned int num_sdma_queues_per_engine; 243 unsigned int num_reserved_sdma_queues_per_engine; 244 DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 245 }; 246 247 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 248 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 249 250 struct kfd_mem_obj { 251 uint32_t range_start; 252 uint32_t range_end; 253 uint64_t gpu_addr; 254 uint32_t *cpu_ptr; 255 void *gtt_mem; 256 }; 257 258 struct kfd_vmid_info { 259 uint32_t first_vmid_kfd; 260 uint32_t last_vmid_kfd; 261 uint32_t vmid_num_kfd; 262 }; 263 264 #define MAX_KFD_NODES 8 265 266 struct kfd_dev; 267 268 struct kfd_node { 269 unsigned int node_id; 270 struct amdgpu_device *adev; /* Duplicated here along with keeping 271 * a copy in kfd_dev to save a hop 272 */ 273 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 274 * keeping a copy in kfd_dev to 275 * save a hop 276 */ 277 struct kfd_vmid_info vm_info; 278 unsigned int id; /* topology stub index */ 279 uint32_t xcc_mask; /* Instance mask of XCCs present */ 280 struct amdgpu_xcp *xcp; 281 282 /* Interrupts */ 283 struct kfifo ih_fifo; 284 struct work_struct interrupt_work; 285 spinlock_t interrupt_lock; 286 287 /* 288 * Interrupts of interest to KFD are copied 289 * from the HW ring into a SW ring. 290 */ 291 bool interrupts_active; 292 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 293 294 /* QCM Device instance */ 295 struct device_queue_manager *dqm; 296 297 /* Global GWS resource shared between processes */ 298 void *gws; 299 300 /* Clients watching SMI events */ 301 struct list_head smi_clients; 302 spinlock_t smi_lock; 303 uint32_t reset_seq_num; 304 305 /* SRAM ECC flag */ 306 atomic_t sram_ecc_flag; 307 308 /*spm process id */ 309 unsigned int spm_pasid; 310 311 /* Maximum process number mapped to HW scheduler */ 312 unsigned int max_proc_per_quantum; 313 314 unsigned int compute_vmid_bitmap; 315 316 struct kfd_local_mem_info local_mem_info; 317 318 struct kfd_dev *kfd; 319 320 /* Track per device allocated watch points */ 321 uint32_t alloc_watch_ids; 322 spinlock_t watch_points_lock; 323 }; 324 325 struct kfd_dev { 326 struct amdgpu_device *adev; 327 328 struct kfd_device_info device_info; 329 330 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 331 * page used by kernel queue 332 */ 333 334 struct kgd2kfd_shared_resources shared_resources; 335 336 const struct kfd2kgd_calls *kfd2kgd; 337 struct mutex doorbell_mutex; 338 339 void *gtt_mem; 340 uint64_t gtt_start_gpu_addr; 341 void *gtt_start_cpu_ptr; 342 void *gtt_sa_bitmap; 343 struct mutex gtt_sa_lock; 344 unsigned int gtt_sa_chunk_size; 345 unsigned int gtt_sa_num_of_chunks; 346 347 bool init_complete; 348 349 /* Firmware versions */ 350 uint16_t mec_fw_version; 351 uint16_t mec2_fw_version; 352 uint16_t sdma_fw_version; 353 354 /* CWSR */ 355 bool cwsr_enabled; 356 const void *cwsr_isa; 357 unsigned int cwsr_isa_size; 358 359 /* xGMI */ 360 uint64_t hive_id; 361 362 bool pci_atomic_requested; 363 364 /* Compute Profile ref. count */ 365 atomic_t compute_profile; 366 367 struct ida doorbell_ida; 368 unsigned int max_doorbell_slices; 369 370 int noretry; 371 372 struct kfd_node *nodes[MAX_KFD_NODES]; 373 unsigned int num_nodes; 374 375 struct workqueue_struct *ih_wq; 376 377 /* Kernel doorbells for KFD device */ 378 struct amdgpu_bo *doorbells; 379 380 /* bitmap for dynamic doorbell allocation from doorbell object */ 381 unsigned long *doorbell_bitmap; 382 383 /* for dynamic partitioning */ 384 int kfd_dev_lock; 385 386 atomic_t kfd_processes_count; 387 }; 388 389 enum kfd_mempool { 390 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 391 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 392 KFD_MEMPOOL_FRAMEBUFFER = 3, 393 }; 394 395 /* Character device interface */ 396 int kfd_chardev_init(void); 397 void kfd_chardev_exit(void); 398 399 /** 400 * enum kfd_unmap_queues_filter - Enum for queue filters. 401 * 402 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 403 * running queues list. 404 * 405 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 406 * in the run list. 407 * 408 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 409 * specific process. 410 * 411 */ 412 enum kfd_unmap_queues_filter { 413 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 414 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 415 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 416 }; 417 418 /** 419 * enum kfd_queue_type - Enum for various queue types. 420 * 421 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 422 * 423 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 424 * 425 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 426 * 427 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 428 * 429 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 430 * 431 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID. 432 */ 433 enum kfd_queue_type { 434 KFD_QUEUE_TYPE_COMPUTE, 435 KFD_QUEUE_TYPE_SDMA, 436 KFD_QUEUE_TYPE_HIQ, 437 KFD_QUEUE_TYPE_DIQ, 438 KFD_QUEUE_TYPE_SDMA_XGMI, 439 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID 440 }; 441 442 enum kfd_queue_format { 443 KFD_QUEUE_FORMAT_PM4, 444 KFD_QUEUE_FORMAT_AQL 445 }; 446 447 enum KFD_QUEUE_PRIORITY { 448 KFD_QUEUE_PRIORITY_MINIMUM = 0, 449 KFD_QUEUE_PRIORITY_MAXIMUM = 15 450 }; 451 452 /** 453 * struct queue_properties 454 * 455 * @type: The queue type. 456 * 457 * @queue_id: Queue identifier. 458 * 459 * @queue_address: Queue ring buffer address. 460 * 461 * @queue_size: Queue ring buffer size. 462 * 463 * @priority: Defines the queue priority relative to other queues in the 464 * process. 465 * This is just an indication and HW scheduling may override the priority as 466 * necessary while keeping the relative prioritization. 467 * the priority granularity is from 0 to f which f is the highest priority. 468 * currently all queues are initialized with the highest priority. 469 * 470 * @queue_percent: This field is partially implemented and currently a zero in 471 * this field defines that the queue is non active. 472 * 473 * @read_ptr: User space address which points to the number of dwords the 474 * cp read from the ring buffer. This field updates automatically by the H/W. 475 * 476 * @write_ptr: Defines the number of dwords written to the ring buffer. 477 * 478 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 479 * buffer. This field should be similar to write_ptr and the user should 480 * update this field after updating the write_ptr. 481 * 482 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 483 * 484 * @is_interop: Defines if this is a interop queue. Interop queue means that 485 * the queue can access both graphics and compute resources. 486 * 487 * @is_evicted: Defines if the queue is evicted. Only active queues 488 * are evicted, rendering them inactive. 489 * 490 * @is_active: Defines if the queue is active or not. @is_active and 491 * @is_evicted are protected by the DQM lock. 492 * 493 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 494 * @is_gws should be protected by the DQM lock, since changing it can yield the 495 * possibility of updating DQM state on number of GWS queues. 496 * 497 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 498 * of the queue. 499 * 500 * This structure represents the queue properties for each queue no matter if 501 * it's user mode or kernel mode queue. 502 * 503 */ 504 505 struct queue_properties { 506 enum kfd_queue_type type; 507 enum kfd_queue_format format; 508 unsigned int queue_id; 509 uint64_t queue_address; 510 uint64_t queue_size; 511 uint32_t priority; 512 uint32_t queue_percent; 513 void __user *read_ptr; 514 void __user *write_ptr; 515 void __iomem *doorbell_ptr; 516 uint32_t doorbell_off; 517 bool is_interop; 518 bool is_evicted; 519 bool is_suspended; 520 bool is_being_destroyed; 521 bool is_active; 522 bool is_gws; 523 uint32_t pm4_target_xcc; 524 bool is_dbg_wa; 525 bool is_user_cu_masked; 526 /* Not relevant for user mode queues in cp scheduling */ 527 unsigned int vmid; 528 /* Relevant only for sdma queues*/ 529 uint32_t sdma_engine_id; 530 uint32_t sdma_queue_id; 531 uint32_t sdma_vm_addr; 532 /* Relevant only for VI */ 533 uint64_t eop_ring_buffer_address; 534 uint32_t eop_ring_buffer_size; 535 uint64_t ctx_save_restore_area_address; 536 uint32_t ctx_save_restore_area_size; 537 uint32_t ctl_stack_size; 538 uint64_t tba_addr; 539 uint64_t tma_addr; 540 uint64_t exception_status; 541 542 struct amdgpu_bo *wptr_bo; 543 struct amdgpu_bo *rptr_bo; 544 struct amdgpu_bo *ring_bo; 545 struct amdgpu_bo *eop_buf_bo; 546 struct amdgpu_bo *cwsr_bo; 547 }; 548 549 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 550 (q).queue_address != 0 && \ 551 (q).queue_percent > 0 && \ 552 !(q).is_evicted && \ 553 !(q).is_suspended) 554 555 enum mqd_update_flag { 556 UPDATE_FLAG_DBG_WA_ENABLE = 1, 557 UPDATE_FLAG_DBG_WA_DISABLE = 2, 558 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 559 }; 560 561 struct mqd_update_info { 562 union { 563 struct { 564 uint32_t count; /* Must be a multiple of 32 */ 565 uint32_t *ptr; 566 } cu_mask; 567 }; 568 enum mqd_update_flag update_flag; 569 }; 570 571 /** 572 * struct queue 573 * 574 * @list: Queue linked list. 575 * 576 * @mqd: The queue MQD (memory queue descriptor). 577 * 578 * @mqd_mem_obj: The MQD local gpu memory object. 579 * 580 * @gart_mqd_addr: The MQD gart mc address. 581 * 582 * @properties: The queue properties. 583 * 584 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 585 * that the queue should be executed on. 586 * 587 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 588 * id. 589 * 590 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 591 * 592 * @process: The kfd process that created this queue. 593 * 594 * @device: The kfd device that created this queue. 595 * 596 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 597 * otherwise. 598 * 599 * This structure represents user mode compute queues. 600 * It contains all the necessary data to handle such queues. 601 * 602 */ 603 604 struct queue { 605 struct list_head list; 606 void *mqd; 607 struct kfd_mem_obj *mqd_mem_obj; 608 uint64_t gart_mqd_addr; 609 struct queue_properties properties; 610 611 uint32_t mec; 612 uint32_t pipe; 613 uint32_t queue; 614 615 unsigned int sdma_id; 616 unsigned int doorbell_id; 617 618 struct kfd_process *process; 619 struct kfd_node *device; 620 void *gws; 621 622 /* procfs */ 623 struct kobject kobj; 624 625 void *gang_ctx_bo; 626 uint64_t gang_ctx_gpu_addr; 627 void *gang_ctx_cpu_ptr; 628 629 struct amdgpu_bo *wptr_bo_gart; 630 }; 631 632 enum KFD_MQD_TYPE { 633 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 634 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 635 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 636 KFD_MQD_TYPE_DIQ, /* for diq */ 637 KFD_MQD_TYPE_MAX 638 }; 639 640 enum KFD_PIPE_PRIORITY { 641 KFD_PIPE_PRIORITY_CS_LOW = 0, 642 KFD_PIPE_PRIORITY_CS_MEDIUM, 643 KFD_PIPE_PRIORITY_CS_HIGH 644 }; 645 646 struct scheduling_resources { 647 unsigned int vmid_mask; 648 enum kfd_queue_type type; 649 uint64_t queue_mask; 650 uint64_t gws_mask; 651 uint32_t oac_mask; 652 uint32_t gds_heap_base; 653 uint32_t gds_heap_size; 654 }; 655 656 struct process_queue_manager { 657 /* data */ 658 struct kfd_process *process; 659 struct list_head queues; 660 unsigned long *queue_slot_bitmap; 661 }; 662 663 struct qcm_process_device { 664 /* The Device Queue Manager that owns this data */ 665 struct device_queue_manager *dqm; 666 struct process_queue_manager *pqm; 667 /* Queues list */ 668 struct list_head queues_list; 669 struct list_head priv_queue_list; 670 671 unsigned int queue_count; 672 unsigned int vmid; 673 bool is_debug; 674 unsigned int evicted; /* eviction counter, 0=active */ 675 676 /* This flag tells if we should reset all wavefronts on 677 * process termination 678 */ 679 bool reset_wavefronts; 680 681 /* This flag tells us if this process has a GWS-capable 682 * queue that will be mapped into the runlist. It's 683 * possible to request a GWS BO, but not have the queue 684 * currently mapped, and this changes how the MAP_PROCESS 685 * PM4 packet is configured. 686 */ 687 bool mapped_gws_queue; 688 689 /* All the memory management data should be here too */ 690 uint64_t gds_context_area; 691 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 692 uint64_t page_table_base; 693 uint32_t sh_mem_config; 694 uint32_t sh_mem_bases; 695 uint32_t sh_mem_ape1_base; 696 uint32_t sh_mem_ape1_limit; 697 uint32_t gds_size; 698 uint32_t num_gws; 699 uint32_t num_oac; 700 uint32_t sh_hidden_private_base; 701 702 /* CWSR memory */ 703 struct kgd_mem *cwsr_mem; 704 void *cwsr_kaddr; 705 uint64_t cwsr_base; 706 uint64_t tba_addr; 707 uint64_t tma_addr; 708 709 /* IB memory */ 710 struct kgd_mem *ib_mem; 711 uint64_t ib_base; 712 void *ib_kaddr; 713 714 /* doorbells for kfd process */ 715 struct amdgpu_bo *proc_doorbells; 716 717 /* bitmap for dynamic doorbell allocation from the bo */ 718 unsigned long *doorbell_bitmap; 719 }; 720 721 /* KFD Memory Eviction */ 722 723 /* Approx. wait time before attempting to restore evicted BOs */ 724 #define PROCESS_RESTORE_TIME_MS 100 725 /* Approx. back off time if restore fails due to lack of memory */ 726 #define PROCESS_BACK_OFF_TIME_MS 100 727 /* Approx. time before evicting the process again */ 728 #define PROCESS_ACTIVE_TIME_MS 10 729 730 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 731 * idr_handle in the least significant 4 bytes 732 */ 733 #define MAKE_HANDLE(gpu_id, idr_handle) \ 734 (((uint64_t)(gpu_id) << 32) + idr_handle) 735 #define GET_GPU_ID(handle) (handle >> 32) 736 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 737 738 enum kfd_pdd_bound { 739 PDD_UNBOUND = 0, 740 PDD_BOUND, 741 PDD_BOUND_SUSPENDED, 742 }; 743 744 #define MAX_SYSFS_FILENAME_LEN 15 745 746 /* 747 * SDMA counter runs at 100MHz frequency. 748 * We display SDMA activity in microsecond granularity in sysfs. 749 * As a result, the divisor is 100. 750 */ 751 #define SDMA_ACTIVITY_DIVISOR 100 752 753 /* Data that is per-process-per device. */ 754 struct kfd_process_device { 755 /* The device that owns this data. */ 756 struct kfd_node *dev; 757 758 /* The process that owns this kfd_process_device. */ 759 struct kfd_process *process; 760 761 /* per-process-per device QCM data structure */ 762 struct qcm_process_device qpd; 763 764 /*Apertures*/ 765 uint64_t lds_base; 766 uint64_t lds_limit; 767 uint64_t gpuvm_base; 768 uint64_t gpuvm_limit; 769 uint64_t scratch_base; 770 uint64_t scratch_limit; 771 772 /* VM context for GPUVM allocations */ 773 struct file *drm_file; 774 void *drm_priv; 775 776 /* GPUVM allocations storage */ 777 struct idr alloc_idr; 778 779 /* Flag used to tell the pdd has dequeued from the dqm. 780 * This is used to prevent dev->dqm->ops.process_termination() from 781 * being called twice when it is already called in IOMMU callback 782 * function. 783 */ 784 bool already_dequeued; 785 bool runtime_inuse; 786 787 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 788 enum kfd_pdd_bound bound; 789 790 /* VRAM usage */ 791 atomic64_t vram_usage; 792 struct attribute attr_vram; 793 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 794 795 /* SDMA activity tracking */ 796 uint64_t sdma_past_activity_counter; 797 struct attribute attr_sdma; 798 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 799 800 /* Eviction activity tracking */ 801 uint64_t last_evict_timestamp; 802 atomic64_t evict_duration_counter; 803 struct attribute attr_evict; 804 805 struct kobject *kobj_stats; 806 807 /* 808 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 809 * that is associated with device encoded by "this" struct instance. The 810 * value reflects CU usage by all of the waves launched by this process 811 * on this device. A very important property of occupancy parameter is 812 * that its value is a snapshot of current use. 813 * 814 * Following is to be noted regarding how this parameter is reported: 815 * 816 * The number of waves that a CU can launch is limited by couple of 817 * parameters. These are encoded by struct amdgpu_cu_info instance 818 * that is part of every device definition. For GFX9 devices this 819 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 820 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 821 * when they do use scratch memory. This could change for future 822 * devices and therefore this example should be considered as a guide. 823 * 824 * All CU's of a device are available for the process. This may not be true 825 * under certain conditions - e.g. CU masking. 826 * 827 * Finally number of CU's that are occupied by a process is affected by both 828 * number of CU's a device has along with number of other competing processes 829 */ 830 struct attribute attr_cu_occupancy; 831 832 /* sysfs counters for GPU retry fault and page migration tracking */ 833 struct kobject *kobj_counters; 834 struct attribute attr_faults; 835 struct attribute attr_page_in; 836 struct attribute attr_page_out; 837 uint64_t faults; 838 uint64_t page_in; 839 uint64_t page_out; 840 841 /* Exception code status*/ 842 uint64_t exception_status; 843 void *vm_fault_exc_data; 844 size_t vm_fault_exc_data_size; 845 846 /* Tracks debug per-vmid request settings */ 847 uint32_t spi_dbg_override; 848 uint32_t spi_dbg_launch_mode; 849 uint32_t watch_points[4]; 850 uint32_t alloc_watch_ids; 851 852 /* 853 * If this process has been checkpointed before, then the user 854 * application will use the original gpu_id on the 855 * checkpointed node to refer to this device. 856 */ 857 uint32_t user_gpu_id; 858 859 void *proc_ctx_bo; 860 uint64_t proc_ctx_gpu_addr; 861 void *proc_ctx_cpu_ptr; 862 863 /* Tracks queue reset status */ 864 bool has_reset_queue; 865 866 u32 pasid; 867 }; 868 869 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 870 871 struct svm_range_list { 872 struct mutex lock; 873 struct rb_root_cached objects; 874 struct list_head list; 875 struct work_struct deferred_list_work; 876 struct list_head deferred_range_list; 877 struct list_head criu_svm_metadata_list; 878 spinlock_t deferred_list_lock; 879 atomic_t evicted_ranges; 880 atomic_t drain_pagefaults; 881 struct delayed_work restore_work; 882 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 883 struct task_struct *faulting_task; 884 /* check point ts decides if page fault recovery need be dropped */ 885 uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; 886 887 /* Default granularity to use in buffer migration 888 * and restoration of backing memory while handling 889 * recoverable page faults 890 */ 891 uint8_t default_granularity; 892 }; 893 894 /* Process data */ 895 struct kfd_process { 896 /* 897 * kfd_process are stored in an mm_struct*->kfd_process* 898 * hash table (kfd_processes in kfd_process.c) 899 */ 900 struct hlist_node kfd_processes; 901 902 /* 903 * Opaque pointer to mm_struct. We don't hold a reference to 904 * it so it should never be dereferenced from here. This is 905 * only used for looking up processes by their mm. 906 */ 907 void *mm; 908 909 struct kref ref; 910 struct work_struct release_work; 911 912 struct mutex mutex; 913 914 /* 915 * In any process, the thread that started main() is the lead 916 * thread and outlives the rest. 917 * It is here because amd_iommu_bind_pasid wants a task_struct. 918 * It can also be used for safely getting a reference to the 919 * mm_struct of the process. 920 */ 921 struct task_struct *lead_thread; 922 923 /* We want to receive a notification when the mm_struct is destroyed */ 924 struct mmu_notifier mmu_notifier; 925 926 /* 927 * Array of kfd_process_device pointers, 928 * one for each device the process is using. 929 */ 930 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 931 uint32_t n_pdds; 932 933 struct process_queue_manager pqm; 934 935 /*Is the user space process 32 bit?*/ 936 bool is_32bit_user_mode; 937 938 /* Event-related data */ 939 struct mutex event_mutex; 940 /* Event ID allocator and lookup */ 941 struct idr event_idr; 942 /* Event page */ 943 u64 signal_handle; 944 struct kfd_signal_page *signal_page; 945 size_t signal_mapped_size; 946 size_t signal_event_count; 947 bool signal_event_limit_reached; 948 949 /* Information used for memory eviction */ 950 void *kgd_process_info; 951 /* Eviction fence that is attached to all the BOs of this process. The 952 * fence will be triggered during eviction and new one will be created 953 * during restore 954 */ 955 struct dma_fence __rcu *ef; 956 957 /* Work items for evicting and restoring BOs */ 958 struct delayed_work eviction_work; 959 struct delayed_work restore_work; 960 /* seqno of the last scheduled eviction */ 961 unsigned int last_eviction_seqno; 962 /* Approx. the last timestamp (in jiffies) when the process was 963 * restored after an eviction 964 */ 965 unsigned long last_restore_timestamp; 966 967 /* Indicates device process is debug attached with reserved vmid. */ 968 bool debug_trap_enabled; 969 970 /* per-process-per device debug event fd file */ 971 struct file *dbg_ev_file; 972 973 /* If the process is a kfd debugger, we need to know so we can clean 974 * up at exit time. If a process enables debugging on itself, it does 975 * its own clean-up, so we don't set the flag here. We track this by 976 * counting the number of processes this process is debugging. 977 */ 978 atomic_t debugged_process_count; 979 980 /* If the process is a debugged, this is the debugger process */ 981 struct kfd_process *debugger_process; 982 983 /* Kobj for our procfs */ 984 struct kobject *kobj; 985 struct kobject *kobj_queues; 986 struct attribute attr_pasid; 987 988 /* Keep track cwsr init */ 989 bool has_cwsr; 990 991 /* Exception code enable mask and status */ 992 uint64_t exception_enable_mask; 993 uint64_t exception_status; 994 995 /* Used to drain stale interrupts */ 996 wait_queue_head_t wait_irq_drain; 997 bool irq_drain_is_open; 998 999 /* shared virtual memory registered by this process */ 1000 struct svm_range_list svms; 1001 1002 bool xnack_enabled; 1003 1004 /* Work area for debugger event writer worker. */ 1005 struct work_struct debug_event_workarea; 1006 1007 /* Tracks debug per-vmid request for debug flags */ 1008 u32 dbg_flags; 1009 1010 atomic_t poison; 1011 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 1012 bool queues_paused; 1013 1014 /* Tracks runtime enable status */ 1015 struct semaphore runtime_enable_sema; 1016 bool is_runtime_retry; 1017 struct kfd_runtime_info runtime_info; 1018 1019 /* if gpu page fault sent to KFD */ 1020 bool gpu_page_fault; 1021 }; 1022 1023 #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ 1024 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 1025 extern struct srcu_struct kfd_processes_srcu; 1026 1027 /** 1028 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 1029 * 1030 * @filep: pointer to file structure. 1031 * @p: amdkfd process pointer. 1032 * @data: pointer to arg that was copied from user. 1033 * 1034 * Return: returns ioctl completion code. 1035 */ 1036 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 1037 void *data); 1038 1039 struct amdkfd_ioctl_desc { 1040 unsigned int cmd; 1041 int flags; 1042 amdkfd_ioctl_t *func; 1043 unsigned int cmd_drv; 1044 const char *name; 1045 }; 1046 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1047 1048 int kfd_process_create_wq(void); 1049 void kfd_process_destroy_wq(void); 1050 void kfd_cleanup_processes(void); 1051 struct kfd_process *kfd_create_process(struct task_struct *thread); 1052 struct kfd_process *kfd_get_process(const struct task_struct *task); 1053 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid, 1054 struct kfd_process_device **pdd); 1055 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1056 1057 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1058 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1059 uint32_t *gpuid, uint32_t *gpuidx); 1060 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1061 uint32_t gpuidx, uint32_t *gpuid) { 1062 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1063 } 1064 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1065 struct kfd_process *p, uint32_t gpuidx) { 1066 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1067 } 1068 1069 void kfd_unref_process(struct kfd_process *p); 1070 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1071 int kfd_process_restore_queues(struct kfd_process *p); 1072 void kfd_suspend_all_processes(void); 1073 int kfd_resume_all_processes(void); 1074 1075 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1076 uint32_t gpu_id); 1077 1078 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1079 1080 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1081 struct file *drm_file); 1082 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1083 struct kfd_process *p); 1084 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1085 struct kfd_process *p); 1086 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1087 struct kfd_process *p); 1088 1089 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1090 1091 int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, 1092 struct vm_area_struct *vma); 1093 1094 /* KFD process API for creating and translating handles */ 1095 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1096 void *mem); 1097 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1098 int handle); 1099 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1100 int handle); 1101 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1102 1103 /* PASIDs */ 1104 int kfd_pasid_init(void); 1105 void kfd_pasid_exit(void); 1106 u32 kfd_pasid_alloc(void); 1107 void kfd_pasid_free(u32 pasid); 1108 1109 /* Doorbells */ 1110 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1111 int kfd_doorbell_init(struct kfd_dev *kfd); 1112 void kfd_doorbell_fini(struct kfd_dev *kfd); 1113 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1114 struct vm_area_struct *vma); 1115 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1116 unsigned int *doorbell_off); 1117 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1118 u32 read_kernel_doorbell(u32 __iomem *db); 1119 void write_kernel_doorbell(void __iomem *db, u32 value); 1120 void write_kernel_doorbell64(void __iomem *db, u64 value); 1121 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1122 struct kfd_process_device *pdd, 1123 unsigned int doorbell_id); 1124 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1125 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1126 struct kfd_process_device *pdd); 1127 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1128 struct kfd_process_device *pdd); 1129 /* GTT Sub-Allocator */ 1130 1131 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1132 struct kfd_mem_obj **mem_obj); 1133 1134 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1135 1136 extern struct device *kfd_device; 1137 1138 /* KFD's procfs */ 1139 void kfd_procfs_init(void); 1140 void kfd_procfs_shutdown(void); 1141 int kfd_procfs_add_queue(struct queue *q); 1142 void kfd_procfs_del_queue(struct queue *q); 1143 1144 /* Topology */ 1145 int kfd_topology_init(void); 1146 void kfd_topology_shutdown(void); 1147 int kfd_topology_add_device(struct kfd_node *gpu); 1148 int kfd_topology_remove_device(struct kfd_node *gpu); 1149 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1150 uint32_t proximity_domain); 1151 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1152 uint32_t proximity_domain); 1153 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1154 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1155 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1156 uint32_t vmid) 1157 { 1158 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1159 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1160 } 1161 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1162 uint32_t node_id, uint32_t vmid) { 1163 struct kfd_dev *dev = adev->kfd.dev; 1164 uint32_t i; 1165 1166 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && 1167 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && 1168 KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) 1169 return dev->nodes[0]; 1170 1171 for (i = 0; i < dev->num_nodes; i++) 1172 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1173 return dev->nodes[i]; 1174 1175 return NULL; 1176 } 1177 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1178 int kfd_numa_node_to_apic_id(int numa_node_id); 1179 1180 /* Interrupts */ 1181 #define KFD_IRQ_FENCE_CLIENTID 0xff 1182 #define KFD_IRQ_FENCE_SOURCEID 0xff 1183 #define KFD_IRQ_IS_FENCE(client, source) \ 1184 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1185 (source) == KFD_IRQ_FENCE_SOURCEID) 1186 int kfd_interrupt_init(struct kfd_node *dev); 1187 void kfd_interrupt_exit(struct kfd_node *dev); 1188 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1189 bool interrupt_is_wanted(struct kfd_node *dev, 1190 const uint32_t *ih_ring_entry, 1191 uint32_t *patched_ihre, bool *flag); 1192 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1193 void kfd_process_close_interrupt_drain(unsigned int pasid); 1194 1195 /* amdkfd Apertures */ 1196 int kfd_init_apertures(struct kfd_process *process); 1197 1198 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1199 uint64_t tba_addr, 1200 uint64_t tma_addr); 1201 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1202 bool enabled); 1203 1204 /* CWSR initialization */ 1205 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); 1206 1207 /* CRIU */ 1208 /* 1209 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1210 * structures: 1211 * kfd_criu_process_priv_data 1212 * kfd_criu_device_priv_data 1213 * kfd_criu_bo_priv_data 1214 * kfd_criu_queue_priv_data 1215 * kfd_criu_event_priv_data 1216 * kfd_criu_svm_range_priv_data 1217 */ 1218 1219 #define KFD_CRIU_PRIV_VERSION 1 1220 1221 struct kfd_criu_process_priv_data { 1222 uint32_t version; 1223 uint32_t xnack_mode; 1224 }; 1225 1226 struct kfd_criu_device_priv_data { 1227 /* For future use */ 1228 uint64_t reserved; 1229 }; 1230 1231 struct kfd_criu_bo_priv_data { 1232 uint64_t user_addr; 1233 uint32_t idr_handle; 1234 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1235 }; 1236 1237 /* 1238 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1239 * kfd_criu_svm_range_priv_data is the object type 1240 */ 1241 enum kfd_criu_object_type { 1242 KFD_CRIU_OBJECT_TYPE_QUEUE, 1243 KFD_CRIU_OBJECT_TYPE_EVENT, 1244 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1245 }; 1246 1247 struct kfd_criu_svm_range_priv_data { 1248 uint32_t object_type; 1249 uint64_t start_addr; 1250 uint64_t size; 1251 /* Variable length array of attributes */ 1252 struct kfd_ioctl_svm_attribute attrs[]; 1253 }; 1254 1255 struct kfd_criu_queue_priv_data { 1256 uint32_t object_type; 1257 uint64_t q_address; 1258 uint64_t q_size; 1259 uint64_t read_ptr_addr; 1260 uint64_t write_ptr_addr; 1261 uint64_t doorbell_off; 1262 uint64_t eop_ring_buffer_address; 1263 uint64_t ctx_save_restore_area_address; 1264 uint32_t gpu_id; 1265 uint32_t type; 1266 uint32_t format; 1267 uint32_t q_id; 1268 uint32_t priority; 1269 uint32_t q_percent; 1270 uint32_t doorbell_id; 1271 uint32_t gws; 1272 uint32_t sdma_id; 1273 uint32_t eop_ring_buffer_size; 1274 uint32_t ctx_save_restore_area_size; 1275 uint32_t ctl_stack_size; 1276 uint32_t mqd_size; 1277 }; 1278 1279 struct kfd_criu_event_priv_data { 1280 uint32_t object_type; 1281 uint64_t user_handle; 1282 uint32_t event_id; 1283 uint32_t auto_reset; 1284 uint32_t type; 1285 uint32_t signaled; 1286 1287 union { 1288 struct kfd_hsa_memory_exception_data memory_exception_data; 1289 struct kfd_hsa_hw_exception_data hw_exception_data; 1290 }; 1291 }; 1292 1293 int kfd_process_get_queue_info(struct kfd_process *p, 1294 uint32_t *num_queues, 1295 uint64_t *priv_data_sizes); 1296 1297 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1298 uint8_t __user *user_priv_data, 1299 uint64_t *priv_data_offset); 1300 1301 int kfd_criu_restore_queue(struct kfd_process *p, 1302 uint8_t __user *user_priv_data, 1303 uint64_t *priv_data_offset, 1304 uint64_t max_priv_data_size); 1305 1306 int kfd_criu_checkpoint_events(struct kfd_process *p, 1307 uint8_t __user *user_priv_data, 1308 uint64_t *priv_data_offset); 1309 1310 int kfd_criu_restore_event(struct file *devkfd, 1311 struct kfd_process *p, 1312 uint8_t __user *user_priv_data, 1313 uint64_t *priv_data_offset, 1314 uint64_t max_priv_data_size); 1315 /* CRIU - End */ 1316 1317 /* Queue Context Management */ 1318 int init_queue(struct queue **q, const struct queue_properties *properties); 1319 void uninit_queue(struct queue *q); 1320 void print_queue_properties(struct queue_properties *q); 1321 void print_queue(struct queue *q); 1322 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo, 1323 u64 expected_size); 1324 void kfd_queue_buffer_put(struct amdgpu_bo **bo); 1325 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1326 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1327 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo); 1328 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd, 1329 struct queue_properties *properties); 1330 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev); 1331 1332 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1333 struct kfd_node *dev); 1334 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1335 struct kfd_node *dev); 1336 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1337 struct kfd_node *dev); 1338 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1339 struct kfd_node *dev); 1340 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1341 struct kfd_node *dev); 1342 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 1343 struct kfd_node *dev); 1344 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1345 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1346 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1347 enum kfd_queue_type type); 1348 void kernel_queue_uninit(struct kernel_queue *kq); 1349 int kfd_evict_process_device(struct kfd_process_device *pdd); 1350 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id); 1351 1352 /* Process Queue Manager */ 1353 struct process_queue_node { 1354 struct queue *q; 1355 struct kernel_queue *kq; 1356 struct list_head process_queue_list; 1357 }; 1358 1359 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1360 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1361 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1362 void pqm_uninit(struct process_queue_manager *pqm); 1363 int pqm_create_queue(struct process_queue_manager *pqm, 1364 struct kfd_node *dev, 1365 struct queue_properties *properties, 1366 unsigned int *qid, 1367 const struct kfd_criu_queue_priv_data *q_data, 1368 const void *restore_mqd, 1369 const void *restore_ctl_stack, 1370 uint32_t *p_doorbell_offset_in_process); 1371 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1372 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1373 struct queue_properties *p); 1374 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1375 struct mqd_update_info *minfo); 1376 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1377 void *gws); 1378 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1379 unsigned int qid); 1380 int pqm_get_wave_state(struct process_queue_manager *pqm, 1381 unsigned int qid, 1382 void __user *ctl_stack, 1383 u32 *ctl_stack_used_size, 1384 u32 *save_area_used_size); 1385 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1386 uint64_t exception_clear_mask, 1387 void __user *buf, 1388 int *num_qss_entries, 1389 uint32_t *entry_size); 1390 1391 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1392 uint64_t fence_value, 1393 unsigned int timeout_ms); 1394 1395 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1396 unsigned int qid, 1397 u32 *mqd_size, 1398 u32 *ctl_stack_size); 1399 /* Packet Manager */ 1400 1401 #define KFD_FENCE_COMPLETED (100) 1402 #define KFD_FENCE_INIT (10) 1403 1404 /** 1405 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring 1406 * dequeue wait counts. 1407 * 1408 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a 1409 * certain ASICs. For these ASICs, this is default value used by RESET 1410 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value 1411 * for certain ASICs. For others set it to default hardware reset value 1412 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait 1413 * 1414 */ 1415 enum kfd_config_dequeue_wait_counts_cmd { 1416 KFD_DEQUEUE_WAIT_INIT = 1, 1417 KFD_DEQUEUE_WAIT_RESET = 2, 1418 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3 1419 }; 1420 1421 1422 struct packet_manager { 1423 struct device_queue_manager *dqm; 1424 struct kernel_queue *priv_queue; 1425 struct mutex lock; 1426 bool allocated; 1427 struct kfd_mem_obj *ib_buffer_obj; 1428 unsigned int ib_size_bytes; 1429 bool is_over_subscription; 1430 1431 const struct packet_manager_funcs *pmf; 1432 }; 1433 1434 struct packet_manager_funcs { 1435 /* Support ASIC-specific packet formats for PM4 packets */ 1436 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1437 struct qcm_process_device *qpd); 1438 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1439 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1440 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1441 struct scheduling_resources *res); 1442 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1443 struct queue *q, bool is_static); 1444 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1445 enum kfd_unmap_queues_filter mode, 1446 uint32_t filter_param, bool reset); 1447 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer, 1448 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value); 1449 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1450 uint64_t fence_address, uint64_t fence_value); 1451 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1452 1453 /* Packet sizes */ 1454 int map_process_size; 1455 int runlist_size; 1456 int set_resources_size; 1457 int map_queues_size; 1458 int unmap_queues_size; 1459 int config_dequeue_wait_counts_size; 1460 int query_status_size; 1461 int release_mem_size; 1462 }; 1463 1464 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1465 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1466 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1467 1468 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1469 void pm_uninit(struct packet_manager *pm); 1470 int pm_send_set_resources(struct packet_manager *pm, 1471 struct scheduling_resources *res); 1472 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1473 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1474 uint64_t fence_value); 1475 1476 int pm_send_unmap_queue(struct packet_manager *pm, 1477 enum kfd_unmap_queues_filter mode, 1478 uint32_t filter_param, bool reset); 1479 1480 void pm_release_ib(struct packet_manager *pm); 1481 1482 int pm_config_dequeue_wait_counts(struct packet_manager *pm, 1483 enum kfd_config_dequeue_wait_counts_cmd cmd, 1484 uint32_t wait_counts_config); 1485 1486 /* Following PM funcs can be shared among VI and AI */ 1487 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1488 1489 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1490 1491 /* Events */ 1492 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1493 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1494 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; 1495 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1496 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1497 1498 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1499 1500 int kfd_event_init_process(struct kfd_process *p); 1501 void kfd_event_free_process(struct kfd_process *p); 1502 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); 1503 int kfd_wait_on_events(struct kfd_process *p, 1504 uint32_t num_events, void __user *data, 1505 bool all, uint32_t *user_timeout_ms, 1506 uint32_t *wait_result); 1507 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1508 uint32_t valid_id_bits); 1509 void kfd_signal_hw_exception_event(u32 pasid); 1510 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1511 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1512 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1513 1514 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1515 uint32_t event_type, bool auto_reset, uint32_t node_id, 1516 uint32_t *event_id, uint32_t *event_trigger_data, 1517 uint64_t *event_page_offset, uint32_t *event_slot_index); 1518 1519 int kfd_get_num_events(struct kfd_process *p); 1520 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1521 1522 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va); 1523 1524 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, 1525 struct kfd_vm_fault_info *info, 1526 struct kfd_hsa_memory_exception_data *data); 1527 1528 void kfd_signal_reset_event(struct kfd_node *dev); 1529 1530 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1531 1532 static inline void kfd_flush_tlb(struct kfd_process_device *pdd, 1533 enum TLB_FLUSH_TYPE type) 1534 { 1535 struct amdgpu_device *adev = pdd->dev->adev; 1536 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); 1537 1538 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); 1539 } 1540 1541 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1542 { 1543 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) || 1544 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1545 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1546 } 1547 1548 int kfd_send_exception_to_runtime(struct kfd_process *p, 1549 unsigned int queue_id, 1550 uint64_t error_reason); 1551 bool kfd_is_locked(struct kfd_dev *kfd); 1552 1553 /* Compute profile */ 1554 void kfd_inc_compute_active(struct kfd_node *dev); 1555 void kfd_dec_compute_active(struct kfd_node *dev); 1556 1557 /* Cgroup Support */ 1558 /* Check with device cgroup if @kfd device is accessible */ 1559 static inline int kfd_devcgroup_check_permission(struct kfd_node *node) 1560 { 1561 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1562 struct drm_device *ddev; 1563 1564 if (node->xcp) 1565 ddev = node->xcp->ddev; 1566 else 1567 ddev = adev_to_drm(node->adev); 1568 1569 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1570 ddev->render->index, 1571 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1572 #else 1573 return 0; 1574 #endif 1575 } 1576 1577 static inline bool kfd_is_first_node(struct kfd_node *node) 1578 { 1579 return (node == node->kfd->nodes[0]); 1580 } 1581 1582 /* Debugfs */ 1583 #if defined(CONFIG_DEBUG_FS) 1584 1585 void kfd_debugfs_init(void); 1586 void kfd_debugfs_fini(void); 1587 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1588 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1589 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1590 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1591 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1592 int pm_debugfs_runlist(struct seq_file *m, void *data); 1593 1594 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1595 int pm_debugfs_hang_hws(struct packet_manager *pm); 1596 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1597 1598 void kfd_debugfs_add_process(struct kfd_process *p); 1599 void kfd_debugfs_remove_process(struct kfd_process *p); 1600 1601 #else 1602 1603 static inline void kfd_debugfs_init(void) {} 1604 static inline void kfd_debugfs_fini(void) {} 1605 static inline void kfd_debugfs_add_process(struct kfd_process *p) {} 1606 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {} 1607 1608 #endif 1609 1610 #endif 1611