1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef KFD_PRIV_H_INCLUDED 25 #define KFD_PRIV_H_INCLUDED 26 27 #include <linux/hashtable.h> 28 #include <linux/mmu_notifier.h> 29 #include <linux/memremap.h> 30 #include <linux/mutex.h> 31 #include <linux/types.h> 32 #include <linux/atomic.h> 33 #include <linux/workqueue.h> 34 #include <linux/spinlock.h> 35 #include <uapi/linux/kfd_ioctl.h> 36 #include <linux/idr.h> 37 #include <linux/kfifo.h> 38 #include <linux/seq_file.h> 39 #include <linux/kref.h> 40 #include <linux/sysfs.h> 41 #include <linux/device_cgroup.h> 42 #include <drm/drm_file.h> 43 #include <drm/drm_drv.h> 44 #include <drm/drm_device.h> 45 #include <drm/drm_ioctl.h> 46 #include <kgd_kfd_interface.h> 47 #include <linux/swap.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu.h" 51 52 #define KFD_MAX_RING_ENTRY_SIZE 8 53 54 #define KFD_SYSFS_FILE_MODE 0444 55 56 /* GPU ID hash width in bits */ 57 #define KFD_GPU_ID_HASH_WIDTH 16 58 59 /* Use upper bits of mmap offset to store KFD driver specific information. 60 * BITS[63:62] - Encode MMAP type 61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to 62 * BITS[45:0] - MMAP offset value 63 * 64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these 65 * defines are w.r.t to PAGE_SIZE 66 */ 67 #define KFD_MMAP_TYPE_SHIFT 62 68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT) 69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT) 70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT) 71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT) 72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT) 73 74 #define KFD_MMAP_GPU_ID_SHIFT 46 75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \ 76 << KFD_MMAP_GPU_ID_SHIFT) 77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\ 78 & KFD_MMAP_GPU_ID_MASK) 79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \ 80 >> KFD_MMAP_GPU_ID_SHIFT) 81 82 /* 83 * When working with cp scheduler we should assign the HIQ manually or via 84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot 85 * definitions for Kaveri. In Kaveri only the first ME queues participates 86 * in the cp scheduling taking that in mind we set the HIQ slot in the 87 * second ME. 88 */ 89 #define KFD_CIK_HIQ_PIPE 4 90 #define KFD_CIK_HIQ_QUEUE 0 91 92 /* Macro for allocating structures */ 93 #define kfd_alloc_struct(ptr_to_struct) \ 94 ((typeof(ptr_to_struct)) kzalloc_obj(*ptr_to_struct)) 95 96 #define KFD_MAX_NUM_OF_PROCESSES 512 97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024 98 99 /* 100 * Size of the per-process TBA+TMA buffer: 2 pages 101 * 102 * The first chunk is the TBA used for the CWSR ISA code. The second 103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode. 104 */ 105 #define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2) 106 #define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048) 107 108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \ 109 (KFD_MAX_NUM_OF_PROCESSES * \ 110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) 111 112 #define KFD_KERNEL_QUEUE_SIZE 2048 113 114 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC 115 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time 116 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is 117 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload 118 * The format here makes CP workload 10% of total timeout 119 */ 120 #define KFD_UNMAP_LATENCY_MS \ 121 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1) 122 123 #define KFD_MAX_SDMA_QUEUES 128 124 125 /* 126 * 512 = 0x200 127 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the 128 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA. 129 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC 130 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in 131 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE. 132 */ 133 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512 134 135 /** 136 * enum kfd_ioctl_flags - KFD ioctl flags 137 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how 138 * userspace can use a given ioctl. 139 */ 140 enum kfd_ioctl_flags { 141 /* 142 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE: 143 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially 144 * perform privileged operations and load arbitrary data into MQDs and 145 * eventually HQD registers when the queue is mapped by HWS. In order to 146 * prevent this we should perform additional security checks. 147 * 148 * This is equivalent to callers with the CHECKPOINT_RESTORE capability. 149 * 150 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE, 151 * we also allow ioctls with SYS_ADMIN capability. 152 */ 153 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), 154 }; 155 /* 156 * Kernel module parameter to specify maximum number of supported queues per 157 * device 158 */ 159 extern int max_num_of_queues_per_device; 160 161 162 /* Kernel module parameter to specify the scheduling policy */ 163 extern int sched_policy; 164 165 /* 166 * Kernel module parameter to specify the maximum process 167 * number per HW scheduler 168 */ 169 extern int hws_max_conc_proc; 170 171 extern int cwsr_enable; 172 173 /* 174 * Kernel module parameter to specify whether to send sigterm to HSA process on 175 * unhandled exception 176 */ 177 extern int send_sigterm; 178 179 /* 180 * This kernel module is used to simulate large bar machine on non-large bar 181 * enabled machines. 182 */ 183 extern int debug_largebar; 184 185 /* Set sh_mem_config.retry_disable on GFX v9 */ 186 extern int amdgpu_noretry; 187 188 /* Halt if HWS hang is detected */ 189 extern int halt_if_hws_hang; 190 191 /* Whether MEC FW support GWS barriers */ 192 extern bool hws_gws_support; 193 194 /* Queue preemption timeout in ms */ 195 extern int queue_preemption_timeout_ms; 196 197 /* 198 * Don't evict process queues on vm fault 199 */ 200 extern int amdgpu_no_queue_eviction_on_vm_fault; 201 202 /* Enable eviction debug messages */ 203 extern bool debug_evictions; 204 205 extern struct mutex kfd_processes_mutex; 206 207 enum cache_policy { 208 cache_policy_coherent, 209 cache_policy_noncoherent 210 }; 211 212 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0)) 213 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1))) 214 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\ 215 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ 216 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ 217 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ 218 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) 219 220 struct kfd_node; 221 222 struct kfd_event_interrupt_class { 223 bool (*interrupt_isr)(struct kfd_node *dev, 224 const uint32_t *ih_ring_entry, uint32_t *patched_ihre, 225 bool *patched_flag); 226 void (*interrupt_wq)(struct kfd_node *dev, 227 const uint32_t *ih_ring_entry); 228 }; 229 230 struct kfd_device_info { 231 uint32_t gfx_target_version; 232 const struct kfd_event_interrupt_class *event_interrupt_class; 233 unsigned int max_pasid_bits; 234 unsigned int max_no_of_hqd; 235 unsigned int doorbell_size; 236 size_t ih_ring_entry_size; 237 uint8_t num_of_watch_points; 238 uint16_t mqd_size_aligned; 239 bool supports_cwsr; 240 bool needs_pci_atomics; 241 uint32_t no_atomic_fw_version; 242 unsigned int num_sdma_queues_per_engine; 243 unsigned int num_reserved_sdma_queues_per_engine; 244 }; 245 246 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); 247 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev); 248 249 struct kfd_mem_obj { 250 uint32_t range_start; 251 uint32_t range_end; 252 uint64_t gpu_addr; 253 uint32_t *cpu_ptr; 254 void *mem; 255 }; 256 257 struct kfd_vmid_info { 258 uint32_t first_vmid_kfd; 259 uint32_t last_vmid_kfd; 260 uint32_t vmid_num_kfd; 261 }; 262 263 #define MAX_KFD_NODES 8 264 265 struct kfd_dev; 266 267 struct kfd_node { 268 unsigned int node_id; 269 struct amdgpu_device *adev; /* Duplicated here along with keeping 270 * a copy in kfd_dev to save a hop 271 */ 272 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with 273 * keeping a copy in kfd_dev to 274 * save a hop 275 */ 276 struct kfd_vmid_info vm_info; 277 unsigned int id; /* topology stub index */ 278 uint32_t xcc_mask; /* Instance mask of XCCs present */ 279 struct amdgpu_xcp *xcp; 280 281 /* Interrupts */ 282 struct kfifo ih_fifo; 283 struct work_struct interrupt_work; 284 spinlock_t interrupt_lock; 285 286 /* 287 * Interrupts of interest to KFD are copied 288 * from the HW ring into a SW ring. 289 */ 290 bool interrupts_active; 291 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */ 292 293 /* QCM Device instance */ 294 struct device_queue_manager *dqm; 295 296 /* Global GWS resource shared between processes */ 297 void *gws; 298 299 /* Clients watching SMI events */ 300 struct list_head smi_clients; 301 spinlock_t smi_lock; 302 uint32_t reset_seq_num; 303 304 /* SRAM ECC flag */ 305 atomic_t sram_ecc_flag; 306 307 /*spm process id */ 308 unsigned int spm_pasid; 309 310 /* Maximum process number mapped to HW scheduler */ 311 unsigned int max_proc_per_quantum; 312 313 unsigned int compute_vmid_bitmap; 314 315 struct kfd_local_mem_info local_mem_info; 316 317 struct kfd_dev *kfd; 318 319 /* Track per device allocated watch points */ 320 uint32_t alloc_watch_ids; 321 spinlock_t watch_points_lock; 322 }; 323 324 struct kfd_dev { 325 struct amdgpu_device *adev; 326 327 struct kfd_device_info device_info; 328 329 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells 330 * page used by kernel queue 331 */ 332 333 struct kgd2kfd_shared_resources shared_resources; 334 335 const struct kfd2kgd_calls *kfd2kgd; 336 struct mutex doorbell_mutex; 337 338 void *gtt_mem; 339 uint64_t gtt_start_gpu_addr; 340 void *gtt_start_cpu_ptr; 341 void *gtt_sa_bitmap; 342 struct mutex gtt_sa_lock; 343 unsigned int gtt_sa_chunk_size; 344 unsigned int gtt_sa_num_of_chunks; 345 346 bool init_complete; 347 348 /* Firmware versions */ 349 uint16_t mec_fw_version; 350 uint16_t mec2_fw_version; 351 uint16_t sdma_fw_version; 352 353 /* CWSR */ 354 bool cwsr_enabled; 355 const void *cwsr_isa; 356 unsigned int cwsr_isa_size; 357 358 /* xGMI */ 359 uint64_t hive_id; 360 361 bool pci_atomic_requested; 362 363 /* Compute Profile ref. count */ 364 atomic_t compute_profile; 365 366 struct ida doorbell_ida; 367 unsigned int max_doorbell_slices; 368 369 int noretry; 370 371 struct kfd_node *nodes[MAX_KFD_NODES]; 372 unsigned int num_nodes; 373 374 struct workqueue_struct *ih_wq; 375 376 /* Kernel doorbells for KFD device */ 377 struct amdgpu_bo *doorbells; 378 379 /* bitmap for dynamic doorbell allocation from doorbell object */ 380 unsigned long *doorbell_bitmap; 381 382 /* for dynamic partitioning */ 383 int kfd_dev_lock; 384 385 atomic_t kfd_processes_count; 386 }; 387 388 enum kfd_mempool { 389 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, 390 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, 391 KFD_MEMPOOL_FRAMEBUFFER = 3, 392 }; 393 394 /* Character device interface */ 395 int kfd_chardev_init(void); 396 void kfd_chardev_exit(void); 397 398 /** 399 * enum kfd_unmap_queues_filter - Enum for queue filters. 400 * 401 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the 402 * running queues list. 403 * 404 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues 405 * in the run list. 406 * 407 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to 408 * specific process. 409 * 410 */ 411 enum kfd_unmap_queues_filter { 412 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1, 413 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2, 414 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3 415 }; 416 417 /** 418 * enum kfd_queue_type - Enum for various queue types. 419 * 420 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type. 421 * 422 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type. 423 * 424 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type. 425 * 426 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type. 427 * 428 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface. 429 * 430 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID. 431 */ 432 enum kfd_queue_type { 433 KFD_QUEUE_TYPE_COMPUTE, 434 KFD_QUEUE_TYPE_SDMA, 435 KFD_QUEUE_TYPE_HIQ, 436 KFD_QUEUE_TYPE_SDMA_XGMI, 437 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID 438 }; 439 440 enum kfd_queue_format { 441 KFD_QUEUE_FORMAT_PM4, 442 KFD_QUEUE_FORMAT_AQL 443 }; 444 445 enum KFD_QUEUE_PRIORITY { 446 KFD_QUEUE_PRIORITY_MINIMUM = 0, 447 KFD_QUEUE_PRIORITY_MAXIMUM = 15 448 }; 449 450 /** 451 * struct queue_properties 452 * 453 * @type: The queue type. 454 * 455 * @queue_id: Queue identifier. 456 * 457 * @queue_address: Queue ring buffer address. 458 * 459 * @queue_size: Queue ring buffer size. 460 * 461 * @priority: Defines the queue priority relative to other queues in the 462 * process. 463 * This is just an indication and HW scheduling may override the priority as 464 * necessary while keeping the relative prioritization. 465 * the priority granularity is from 0 to f which f is the highest priority. 466 * currently all queues are initialized with the highest priority. 467 * 468 * @queue_percent: This field is partially implemented and currently a zero in 469 * this field defines that the queue is non active. 470 * 471 * @read_ptr: User space address which points to the number of dwords the 472 * cp read from the ring buffer. This field updates automatically by the H/W. 473 * 474 * @write_ptr: Defines the number of dwords written to the ring buffer. 475 * 476 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring 477 * buffer. This field should be similar to write_ptr and the user should 478 * update this field after updating the write_ptr. 479 * 480 * @doorbell_off: The doorbell offset in the doorbell pci-bar. 481 * 482 * @is_interop: Defines if this is a interop queue. Interop queue means that 483 * the queue can access both graphics and compute resources. 484 * 485 * @is_evicted: Defines if the queue is evicted. Only active queues 486 * are evicted, rendering them inactive. 487 * 488 * @is_active: Defines if the queue is active or not. @is_active and 489 * @is_evicted are protected by the DQM lock. 490 * 491 * @is_gws: Defines if the queue has been updated to be GWS-capable or not. 492 * @is_gws should be protected by the DQM lock, since changing it can yield the 493 * possibility of updating DQM state on number of GWS queues. 494 * 495 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid 496 * of the queue. 497 * 498 * This structure represents the queue properties for each queue no matter if 499 * it's user mode or kernel mode queue. 500 * 501 */ 502 503 struct queue_properties { 504 enum kfd_queue_type type; 505 enum kfd_queue_format format; 506 unsigned int queue_id; 507 uint64_t queue_address; 508 uint64_t queue_size; 509 uint64_t metadata_queue_size; 510 uint32_t priority; 511 uint32_t queue_percent; 512 void __user *read_ptr; 513 void __user *write_ptr; 514 void __iomem *doorbell_ptr; 515 uint32_t doorbell_off; 516 bool is_interop; 517 bool is_evicted; 518 bool is_suspended; 519 bool is_being_destroyed; 520 bool is_active; 521 bool is_gws; 522 uint32_t pm4_target_xcc; 523 bool is_dbg_wa; 524 bool is_user_cu_masked; 525 bool is_reset; 526 /* Not relevant for user mode queues in cp scheduling */ 527 unsigned int vmid; 528 /* Relevant only for sdma queues*/ 529 uint32_t sdma_engine_id; 530 uint32_t sdma_queue_id; 531 uint32_t sdma_vm_addr; 532 /* Relevant only for VI */ 533 uint64_t eop_ring_buffer_address; 534 uint32_t eop_ring_buffer_size; 535 uint64_t ctx_save_restore_area_address; 536 uint32_t ctx_save_restore_area_size; 537 uint32_t ctl_stack_size; 538 uint64_t tba_addr; 539 uint64_t tma_addr; 540 uint64_t exception_status; 541 542 struct amdgpu_bo *wptr_bo; 543 struct amdgpu_bo *rptr_bo; 544 struct amdgpu_bo *ring_bo; 545 struct amdgpu_bo *eop_buf_bo; 546 struct amdgpu_bo *cwsr_bo; 547 }; 548 549 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \ 550 (q).queue_address != 0 && \ 551 (q).queue_percent > 0 && \ 552 !(q).is_evicted && \ 553 !(q).is_suspended) 554 555 enum mqd_update_flag { 556 UPDATE_FLAG_DBG_WA_ENABLE = 1, 557 UPDATE_FLAG_DBG_WA_DISABLE = 2, 558 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 559 }; 560 561 struct mqd_update_info { 562 union { 563 struct { 564 uint32_t count; /* Must be a multiple of 32 */ 565 uint32_t *ptr; 566 } cu_mask; 567 }; 568 enum mqd_update_flag update_flag; 569 }; 570 571 /** 572 * struct queue 573 * 574 * @list: Queue linked list. 575 * 576 * @mqd: The queue MQD (memory queue descriptor). 577 * 578 * @mqd_mem_obj: The MQD local gpu memory object. 579 * 580 * @gart_mqd_addr: The MQD gart mc address. 581 * 582 * @properties: The queue properties. 583 * 584 * @mec: Used only in no cp scheduling mode and identifies to micro engine id 585 * that the queue should be executed on. 586 * 587 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe 588 * id. 589 * 590 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot. 591 * 592 * @process: The kfd process that created this queue. 593 * 594 * @device: The kfd device that created this queue. 595 * 596 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL 597 * otherwise. 598 * 599 * This structure represents user mode compute queues. 600 * It contains all the necessary data to handle such queues. 601 * 602 */ 603 604 struct queue { 605 struct list_head list; 606 void *mqd; 607 struct kfd_mem_obj *mqd_mem_obj; 608 uint64_t gart_mqd_addr; 609 struct queue_properties properties; 610 611 uint32_t mec; 612 uint32_t pipe; 613 uint32_t queue; 614 615 unsigned int sdma_id; 616 unsigned int doorbell_id; 617 618 struct kfd_process *process; 619 struct kfd_node *device; 620 void *gws; 621 622 /* procfs */ 623 struct kobject kobj; 624 625 void *gang_ctx_bo; 626 uint64_t gang_ctx_gpu_addr; 627 void *gang_ctx_cpu_ptr; 628 629 struct amdgpu_bo *wptr_bo_gart; 630 }; 631 632 enum KFD_MQD_TYPE { 633 KFD_MQD_TYPE_HIQ = 0, /* for hiq */ 634 KFD_MQD_TYPE_CP, /* for cp queues and diq */ 635 KFD_MQD_TYPE_SDMA, /* for sdma queues */ 636 KFD_MQD_TYPE_DIQ, /* for diq */ 637 KFD_MQD_TYPE_MAX 638 }; 639 640 enum KFD_PIPE_PRIORITY { 641 KFD_PIPE_PRIORITY_CS_LOW = 0, 642 KFD_PIPE_PRIORITY_CS_MEDIUM, 643 KFD_PIPE_PRIORITY_CS_HIGH 644 }; 645 646 struct scheduling_resources { 647 unsigned int vmid_mask; 648 enum kfd_queue_type type; 649 uint64_t queue_mask; 650 uint64_t gws_mask; 651 uint32_t oac_mask; 652 uint32_t gds_heap_base; 653 uint32_t gds_heap_size; 654 }; 655 656 struct process_queue_manager { 657 /* data */ 658 struct kfd_process *process; 659 struct list_head queues; 660 unsigned long *queue_slot_bitmap; 661 }; 662 663 struct qcm_process_device { 664 /* The Device Queue Manager that owns this data */ 665 struct device_queue_manager *dqm; 666 struct process_queue_manager *pqm; 667 /* Queues list */ 668 struct list_head queues_list; 669 struct list_head priv_queue_list; 670 671 unsigned int queue_count; 672 unsigned int vmid; 673 bool is_debug; 674 unsigned int evicted; /* eviction counter, 0=active */ 675 676 /* This flag tells if we should reset all wavefronts on 677 * process termination 678 */ 679 bool reset_wavefronts; 680 681 /* This flag tells us if this process has a GWS-capable 682 * queue that will be mapped into the runlist. It's 683 * possible to request a GWS BO, but not have the queue 684 * currently mapped, and this changes how the MAP_PROCESS 685 * PM4 packet is configured. 686 */ 687 bool mapped_gws_queue; 688 689 /* All the memory management data should be here too */ 690 uint64_t gds_context_area; 691 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */ 692 uint64_t page_table_base; 693 uint32_t sh_mem_config; 694 uint32_t sh_mem_bases; 695 uint32_t sh_mem_ape1_base; 696 uint32_t sh_mem_ape1_limit; 697 uint32_t gds_size; 698 uint32_t num_gws; 699 uint32_t num_oac; 700 uint32_t sh_hidden_private_base; 701 uint32_t vm_cntx_cntl; 702 703 /* CWSR memory */ 704 struct kgd_mem *cwsr_mem; 705 void *cwsr_kaddr; 706 uint64_t cwsr_base; 707 uint64_t tba_addr; 708 uint64_t tma_addr; 709 710 /* IB memory */ 711 struct kgd_mem *ib_mem; 712 uint64_t ib_base; 713 void *ib_kaddr; 714 715 /* doorbells for kfd process */ 716 struct amdgpu_bo *proc_doorbells; 717 718 /* bitmap for dynamic doorbell allocation from the bo */ 719 unsigned long *doorbell_bitmap; 720 }; 721 722 /* KFD Memory Eviction */ 723 724 /* Approx. wait time before attempting to restore evicted BOs */ 725 #define PROCESS_RESTORE_TIME_MS 100 726 /* Approx. back off time if restore fails due to lack of memory */ 727 #define PROCESS_BACK_OFF_TIME_MS 100 728 /* Approx. time before evicting the process again */ 729 #define PROCESS_ACTIVE_TIME_MS 10 730 731 /* 8 byte handle containing GPU ID in the most significant 4 bytes and 732 * idr_handle in the least significant 4 bytes 733 */ 734 #define MAKE_HANDLE(gpu_id, idr_handle) \ 735 (((uint64_t)(gpu_id) << 32) + idr_handle) 736 #define GET_GPU_ID(handle) (handle >> 32) 737 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF) 738 739 enum kfd_pdd_bound { 740 PDD_UNBOUND = 0, 741 PDD_BOUND, 742 PDD_BOUND_SUSPENDED, 743 }; 744 745 #define MAX_SYSFS_FILENAME_LEN 15 746 747 /* 748 * SDMA counter runs at 100MHz frequency. 749 * We display SDMA activity in microsecond granularity in sysfs. 750 * As a result, the divisor is 100. 751 */ 752 #define SDMA_ACTIVITY_DIVISOR 100 753 754 /* Data that is per-process-per device. */ 755 struct kfd_process_device { 756 /* The device that owns this data. */ 757 struct kfd_node *dev; 758 759 /* The process that owns this kfd_process_device. */ 760 struct kfd_process *process; 761 762 /* per-process-per device QCM data structure */ 763 struct qcm_process_device qpd; 764 765 /*Apertures*/ 766 uint64_t lds_base; 767 uint64_t lds_limit; 768 uint64_t gpuvm_base; 769 uint64_t gpuvm_limit; 770 uint64_t scratch_base; 771 uint64_t scratch_limit; 772 773 /* VM context for GPUVM allocations */ 774 struct file *drm_file; 775 void *drm_priv; 776 777 /* GPUVM allocations storage */ 778 struct idr alloc_idr; 779 780 /* Flag used to tell the pdd has dequeued from the dqm. 781 * This is used to prevent dev->dqm->ops.process_termination() from 782 * being called twice when it is already called in IOMMU callback 783 * function. 784 */ 785 bool already_dequeued; 786 bool runtime_inuse; 787 788 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */ 789 enum kfd_pdd_bound bound; 790 791 /* VRAM usage */ 792 atomic64_t vram_usage; 793 struct attribute attr_vram; 794 char vram_filename[MAX_SYSFS_FILENAME_LEN]; 795 796 /* SDMA activity tracking */ 797 uint64_t sdma_past_activity_counter; 798 struct attribute attr_sdma; 799 char sdma_filename[MAX_SYSFS_FILENAME_LEN]; 800 801 /* Eviction activity tracking */ 802 uint64_t last_evict_timestamp; 803 atomic64_t evict_duration_counter; 804 struct attribute attr_evict; 805 806 struct kobject *kobj_stats; 807 808 /* 809 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process 810 * that is associated with device encoded by "this" struct instance. The 811 * value reflects CU usage by all of the waves launched by this process 812 * on this device. A very important property of occupancy parameter is 813 * that its value is a snapshot of current use. 814 * 815 * Following is to be noted regarding how this parameter is reported: 816 * 817 * The number of waves that a CU can launch is limited by couple of 818 * parameters. These are encoded by struct amdgpu_cu_info instance 819 * that is part of every device definition. For GFX9 devices this 820 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves 821 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu) 822 * when they do use scratch memory. This could change for future 823 * devices and therefore this example should be considered as a guide. 824 * 825 * All CU's of a device are available for the process. This may not be true 826 * under certain conditions - e.g. CU masking. 827 * 828 * Finally number of CU's that are occupied by a process is affected by both 829 * number of CU's a device has along with number of other competing processes 830 */ 831 struct attribute attr_cu_occupancy; 832 833 /* sysfs counters for GPU retry fault and page migration tracking */ 834 struct kobject *kobj_counters; 835 struct attribute attr_faults; 836 struct attribute attr_page_in; 837 struct attribute attr_page_out; 838 uint64_t faults; 839 uint64_t page_in; 840 uint64_t page_out; 841 842 /* Exception code status*/ 843 uint64_t exception_status; 844 void *vm_fault_exc_data; 845 size_t vm_fault_exc_data_size; 846 847 /* Tracks debug per-vmid request settings */ 848 uint32_t spi_dbg_override; 849 uint32_t spi_dbg_launch_mode; 850 uint32_t watch_points[4]; 851 uint32_t alloc_watch_ids; 852 853 /* 854 * If this process has been checkpointed before, then the user 855 * application will use the original gpu_id on the 856 * checkpointed node to refer to this device. 857 */ 858 uint32_t user_gpu_id; 859 860 void *proc_ctx_bo; 861 uint64_t proc_ctx_gpu_addr; 862 void *proc_ctx_cpu_ptr; 863 864 /* Tracks queue reset status */ 865 bool has_reset_queue; 866 867 u32 pasid; 868 }; 869 870 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) 871 872 struct svm_range_list { 873 struct mutex lock; 874 struct rb_root_cached objects; 875 struct list_head list; 876 struct work_struct deferred_list_work; 877 struct list_head deferred_range_list; 878 struct list_head criu_svm_metadata_list; 879 spinlock_t deferred_list_lock; 880 atomic_t evicted_ranges; 881 atomic_t drain_pagefaults; 882 struct delayed_work restore_work; 883 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); 884 struct task_struct *faulting_task; 885 /* check point ts decides if page fault recovery need be dropped */ 886 uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; 887 888 /* Default granularity to use in buffer migration 889 * and restoration of backing memory while handling 890 * recoverable page faults 891 */ 892 uint8_t default_granularity; 893 }; 894 895 /* Process data */ 896 struct kfd_process { 897 /* 898 * kfd_process are stored in an mm_struct*->kfd_process* 899 * hash table (kfd_processes in kfd_process.c) 900 */ 901 struct hlist_node kfd_processes; 902 903 /* 904 * Opaque pointer to mm_struct. We don't hold a reference to 905 * it so it should never be dereferenced from here. This is 906 * only used for looking up processes by their mm. 907 */ 908 void *mm; 909 910 struct kref ref; 911 struct work_struct release_work; 912 913 struct mutex mutex; 914 915 /* 916 * In any process, the thread that started main() is the lead 917 * thread and outlives the rest. 918 * It is here because amd_iommu_bind_pasid wants a task_struct. 919 * It can also be used for safely getting a reference to the 920 * mm_struct of the process. 921 */ 922 struct task_struct *lead_thread; 923 924 /* We want to receive a notification when the mm_struct is destroyed */ 925 struct mmu_notifier mmu_notifier; 926 927 /* 928 * Array of kfd_process_device pointers, 929 * one for each device the process is using. 930 */ 931 struct kfd_process_device *pdds[MAX_GPU_INSTANCE]; 932 uint32_t n_pdds; 933 934 struct process_queue_manager pqm; 935 936 /*Is the user space process 32 bit?*/ 937 bool is_32bit_user_mode; 938 939 /* Event-related data */ 940 struct mutex event_mutex; 941 /* Event ID allocator and lookup */ 942 struct idr event_idr; 943 /* Event page */ 944 u64 signal_handle; 945 struct kfd_signal_page *signal_page; 946 size_t signal_mapped_size; 947 size_t signal_event_count; 948 bool signal_event_limit_reached; 949 950 /* Information used for memory eviction */ 951 void *kgd_process_info; 952 /* Eviction fence that is attached to all the BOs of this process. The 953 * fence will be triggered during eviction and new one will be created 954 * during restore 955 */ 956 struct dma_fence __rcu *ef; 957 958 /* Work items for evicting and restoring BOs */ 959 struct delayed_work eviction_work; 960 struct delayed_work restore_work; 961 /* seqno of the last scheduled eviction */ 962 unsigned int last_eviction_seqno; 963 /* Approx. the last timestamp (in jiffies) when the process was 964 * restored after an eviction 965 */ 966 unsigned long last_restore_timestamp; 967 968 /* Indicates device process is debug attached with reserved vmid. */ 969 bool debug_trap_enabled; 970 971 /* per-process-per device debug event fd file */ 972 struct file *dbg_ev_file; 973 974 /* If the process is a kfd debugger, we need to know so we can clean 975 * up at exit time. If a process enables debugging on itself, it does 976 * its own clean-up, so we don't set the flag here. We track this by 977 * counting the number of processes this process is debugging. 978 */ 979 atomic_t debugged_process_count; 980 981 /* If the process is a debugged, this is the debugger process */ 982 struct kfd_process *debugger_process; 983 984 /* Kobj for our procfs */ 985 struct kobject *kobj; 986 struct kobject *kobj_queues; 987 struct attribute attr_pasid; 988 989 /* Exception code enable mask and status */ 990 uint64_t exception_enable_mask; 991 uint64_t exception_status; 992 993 /* Used to drain stale interrupts */ 994 wait_queue_head_t wait_irq_drain; 995 bool irq_drain_is_open; 996 997 /* shared virtual memory registered by this process */ 998 struct svm_range_list svms; 999 1000 bool xnack_enabled; 1001 1002 /* Work area for debugger event writer worker. */ 1003 struct work_struct debug_event_workarea; 1004 1005 /* Tracks debug per-vmid request for debug flags */ 1006 u32 dbg_flags; 1007 1008 atomic_t poison; 1009 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */ 1010 bool queues_paused; 1011 1012 /* Tracks runtime enable status */ 1013 struct semaphore runtime_enable_sema; 1014 bool is_runtime_retry; 1015 struct kfd_runtime_info runtime_info; 1016 1017 /* if gpu page fault sent to KFD */ 1018 bool gpu_page_fault; 1019 1020 /*kfd context id */ 1021 u16 context_id; 1022 1023 /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */ 1024 struct ida id_table; 1025 1026 }; 1027 1028 #define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */ 1029 #define KFD_CONTEXT_ID_PRIMARY 0xFFFF 1030 #define KFD_CONTEXT_ID_MIN 0 1031 1032 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); 1033 extern struct srcu_struct kfd_processes_srcu; 1034 1035 /** 1036 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer. 1037 * 1038 * @filep: pointer to file structure. 1039 * @p: amdkfd process pointer. 1040 * @data: pointer to arg that was copied from user. 1041 * 1042 * Return: returns ioctl completion code. 1043 */ 1044 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p, 1045 void *data); 1046 1047 typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize); 1048 1049 struct amdkfd_ioctl_desc { 1050 unsigned int cmd; 1051 int flags; 1052 amdkfd_ioctl_t *func; 1053 amdkfd_ioctl_validate_t *validate; 1054 unsigned int cmd_drv; 1055 const char *name; 1056 }; 1057 bool kfd_dev_is_large_bar(struct kfd_node *dev); 1058 1059 struct kfd_process *create_process(const struct task_struct *thread, bool primary); 1060 int kfd_process_create_wq(void); 1061 void kfd_process_destroy_wq(void); 1062 void kfd_cleanup_processes(void); 1063 struct kfd_process *kfd_create_process(struct task_struct *thread); 1064 int kfd_create_process_sysfs(struct kfd_process *process); 1065 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid, 1066 struct kfd_process_device **pdd); 1067 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); 1068 struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id); 1069 1070 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); 1071 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, 1072 uint32_t *gpuid, uint32_t *gpuidx); 1073 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p, 1074 uint32_t gpuidx, uint32_t *gpuid) { 1075 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL; 1076 } 1077 static inline struct kfd_process_device *kfd_process_device_from_gpuidx( 1078 struct kfd_process *p, uint32_t gpuidx) { 1079 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL; 1080 } 1081 1082 void kfd_unref_process(struct kfd_process *p); 1083 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); 1084 int kfd_process_restore_queues(struct kfd_process *p); 1085 void kfd_suspend_all_processes(void); 1086 int kfd_resume_all_processes(void); 1087 1088 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, 1089 uint32_t gpu_id); 1090 1091 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id); 1092 1093 int kfd_process_device_init_vm(struct kfd_process_device *pdd, 1094 struct file *drm_file); 1095 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, 1096 struct kfd_process *p); 1097 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev, 1098 struct kfd_process *p); 1099 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, 1100 struct kfd_process *p); 1101 1102 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); 1103 1104 void kfd_process_notifier_release_internal(struct kfd_process *p); 1105 1106 /* KFD process API for creating and translating handles */ 1107 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, 1108 void *mem); 1109 void *kfd_process_device_translate_handle(struct kfd_process_device *p, 1110 int handle); 1111 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, 1112 int handle); 1113 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); 1114 1115 /* PASIDs */ 1116 int kfd_pasid_init(void); 1117 void kfd_pasid_exit(void); 1118 u32 kfd_pasid_alloc(void); 1119 void kfd_pasid_free(u32 pasid); 1120 1121 /* Doorbells */ 1122 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd); 1123 int kfd_doorbell_init(struct kfd_dev *kfd); 1124 void kfd_doorbell_fini(struct kfd_dev *kfd); 1125 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, 1126 struct vm_area_struct *vma); 1127 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, 1128 unsigned int *doorbell_off); 1129 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); 1130 u32 read_kernel_doorbell(u32 __iomem *db); 1131 void write_kernel_doorbell(void __iomem *db, u32 value); 1132 void write_kernel_doorbell64(void __iomem *db, u64 value); 1133 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd, 1134 struct kfd_process_device *pdd, 1135 unsigned int doorbell_id); 1136 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd); 1137 int kfd_alloc_process_doorbells(struct kfd_dev *kfd, 1138 struct kfd_process_device *pdd); 1139 void kfd_free_process_doorbells(struct kfd_dev *kfd, 1140 struct kfd_process_device *pdd); 1141 /* GTT Sub-Allocator */ 1142 1143 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1144 struct kfd_mem_obj **mem_obj); 1145 1146 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj); 1147 1148 extern struct device *kfd_device; 1149 1150 /* KFD's procfs */ 1151 void kfd_procfs_init(void); 1152 void kfd_procfs_shutdown(void); 1153 int kfd_procfs_add_queue(struct queue *q); 1154 void kfd_procfs_del_queue(struct queue *q); 1155 1156 /* Topology */ 1157 int kfd_topology_init(void); 1158 void kfd_topology_shutdown(void); 1159 int kfd_topology_add_device(struct kfd_node *gpu); 1160 int kfd_topology_remove_device(struct kfd_node *gpu); 1161 struct kfd_topology_device *kfd_topology_device_by_proximity_domain( 1162 uint32_t proximity_domain); 1163 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock( 1164 uint32_t proximity_domain); 1165 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id); 1166 struct kfd_node *kfd_device_by_id(uint32_t gpu_id); 1167 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id, 1168 uint32_t vmid) 1169 { 1170 return (node->interrupt_bitmap & (1 << node_id)) != 0 && 1171 (node->compute_vmid_bitmap & (1 << vmid)) != 0; 1172 } 1173 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, 1174 uint32_t node_id, uint32_t vmid) { 1175 struct kfd_dev *dev = adev->kfd.dev; 1176 uint32_t i; 1177 1178 /* 1179 * On multi-aid system, attempt per-node matching. Otherwise, 1180 * fall back to the first node. 1181 */ 1182 if (!amdgpu_is_multi_aid(adev)) 1183 return dev->nodes[0]; 1184 1185 for (i = 0; i < dev->num_nodes; i++) 1186 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid)) 1187 return dev->nodes[i]; 1188 1189 return NULL; 1190 } 1191 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); 1192 uint32_t kfd_topology_get_num_devices(void); 1193 int kfd_numa_node_to_apic_id(int numa_node_id); 1194 uint32_t kfd_gpu_node_num(void); 1195 1196 /* Interrupts */ 1197 #define KFD_IRQ_FENCE_CLIENTID 0xff 1198 #define KFD_IRQ_FENCE_SOURCEID 0xff 1199 #define KFD_IRQ_IS_FENCE(client, source) \ 1200 ((client) == KFD_IRQ_FENCE_CLIENTID && \ 1201 (source) == KFD_IRQ_FENCE_SOURCEID) 1202 int kfd_interrupt_init(struct kfd_node *dev); 1203 void kfd_interrupt_exit(struct kfd_node *dev); 1204 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry); 1205 bool interrupt_is_wanted(struct kfd_node *dev, 1206 const uint32_t *ih_ring_entry, 1207 uint32_t *patched_ihre, bool *flag); 1208 int kfd_process_drain_interrupts(struct kfd_process_device *pdd); 1209 void kfd_process_close_interrupt_drain(unsigned int pasid); 1210 1211 /* amdkfd Apertures */ 1212 int kfd_init_apertures(struct kfd_process *process); 1213 1214 void kfd_process_set_trap_handler(struct qcm_process_device *qpd, 1215 uint64_t tba_addr, 1216 uint64_t tma_addr); 1217 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, 1218 bool enabled); 1219 1220 /* CRIU */ 1221 /* 1222 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private 1223 * structures: 1224 * kfd_criu_process_priv_data 1225 * kfd_criu_device_priv_data 1226 * kfd_criu_bo_priv_data 1227 * kfd_criu_queue_priv_data 1228 * kfd_criu_event_priv_data 1229 * kfd_criu_svm_range_priv_data 1230 */ 1231 1232 #define KFD_CRIU_PRIV_VERSION 1 1233 1234 struct kfd_criu_process_priv_data { 1235 uint32_t version; 1236 uint32_t xnack_mode; 1237 }; 1238 1239 struct kfd_criu_device_priv_data { 1240 /* For future use */ 1241 uint64_t reserved; 1242 }; 1243 1244 struct kfd_criu_bo_priv_data { 1245 uint64_t user_addr; 1246 uint32_t idr_handle; 1247 uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; 1248 }; 1249 1250 /* 1251 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data, 1252 * kfd_criu_svm_range_priv_data is the object type 1253 */ 1254 enum kfd_criu_object_type { 1255 KFD_CRIU_OBJECT_TYPE_QUEUE, 1256 KFD_CRIU_OBJECT_TYPE_EVENT, 1257 KFD_CRIU_OBJECT_TYPE_SVM_RANGE, 1258 }; 1259 1260 struct kfd_criu_svm_range_priv_data { 1261 uint32_t object_type; 1262 uint64_t start_addr; 1263 uint64_t size; 1264 /* Variable length array of attributes */ 1265 struct kfd_ioctl_svm_attribute attrs[]; 1266 }; 1267 1268 struct kfd_criu_queue_priv_data { 1269 uint32_t object_type; 1270 uint64_t q_address; 1271 uint64_t q_size; 1272 uint64_t read_ptr_addr; 1273 uint64_t write_ptr_addr; 1274 uint64_t doorbell_off; 1275 uint64_t eop_ring_buffer_address; 1276 uint64_t ctx_save_restore_area_address; 1277 uint32_t gpu_id; 1278 uint32_t type; 1279 uint32_t format; 1280 uint32_t q_id; 1281 uint32_t priority; 1282 uint32_t q_percent; 1283 uint32_t doorbell_id; 1284 uint32_t gws; 1285 uint32_t sdma_id; 1286 uint32_t eop_ring_buffer_size; 1287 uint32_t ctx_save_restore_area_size; 1288 uint32_t ctl_stack_size; 1289 uint32_t mqd_size; 1290 }; 1291 1292 struct kfd_criu_event_priv_data { 1293 uint32_t object_type; 1294 uint64_t user_handle; 1295 uint32_t event_id; 1296 uint32_t auto_reset; 1297 uint32_t type; 1298 uint32_t signaled; 1299 1300 union { 1301 struct kfd_hsa_memory_exception_data memory_exception_data; 1302 struct kfd_hsa_hw_exception_data hw_exception_data; 1303 }; 1304 }; 1305 1306 int kfd_process_get_queue_info(struct kfd_process *p, 1307 uint32_t *num_queues, 1308 uint64_t *priv_data_sizes); 1309 1310 int kfd_criu_checkpoint_queues(struct kfd_process *p, 1311 uint8_t __user *user_priv_data, 1312 uint64_t *priv_data_offset); 1313 1314 int kfd_criu_restore_queue(struct kfd_process *p, 1315 uint8_t __user *user_priv_data, 1316 uint64_t *priv_data_offset, 1317 uint64_t max_priv_data_size); 1318 1319 int kfd_criu_checkpoint_events(struct kfd_process *p, 1320 uint8_t __user *user_priv_data, 1321 uint64_t *priv_data_offset); 1322 1323 int kfd_criu_restore_event(struct file *devkfd, 1324 struct kfd_process *p, 1325 uint8_t __user *user_priv_data, 1326 uint64_t *priv_data_offset, 1327 uint64_t max_priv_data_size); 1328 /* CRIU - End */ 1329 1330 /* Queue Context Management */ 1331 int init_queue(struct queue **q, const struct queue_properties *properties); 1332 void uninit_queue(struct queue *q); 1333 void print_queue_properties(struct queue_properties *q); 1334 void print_queue(struct queue *q); 1335 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo, 1336 u64 expected_size); 1337 void kfd_queue_buffer_put(struct amdgpu_bo **bo); 1338 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1339 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties); 1340 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo); 1341 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd, 1342 struct queue_properties *properties); 1343 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev); 1344 1345 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 1346 struct kfd_node *dev); 1347 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, 1348 struct kfd_node *dev); 1349 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 1350 struct kfd_node *dev); 1351 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 1352 struct kfd_node *dev); 1353 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 1354 struct kfd_node *dev); 1355 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 1356 struct kfd_node *dev); 1357 struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, 1358 struct kfd_node *dev); 1359 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); 1360 void device_queue_manager_uninit(struct device_queue_manager *dqm); 1361 struct kernel_queue *kernel_queue_init(struct kfd_node *dev, 1362 enum kfd_queue_type type); 1363 void kernel_queue_uninit(struct kernel_queue *kq); 1364 int kfd_evict_process_device(struct kfd_process_device *pdd); 1365 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id); 1366 1367 /* Process Queue Manager */ 1368 struct process_queue_node { 1369 struct queue *q; 1370 struct kernel_queue *kq; 1371 struct list_head process_queue_list; 1372 }; 1373 1374 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd); 1375 void kfd_process_dequeue_from_all_devices(struct kfd_process *p); 1376 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); 1377 void pqm_uninit(struct process_queue_manager *pqm); 1378 int pqm_create_queue(struct process_queue_manager *pqm, 1379 struct kfd_node *dev, 1380 struct queue_properties *properties, 1381 unsigned int *qid, 1382 const struct kfd_criu_queue_priv_data *q_data, 1383 const void *restore_mqd, 1384 const void *restore_ctl_stack, 1385 uint32_t *p_doorbell_offset_in_process); 1386 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid); 1387 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid, 1388 struct queue_properties *p); 1389 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid, 1390 struct mqd_update_info *minfo); 1391 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid, 1392 void *gws); 1393 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm, 1394 unsigned int qid); 1395 int pqm_get_wave_state(struct process_queue_manager *pqm, 1396 unsigned int qid, 1397 void __user *ctl_stack, 1398 u32 *ctl_stack_used_size, 1399 u32 *save_area_used_size); 1400 int pqm_get_queue_snapshot(struct process_queue_manager *pqm, 1401 uint64_t exception_clear_mask, 1402 void __user *buf, 1403 int *num_qss_entries, 1404 uint32_t *entry_size); 1405 1406 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, 1407 uint64_t fence_value, 1408 unsigned int timeout_ms); 1409 1410 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, 1411 unsigned int qid, 1412 u32 *mqd_size, 1413 u32 *ctl_stack_size); 1414 /* Packet Manager */ 1415 1416 #define KFD_FENCE_COMPLETED (100) 1417 #define KFD_FENCE_INIT (10) 1418 1419 /** 1420 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring 1421 * dequeue wait counts. 1422 * 1423 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a 1424 * certain ASICs. For these ASICs, this is default value used by RESET 1425 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value 1426 * for certain ASICs. For others set it to default hardware reset value 1427 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait 1428 * 1429 */ 1430 enum kfd_config_dequeue_wait_counts_cmd { 1431 KFD_DEQUEUE_WAIT_INIT = 1, 1432 KFD_DEQUEUE_WAIT_RESET = 2, 1433 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3 1434 }; 1435 1436 1437 struct packet_manager { 1438 struct device_queue_manager *dqm; 1439 struct kernel_queue *priv_queue; 1440 struct mutex lock; 1441 bool allocated; 1442 struct kfd_mem_obj *ib_buffer_obj; 1443 unsigned int ib_size_bytes; 1444 bool is_over_subscription; 1445 1446 const struct packet_manager_funcs *pmf; 1447 }; 1448 1449 struct packet_manager_funcs { 1450 /* Support ASIC-specific packet formats for PM4 packets */ 1451 int (*map_process)(struct packet_manager *pm, uint32_t *buffer, 1452 struct qcm_process_device *qpd); 1453 int (*runlist)(struct packet_manager *pm, uint32_t *buffer, 1454 uint64_t ib, size_t ib_size_in_dwords, bool chain); 1455 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer, 1456 struct scheduling_resources *res); 1457 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer, 1458 struct queue *q, bool is_static); 1459 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer, 1460 enum kfd_unmap_queues_filter mode, 1461 uint32_t filter_param, bool reset); 1462 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer, 1463 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value); 1464 int (*query_status)(struct packet_manager *pm, uint32_t *buffer, 1465 uint64_t fence_address, uint64_t fence_value); 1466 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); 1467 1468 /* Packet sizes */ 1469 int map_process_size; 1470 int runlist_size; 1471 int set_resources_size; 1472 int map_queues_size; 1473 int unmap_queues_size; 1474 int config_dequeue_wait_counts_size; 1475 int query_status_size; 1476 int release_mem_size; 1477 }; 1478 1479 extern const struct packet_manager_funcs kfd_vi_pm_funcs; 1480 extern const struct packet_manager_funcs kfd_v9_pm_funcs; 1481 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs; 1482 1483 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm); 1484 void pm_uninit(struct packet_manager *pm); 1485 int pm_send_set_resources(struct packet_manager *pm, 1486 struct scheduling_resources *res); 1487 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); 1488 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, 1489 uint64_t fence_value); 1490 1491 int pm_send_unmap_queue(struct packet_manager *pm, 1492 enum kfd_unmap_queues_filter mode, 1493 uint32_t filter_param, bool reset); 1494 1495 void pm_release_ib(struct packet_manager *pm); 1496 1497 int pm_config_dequeue_wait_counts(struct packet_manager *pm, 1498 enum kfd_config_dequeue_wait_counts_cmd cmd, 1499 uint32_t wait_counts_config); 1500 1501 /* Following PM funcs can be shared among VI and AI */ 1502 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size); 1503 1504 uint64_t kfd_get_number_elems(struct kfd_dev *kfd); 1505 1506 /* Events */ 1507 extern const struct kfd_event_interrupt_class event_interrupt_class_cik; 1508 extern const struct kfd_event_interrupt_class event_interrupt_class_v9; 1509 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; 1510 extern const struct kfd_event_interrupt_class event_interrupt_class_v10; 1511 extern const struct kfd_event_interrupt_class event_interrupt_class_v11; 1512 extern const struct kfd_event_interrupt_class event_interrupt_class_v12_1; 1513 1514 extern const struct kfd_device_global_init_class device_global_init_class_cik; 1515 1516 int kfd_event_init_process(struct kfd_process *p); 1517 void kfd_event_free_process(struct kfd_process *p); 1518 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma); 1519 int kfd_wait_on_events(struct kfd_process *p, 1520 uint32_t num_events, void __user *data, 1521 bool all, uint32_t *user_timeout_ms, 1522 uint32_t *wait_result); 1523 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, 1524 uint32_t valid_id_bits, bool signal_mailbox_updated); 1525 void kfd_signal_hw_exception_event(u32 pasid); 1526 int kfd_set_event(struct kfd_process *p, uint32_t event_id); 1527 int kfd_reset_event(struct kfd_process *p, uint32_t event_id); 1528 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset); 1529 1530 int kfd_event_create(struct file *devkfd, struct kfd_process *p, 1531 uint32_t event_type, bool auto_reset, uint32_t node_id, 1532 uint32_t *event_id, uint32_t *event_trigger_data, 1533 uint64_t *event_page_offset, uint32_t *event_slot_index); 1534 1535 int kfd_get_num_events(struct kfd_process *p); 1536 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id); 1537 1538 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va); 1539 1540 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, 1541 struct kfd_vm_fault_info *info, 1542 struct kfd_hsa_memory_exception_data *data); 1543 1544 void kfd_signal_reset_event(struct kfd_node *dev); 1545 1546 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); 1547 void kfd_signal_process_terminate_event(struct kfd_process *p); 1548 1549 static inline void kfd_flush_tlb(struct kfd_process_device *pdd) 1550 { 1551 struct amdgpu_device *adev = pdd->dev->adev; 1552 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv); 1553 1554 amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT, 1555 pdd->dev->xcc_mask); 1556 } 1557 1558 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) 1559 { 1560 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) || 1561 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || 1562 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); 1563 } 1564 1565 int kfd_send_exception_to_runtime(struct kfd_process *p, 1566 unsigned int queue_id, 1567 uint64_t error_reason); 1568 bool kfd_is_locked(struct kfd_dev *kfd); 1569 1570 /* Compute profile */ 1571 void kfd_inc_compute_active(struct kfd_node *dev); 1572 void kfd_dec_compute_active(struct kfd_node *dev); 1573 1574 /* Cgroup Support */ 1575 /* Check with device cgroup if @kfd device is accessible */ 1576 static inline int kfd_devcgroup_check_permission(struct kfd_node *node) 1577 { 1578 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1579 struct drm_device *ddev; 1580 1581 if (node->xcp) 1582 ddev = node->xcp->ddev; 1583 else 1584 ddev = adev_to_drm(node->adev); 1585 1586 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1587 ddev->render->index, 1588 DEVCG_ACC_WRITE | DEVCG_ACC_READ); 1589 #else 1590 return 0; 1591 #endif 1592 } 1593 1594 static inline bool kfd_is_first_node(struct kfd_node *node) 1595 { 1596 return (node == node->kfd->nodes[0]); 1597 } 1598 1599 /* Debugfs */ 1600 #if defined(CONFIG_DEBUG_FS) 1601 1602 void kfd_debugfs_init(void); 1603 void kfd_debugfs_fini(void); 1604 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data); 1605 int pqm_debugfs_mqds(struct seq_file *m, void *data); 1606 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data); 1607 int dqm_debugfs_hqds(struct seq_file *m, void *data); 1608 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data); 1609 int pm_debugfs_runlist(struct seq_file *m, void *data); 1610 1611 int kfd_debugfs_hang_hws(struct kfd_node *dev); 1612 int pm_debugfs_hang_hws(struct packet_manager *pm); 1613 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm); 1614 1615 void kfd_debugfs_add_process(struct kfd_process *p); 1616 void kfd_debugfs_remove_process(struct kfd_process *p); 1617 1618 #else 1619 1620 static inline void kfd_debugfs_init(void) {} 1621 static inline void kfd_debugfs_fini(void) {} 1622 static inline void kfd_debugfs_add_process(struct kfd_process *p) {} 1623 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {} 1624 1625 #endif 1626 1627 #endif 1628