1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 #include "kfd_device_queue_manager.h" 36 37 static void update_mqd(struct mqd_manager *mm, void *mqd, 38 struct queue_properties *q, 39 struct mqd_update_info *minfo); 40 41 static uint64_t mqd_stride_v9(struct mqd_manager *mm, 42 struct queue_properties *q) 43 { 44 if (mm->dev->kfd->cwsr_enabled && 45 q->type == KFD_QUEUE_TYPE_COMPUTE) 46 return ALIGN(q->ctl_stack_size, PAGE_SIZE) + 47 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); 48 49 return mm->mqd_size; 50 } 51 52 static inline struct v9_mqd *get_mqd(void *mqd) 53 { 54 return (struct v9_mqd *)mqd; 55 } 56 57 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 58 { 59 return (struct v9_sdma_mqd *)mqd; 60 } 61 62 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 63 struct mqd_update_info *minfo, uint32_t inst) 64 { 65 struct v9_mqd *m; 66 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 67 68 if (!minfo || !minfo->cu_mask.ptr) 69 return; 70 71 mqd_symmetrically_map_cu_mask(mm, 72 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); 73 74 m = get_mqd(mqd); 75 76 m->compute_static_thread_mgmt_se0 = se_mask[0]; 77 m->compute_static_thread_mgmt_se1 = se_mask[1]; 78 m->compute_static_thread_mgmt_se2 = se_mask[2]; 79 m->compute_static_thread_mgmt_se3 = se_mask[3]; 80 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 81 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && 82 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) { 83 m->compute_static_thread_mgmt_se4 = se_mask[4]; 84 m->compute_static_thread_mgmt_se5 = se_mask[5]; 85 m->compute_static_thread_mgmt_se6 = se_mask[6]; 86 m->compute_static_thread_mgmt_se7 = se_mask[7]; 87 88 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 89 m->compute_static_thread_mgmt_se0, 90 m->compute_static_thread_mgmt_se1, 91 m->compute_static_thread_mgmt_se2, 92 m->compute_static_thread_mgmt_se3, 93 m->compute_static_thread_mgmt_se4, 94 m->compute_static_thread_mgmt_se5, 95 m->compute_static_thread_mgmt_se6, 96 m->compute_static_thread_mgmt_se7); 97 } else { 98 pr_debug("inst: %u, update cu mask to %#x %#x %#x %#x\n", 99 inst, m->compute_static_thread_mgmt_se0, 100 m->compute_static_thread_mgmt_se1, 101 m->compute_static_thread_mgmt_se2, 102 m->compute_static_thread_mgmt_se3); 103 } 104 } 105 106 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 107 { 108 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 109 m->cp_hqd_queue_priority = q->priority; 110 } 111 112 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 113 struct queue_properties *q) 114 { 115 int retval; 116 struct kfd_mem_obj *mqd_mem_obj = NULL; 117 118 /* For V9 only, due to a HW bug, the control stack of a user mode 119 * compute queue needs to be allocated just behind the page boundary 120 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 121 * the first page of the buffer serves as the regular MQD buffer 122 * purpose and the remaining is for control stack. Although the two 123 * parts are in the same buffer object, they need different memory 124 * types: MQD part needs UC (uncached) as usual, while control stack 125 * needs NC (non coherent), which is different from the UC type which 126 * is used when control stack is allocated in user space. 127 * 128 * Because of all those, we use the gtt allocation function instead 129 * of sub-allocation function for this enlarged MQD buffer. Moreover, 130 * in order to achieve two memory types in a single buffer object, we 131 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 132 * amdgpu memory functions to do so. 133 */ 134 if (node->kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 135 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 136 if (!mqd_mem_obj) 137 return NULL; 138 retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev, 139 (ALIGN(q->ctl_stack_size, PAGE_SIZE) + 140 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * 141 NUM_XCC(node->xcc_mask), 142 &(mqd_mem_obj->gtt_mem), 143 &(mqd_mem_obj->gpu_addr), 144 (void *)&(mqd_mem_obj->cpu_ptr), true); 145 146 if (retval) { 147 kfree(mqd_mem_obj); 148 return NULL; 149 } 150 } else { 151 retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd), 152 &mqd_mem_obj); 153 if (retval) 154 return NULL; 155 } 156 157 return mqd_mem_obj; 158 } 159 160 static void init_mqd(struct mqd_manager *mm, void **mqd, 161 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 162 struct queue_properties *q) 163 { 164 uint64_t addr; 165 struct v9_mqd *m; 166 167 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 168 addr = mqd_mem_obj->gpu_addr; 169 170 memset(m, 0, sizeof(struct v9_mqd)); 171 172 m->header = 0xC0310800; 173 m->compute_pipelinestat_enable = 1; 174 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 175 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 176 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 177 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 178 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 179 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 180 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 181 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 182 183 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 184 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 185 186 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 187 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 188 189 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 190 191 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 192 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 193 194 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 195 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 196 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 197 198 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 199 * DISPATCH_PTR. This is required for the kfd debugger 200 */ 201 m->cp_hqd_hq_status0 = 1 << 14; 202 203 if (q->format == KFD_QUEUE_FORMAT_AQL) 204 m->cp_hqd_aql_control = 205 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 206 207 if (q->tba_addr) { 208 m->compute_pgm_rsrc2 |= 209 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 210 } 211 212 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { 213 m->cp_hqd_persistent_state |= 214 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 215 m->cp_hqd_ctx_save_base_addr_lo = 216 lower_32_bits(q->ctx_save_restore_area_address); 217 m->cp_hqd_ctx_save_base_addr_hi = 218 upper_32_bits(q->ctx_save_restore_area_address); 219 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 220 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 221 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 222 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 223 } 224 225 *mqd = m; 226 if (gart_addr) 227 *gart_addr = addr; 228 update_mqd(mm, m, q, NULL); 229 } 230 231 static int load_mqd(struct mqd_manager *mm, void *mqd, 232 uint32_t pipe_id, uint32_t queue_id, 233 struct queue_properties *p, struct mm_struct *mms) 234 { 235 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 236 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 237 238 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 239 (uint32_t __user *)p->write_ptr, 240 wptr_shift, 0, mms, 0); 241 } 242 243 static void update_mqd(struct mqd_manager *mm, void *mqd, 244 struct queue_properties *q, 245 struct mqd_update_info *minfo) 246 { 247 struct v9_mqd *m; 248 249 m = get_mqd(mqd); 250 251 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 252 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 253 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 254 255 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 256 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 257 258 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 259 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 260 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 261 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 262 263 m->cp_hqd_pq_doorbell_control = 264 q->doorbell_off << 265 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 266 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 267 m->cp_hqd_pq_doorbell_control); 268 269 m->cp_hqd_ib_control = 270 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 271 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 272 273 /* 274 * HW does not clamp this field correctly. Maximum EOP queue size 275 * is constrained by per-SE EOP done signal count, which is 8-bit. 276 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 277 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 278 * is safe, giving a maximum field value of 0xA. 279 * 280 * Also, do calculation only if EOP is used (size > 0), otherwise 281 * the order_base_2 calculation provides incorrect result. 282 * 283 */ 284 m->cp_hqd_eop_control = q->eop_ring_buffer_size ? 285 min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0; 286 287 m->cp_hqd_eop_base_addr_lo = 288 lower_32_bits(q->eop_ring_buffer_address >> 8); 289 m->cp_hqd_eop_base_addr_hi = 290 upper_32_bits(q->eop_ring_buffer_address >> 8); 291 292 m->cp_hqd_iq_timer = 0; 293 294 m->cp_hqd_vmid = q->vmid; 295 296 if (q->format == KFD_QUEUE_FORMAT_AQL) { 297 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 298 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 299 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 300 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 301 m->cp_hqd_pq_doorbell_control |= 1 << 302 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 303 } 304 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) 305 m->cp_hqd_ctx_save_control = 0; 306 307 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 308 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && 309 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) 310 update_cu_mask(mm, mqd, minfo, 0); 311 set_priority(m, q); 312 313 if (minfo && KFD_GC_VERSION(mm->dev) >= IP_VERSION(9, 4, 2)) { 314 if (minfo->update_flag & UPDATE_FLAG_IS_GWS) 315 m->compute_resource_limits |= 316 COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 317 else 318 m->compute_resource_limits &= 319 ~COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 320 } 321 322 q->is_active = QUEUE_IS_ACTIVE(*q); 323 } 324 325 326 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 327 { 328 struct v9_mqd *m = (struct v9_mqd *)mqd; 329 uint32_t doorbell_id = m->queue_doorbell_id0; 330 331 m->queue_doorbell_id0 = 0; 332 333 return kfd_check_hiq_mqd_doorbell_id(mm->dev, doorbell_id, 0); 334 } 335 336 static int get_wave_state(struct mqd_manager *mm, void *mqd, 337 struct queue_properties *q, 338 void __user *ctl_stack, 339 u32 *ctl_stack_used_size, 340 u32 *save_area_used_size) 341 { 342 struct v9_mqd *m; 343 struct kfd_context_save_area_header header; 344 345 /* Control stack is located one page after MQD. */ 346 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 347 348 m = get_mqd(mqd); 349 350 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 351 m->cp_hqd_cntl_stack_offset; 352 *save_area_used_size = m->cp_hqd_wg_state_offset - 353 m->cp_hqd_cntl_stack_size; 354 355 header.wave_state.control_stack_size = *ctl_stack_used_size; 356 header.wave_state.wave_state_size = *save_area_used_size; 357 358 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 359 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 360 361 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 362 return -EFAULT; 363 364 if (copy_to_user(ctl_stack + m->cp_hqd_cntl_stack_offset, 365 mqd_ctl_stack + m->cp_hqd_cntl_stack_offset, 366 *ctl_stack_used_size)) 367 return -EFAULT; 368 369 return 0; 370 } 371 372 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 373 { 374 struct v9_mqd *m = get_mqd(mqd); 375 376 *ctl_stack_size = m->cp_hqd_cntl_stack_size * NUM_XCC(mm->dev->xcc_mask); 377 } 378 379 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 380 { 381 struct v9_mqd *m; 382 /* Control stack is located one page after MQD. */ 383 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 384 385 m = get_mqd(mqd); 386 387 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 388 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 389 } 390 391 static void checkpoint_mqd_v9_4_3(struct mqd_manager *mm, 392 void *mqd, 393 void *mqd_dst, 394 void *ctl_stack_dst) 395 { 396 struct v9_mqd *m; 397 int xcc; 398 uint64_t size = get_mqd(mqd)->cp_mqd_stride_size; 399 400 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 401 m = get_mqd(mqd + size * xcc); 402 403 checkpoint_mqd(mm, m, 404 (uint8_t *)mqd_dst + sizeof(*m) * xcc, 405 (uint8_t *)ctl_stack_dst + m->cp_hqd_cntl_stack_size * xcc); 406 } 407 } 408 409 static void restore_mqd(struct mqd_manager *mm, void **mqd, 410 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 411 struct queue_properties *qp, 412 const void *mqd_src, 413 const void *ctl_stack_src, u32 ctl_stack_size) 414 { 415 uint64_t addr; 416 struct v9_mqd *m; 417 void *ctl_stack; 418 419 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 420 addr = mqd_mem_obj->gpu_addr; 421 422 memcpy(m, mqd_src, sizeof(*m)); 423 424 *mqd = m; 425 if (gart_addr) 426 *gart_addr = addr; 427 428 /* Control stack is located one page after MQD. */ 429 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 430 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 431 432 m->cp_hqd_pq_doorbell_control = 433 qp->doorbell_off << 434 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 435 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 436 m->cp_hqd_pq_doorbell_control); 437 438 qp->is_active = 0; 439 } 440 441 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 442 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 443 struct queue_properties *q) 444 { 445 struct v9_mqd *m; 446 447 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 448 449 m = get_mqd(*mqd); 450 451 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 452 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 453 } 454 455 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 456 enum kfd_preempt_type type, unsigned int timeout, 457 uint32_t pipe_id, uint32_t queue_id) 458 { 459 int err; 460 struct v9_mqd *m; 461 u32 doorbell_off; 462 463 m = get_mqd(mqd); 464 465 doorbell_off = m->cp_hqd_pq_doorbell_control >> 466 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 467 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 468 if (err) 469 pr_debug("Destroy HIQ MQD failed: %d\n", err); 470 471 return err; 472 } 473 474 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 475 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 476 struct queue_properties *q) 477 { 478 struct v9_sdma_mqd *m; 479 480 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 481 482 memset(m, 0, sizeof(struct v9_sdma_mqd)); 483 484 *mqd = m; 485 if (gart_addr) 486 *gart_addr = mqd_mem_obj->gpu_addr; 487 488 mm->update_mqd(mm, m, q, NULL); 489 } 490 491 #define SDMA_RLC_DUMMY_DEFAULT 0xf 492 493 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 494 struct queue_properties *q, 495 struct mqd_update_info *minfo) 496 { 497 struct v9_sdma_mqd *m; 498 499 m = get_sdma_mqd(mqd); 500 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 501 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 502 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 503 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 504 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 505 506 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 507 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 508 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 509 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 510 m->sdmax_rlcx_doorbell_offset = 511 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 512 513 m->sdma_engine_id = q->sdma_engine_id; 514 m->sdma_queue_id = q->sdma_queue_id; 515 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 516 /* Allow context switch so we don't cross-process starve with a massive 517 * command buffer of long-running SDMA commands 518 */ 519 m->sdmax_rlcx_ib_cntl |= SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK; 520 521 q->is_active = QUEUE_IS_ACTIVE(*q); 522 } 523 524 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 525 void *mqd, 526 void *mqd_dst, 527 void *ctl_stack_dst) 528 { 529 struct v9_sdma_mqd *m; 530 531 m = get_sdma_mqd(mqd); 532 533 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 534 } 535 536 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 537 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 538 struct queue_properties *qp, 539 const void *mqd_src, 540 const void *ctl_stack_src, const u32 ctl_stack_size) 541 { 542 uint64_t addr; 543 struct v9_sdma_mqd *m; 544 545 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 546 addr = mqd_mem_obj->gpu_addr; 547 548 memcpy(m, mqd_src, sizeof(*m)); 549 550 m->sdmax_rlcx_doorbell_offset = 551 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 552 553 *mqd = m; 554 if (gart_addr) 555 *gart_addr = addr; 556 557 qp->is_active = 0; 558 } 559 560 static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd, 561 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 562 struct queue_properties *q) 563 { 564 struct v9_mqd *m; 565 int xcc = 0; 566 struct kfd_mem_obj xcc_mqd_mem_obj; 567 uint64_t xcc_gart_addr = 0; 568 569 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 570 571 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 572 kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc); 573 574 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 575 576 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 577 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 578 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 579 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 580 m->cp_hqd_pq_doorbell_control |= 1 << 581 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 582 m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev); 583 if (xcc == 0) { 584 /* Set no_update_rptr = 0 in Master XCC */ 585 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 586 587 /* Set the MQD pointer and gart address to XCC0 MQD */ 588 *mqd = m; 589 *gart_addr = xcc_gart_addr; 590 } 591 } 592 } 593 594 static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd, 595 uint32_t pipe_id, uint32_t queue_id, 596 struct queue_properties *p, struct mm_struct *mms) 597 { 598 uint32_t xcc_mask = mm->dev->xcc_mask; 599 int xcc_id, err, inst = 0; 600 void *xcc_mqd; 601 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 602 603 for_each_inst(xcc_id, xcc_mask) { 604 xcc_mqd = mqd + hiq_mqd_size * inst; 605 err = mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, xcc_mqd, 606 pipe_id, queue_id, 607 p->doorbell_off, xcc_id); 608 if (err) { 609 pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst); 610 break; 611 } 612 ++inst; 613 } 614 615 return err; 616 } 617 618 static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 619 enum kfd_preempt_type type, unsigned int timeout, 620 uint32_t pipe_id, uint32_t queue_id) 621 { 622 uint32_t xcc_mask = mm->dev->xcc_mask; 623 int xcc_id, err, inst = 0; 624 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 625 struct v9_mqd *m; 626 u32 doorbell_off; 627 628 for_each_inst(xcc_id, xcc_mask) { 629 m = get_mqd(mqd + hiq_mqd_size * inst); 630 631 doorbell_off = m->cp_hqd_pq_doorbell_control >> 632 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 633 634 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); 635 if (err) { 636 pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst); 637 break; 638 } 639 ++inst; 640 } 641 642 return err; 643 } 644 645 static bool check_preemption_failed_v9_4_3(struct mqd_manager *mm, void *mqd) 646 { 647 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 648 uint32_t xcc_mask = mm->dev->xcc_mask; 649 int inst = 0, xcc_id; 650 struct v9_mqd *m; 651 bool ret = false; 652 653 for_each_inst(xcc_id, xcc_mask) { 654 m = get_mqd(mqd + hiq_mqd_size * inst); 655 ret |= kfd_check_hiq_mqd_doorbell_id(mm->dev, 656 m->queue_doorbell_id0, inst); 657 m->queue_doorbell_id0 = 0; 658 ++inst; 659 } 660 661 return ret; 662 } 663 664 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, 665 struct kfd_mem_obj *xcc_mqd_mem_obj, 666 uint64_t offset) 667 { 668 xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? 669 mqd_mem_obj->gtt_mem : NULL; 670 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 671 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 672 + offset); 673 } 674 675 static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 676 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 677 struct queue_properties *q) 678 { 679 struct v9_mqd *m; 680 int xcc = 0; 681 struct kfd_mem_obj xcc_mqd_mem_obj; 682 uint64_t xcc_gart_addr = 0; 683 uint64_t xcc_ctx_save_restore_area_address; 684 uint64_t offset = mm->mqd_stride(mm, q); 685 uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; 686 687 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 688 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 689 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 690 691 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 692 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 693 m->cp_hqd_pq_doorbell_control |= 1 << 694 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 695 m->cp_mqd_stride_size = offset; 696 697 /* 698 * Update the CWSR address for each XCC if CWSR is enabled 699 * and CWSR area is allocated in thunk 700 */ 701 if (mm->dev->kfd->cwsr_enabled && 702 q->ctx_save_restore_area_address) { 703 xcc_ctx_save_restore_area_address = 704 q->ctx_save_restore_area_address + 705 (xcc * q->ctx_save_restore_area_size); 706 707 m->cp_hqd_ctx_save_base_addr_lo = 708 lower_32_bits(xcc_ctx_save_restore_area_address); 709 m->cp_hqd_ctx_save_base_addr_hi = 710 upper_32_bits(xcc_ctx_save_restore_area_address); 711 } 712 713 if (q->format == KFD_QUEUE_FORMAT_AQL) { 714 m->compute_tg_chunk_size = 1; 715 m->compute_current_logic_xcc_id = 716 (local_xcc_start + xcc) % 717 NUM_XCC(mm->dev->xcc_mask); 718 719 switch (xcc) { 720 case 0: 721 /* Master XCC */ 722 m->cp_hqd_pq_control &= 723 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 724 break; 725 default: 726 break; 727 } 728 } else { 729 /* PM4 Queue */ 730 m->compute_current_logic_xcc_id = 0; 731 m->compute_tg_chunk_size = 0; 732 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 733 } 734 735 if (xcc == 0) { 736 /* Set the MQD pointer and gart address to XCC0 MQD */ 737 *mqd = m; 738 *gart_addr = xcc_gart_addr; 739 } 740 } 741 } 742 743 static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 744 struct queue_properties *q, struct mqd_update_info *minfo) 745 { 746 struct v9_mqd *m; 747 int xcc = 0; 748 uint64_t size = mm->mqd_stride(mm, q); 749 750 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 751 m = get_mqd(mqd + size * xcc); 752 update_mqd(mm, m, q, minfo); 753 754 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 755 m->cp_hqd_pq_doorbell_control |= 1 << 756 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 757 update_cu_mask(mm, m, minfo, xcc); 758 759 if (q->format == KFD_QUEUE_FORMAT_AQL) { 760 switch (xcc) { 761 case 0: 762 /* Master XCC */ 763 m->cp_hqd_pq_control &= 764 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 765 break; 766 default: 767 break; 768 } 769 m->compute_tg_chunk_size = 1; 770 } else { 771 /* PM4 Queue */ 772 m->compute_current_logic_xcc_id = 0; 773 m->compute_tg_chunk_size = 0; 774 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 775 } 776 } 777 } 778 779 static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 780 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 781 struct queue_properties *qp, 782 const void *mqd_src, 783 const void *ctl_stack_src, u32 ctl_stack_size) 784 { 785 struct kfd_mem_obj xcc_mqd_mem_obj; 786 u32 mqd_ctl_stack_size; 787 struct v9_mqd *m; 788 u32 num_xcc; 789 int xcc; 790 791 uint64_t offset = mm->mqd_stride(mm, qp); 792 793 mm->dev->dqm->current_logical_xcc_start++; 794 795 num_xcc = NUM_XCC(mm->dev->xcc_mask); 796 mqd_ctl_stack_size = ctl_stack_size / num_xcc; 797 798 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 799 800 /* Set the MQD pointer and gart address to XCC0 MQD */ 801 *mqd = mqd_mem_obj->cpu_ptr; 802 if (gart_addr) 803 *gart_addr = mqd_mem_obj->gpu_addr; 804 805 for (xcc = 0; xcc < num_xcc; xcc++) { 806 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset * xcc); 807 restore_mqd(mm, (void **)&m, 808 &xcc_mqd_mem_obj, 809 NULL, 810 qp, 811 (uint8_t *)mqd_src + xcc * sizeof(*m), 812 (uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size, 813 mqd_ctl_stack_size); 814 } 815 } 816 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 817 enum kfd_preempt_type type, unsigned int timeout, 818 uint32_t pipe_id, uint32_t queue_id) 819 { 820 uint32_t xcc_mask = mm->dev->xcc_mask; 821 int xcc_id, err, inst = 0; 822 void *xcc_mqd; 823 struct v9_mqd *m; 824 uint64_t mqd_offset; 825 826 m = get_mqd(mqd); 827 mqd_offset = m->cp_mqd_stride_size; 828 829 for_each_inst(xcc_id, xcc_mask) { 830 xcc_mqd = mqd + mqd_offset * inst; 831 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 832 type, timeout, pipe_id, 833 queue_id, xcc_id); 834 if (err) { 835 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 836 break; 837 } 838 ++inst; 839 } 840 841 return err; 842 } 843 844 static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 845 uint32_t pipe_id, uint32_t queue_id, 846 struct queue_properties *p, struct mm_struct *mms) 847 { 848 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 849 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 850 uint32_t xcc_mask = mm->dev->xcc_mask; 851 int xcc_id, err, inst = 0; 852 void *xcc_mqd; 853 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 854 855 for_each_inst(xcc_id, xcc_mask) { 856 xcc_mqd = mqd + mqd_stride_size * inst; 857 err = mm->dev->kfd2kgd->hqd_load( 858 mm->dev->adev, xcc_mqd, pipe_id, queue_id, 859 (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, 860 xcc_id); 861 if (err) { 862 pr_debug("Load MQD failed for xcc: %d\n", inst); 863 break; 864 } 865 ++inst; 866 } 867 868 return err; 869 } 870 871 static int get_wave_state_v9_4_3(struct mqd_manager *mm, void *mqd, 872 struct queue_properties *q, 873 void __user *ctl_stack, 874 u32 *ctl_stack_used_size, 875 u32 *save_area_used_size) 876 { 877 int xcc, err = 0; 878 void *xcc_mqd; 879 void __user *xcc_ctl_stack; 880 uint64_t mqd_stride_size = mm->mqd_stride(mm, q); 881 u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; 882 883 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 884 xcc_mqd = mqd + mqd_stride_size * xcc; 885 xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + 886 q->ctx_save_restore_area_size * xcc); 887 888 err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, 889 &tmp_ctl_stack_used_size, 890 &tmp_save_area_used_size); 891 if (err) 892 break; 893 894 /* 895 * Set the ctl_stack_used_size and save_area_used_size to 896 * ctl_stack_used_size and save_area_used_size of XCC 0 when 897 * passing the info the user-space. 898 * For multi XCC, user-space would have to look at the header 899 * info of each Control stack area to determine the control 900 * stack size and save area used. 901 */ 902 if (xcc == 0) { 903 *ctl_stack_used_size = tmp_ctl_stack_used_size; 904 *save_area_used_size = tmp_save_area_used_size; 905 } 906 } 907 908 return err; 909 } 910 911 #if defined(CONFIG_DEBUG_FS) 912 913 static int debugfs_show_mqd(struct seq_file *m, void *data) 914 { 915 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 916 data, sizeof(struct v9_mqd), false); 917 return 0; 918 } 919 920 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 921 { 922 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 923 data, sizeof(struct v9_sdma_mqd), false); 924 return 0; 925 } 926 927 #endif 928 929 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 930 struct kfd_node *dev) 931 { 932 struct mqd_manager *mqd; 933 934 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 935 return NULL; 936 937 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 938 if (!mqd) 939 return NULL; 940 941 mqd->dev = dev; 942 943 switch (type) { 944 case KFD_MQD_TYPE_CP: 945 mqd->allocate_mqd = allocate_mqd; 946 mqd->free_mqd = kfd_free_mqd_cp; 947 mqd->is_occupied = kfd_is_occupied_cp; 948 mqd->get_checkpoint_info = get_checkpoint_info; 949 mqd->mqd_size = sizeof(struct v9_mqd); 950 mqd->mqd_stride = mqd_stride_v9; 951 #if defined(CONFIG_DEBUG_FS) 952 mqd->debugfs_show_mqd = debugfs_show_mqd; 953 #endif 954 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 955 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 956 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) { 957 mqd->init_mqd = init_mqd_v9_4_3; 958 mqd->load_mqd = load_mqd_v9_4_3; 959 mqd->update_mqd = update_mqd_v9_4_3; 960 mqd->destroy_mqd = destroy_mqd_v9_4_3; 961 mqd->get_wave_state = get_wave_state_v9_4_3; 962 mqd->checkpoint_mqd = checkpoint_mqd_v9_4_3; 963 mqd->restore_mqd = restore_mqd_v9_4_3; 964 } else { 965 mqd->init_mqd = init_mqd; 966 mqd->load_mqd = load_mqd; 967 mqd->update_mqd = update_mqd; 968 mqd->destroy_mqd = kfd_destroy_mqd_cp; 969 mqd->get_wave_state = get_wave_state; 970 mqd->checkpoint_mqd = checkpoint_mqd; 971 mqd->restore_mqd = restore_mqd; 972 } 973 break; 974 case KFD_MQD_TYPE_HIQ: 975 mqd->allocate_mqd = allocate_hiq_mqd; 976 mqd->free_mqd = free_mqd_hiq_sdma; 977 mqd->update_mqd = update_mqd; 978 mqd->is_occupied = kfd_is_occupied_cp; 979 mqd->mqd_size = sizeof(struct v9_mqd); 980 mqd->mqd_stride = kfd_mqd_stride; 981 #if defined(CONFIG_DEBUG_FS) 982 mqd->debugfs_show_mqd = debugfs_show_mqd; 983 #endif 984 mqd->check_preemption_failed = check_preemption_failed; 985 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 986 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 987 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) { 988 mqd->init_mqd = init_mqd_hiq_v9_4_3; 989 mqd->load_mqd = hiq_load_mqd_kiq_v9_4_3; 990 mqd->destroy_mqd = destroy_hiq_mqd_v9_4_3; 991 mqd->check_preemption_failed = check_preemption_failed_v9_4_3; 992 } else { 993 mqd->init_mqd = init_mqd_hiq; 994 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 995 mqd->destroy_mqd = destroy_hiq_mqd; 996 mqd->check_preemption_failed = check_preemption_failed; 997 } 998 break; 999 case KFD_MQD_TYPE_DIQ: 1000 mqd->allocate_mqd = allocate_mqd; 1001 mqd->init_mqd = init_mqd_hiq; 1002 mqd->free_mqd = kfd_free_mqd_cp; 1003 mqd->load_mqd = load_mqd; 1004 mqd->update_mqd = update_mqd; 1005 mqd->destroy_mqd = kfd_destroy_mqd_cp; 1006 mqd->is_occupied = kfd_is_occupied_cp; 1007 mqd->mqd_size = sizeof(struct v9_mqd); 1008 #if defined(CONFIG_DEBUG_FS) 1009 mqd->debugfs_show_mqd = debugfs_show_mqd; 1010 #endif 1011 break; 1012 case KFD_MQD_TYPE_SDMA: 1013 mqd->allocate_mqd = allocate_sdma_mqd; 1014 mqd->init_mqd = init_mqd_sdma; 1015 mqd->free_mqd = free_mqd_hiq_sdma; 1016 mqd->load_mqd = kfd_load_mqd_sdma; 1017 mqd->update_mqd = update_mqd_sdma; 1018 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 1019 mqd->is_occupied = kfd_is_occupied_sdma; 1020 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 1021 mqd->restore_mqd = restore_mqd_sdma; 1022 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 1023 mqd->mqd_stride = kfd_mqd_stride; 1024 #if defined(CONFIG_DEBUG_FS) 1025 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 1026 #endif 1027 break; 1028 default: 1029 kfree(mqd); 1030 return NULL; 1031 } 1032 1033 return mqd; 1034 } 1035