1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 #include "kfd_device_queue_manager.h" 36 37 static void update_mqd(struct mqd_manager *mm, void *mqd, 38 struct queue_properties *q, 39 struct mqd_update_info *minfo); 40 41 static uint64_t mqd_stride_v9(struct mqd_manager *mm, 42 struct queue_properties *q) 43 { 44 if (mm->dev->kfd->cwsr_enabled && 45 q->type == KFD_QUEUE_TYPE_COMPUTE) { 46 47 /* On gfxv9, the MQD resides in the first 4K page, 48 * followed by the control stack. Align both to 49 * AMDGPU_GPU_PAGE_SIZE to maintain the required 4K boundary. 50 */ 51 52 return ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + 53 ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE); 54 } 55 56 return mm->mqd_size; 57 } 58 59 static inline struct v9_mqd *get_mqd(void *mqd) 60 { 61 return (struct v9_mqd *)mqd; 62 } 63 64 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 65 { 66 return (struct v9_sdma_mqd *)mqd; 67 } 68 69 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 70 struct mqd_update_info *minfo, uint32_t inst) 71 { 72 struct v9_mqd *m; 73 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 74 75 if (!minfo || !minfo->cu_mask.ptr) 76 return; 77 78 mqd_symmetrically_map_cu_mask(mm, 79 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); 80 81 m = get_mqd(mqd); 82 83 m->compute_static_thread_mgmt_se0 = se_mask[0]; 84 m->compute_static_thread_mgmt_se1 = se_mask[1]; 85 m->compute_static_thread_mgmt_se2 = se_mask[2]; 86 m->compute_static_thread_mgmt_se3 = se_mask[3]; 87 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 88 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && 89 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) { 90 m->compute_static_thread_mgmt_se4 = se_mask[4]; 91 m->compute_static_thread_mgmt_se5 = se_mask[5]; 92 m->compute_static_thread_mgmt_se6 = se_mask[6]; 93 m->compute_static_thread_mgmt_se7 = se_mask[7]; 94 95 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 96 m->compute_static_thread_mgmt_se0, 97 m->compute_static_thread_mgmt_se1, 98 m->compute_static_thread_mgmt_se2, 99 m->compute_static_thread_mgmt_se3, 100 m->compute_static_thread_mgmt_se4, 101 m->compute_static_thread_mgmt_se5, 102 m->compute_static_thread_mgmt_se6, 103 m->compute_static_thread_mgmt_se7); 104 } else { 105 pr_debug("inst: %u, update cu mask to %#x %#x %#x %#x\n", 106 inst, m->compute_static_thread_mgmt_se0, 107 m->compute_static_thread_mgmt_se1, 108 m->compute_static_thread_mgmt_se2, 109 m->compute_static_thread_mgmt_se3); 110 } 111 } 112 113 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 114 { 115 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 116 } 117 118 static bool mqd_on_vram(struct amdgpu_device *adev) 119 { 120 if (adev->apu_prefer_gtt) 121 return false; 122 123 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 124 case IP_VERSION(9, 4, 3): 125 case IP_VERSION(9, 5, 0): 126 return true; 127 default: 128 return false; 129 } 130 } 131 132 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 133 struct queue_properties *q) 134 { 135 int retval; 136 struct kfd_node *node = mm->dev; 137 struct kfd_mem_obj *mqd_mem_obj = NULL; 138 139 /* For V9 only, due to a HW bug, the control stack of a user mode 140 * compute queue needs to be allocated just behind the page boundary 141 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 142 * the first page of the buffer serves as the regular MQD buffer 143 * purpose and the remaining is for control stack. Although the two 144 * parts are in the same buffer object, they need different memory 145 * types: MQD part needs UC (uncached) as usual, while control stack 146 * needs NC (non coherent), which is different from the UC type which 147 * is used when control stack is allocated in user space. 148 * 149 * Because of all those, we use the gtt allocation function instead 150 * of sub-allocation function for this enlarged MQD buffer. Moreover, 151 * in order to achieve two memory types in a single buffer object, we 152 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 153 * amdgpu memory functions to do so. 154 */ 155 if (node->kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 156 mqd_mem_obj = kzalloc_obj(struct kfd_mem_obj); 157 if (!mqd_mem_obj) 158 return NULL; 159 retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev, 160 (ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + 161 ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE)) * 162 NUM_XCC(node->xcc_mask), 163 mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM : 164 AMDGPU_GEM_DOMAIN_GTT, 165 &(mqd_mem_obj->mem), 166 &(mqd_mem_obj->gpu_addr), 167 (void *)&(mqd_mem_obj->cpu_ptr), true); 168 169 if (retval) { 170 kfree(mqd_mem_obj); 171 return NULL; 172 } 173 } else { 174 retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd), 175 &mqd_mem_obj); 176 if (retval) 177 return NULL; 178 } 179 180 return mqd_mem_obj; 181 } 182 183 static void init_mqd(struct mqd_manager *mm, void **mqd, 184 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 185 struct queue_properties *q) 186 { 187 uint64_t addr; 188 struct v9_mqd *m; 189 190 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 191 addr = mqd_mem_obj->gpu_addr; 192 193 memset(m, 0, sizeof(struct v9_mqd)); 194 195 m->header = 0xC0310800; 196 m->compute_pipelinestat_enable = 1; 197 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 198 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 199 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 200 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 201 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 202 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 203 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 204 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 205 206 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 207 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 208 209 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 210 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 211 212 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 213 214 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 215 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 216 217 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 218 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 219 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 220 221 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 222 * DISPATCH_PTR. This is required for the kfd debugger 223 */ 224 m->cp_hqd_hq_status0 = 1 << 14; 225 226 if (q->format == KFD_QUEUE_FORMAT_AQL) 227 m->cp_hqd_aql_control = 228 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 229 230 if (q->tba_addr) { 231 m->compute_pgm_rsrc2 |= 232 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 233 } 234 235 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { 236 m->cp_hqd_persistent_state |= 237 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 238 m->cp_hqd_ctx_save_base_addr_lo = 239 lower_32_bits(q->ctx_save_restore_area_address); 240 m->cp_hqd_ctx_save_base_addr_hi = 241 upper_32_bits(q->ctx_save_restore_area_address); 242 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 243 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 244 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 245 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 246 } 247 248 *mqd = m; 249 if (gart_addr) 250 *gart_addr = addr; 251 update_mqd(mm, m, q, NULL); 252 } 253 254 static int load_mqd(struct mqd_manager *mm, void *mqd, 255 uint32_t pipe_id, uint32_t queue_id, 256 struct queue_properties *p, struct mm_struct *mms) 257 { 258 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 259 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 260 261 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 262 (uint32_t __user *)p->write_ptr, 263 wptr_shift, 0, mms, 0); 264 } 265 266 static void update_mqd(struct mqd_manager *mm, void *mqd, 267 struct queue_properties *q, 268 struct mqd_update_info *minfo) 269 { 270 struct v9_mqd *m; 271 272 m = get_mqd(mqd); 273 274 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 275 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 276 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 277 278 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 279 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 280 281 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 282 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 283 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 284 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 285 286 m->cp_hqd_pq_doorbell_control = 287 q->doorbell_off << 288 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 289 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 290 m->cp_hqd_pq_doorbell_control); 291 292 m->cp_hqd_ib_control = 293 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 294 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 295 296 /* 297 * HW does not clamp this field correctly. Maximum EOP queue size 298 * is constrained by per-SE EOP done signal count, which is 8-bit. 299 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 300 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 301 * is safe, giving a maximum field value of 0xA. 302 * 303 * Also, do calculation only if EOP is used (size > 0), otherwise 304 * the order_base_2 calculation provides incorrect result. 305 * 306 */ 307 m->cp_hqd_eop_control = q->eop_ring_buffer_size ? 308 min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0; 309 310 m->cp_hqd_eop_base_addr_lo = 311 lower_32_bits(q->eop_ring_buffer_address >> 8); 312 m->cp_hqd_eop_base_addr_hi = 313 upper_32_bits(q->eop_ring_buffer_address >> 8); 314 315 m->cp_hqd_iq_timer = 0; 316 317 m->cp_hqd_vmid = q->vmid; 318 319 if (q->format == KFD_QUEUE_FORMAT_AQL) { 320 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 321 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 322 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 323 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 324 m->cp_hqd_pq_doorbell_control |= 1 << 325 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 326 } 327 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) 328 m->cp_hqd_ctx_save_control = 0; 329 330 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 331 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && 332 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) 333 update_cu_mask(mm, mqd, minfo, 0); 334 set_priority(m, q); 335 336 if (minfo && KFD_GC_VERSION(mm->dev) >= IP_VERSION(9, 4, 2)) { 337 if (minfo->update_flag & UPDATE_FLAG_IS_GWS) 338 m->compute_resource_limits |= 339 COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 340 else 341 m->compute_resource_limits &= 342 ~COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 343 } 344 345 q->is_active = QUEUE_IS_ACTIVE(*q); 346 } 347 348 349 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 350 { 351 struct v9_mqd *m = (struct v9_mqd *)mqd; 352 uint32_t doorbell_id = m->queue_doorbell_id0; 353 354 m->queue_doorbell_id0 = 0; 355 356 return kfd_check_hiq_mqd_doorbell_id(mm->dev, doorbell_id, 0); 357 } 358 359 static int get_wave_state(struct mqd_manager *mm, void *mqd, 360 struct queue_properties *q, 361 void __user *ctl_stack, 362 u32 *ctl_stack_used_size, 363 u32 *save_area_used_size) 364 { 365 struct v9_mqd *m; 366 struct kfd_context_save_area_header header; 367 u32 cntl_stack_size; 368 u32 cntl_stack_offset; 369 370 /* Control stack is located one page after MQD. */ 371 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); 372 373 m = get_mqd(mqd); 374 cntl_stack_size = min_t(u32, m->cp_hqd_cntl_stack_size, q->ctl_stack_size); 375 cntl_stack_offset = min_t(u32, m->cp_hqd_cntl_stack_offset, cntl_stack_size); 376 377 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 378 m->cp_hqd_cntl_stack_offset; 379 *save_area_used_size = m->cp_hqd_wg_state_offset - 380 m->cp_hqd_cntl_stack_size; 381 382 header.wave_state.control_stack_size = *ctl_stack_used_size; 383 header.wave_state.wave_state_size = *save_area_used_size; 384 385 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 386 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 387 388 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 389 return -EFAULT; 390 391 *ctl_stack_used_size = cntl_stack_size - cntl_stack_offset; 392 393 if (copy_to_user(ctl_stack + cntl_stack_offset, mqd_ctl_stack + cntl_stack_offset, 394 *ctl_stack_used_size)) 395 return -EFAULT; 396 397 return 0; 398 } 399 400 static int get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 401 { 402 struct v9_mqd *m = get_mqd(mqd); 403 404 if (check_mul_overflow(m->cp_hqd_cntl_stack_size, NUM_XCC(mm->dev->xcc_mask), ctl_stack_size)) 405 return -EINVAL; 406 407 return 0; 408 } 409 410 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 411 { 412 struct v9_mqd *m; 413 /* Control stack is located one page after MQD. */ 414 void *ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); 415 416 m = get_mqd(mqd); 417 418 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 419 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 420 } 421 422 static void checkpoint_mqd_v9_4_3(struct mqd_manager *mm, 423 void *mqd, 424 void *mqd_dst, 425 void *ctl_stack_dst) 426 { 427 struct v9_mqd *m; 428 int xcc; 429 uint64_t size = get_mqd(mqd)->cp_mqd_stride_size; 430 431 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 432 m = get_mqd(mqd + size * xcc); 433 434 checkpoint_mqd(mm, m, 435 (uint8_t *)mqd_dst + sizeof(*m) * xcc, 436 (uint8_t *)ctl_stack_dst + m->cp_hqd_cntl_stack_size * xcc); 437 } 438 } 439 440 static void restore_mqd(struct mqd_manager *mm, void **mqd, 441 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 442 struct queue_properties *qp, 443 const void *mqd_src, 444 const void *ctl_stack_src, u32 ctl_stack_size) 445 { 446 uint64_t addr; 447 struct v9_mqd *m; 448 void *ctl_stack; 449 450 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 451 addr = mqd_mem_obj->gpu_addr; 452 453 memcpy(m, mqd_src, sizeof(*m)); 454 455 *mqd = m; 456 if (gart_addr) 457 *gart_addr = addr; 458 459 /* Control stack is located one page after MQD. */ 460 ctl_stack = (void *)((uintptr_t)*mqd + AMDGPU_GPU_PAGE_SIZE); 461 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 462 463 m->cp_hqd_pq_doorbell_control = 464 qp->doorbell_off << 465 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 466 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 467 m->cp_hqd_pq_doorbell_control); 468 469 qp->is_active = 0; 470 } 471 472 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 473 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 474 struct queue_properties *q) 475 { 476 struct v9_mqd *m; 477 478 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 479 480 m = get_mqd(*mqd); 481 482 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 483 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 484 } 485 486 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 487 enum kfd_preempt_type type, unsigned int timeout, 488 uint32_t pipe_id, uint32_t queue_id) 489 { 490 int err; 491 struct v9_mqd *m; 492 u32 doorbell_off; 493 494 m = get_mqd(mqd); 495 496 doorbell_off = m->cp_hqd_pq_doorbell_control >> 497 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 498 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 499 if (err) 500 pr_debug("Destroy HIQ MQD failed: %d\n", err); 501 502 return err; 503 } 504 505 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 506 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 507 struct queue_properties *q) 508 { 509 struct v9_sdma_mqd *m; 510 511 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 512 513 memset(m, 0, sizeof(struct v9_sdma_mqd)); 514 515 *mqd = m; 516 if (gart_addr) 517 *gart_addr = mqd_mem_obj->gpu_addr; 518 519 mm->update_mqd(mm, m, q, NULL); 520 } 521 522 #define SDMA_RLC_DUMMY_DEFAULT 0xf 523 524 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 525 struct queue_properties *q, 526 struct mqd_update_info *minfo) 527 { 528 struct v9_sdma_mqd *m; 529 530 m = get_sdma_mqd(mqd); 531 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 532 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 533 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 534 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 535 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 536 537 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 538 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 539 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 540 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 541 m->sdmax_rlcx_doorbell_offset = 542 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 543 544 m->sdma_engine_id = q->sdma_engine_id; 545 m->sdma_queue_id = q->sdma_queue_id; 546 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 547 /* Allow context switch so we don't cross-process starve with a massive 548 * command buffer of long-running SDMA commands 549 */ 550 m->sdmax_rlcx_ib_cntl |= SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK; 551 552 q->is_active = QUEUE_IS_ACTIVE(*q); 553 } 554 555 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 556 void *mqd, 557 void *mqd_dst, 558 void *ctl_stack_dst) 559 { 560 struct v9_sdma_mqd *m; 561 562 m = get_sdma_mqd(mqd); 563 564 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 565 } 566 567 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 568 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 569 struct queue_properties *qp, 570 const void *mqd_src, 571 const void *ctl_stack_src, const u32 ctl_stack_size) 572 { 573 uint64_t addr; 574 struct v9_sdma_mqd *m; 575 576 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 577 addr = mqd_mem_obj->gpu_addr; 578 579 memcpy(m, mqd_src, sizeof(*m)); 580 581 m->sdmax_rlcx_doorbell_offset = 582 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 583 584 *mqd = m; 585 if (gart_addr) 586 *gart_addr = addr; 587 588 qp->is_active = 0; 589 } 590 591 static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd, 592 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 593 struct queue_properties *q) 594 { 595 struct v9_mqd *m; 596 int xcc = 0; 597 struct kfd_mem_obj xcc_mqd_mem_obj; 598 uint64_t xcc_gart_addr = 0; 599 600 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 601 602 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 603 kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc); 604 605 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 606 607 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 608 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 609 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 610 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 611 m->cp_hqd_pq_doorbell_control |= 1 << 612 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 613 m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev); 614 if (xcc == 0) { 615 /* Set no_update_rptr = 0 in Master XCC */ 616 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 617 618 /* Set the MQD pointer and gart address to XCC0 MQD */ 619 *mqd = m; 620 *gart_addr = xcc_gart_addr; 621 } 622 } 623 } 624 625 static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd, 626 uint32_t pipe_id, uint32_t queue_id, 627 struct queue_properties *p, struct mm_struct *mms) 628 { 629 uint32_t xcc_mask = mm->dev->xcc_mask; 630 int xcc_id, err = 0, inst = 0; 631 void *xcc_mqd; 632 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 633 634 for_each_inst(xcc_id, xcc_mask) { 635 xcc_mqd = mqd + hiq_mqd_size * inst; 636 err = mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, xcc_mqd, 637 pipe_id, queue_id, 638 p->doorbell_off, xcc_id); 639 if (err) { 640 pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst); 641 break; 642 } 643 ++inst; 644 } 645 646 return err; 647 } 648 649 static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 650 enum kfd_preempt_type type, unsigned int timeout, 651 uint32_t pipe_id, uint32_t queue_id) 652 { 653 uint32_t xcc_mask = mm->dev->xcc_mask; 654 int xcc_id, err = 0, inst = 0; 655 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 656 struct v9_mqd *m; 657 u32 doorbell_off; 658 659 for_each_inst(xcc_id, xcc_mask) { 660 m = get_mqd(mqd + hiq_mqd_size * inst); 661 662 doorbell_off = m->cp_hqd_pq_doorbell_control >> 663 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 664 665 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); 666 if (err) { 667 pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst); 668 break; 669 } 670 ++inst; 671 } 672 673 return err; 674 } 675 676 static bool check_preemption_failed_v9_4_3(struct mqd_manager *mm, void *mqd) 677 { 678 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 679 uint32_t xcc_mask = mm->dev->xcc_mask; 680 int inst = 0, xcc_id; 681 struct v9_mqd *m; 682 bool ret = false; 683 684 for_each_inst(xcc_id, xcc_mask) { 685 m = get_mqd(mqd + hiq_mqd_size * inst); 686 ret |= kfd_check_hiq_mqd_doorbell_id(mm->dev, 687 m->queue_doorbell_id0, inst); 688 m->queue_doorbell_id0 = 0; 689 ++inst; 690 } 691 692 return ret; 693 } 694 695 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, 696 struct kfd_mem_obj *xcc_mqd_mem_obj, 697 uint64_t offset) 698 { 699 xcc_mqd_mem_obj->mem = (offset == 0) ? 700 mqd_mem_obj->mem : NULL; 701 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 702 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 703 + offset); 704 } 705 706 static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 707 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 708 struct queue_properties *q) 709 { 710 struct v9_mqd *m; 711 int xcc = 0; 712 struct kfd_mem_obj xcc_mqd_mem_obj; 713 uint64_t xcc_gart_addr = 0; 714 uint64_t xcc_ctx_save_restore_area_address; 715 uint64_t offset = mm->mqd_stride(mm, q); 716 uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; 717 718 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 719 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 720 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 721 722 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 723 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 724 m->cp_hqd_pq_doorbell_control |= 1 << 725 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 726 m->cp_mqd_stride_size = offset; 727 728 /* 729 * Update the CWSR address for each XCC if CWSR is enabled 730 * and CWSR area is allocated in thunk 731 */ 732 if (mm->dev->kfd->cwsr_enabled && 733 q->ctx_save_restore_area_address) { 734 xcc_ctx_save_restore_area_address = 735 q->ctx_save_restore_area_address + 736 (xcc * q->ctx_save_restore_area_size); 737 738 m->cp_hqd_ctx_save_base_addr_lo = 739 lower_32_bits(xcc_ctx_save_restore_area_address); 740 m->cp_hqd_ctx_save_base_addr_hi = 741 upper_32_bits(xcc_ctx_save_restore_area_address); 742 } 743 744 if (q->format == KFD_QUEUE_FORMAT_AQL) { 745 m->compute_tg_chunk_size = 1; 746 m->compute_current_logic_xcc_id = 747 (local_xcc_start + xcc) % 748 NUM_XCC(mm->dev->xcc_mask); 749 750 switch (xcc) { 751 case 0: 752 /* Master XCC */ 753 m->cp_hqd_pq_control &= 754 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 755 break; 756 default: 757 break; 758 } 759 } else { 760 /* PM4 Queue */ 761 m->compute_current_logic_xcc_id = 0; 762 m->compute_tg_chunk_size = 0; 763 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 764 } 765 766 if (xcc == 0) { 767 /* Set the MQD pointer and gart address to XCC0 MQD */ 768 *mqd = m; 769 *gart_addr = xcc_gart_addr; 770 } 771 } 772 773 if (mqd_on_vram(mm->dev->adev)) 774 amdgpu_device_flush_hdp(mm->dev->adev, NULL); 775 } 776 777 static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 778 struct queue_properties *q, struct mqd_update_info *minfo) 779 { 780 struct v9_mqd *m; 781 int xcc = 0; 782 uint64_t size = mm->mqd_stride(mm, q); 783 784 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 785 m = get_mqd(mqd + size * xcc); 786 update_mqd(mm, m, q, minfo); 787 788 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 789 m->cp_hqd_pq_doorbell_control |= 1 << 790 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 791 update_cu_mask(mm, m, minfo, xcc); 792 793 if (q->format == KFD_QUEUE_FORMAT_AQL) { 794 switch (xcc) { 795 case 0: 796 /* Master XCC */ 797 m->cp_hqd_pq_control &= 798 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 799 break; 800 default: 801 break; 802 } 803 m->compute_tg_chunk_size = 1; 804 } else { 805 /* PM4 Queue */ 806 m->compute_current_logic_xcc_id = 0; 807 m->compute_tg_chunk_size = 0; 808 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 809 } 810 } 811 812 if (mqd_on_vram(mm->dev->adev)) 813 amdgpu_device_flush_hdp(mm->dev->adev, NULL); 814 } 815 816 static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 817 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 818 struct queue_properties *qp, 819 const void *mqd_src, 820 const void *ctl_stack_src, u32 ctl_stack_size) 821 { 822 struct kfd_mem_obj xcc_mqd_mem_obj; 823 u32 mqd_ctl_stack_size; 824 struct v9_mqd *m; 825 u32 num_xcc; 826 int xcc; 827 828 uint64_t offset = mm->mqd_stride(mm, qp); 829 830 mm->dev->dqm->current_logical_xcc_start++; 831 832 num_xcc = NUM_XCC(mm->dev->xcc_mask); 833 mqd_ctl_stack_size = ctl_stack_size / num_xcc; 834 835 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 836 837 /* Set the MQD pointer and gart address to XCC0 MQD */ 838 *mqd = mqd_mem_obj->cpu_ptr; 839 if (gart_addr) 840 *gart_addr = mqd_mem_obj->gpu_addr; 841 842 for (xcc = 0; xcc < num_xcc; xcc++) { 843 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset * xcc); 844 restore_mqd(mm, (void **)&m, 845 &xcc_mqd_mem_obj, 846 NULL, 847 qp, 848 (uint8_t *)mqd_src + xcc * sizeof(*m), 849 (uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size, 850 mqd_ctl_stack_size); 851 } 852 853 if (mqd_on_vram(mm->dev->adev)) 854 amdgpu_device_flush_hdp(mm->dev->adev, NULL); 855 } 856 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 857 enum kfd_preempt_type type, unsigned int timeout, 858 uint32_t pipe_id, uint32_t queue_id) 859 { 860 uint32_t xcc_mask = mm->dev->xcc_mask; 861 int xcc_id, err = 0, inst = 0; 862 void *xcc_mqd; 863 struct v9_mqd *m; 864 uint64_t mqd_offset; 865 866 m = get_mqd(mqd); 867 mqd_offset = m->cp_mqd_stride_size; 868 869 for_each_inst(xcc_id, xcc_mask) { 870 xcc_mqd = mqd + mqd_offset * inst; 871 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 872 type, timeout, pipe_id, 873 queue_id, xcc_id); 874 if (err) { 875 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 876 break; 877 } 878 ++inst; 879 } 880 881 return err; 882 } 883 884 static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 885 uint32_t pipe_id, uint32_t queue_id, 886 struct queue_properties *p, struct mm_struct *mms) 887 { 888 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 889 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 890 uint32_t xcc_mask = mm->dev->xcc_mask; 891 int xcc_id, err = 0, inst = 0; 892 void *xcc_mqd; 893 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 894 895 for_each_inst(xcc_id, xcc_mask) { 896 xcc_mqd = mqd + mqd_stride_size * inst; 897 err = mm->dev->kfd2kgd->hqd_load( 898 mm->dev->adev, xcc_mqd, pipe_id, queue_id, 899 (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, 900 xcc_id); 901 if (err) { 902 pr_debug("Load MQD failed for xcc: %d\n", inst); 903 break; 904 } 905 ++inst; 906 } 907 908 return err; 909 } 910 911 static int get_wave_state_v9_4_3(struct mqd_manager *mm, void *mqd, 912 struct queue_properties *q, 913 void __user *ctl_stack, 914 u32 *ctl_stack_used_size, 915 u32 *save_area_used_size) 916 { 917 int xcc, err = 0; 918 void *xcc_mqd; 919 void __user *xcc_ctl_stack; 920 uint64_t mqd_stride_size = mm->mqd_stride(mm, q); 921 u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; 922 923 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 924 xcc_mqd = mqd + mqd_stride_size * xcc; 925 xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + 926 q->ctx_save_restore_area_size * xcc); 927 928 err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, 929 &tmp_ctl_stack_used_size, 930 &tmp_save_area_used_size); 931 if (err) 932 break; 933 934 /* 935 * Set the ctl_stack_used_size and save_area_used_size to 936 * ctl_stack_used_size and save_area_used_size of XCC 0 when 937 * passing the info the user-space. 938 * For multi XCC, user-space would have to look at the header 939 * info of each Control stack area to determine the control 940 * stack size and save area used. 941 */ 942 if (xcc == 0) { 943 *ctl_stack_used_size = tmp_ctl_stack_used_size; 944 *save_area_used_size = tmp_save_area_used_size; 945 } 946 } 947 948 return err; 949 } 950 951 #if defined(CONFIG_DEBUG_FS) 952 953 static int debugfs_show_mqd(struct seq_file *m, void *data) 954 { 955 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 956 data, sizeof(struct v9_mqd), false); 957 return 0; 958 } 959 960 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 961 { 962 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 963 data, sizeof(struct v9_sdma_mqd), false); 964 return 0; 965 } 966 967 #endif 968 969 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 970 struct kfd_node *dev) 971 { 972 struct mqd_manager *mqd; 973 974 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 975 return NULL; 976 977 mqd = kzalloc_obj(*mqd); 978 if (!mqd) 979 return NULL; 980 981 mqd->dev = dev; 982 983 switch (type) { 984 case KFD_MQD_TYPE_CP: 985 mqd->allocate_mqd = allocate_mqd; 986 mqd->free_mqd = kfd_free_mqd_cp; 987 mqd->is_occupied = kfd_is_occupied_cp; 988 mqd->get_checkpoint_info = get_checkpoint_info; 989 mqd->mqd_size = sizeof(struct v9_mqd); 990 mqd->mqd_stride = mqd_stride_v9; 991 #if defined(CONFIG_DEBUG_FS) 992 mqd->debugfs_show_mqd = debugfs_show_mqd; 993 #endif 994 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 995 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 996 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) { 997 mqd->init_mqd = init_mqd_v9_4_3; 998 mqd->load_mqd = load_mqd_v9_4_3; 999 mqd->update_mqd = update_mqd_v9_4_3; 1000 mqd->destroy_mqd = destroy_mqd_v9_4_3; 1001 mqd->get_wave_state = get_wave_state_v9_4_3; 1002 mqd->checkpoint_mqd = checkpoint_mqd_v9_4_3; 1003 mqd->restore_mqd = restore_mqd_v9_4_3; 1004 } else { 1005 mqd->init_mqd = init_mqd; 1006 mqd->load_mqd = load_mqd; 1007 mqd->update_mqd = update_mqd; 1008 mqd->destroy_mqd = kfd_destroy_mqd_cp; 1009 mqd->get_wave_state = get_wave_state; 1010 mqd->checkpoint_mqd = checkpoint_mqd; 1011 mqd->restore_mqd = restore_mqd; 1012 } 1013 break; 1014 case KFD_MQD_TYPE_HIQ: 1015 mqd->allocate_mqd = allocate_hiq_mqd; 1016 mqd->free_mqd = free_mqd_hiq_sdma; 1017 mqd->update_mqd = update_mqd; 1018 mqd->is_occupied = kfd_is_occupied_cp; 1019 mqd->mqd_size = sizeof(struct v9_mqd); 1020 mqd->mqd_stride = kfd_mqd_stride; 1021 #if defined(CONFIG_DEBUG_FS) 1022 mqd->debugfs_show_mqd = debugfs_show_mqd; 1023 #endif 1024 mqd->check_preemption_failed = check_preemption_failed; 1025 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 1026 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 1027 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) { 1028 mqd->init_mqd = init_mqd_hiq_v9_4_3; 1029 mqd->load_mqd = hiq_load_mqd_kiq_v9_4_3; 1030 mqd->destroy_mqd = destroy_hiq_mqd_v9_4_3; 1031 mqd->check_preemption_failed = check_preemption_failed_v9_4_3; 1032 } else { 1033 mqd->init_mqd = init_mqd_hiq; 1034 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 1035 mqd->destroy_mqd = destroy_hiq_mqd; 1036 mqd->check_preemption_failed = check_preemption_failed; 1037 } 1038 break; 1039 case KFD_MQD_TYPE_DIQ: 1040 mqd->allocate_mqd = allocate_mqd; 1041 mqd->init_mqd = init_mqd_hiq; 1042 mqd->free_mqd = kfd_free_mqd_cp; 1043 mqd->load_mqd = load_mqd; 1044 mqd->update_mqd = update_mqd; 1045 mqd->destroy_mqd = kfd_destroy_mqd_cp; 1046 mqd->is_occupied = kfd_is_occupied_cp; 1047 mqd->mqd_size = sizeof(struct v9_mqd); 1048 #if defined(CONFIG_DEBUG_FS) 1049 mqd->debugfs_show_mqd = debugfs_show_mqd; 1050 #endif 1051 break; 1052 case KFD_MQD_TYPE_SDMA: 1053 mqd->allocate_mqd = allocate_sdma_mqd; 1054 mqd->init_mqd = init_mqd_sdma; 1055 mqd->free_mqd = free_mqd_hiq_sdma; 1056 mqd->load_mqd = kfd_load_mqd_sdma; 1057 mqd->update_mqd = update_mqd_sdma; 1058 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 1059 mqd->is_occupied = kfd_is_occupied_sdma; 1060 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 1061 mqd->restore_mqd = restore_mqd_sdma; 1062 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 1063 mqd->mqd_stride = kfd_mqd_stride; 1064 #if defined(CONFIG_DEBUG_FS) 1065 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 1066 #endif 1067 break; 1068 default: 1069 kfree(mqd); 1070 return NULL; 1071 } 1072 1073 return mqd; 1074 } 1075