1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 #include "kfd_device_queue_manager.h" 36 37 static void update_mqd(struct mqd_manager *mm, void *mqd, 38 struct queue_properties *q, 39 struct mqd_update_info *minfo); 40 41 static uint64_t mqd_stride_v9(struct mqd_manager *mm, 42 struct queue_properties *q) 43 { 44 if (mm->dev->kfd->cwsr_enabled && 45 q->type == KFD_QUEUE_TYPE_COMPUTE) 46 return ALIGN(q->ctl_stack_size, PAGE_SIZE) + 47 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); 48 49 return mm->mqd_size; 50 } 51 52 static inline struct v9_mqd *get_mqd(void *mqd) 53 { 54 return (struct v9_mqd *)mqd; 55 } 56 57 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 58 { 59 return (struct v9_sdma_mqd *)mqd; 60 } 61 62 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 63 struct mqd_update_info *minfo, uint32_t inst) 64 { 65 struct v9_mqd *m; 66 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 67 68 if (!minfo || !minfo->cu_mask.ptr) 69 return; 70 71 mqd_symmetrically_map_cu_mask(mm, 72 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); 73 74 m = get_mqd(mqd); 75 76 m->compute_static_thread_mgmt_se0 = se_mask[0]; 77 m->compute_static_thread_mgmt_se1 = se_mask[1]; 78 m->compute_static_thread_mgmt_se2 = se_mask[2]; 79 m->compute_static_thread_mgmt_se3 = se_mask[3]; 80 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 81 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4)) { 82 m->compute_static_thread_mgmt_se4 = se_mask[4]; 83 m->compute_static_thread_mgmt_se5 = se_mask[5]; 84 m->compute_static_thread_mgmt_se6 = se_mask[6]; 85 m->compute_static_thread_mgmt_se7 = se_mask[7]; 86 87 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 88 m->compute_static_thread_mgmt_se0, 89 m->compute_static_thread_mgmt_se1, 90 m->compute_static_thread_mgmt_se2, 91 m->compute_static_thread_mgmt_se3, 92 m->compute_static_thread_mgmt_se4, 93 m->compute_static_thread_mgmt_se5, 94 m->compute_static_thread_mgmt_se6, 95 m->compute_static_thread_mgmt_se7); 96 } else { 97 pr_debug("inst: %u, update cu mask to %#x %#x %#x %#x\n", 98 inst, m->compute_static_thread_mgmt_se0, 99 m->compute_static_thread_mgmt_se1, 100 m->compute_static_thread_mgmt_se2, 101 m->compute_static_thread_mgmt_se3); 102 } 103 } 104 105 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 106 { 107 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 108 m->cp_hqd_queue_priority = q->priority; 109 } 110 111 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 112 struct queue_properties *q) 113 { 114 int retval; 115 struct kfd_mem_obj *mqd_mem_obj = NULL; 116 117 /* For V9 only, due to a HW bug, the control stack of a user mode 118 * compute queue needs to be allocated just behind the page boundary 119 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 120 * the first page of the buffer serves as the regular MQD buffer 121 * purpose and the remaining is for control stack. Although the two 122 * parts are in the same buffer object, they need different memory 123 * types: MQD part needs UC (uncached) as usual, while control stack 124 * needs NC (non coherent), which is different from the UC type which 125 * is used when control stack is allocated in user space. 126 * 127 * Because of all those, we use the gtt allocation function instead 128 * of sub-allocation function for this enlarged MQD buffer. Moreover, 129 * in order to achieve two memory types in a single buffer object, we 130 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 131 * amdgpu memory functions to do so. 132 */ 133 if (node->kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 134 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 135 if (!mqd_mem_obj) 136 return NULL; 137 retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev, 138 (ALIGN(q->ctl_stack_size, PAGE_SIZE) + 139 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * 140 NUM_XCC(node->xcc_mask), 141 &(mqd_mem_obj->gtt_mem), 142 &(mqd_mem_obj->gpu_addr), 143 (void *)&(mqd_mem_obj->cpu_ptr), true); 144 145 if (retval) { 146 kfree(mqd_mem_obj); 147 return NULL; 148 } 149 } else { 150 retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd), 151 &mqd_mem_obj); 152 if (retval) 153 return NULL; 154 } 155 156 return mqd_mem_obj; 157 } 158 159 static void init_mqd(struct mqd_manager *mm, void **mqd, 160 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 161 struct queue_properties *q) 162 { 163 uint64_t addr; 164 struct v9_mqd *m; 165 166 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 167 addr = mqd_mem_obj->gpu_addr; 168 169 memset(m, 0, sizeof(struct v9_mqd)); 170 171 m->header = 0xC0310800; 172 m->compute_pipelinestat_enable = 1; 173 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 174 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 175 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 176 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 177 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 178 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 179 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 180 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 181 182 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 183 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 184 185 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 186 187 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 188 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 189 190 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 191 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 192 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 193 194 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 195 * DISPATCH_PTR. This is required for the kfd debugger 196 */ 197 m->cp_hqd_hq_status0 = 1 << 14; 198 199 if (q->format == KFD_QUEUE_FORMAT_AQL) 200 m->cp_hqd_aql_control = 201 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 202 203 if (q->tba_addr) { 204 m->compute_pgm_rsrc2 |= 205 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 206 } 207 208 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { 209 m->cp_hqd_persistent_state |= 210 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 211 m->cp_hqd_ctx_save_base_addr_lo = 212 lower_32_bits(q->ctx_save_restore_area_address); 213 m->cp_hqd_ctx_save_base_addr_hi = 214 upper_32_bits(q->ctx_save_restore_area_address); 215 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 216 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 217 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 218 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 219 } 220 221 *mqd = m; 222 if (gart_addr) 223 *gart_addr = addr; 224 update_mqd(mm, m, q, NULL); 225 } 226 227 static int load_mqd(struct mqd_manager *mm, void *mqd, 228 uint32_t pipe_id, uint32_t queue_id, 229 struct queue_properties *p, struct mm_struct *mms) 230 { 231 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 232 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 233 234 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 235 (uint32_t __user *)p->write_ptr, 236 wptr_shift, 0, mms, 0); 237 } 238 239 static void update_mqd(struct mqd_manager *mm, void *mqd, 240 struct queue_properties *q, 241 struct mqd_update_info *minfo) 242 { 243 struct v9_mqd *m; 244 245 m = get_mqd(mqd); 246 247 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 248 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 249 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 250 251 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 252 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 253 254 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 255 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 256 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 257 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 258 259 m->cp_hqd_pq_doorbell_control = 260 q->doorbell_off << 261 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 262 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 263 m->cp_hqd_pq_doorbell_control); 264 265 m->cp_hqd_ib_control = 266 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 267 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 268 269 /* 270 * HW does not clamp this field correctly. Maximum EOP queue size 271 * is constrained by per-SE EOP done signal count, which is 8-bit. 272 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 273 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 274 * is safe, giving a maximum field value of 0xA. 275 * 276 * Also, do calculation only if EOP is used (size > 0), otherwise 277 * the order_base_2 calculation provides incorrect result. 278 * 279 */ 280 m->cp_hqd_eop_control = q->eop_ring_buffer_size ? 281 min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0; 282 283 m->cp_hqd_eop_base_addr_lo = 284 lower_32_bits(q->eop_ring_buffer_address >> 8); 285 m->cp_hqd_eop_base_addr_hi = 286 upper_32_bits(q->eop_ring_buffer_address >> 8); 287 288 m->cp_hqd_iq_timer = 0; 289 290 m->cp_hqd_vmid = q->vmid; 291 292 if (q->format == KFD_QUEUE_FORMAT_AQL) { 293 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 294 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 295 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 296 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 297 m->cp_hqd_pq_doorbell_control |= 1 << 298 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 299 } 300 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) 301 m->cp_hqd_ctx_save_control = 0; 302 303 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 304 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4)) 305 update_cu_mask(mm, mqd, minfo, 0); 306 set_priority(m, q); 307 308 if (minfo && KFD_GC_VERSION(mm->dev) >= IP_VERSION(9, 4, 2)) { 309 if (minfo->update_flag & UPDATE_FLAG_IS_GWS) 310 m->compute_resource_limits |= 311 COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 312 else 313 m->compute_resource_limits &= 314 ~COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 315 } 316 317 q->is_active = QUEUE_IS_ACTIVE(*q); 318 } 319 320 321 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 322 { 323 struct v9_mqd *m = (struct v9_mqd *)mqd; 324 325 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 326 } 327 328 static int get_wave_state(struct mqd_manager *mm, void *mqd, 329 struct queue_properties *q, 330 void __user *ctl_stack, 331 u32 *ctl_stack_used_size, 332 u32 *save_area_used_size) 333 { 334 struct v9_mqd *m; 335 struct kfd_context_save_area_header header; 336 337 /* Control stack is located one page after MQD. */ 338 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 339 340 m = get_mqd(mqd); 341 342 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 343 m->cp_hqd_cntl_stack_offset; 344 *save_area_used_size = m->cp_hqd_wg_state_offset - 345 m->cp_hqd_cntl_stack_size; 346 347 header.wave_state.control_stack_size = *ctl_stack_used_size; 348 header.wave_state.wave_state_size = *save_area_used_size; 349 350 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 351 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 352 353 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 354 return -EFAULT; 355 356 if (copy_to_user(ctl_stack + m->cp_hqd_cntl_stack_offset, 357 mqd_ctl_stack + m->cp_hqd_cntl_stack_offset, 358 *ctl_stack_used_size)) 359 return -EFAULT; 360 361 return 0; 362 } 363 364 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 365 { 366 struct v9_mqd *m = get_mqd(mqd); 367 368 *ctl_stack_size = m->cp_hqd_cntl_stack_size; 369 } 370 371 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 372 { 373 struct v9_mqd *m; 374 /* Control stack is located one page after MQD. */ 375 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 376 377 m = get_mqd(mqd); 378 379 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 380 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 381 } 382 383 static void restore_mqd(struct mqd_manager *mm, void **mqd, 384 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 385 struct queue_properties *qp, 386 const void *mqd_src, 387 const void *ctl_stack_src, u32 ctl_stack_size) 388 { 389 uint64_t addr; 390 struct v9_mqd *m; 391 void *ctl_stack; 392 393 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 394 addr = mqd_mem_obj->gpu_addr; 395 396 memcpy(m, mqd_src, sizeof(*m)); 397 398 *mqd = m; 399 if (gart_addr) 400 *gart_addr = addr; 401 402 /* Control stack is located one page after MQD. */ 403 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 404 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 405 406 m->cp_hqd_pq_doorbell_control = 407 qp->doorbell_off << 408 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 409 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 410 m->cp_hqd_pq_doorbell_control); 411 412 qp->is_active = 0; 413 } 414 415 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 416 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 417 struct queue_properties *q) 418 { 419 struct v9_mqd *m; 420 421 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 422 423 m = get_mqd(*mqd); 424 425 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 426 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 427 } 428 429 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 430 enum kfd_preempt_type type, unsigned int timeout, 431 uint32_t pipe_id, uint32_t queue_id) 432 { 433 int err; 434 struct v9_mqd *m; 435 u32 doorbell_off; 436 437 m = get_mqd(mqd); 438 439 doorbell_off = m->cp_hqd_pq_doorbell_control >> 440 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 441 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 442 if (err) 443 pr_debug("Destroy HIQ MQD failed: %d\n", err); 444 445 return err; 446 } 447 448 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 449 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 450 struct queue_properties *q) 451 { 452 struct v9_sdma_mqd *m; 453 454 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 455 456 memset(m, 0, sizeof(struct v9_sdma_mqd)); 457 458 *mqd = m; 459 if (gart_addr) 460 *gart_addr = mqd_mem_obj->gpu_addr; 461 462 mm->update_mqd(mm, m, q, NULL); 463 } 464 465 #define SDMA_RLC_DUMMY_DEFAULT 0xf 466 467 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 468 struct queue_properties *q, 469 struct mqd_update_info *minfo) 470 { 471 struct v9_sdma_mqd *m; 472 473 m = get_sdma_mqd(mqd); 474 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 475 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 476 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 477 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 478 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 479 480 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 481 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 482 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 483 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 484 m->sdmax_rlcx_doorbell_offset = 485 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 486 487 m->sdma_engine_id = q->sdma_engine_id; 488 m->sdma_queue_id = q->sdma_queue_id; 489 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 490 491 q->is_active = QUEUE_IS_ACTIVE(*q); 492 } 493 494 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 495 void *mqd, 496 void *mqd_dst, 497 void *ctl_stack_dst) 498 { 499 struct v9_sdma_mqd *m; 500 501 m = get_sdma_mqd(mqd); 502 503 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 504 } 505 506 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 507 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 508 struct queue_properties *qp, 509 const void *mqd_src, 510 const void *ctl_stack_src, const u32 ctl_stack_size) 511 { 512 uint64_t addr; 513 struct v9_sdma_mqd *m; 514 515 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 516 addr = mqd_mem_obj->gpu_addr; 517 518 memcpy(m, mqd_src, sizeof(*m)); 519 520 m->sdmax_rlcx_doorbell_offset = 521 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 522 523 *mqd = m; 524 if (gart_addr) 525 *gart_addr = addr; 526 527 qp->is_active = 0; 528 } 529 530 static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd, 531 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 532 struct queue_properties *q) 533 { 534 struct v9_mqd *m; 535 int xcc = 0; 536 struct kfd_mem_obj xcc_mqd_mem_obj; 537 uint64_t xcc_gart_addr = 0; 538 539 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 540 541 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 542 kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc); 543 544 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 545 546 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 547 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 548 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 549 if (amdgpu_sriov_vf(mm->dev->adev)) 550 m->cp_hqd_pq_doorbell_control |= 1 << 551 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 552 m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev); 553 if (xcc == 0) { 554 /* Set no_update_rptr = 0 in Master XCC */ 555 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 556 557 /* Set the MQD pointer and gart address to XCC0 MQD */ 558 *mqd = m; 559 *gart_addr = xcc_gart_addr; 560 } 561 } 562 } 563 564 static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd, 565 uint32_t pipe_id, uint32_t queue_id, 566 struct queue_properties *p, struct mm_struct *mms) 567 { 568 uint32_t xcc_mask = mm->dev->xcc_mask; 569 int xcc_id, err, inst = 0; 570 void *xcc_mqd; 571 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 572 573 for_each_inst(xcc_id, xcc_mask) { 574 xcc_mqd = mqd + hiq_mqd_size * inst; 575 err = mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, xcc_mqd, 576 pipe_id, queue_id, 577 p->doorbell_off, xcc_id); 578 if (err) { 579 pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst); 580 break; 581 } 582 ++inst; 583 } 584 585 return err; 586 } 587 588 static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 589 enum kfd_preempt_type type, unsigned int timeout, 590 uint32_t pipe_id, uint32_t queue_id) 591 { 592 uint32_t xcc_mask = mm->dev->xcc_mask; 593 int xcc_id, err, inst = 0; 594 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 595 struct v9_mqd *m; 596 u32 doorbell_off; 597 598 for_each_inst(xcc_id, xcc_mask) { 599 m = get_mqd(mqd + hiq_mqd_size * inst); 600 601 doorbell_off = m->cp_hqd_pq_doorbell_control >> 602 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 603 604 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); 605 if (err) { 606 pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst); 607 break; 608 } 609 ++inst; 610 } 611 612 return err; 613 } 614 615 static bool check_preemption_failed_v9_4_3(struct mqd_manager *mm, void *mqd) 616 { 617 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 618 uint32_t xcc_mask = mm->dev->xcc_mask; 619 int inst = 0, xcc_id; 620 struct v9_mqd *m; 621 bool ret = false; 622 623 for_each_inst(xcc_id, xcc_mask) { 624 m = get_mqd(mqd + hiq_mqd_size * inst); 625 ret |= kfd_check_hiq_mqd_doorbell_id(mm->dev, 626 m->queue_doorbell_id0, inst); 627 ++inst; 628 } 629 630 return ret; 631 } 632 633 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, 634 struct kfd_mem_obj *xcc_mqd_mem_obj, 635 uint64_t offset) 636 { 637 xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? 638 mqd_mem_obj->gtt_mem : NULL; 639 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 640 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 641 + offset); 642 } 643 644 static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 645 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 646 struct queue_properties *q) 647 { 648 struct v9_mqd *m; 649 int xcc = 0; 650 struct kfd_mem_obj xcc_mqd_mem_obj; 651 uint64_t xcc_gart_addr = 0; 652 uint64_t xcc_ctx_save_restore_area_address; 653 uint64_t offset = mm->mqd_stride(mm, q); 654 uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; 655 656 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 657 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 658 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 659 660 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 661 662 m->cp_mqd_stride_size = offset; 663 664 /* 665 * Update the CWSR address for each XCC if CWSR is enabled 666 * and CWSR area is allocated in thunk 667 */ 668 if (mm->dev->kfd->cwsr_enabled && 669 q->ctx_save_restore_area_address) { 670 xcc_ctx_save_restore_area_address = 671 q->ctx_save_restore_area_address + 672 (xcc * q->ctx_save_restore_area_size); 673 674 m->cp_hqd_ctx_save_base_addr_lo = 675 lower_32_bits(xcc_ctx_save_restore_area_address); 676 m->cp_hqd_ctx_save_base_addr_hi = 677 upper_32_bits(xcc_ctx_save_restore_area_address); 678 } 679 680 if (q->format == KFD_QUEUE_FORMAT_AQL) { 681 m->compute_tg_chunk_size = 1; 682 m->compute_current_logic_xcc_id = 683 (local_xcc_start + xcc) % 684 NUM_XCC(mm->dev->xcc_mask); 685 686 switch (xcc) { 687 case 0: 688 /* Master XCC */ 689 m->cp_hqd_pq_control &= 690 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 691 break; 692 default: 693 break; 694 } 695 } else { 696 /* PM4 Queue */ 697 m->compute_current_logic_xcc_id = 0; 698 m->compute_tg_chunk_size = 0; 699 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 700 } 701 702 if (xcc == 0) { 703 /* Set the MQD pointer and gart address to XCC0 MQD */ 704 *mqd = m; 705 *gart_addr = xcc_gart_addr; 706 } 707 } 708 } 709 710 static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 711 struct queue_properties *q, struct mqd_update_info *minfo) 712 { 713 struct v9_mqd *m; 714 int xcc = 0; 715 uint64_t size = mm->mqd_stride(mm, q); 716 717 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 718 m = get_mqd(mqd + size * xcc); 719 update_mqd(mm, m, q, minfo); 720 721 update_cu_mask(mm, m, minfo, xcc); 722 723 if (q->format == KFD_QUEUE_FORMAT_AQL) { 724 switch (xcc) { 725 case 0: 726 /* Master XCC */ 727 m->cp_hqd_pq_control &= 728 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 729 break; 730 default: 731 break; 732 } 733 m->compute_tg_chunk_size = 1; 734 } else { 735 /* PM4 Queue */ 736 m->compute_current_logic_xcc_id = 0; 737 m->compute_tg_chunk_size = 0; 738 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 739 } 740 } 741 } 742 743 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 744 enum kfd_preempt_type type, unsigned int timeout, 745 uint32_t pipe_id, uint32_t queue_id) 746 { 747 uint32_t xcc_mask = mm->dev->xcc_mask; 748 int xcc_id, err, inst = 0; 749 void *xcc_mqd; 750 struct v9_mqd *m; 751 uint64_t mqd_offset; 752 753 m = get_mqd(mqd); 754 mqd_offset = m->cp_mqd_stride_size; 755 756 for_each_inst(xcc_id, xcc_mask) { 757 xcc_mqd = mqd + mqd_offset * inst; 758 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 759 type, timeout, pipe_id, 760 queue_id, xcc_id); 761 if (err) { 762 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 763 break; 764 } 765 ++inst; 766 } 767 768 return err; 769 } 770 771 static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 772 uint32_t pipe_id, uint32_t queue_id, 773 struct queue_properties *p, struct mm_struct *mms) 774 { 775 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 776 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 777 uint32_t xcc_mask = mm->dev->xcc_mask; 778 int xcc_id, err, inst = 0; 779 void *xcc_mqd; 780 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 781 782 for_each_inst(xcc_id, xcc_mask) { 783 xcc_mqd = mqd + mqd_stride_size * inst; 784 err = mm->dev->kfd2kgd->hqd_load( 785 mm->dev->adev, xcc_mqd, pipe_id, queue_id, 786 (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, 787 xcc_id); 788 if (err) { 789 pr_debug("Load MQD failed for xcc: %d\n", inst); 790 break; 791 } 792 ++inst; 793 } 794 795 return err; 796 } 797 798 static int get_wave_state_v9_4_3(struct mqd_manager *mm, void *mqd, 799 struct queue_properties *q, 800 void __user *ctl_stack, 801 u32 *ctl_stack_used_size, 802 u32 *save_area_used_size) 803 { 804 int xcc, err = 0; 805 void *xcc_mqd; 806 void __user *xcc_ctl_stack; 807 uint64_t mqd_stride_size = mm->mqd_stride(mm, q); 808 u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; 809 810 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 811 xcc_mqd = mqd + mqd_stride_size * xcc; 812 xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + 813 q->ctx_save_restore_area_size * xcc); 814 815 err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, 816 &tmp_ctl_stack_used_size, 817 &tmp_save_area_used_size); 818 if (err) 819 break; 820 821 /* 822 * Set the ctl_stack_used_size and save_area_used_size to 823 * ctl_stack_used_size and save_area_used_size of XCC 0 when 824 * passing the info the user-space. 825 * For multi XCC, user-space would have to look at the header 826 * info of each Control stack area to determine the control 827 * stack size and save area used. 828 */ 829 if (xcc == 0) { 830 *ctl_stack_used_size = tmp_ctl_stack_used_size; 831 *save_area_used_size = tmp_save_area_used_size; 832 } 833 } 834 835 return err; 836 } 837 838 #if defined(CONFIG_DEBUG_FS) 839 840 static int debugfs_show_mqd(struct seq_file *m, void *data) 841 { 842 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 843 data, sizeof(struct v9_mqd), false); 844 return 0; 845 } 846 847 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 848 { 849 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 850 data, sizeof(struct v9_sdma_mqd), false); 851 return 0; 852 } 853 854 #endif 855 856 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 857 struct kfd_node *dev) 858 { 859 struct mqd_manager *mqd; 860 861 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 862 return NULL; 863 864 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 865 if (!mqd) 866 return NULL; 867 868 mqd->dev = dev; 869 870 switch (type) { 871 case KFD_MQD_TYPE_CP: 872 mqd->allocate_mqd = allocate_mqd; 873 mqd->free_mqd = kfd_free_mqd_cp; 874 mqd->is_occupied = kfd_is_occupied_cp; 875 mqd->get_checkpoint_info = get_checkpoint_info; 876 mqd->checkpoint_mqd = checkpoint_mqd; 877 mqd->restore_mqd = restore_mqd; 878 mqd->mqd_size = sizeof(struct v9_mqd); 879 mqd->mqd_stride = mqd_stride_v9; 880 #if defined(CONFIG_DEBUG_FS) 881 mqd->debugfs_show_mqd = debugfs_show_mqd; 882 #endif 883 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 884 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) { 885 mqd->init_mqd = init_mqd_v9_4_3; 886 mqd->load_mqd = load_mqd_v9_4_3; 887 mqd->update_mqd = update_mqd_v9_4_3; 888 mqd->destroy_mqd = destroy_mqd_v9_4_3; 889 mqd->get_wave_state = get_wave_state_v9_4_3; 890 } else { 891 mqd->init_mqd = init_mqd; 892 mqd->load_mqd = load_mqd; 893 mqd->update_mqd = update_mqd; 894 mqd->destroy_mqd = kfd_destroy_mqd_cp; 895 mqd->get_wave_state = get_wave_state; 896 } 897 break; 898 case KFD_MQD_TYPE_HIQ: 899 mqd->allocate_mqd = allocate_hiq_mqd; 900 mqd->free_mqd = free_mqd_hiq_sdma; 901 mqd->update_mqd = update_mqd; 902 mqd->is_occupied = kfd_is_occupied_cp; 903 mqd->mqd_size = sizeof(struct v9_mqd); 904 mqd->mqd_stride = kfd_mqd_stride; 905 #if defined(CONFIG_DEBUG_FS) 906 mqd->debugfs_show_mqd = debugfs_show_mqd; 907 #endif 908 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 909 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) { 910 mqd->init_mqd = init_mqd_hiq_v9_4_3; 911 mqd->load_mqd = hiq_load_mqd_kiq_v9_4_3; 912 mqd->destroy_mqd = destroy_hiq_mqd_v9_4_3; 913 mqd->check_preemption_failed = check_preemption_failed_v9_4_3; 914 } else { 915 mqd->init_mqd = init_mqd_hiq; 916 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 917 mqd->destroy_mqd = destroy_hiq_mqd; 918 mqd->check_preemption_failed = check_preemption_failed; 919 } 920 break; 921 case KFD_MQD_TYPE_DIQ: 922 mqd->allocate_mqd = allocate_mqd; 923 mqd->init_mqd = init_mqd_hiq; 924 mqd->free_mqd = kfd_free_mqd_cp; 925 mqd->load_mqd = load_mqd; 926 mqd->update_mqd = update_mqd; 927 mqd->destroy_mqd = kfd_destroy_mqd_cp; 928 mqd->is_occupied = kfd_is_occupied_cp; 929 mqd->mqd_size = sizeof(struct v9_mqd); 930 #if defined(CONFIG_DEBUG_FS) 931 mqd->debugfs_show_mqd = debugfs_show_mqd; 932 #endif 933 break; 934 case KFD_MQD_TYPE_SDMA: 935 mqd->allocate_mqd = allocate_sdma_mqd; 936 mqd->init_mqd = init_mqd_sdma; 937 mqd->free_mqd = free_mqd_hiq_sdma; 938 mqd->load_mqd = kfd_load_mqd_sdma; 939 mqd->update_mqd = update_mqd_sdma; 940 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 941 mqd->is_occupied = kfd_is_occupied_sdma; 942 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 943 mqd->restore_mqd = restore_mqd_sdma; 944 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 945 mqd->mqd_stride = kfd_mqd_stride; 946 #if defined(CONFIG_DEBUG_FS) 947 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 948 #endif 949 break; 950 default: 951 kfree(mqd); 952 return NULL; 953 } 954 955 return mqd; 956 } 957