xref: /linux/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c (revision 08b7174fb8d126e607e385e34b9e1da4f3be274f)
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3  * Copyright 2016-2022 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  */
24 
25 #include <linux/printk.h>
26 #include <linux/slab.h>
27 #include <linux/uaccess.h>
28 #include "kfd_priv.h"
29 #include "kfd_mqd_manager.h"
30 #include "v9_structs.h"
31 #include "gc/gc_9_0_offset.h"
32 #include "gc/gc_9_0_sh_mask.h"
33 #include "sdma0/sdma0_4_0_sh_mask.h"
34 #include "amdgpu_amdkfd.h"
35 #include "kfd_device_queue_manager.h"
36 
37 static void update_mqd(struct mqd_manager *mm, void *mqd,
38 		       struct queue_properties *q,
39 		       struct mqd_update_info *minfo);
40 
41 static uint64_t mqd_stride_v9(struct mqd_manager *mm,
42 				struct queue_properties *q)
43 {
44 	if (mm->dev->kfd->cwsr_enabled &&
45 	    q->type == KFD_QUEUE_TYPE_COMPUTE)
46 		return ALIGN(q->ctl_stack_size, PAGE_SIZE) +
47 			ALIGN(sizeof(struct v9_mqd), PAGE_SIZE);
48 
49 	return mm->mqd_size;
50 }
51 
52 static inline struct v9_mqd *get_mqd(void *mqd)
53 {
54 	return (struct v9_mqd *)mqd;
55 }
56 
57 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
58 {
59 	return (struct v9_sdma_mqd *)mqd;
60 }
61 
62 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
63 			struct mqd_update_info *minfo)
64 {
65 	struct v9_mqd *m;
66 	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
67 
68 	if (!minfo || !minfo->cu_mask.ptr)
69 		return;
70 
71 	mqd_symmetrically_map_cu_mask(mm,
72 		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
73 
74 	m = get_mqd(mqd);
75 	m->compute_static_thread_mgmt_se0 = se_mask[0];
76 	m->compute_static_thread_mgmt_se1 = se_mask[1];
77 	m->compute_static_thread_mgmt_se2 = se_mask[2];
78 	m->compute_static_thread_mgmt_se3 = se_mask[3];
79 	m->compute_static_thread_mgmt_se4 = se_mask[4];
80 	m->compute_static_thread_mgmt_se5 = se_mask[5];
81 	m->compute_static_thread_mgmt_se6 = se_mask[6];
82 	m->compute_static_thread_mgmt_se7 = se_mask[7];
83 
84 	pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
85 		m->compute_static_thread_mgmt_se0,
86 		m->compute_static_thread_mgmt_se1,
87 		m->compute_static_thread_mgmt_se2,
88 		m->compute_static_thread_mgmt_se3,
89 		m->compute_static_thread_mgmt_se4,
90 		m->compute_static_thread_mgmt_se5,
91 		m->compute_static_thread_mgmt_se6,
92 		m->compute_static_thread_mgmt_se7);
93 }
94 
95 static void set_priority(struct v9_mqd *m, struct queue_properties *q)
96 {
97 	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
98 	m->cp_hqd_queue_priority = q->priority;
99 }
100 
101 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node,
102 		struct queue_properties *q)
103 {
104 	int retval;
105 	struct kfd_mem_obj *mqd_mem_obj = NULL;
106 
107 	/* For V9 only, due to a HW bug, the control stack of a user mode
108 	 * compute queue needs to be allocated just behind the page boundary
109 	 * of its regular MQD buffer. So we allocate an enlarged MQD buffer:
110 	 * the first page of the buffer serves as the regular MQD buffer
111 	 * purpose and the remaining is for control stack. Although the two
112 	 * parts are in the same buffer object, they need different memory
113 	 * types: MQD part needs UC (uncached) as usual, while control stack
114 	 * needs NC (non coherent), which is different from the UC type which
115 	 * is used when control stack is allocated in user space.
116 	 *
117 	 * Because of all those, we use the gtt allocation function instead
118 	 * of sub-allocation function for this enlarged MQD buffer. Moreover,
119 	 * in order to achieve two memory types in a single buffer object, we
120 	 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct
121 	 * amdgpu memory functions to do so.
122 	 */
123 	if (node->kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
124 		mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
125 		if (!mqd_mem_obj)
126 			return NULL;
127 		retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev,
128 			(ALIGN(q->ctl_stack_size, PAGE_SIZE) +
129 			ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) *
130 			NUM_XCC(node->xcc_mask),
131 			&(mqd_mem_obj->gtt_mem),
132 			&(mqd_mem_obj->gpu_addr),
133 			(void *)&(mqd_mem_obj->cpu_ptr), true);
134 
135 		if (retval) {
136 			kfree(mqd_mem_obj);
137 			return NULL;
138 		}
139 	} else {
140 		retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd),
141 				&mqd_mem_obj);
142 		if (retval)
143 			return NULL;
144 	}
145 
146 	return mqd_mem_obj;
147 }
148 
149 static void init_mqd(struct mqd_manager *mm, void **mqd,
150 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
151 			struct queue_properties *q)
152 {
153 	uint64_t addr;
154 	struct v9_mqd *m;
155 
156 	m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr;
157 	addr = mqd_mem_obj->gpu_addr;
158 
159 	memset(m, 0, sizeof(struct v9_mqd));
160 
161 	m->header = 0xC0310800;
162 	m->compute_pipelinestat_enable = 1;
163 	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
164 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
165 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
166 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
167 	m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
168 	m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
169 	m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
170 	m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
171 
172 	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
173 			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
174 
175 	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
176 
177 	m->cp_mqd_base_addr_lo        = lower_32_bits(addr);
178 	m->cp_mqd_base_addr_hi        = upper_32_bits(addr);
179 
180 	m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
181 			1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
182 			1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
183 
184 	/* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the
185 	 * DISPATCH_PTR.  This is required for the kfd debugger
186 	 */
187 	m->cp_hqd_hq_status0 = 1 << 14;
188 
189 	if (q->format == KFD_QUEUE_FORMAT_AQL)
190 		m->cp_hqd_aql_control =
191 			1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
192 
193 	if (q->tba_addr) {
194 		m->compute_pgm_rsrc2 |=
195 			(1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
196 	}
197 
198 	if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) {
199 		m->cp_hqd_persistent_state |=
200 			(1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
201 		m->cp_hqd_ctx_save_base_addr_lo =
202 			lower_32_bits(q->ctx_save_restore_area_address);
203 		m->cp_hqd_ctx_save_base_addr_hi =
204 			upper_32_bits(q->ctx_save_restore_area_address);
205 		m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
206 		m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
207 		m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
208 		m->cp_hqd_wg_state_offset = q->ctl_stack_size;
209 	}
210 
211 	*mqd = m;
212 	if (gart_addr)
213 		*gart_addr = addr;
214 	update_mqd(mm, m, q, NULL);
215 }
216 
217 static int load_mqd(struct mqd_manager *mm, void *mqd,
218 			uint32_t pipe_id, uint32_t queue_id,
219 			struct queue_properties *p, struct mm_struct *mms)
220 {
221 	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
222 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
223 
224 	return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
225 					  (uint32_t __user *)p->write_ptr,
226 					  wptr_shift, 0, mms, 0);
227 }
228 
229 static void update_mqd(struct mqd_manager *mm, void *mqd,
230 			struct queue_properties *q,
231 			struct mqd_update_info *minfo)
232 {
233 	struct v9_mqd *m;
234 
235 	m = get_mqd(mqd);
236 
237 	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
238 	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
239 	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
240 
241 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
242 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
243 
244 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
245 	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
246 	m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
247 	m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
248 
249 	m->cp_hqd_pq_doorbell_control =
250 		q->doorbell_off <<
251 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
252 	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
253 			m->cp_hqd_pq_doorbell_control);
254 
255 	m->cp_hqd_ib_control =
256 		3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
257 		1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT;
258 
259 	/*
260 	 * HW does not clamp this field correctly. Maximum EOP queue size
261 	 * is constrained by per-SE EOP done signal count, which is 8-bit.
262 	 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
263 	 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
264 	 * is safe, giving a maximum field value of 0xA.
265 	 *
266 	 * Also, do calculation only if EOP is used (size > 0), otherwise
267 	 * the order_base_2 calculation provides incorrect result.
268 	 *
269 	 */
270 	m->cp_hqd_eop_control = q->eop_ring_buffer_size ?
271 		min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0;
272 
273 	m->cp_hqd_eop_base_addr_lo =
274 			lower_32_bits(q->eop_ring_buffer_address >> 8);
275 	m->cp_hqd_eop_base_addr_hi =
276 			upper_32_bits(q->eop_ring_buffer_address >> 8);
277 
278 	m->cp_hqd_iq_timer = 0;
279 
280 	m->cp_hqd_vmid = q->vmid;
281 
282 	if (q->format == KFD_QUEUE_FORMAT_AQL) {
283 		m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
284 				2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
285 				1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT |
286 				1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT;
287 		m->cp_hqd_pq_doorbell_control |= 1 <<
288 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
289 	}
290 	if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address)
291 		m->cp_hqd_ctx_save_control = 0;
292 
293 	update_cu_mask(mm, mqd, minfo);
294 	set_priority(m, q);
295 
296 	q->is_active = QUEUE_IS_ACTIVE(*q);
297 }
298 
299 
300 static uint32_t read_doorbell_id(void *mqd)
301 {
302 	struct v9_mqd *m = (struct v9_mqd *)mqd;
303 
304 	return m->queue_doorbell_id0;
305 }
306 
307 static int get_wave_state(struct mqd_manager *mm, void *mqd,
308 			  struct queue_properties *q,
309 			  void __user *ctl_stack,
310 			  u32 *ctl_stack_used_size,
311 			  u32 *save_area_used_size)
312 {
313 	struct v9_mqd *m;
314 	struct kfd_context_save_area_header header;
315 
316 	/* Control stack is located one page after MQD. */
317 	void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
318 
319 	m = get_mqd(mqd);
320 
321 	*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
322 		m->cp_hqd_cntl_stack_offset;
323 	*save_area_used_size = m->cp_hqd_wg_state_offset -
324 		m->cp_hqd_cntl_stack_size;
325 
326 	header.wave_state.control_stack_size = *ctl_stack_used_size;
327 	header.wave_state.wave_state_size = *save_area_used_size;
328 
329 	header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset;
330 	header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset;
331 
332 	if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state)))
333 		return -EFAULT;
334 
335 	if (copy_to_user(ctl_stack + m->cp_hqd_cntl_stack_offset,
336 				mqd_ctl_stack + m->cp_hqd_cntl_stack_offset,
337 				*ctl_stack_used_size))
338 		return -EFAULT;
339 
340 	return 0;
341 }
342 
343 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size)
344 {
345 	struct v9_mqd *m = get_mqd(mqd);
346 
347 	*ctl_stack_size = m->cp_hqd_cntl_stack_size;
348 }
349 
350 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst)
351 {
352 	struct v9_mqd *m;
353 	/* Control stack is located one page after MQD. */
354 	void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE);
355 
356 	m = get_mqd(mqd);
357 
358 	memcpy(mqd_dst, m, sizeof(struct v9_mqd));
359 	memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size);
360 }
361 
362 static void restore_mqd(struct mqd_manager *mm, void **mqd,
363 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
364 			struct queue_properties *qp,
365 			const void *mqd_src,
366 			const void *ctl_stack_src, u32 ctl_stack_size)
367 {
368 	uint64_t addr;
369 	struct v9_mqd *m;
370 	void *ctl_stack;
371 
372 	m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr;
373 	addr = mqd_mem_obj->gpu_addr;
374 
375 	memcpy(m, mqd_src, sizeof(*m));
376 
377 	*mqd = m;
378 	if (gart_addr)
379 		*gart_addr = addr;
380 
381 	/* Control stack is located one page after MQD. */
382 	ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE);
383 	memcpy(ctl_stack, ctl_stack_src, ctl_stack_size);
384 
385 	m->cp_hqd_pq_doorbell_control =
386 		qp->doorbell_off <<
387 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
388 	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
389 				m->cp_hqd_pq_doorbell_control);
390 
391 	qp->is_active = 0;
392 }
393 
394 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
395 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
396 			struct queue_properties *q)
397 {
398 	struct v9_mqd *m;
399 
400 	init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
401 
402 	m = get_mqd(*mqd);
403 
404 	m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
405 			1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
406 }
407 
408 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd,
409 			enum kfd_preempt_type type, unsigned int timeout,
410 			uint32_t pipe_id, uint32_t queue_id)
411 {
412 	int err;
413 	struct v9_mqd *m;
414 	u32 doorbell_off;
415 
416 	m = get_mqd(mqd);
417 
418 	doorbell_off = m->cp_hqd_pq_doorbell_control >>
419 			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
420 	err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0);
421 	if (err)
422 		pr_debug("Destroy HIQ MQD failed: %d\n", err);
423 
424 	return err;
425 }
426 
427 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
428 		struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
429 		struct queue_properties *q)
430 {
431 	struct v9_sdma_mqd *m;
432 
433 	m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr;
434 
435 	memset(m, 0, sizeof(struct v9_sdma_mqd));
436 
437 	*mqd = m;
438 	if (gart_addr)
439 		*gart_addr = mqd_mem_obj->gpu_addr;
440 
441 	mm->update_mqd(mm, m, q, NULL);
442 }
443 
444 #define SDMA_RLC_DUMMY_DEFAULT 0xf
445 
446 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
447 			struct queue_properties *q,
448 			struct mqd_update_info *minfo)
449 {
450 	struct v9_sdma_mqd *m;
451 
452 	m = get_sdma_mqd(mqd);
453 	m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
454 		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
455 		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
456 		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
457 		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
458 
459 	m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
460 	m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
461 	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
462 	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
463 	m->sdmax_rlcx_doorbell_offset =
464 		q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
465 
466 	m->sdma_engine_id = q->sdma_engine_id;
467 	m->sdma_queue_id = q->sdma_queue_id;
468 	m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
469 
470 	q->is_active = QUEUE_IS_ACTIVE(*q);
471 }
472 
473 static void checkpoint_mqd_sdma(struct mqd_manager *mm,
474 				void *mqd,
475 				void *mqd_dst,
476 				void *ctl_stack_dst)
477 {
478 	struct v9_sdma_mqd *m;
479 
480 	m = get_sdma_mqd(mqd);
481 
482 	memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd));
483 }
484 
485 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd,
486 			     struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
487 			     struct queue_properties *qp,
488 			     const void *mqd_src,
489 			     const void *ctl_stack_src, const u32 ctl_stack_size)
490 {
491 	uint64_t addr;
492 	struct v9_sdma_mqd *m;
493 
494 	m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr;
495 	addr = mqd_mem_obj->gpu_addr;
496 
497 	memcpy(m, mqd_src, sizeof(*m));
498 
499 	m->sdmax_rlcx_doorbell_offset =
500 		qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
501 
502 	*mqd = m;
503 	if (gart_addr)
504 		*gart_addr = addr;
505 
506 	qp->is_active = 0;
507 }
508 
509 static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd,
510 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
511 			struct queue_properties *q)
512 {
513 	struct v9_mqd *m;
514 	int xcc = 0;
515 	struct kfd_mem_obj xcc_mqd_mem_obj;
516 	uint64_t xcc_gart_addr = 0;
517 
518 	memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj));
519 
520 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {
521 		kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc);
522 
523 		init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q);
524 
525 		m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
526 					1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
527 					1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
528 		m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev);
529 		if (xcc == 0) {
530 			/* Set no_update_rptr = 0 in Master XCC */
531 			m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK;
532 
533 			/* Set the MQD pointer and gart address to XCC0 MQD */
534 			*mqd = m;
535 			*gart_addr = xcc_gart_addr;
536 		}
537 	}
538 }
539 
540 static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd,
541 			uint32_t pipe_id, uint32_t queue_id,
542 			struct queue_properties *p, struct mm_struct *mms)
543 {
544 	uint32_t xcc_mask = mm->dev->xcc_mask;
545 	int xcc_id, err, inst = 0;
546 	void *xcc_mqd;
547 	uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev);
548 
549 	for_each_inst(xcc_id, xcc_mask) {
550 		xcc_mqd = mqd + hiq_mqd_size * inst;
551 		err = mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, xcc_mqd,
552 						     pipe_id, queue_id,
553 						     p->doorbell_off, xcc_id);
554 		if (err) {
555 			pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst);
556 			break;
557 		}
558 		++inst;
559 	}
560 
561 	return err;
562 }
563 
564 static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
565 			enum kfd_preempt_type type, unsigned int timeout,
566 			uint32_t pipe_id, uint32_t queue_id)
567 {
568 	uint32_t xcc_mask = mm->dev->xcc_mask;
569 	int xcc_id, err, inst = 0;
570 	uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev);
571 	struct v9_mqd *m;
572 	u32 doorbell_off;
573 
574 	for_each_inst(xcc_id, xcc_mask) {
575 		m = get_mqd(mqd + hiq_mqd_size * inst);
576 
577 		doorbell_off = m->cp_hqd_pq_doorbell_control >>
578 				CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
579 
580 		err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id);
581 		if (err) {
582 			pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst);
583 			break;
584 		}
585 		++inst;
586 	}
587 
588 	return err;
589 }
590 
591 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj,
592 			       struct kfd_mem_obj *xcc_mqd_mem_obj,
593 			       uint64_t offset)
594 {
595 	xcc_mqd_mem_obj->gtt_mem = (offset == 0) ?
596 					mqd_mem_obj->gtt_mem : NULL;
597 	xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset;
598 	xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr
599 						+ offset);
600 }
601 
602 static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd,
603 			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
604 			struct queue_properties *q)
605 {
606 	struct v9_mqd *m;
607 	int xcc = 0;
608 	struct kfd_mem_obj xcc_mqd_mem_obj;
609 	uint64_t xcc_gart_addr = 0;
610 	uint64_t xcc_ctx_save_restore_area_address;
611 	uint64_t offset = mm->mqd_stride(mm, q);
612 	uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++;
613 
614 	memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj));
615 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {
616 		get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc);
617 
618 		init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q);
619 
620 		m->cp_mqd_stride_size = offset;
621 
622 		/*
623 		 * Update the CWSR address for each XCC if CWSR is enabled
624 		 * and CWSR area is allocated in thunk
625 		 */
626 		if (mm->dev->kfd->cwsr_enabled &&
627 		    q->ctx_save_restore_area_address) {
628 			xcc_ctx_save_restore_area_address =
629 				q->ctx_save_restore_area_address +
630 				(xcc * q->ctx_save_restore_area_size);
631 
632 			m->cp_hqd_ctx_save_base_addr_lo =
633 				lower_32_bits(xcc_ctx_save_restore_area_address);
634 			m->cp_hqd_ctx_save_base_addr_hi =
635 				upper_32_bits(xcc_ctx_save_restore_area_address);
636 		}
637 
638 		if (q->format == KFD_QUEUE_FORMAT_AQL) {
639 			m->compute_tg_chunk_size = 1;
640 			m->compute_current_logic_xcc_id =
641 					(local_xcc_start + xcc) %
642 					NUM_XCC(mm->dev->xcc_mask);
643 
644 			switch (xcc) {
645 			case 0:
646 				/* Master XCC */
647 				m->cp_hqd_pq_control &=
648 					~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK;
649 				break;
650 			default:
651 				break;
652 			}
653 		} else {
654 			/* PM4 Queue */
655 			m->compute_current_logic_xcc_id = 0;
656 			m->compute_tg_chunk_size = 0;
657 			m->pm4_target_xcc_in_xcp = q->pm4_target_xcc;
658 		}
659 
660 		if (xcc == 0) {
661 			/* Set the MQD pointer and gart address to XCC0 MQD */
662 			*mqd = m;
663 			*gart_addr = xcc_gart_addr;
664 		}
665 	}
666 }
667 
668 static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
669 		      struct queue_properties *q, struct mqd_update_info *minfo)
670 {
671 	struct v9_mqd *m;
672 	int xcc = 0;
673 	uint64_t size = mm->mqd_stride(mm, q);
674 
675 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {
676 		m = get_mqd(mqd + size * xcc);
677 		update_mqd(mm, m, q, minfo);
678 
679 		if (q->format == KFD_QUEUE_FORMAT_AQL) {
680 			switch (xcc) {
681 			case 0:
682 				/* Master XCC */
683 				m->cp_hqd_pq_control &=
684 					~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK;
685 				break;
686 			default:
687 				break;
688 			}
689 			m->compute_tg_chunk_size = 1;
690 		} else {
691 			/* PM4 Queue */
692 			m->compute_current_logic_xcc_id = 0;
693 			m->compute_tg_chunk_size = 0;
694 			m->pm4_target_xcc_in_xcp = q->pm4_target_xcc;
695 		}
696 	}
697 }
698 
699 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
700 		   enum kfd_preempt_type type, unsigned int timeout,
701 		   uint32_t pipe_id, uint32_t queue_id)
702 {
703 	uint32_t xcc_mask = mm->dev->xcc_mask;
704 	int xcc_id, err, inst = 0;
705 	void *xcc_mqd;
706 	struct v9_mqd *m;
707 	uint64_t mqd_offset;
708 
709 	m = get_mqd(mqd);
710 	mqd_offset = m->cp_mqd_stride_size;
711 
712 	for_each_inst(xcc_id, xcc_mask) {
713 		xcc_mqd = mqd + mqd_offset * inst;
714 		err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd,
715 						    type, timeout, pipe_id,
716 						    queue_id, xcc_id);
717 		if (err) {
718 			pr_debug("Destroy MQD failed for xcc: %d\n", inst);
719 			break;
720 		}
721 		++inst;
722 	}
723 
724 	return err;
725 }
726 
727 static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd,
728 			uint32_t pipe_id, uint32_t queue_id,
729 			struct queue_properties *p, struct mm_struct *mms)
730 {
731 	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
732 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
733 	uint32_t xcc_mask = mm->dev->xcc_mask;
734 	int xcc_id, err, inst = 0;
735 	void *xcc_mqd;
736 	uint64_t mqd_stride_size = mm->mqd_stride(mm, p);
737 
738 	for_each_inst(xcc_id, xcc_mask) {
739 		xcc_mqd = mqd + mqd_stride_size * inst;
740 		err = mm->dev->kfd2kgd->hqd_load(
741 			mm->dev->adev, xcc_mqd, pipe_id, queue_id,
742 			(uint32_t __user *)p->write_ptr, wptr_shift, 0, mms,
743 			xcc_id);
744 		if (err) {
745 			pr_debug("Load MQD failed for xcc: %d\n", inst);
746 			break;
747 		}
748 		++inst;
749 	}
750 
751 	return err;
752 }
753 
754 static int get_wave_state_v9_4_3(struct mqd_manager *mm, void *mqd,
755 				 struct queue_properties *q,
756 				 void __user *ctl_stack,
757 				 u32 *ctl_stack_used_size,
758 				 u32 *save_area_used_size)
759 {
760 	int xcc, err = 0;
761 	void *xcc_mqd;
762 	void __user *xcc_ctl_stack;
763 	uint64_t mqd_stride_size = mm->mqd_stride(mm, q);
764 	u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0;
765 
766 	for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) {
767 		xcc_mqd = mqd + mqd_stride_size * xcc;
768 		xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack +
769 					q->ctx_save_restore_area_size * xcc);
770 
771 		err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack,
772 				     &tmp_ctl_stack_used_size,
773 				     &tmp_save_area_used_size);
774 		if (err)
775 			break;
776 
777 		/*
778 		 * Set the ctl_stack_used_size and save_area_used_size to
779 		 * ctl_stack_used_size and save_area_used_size of XCC 0 when
780 		 * passing the info the user-space.
781 		 * For multi XCC, user-space would have to look at the header
782 		 * info of each Control stack area to determine the control
783 		 * stack size and save area used.
784 		 */
785 		if (xcc == 0) {
786 			*ctl_stack_used_size = tmp_ctl_stack_used_size;
787 			*save_area_used_size = tmp_save_area_used_size;
788 		}
789 	}
790 
791 	return err;
792 }
793 
794 #if defined(CONFIG_DEBUG_FS)
795 
796 static int debugfs_show_mqd(struct seq_file *m, void *data)
797 {
798 	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
799 		     data, sizeof(struct v9_mqd), false);
800 	return 0;
801 }
802 
803 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
804 {
805 	seq_hex_dump(m, "    ", DUMP_PREFIX_OFFSET, 32, 4,
806 		     data, sizeof(struct v9_sdma_mqd), false);
807 	return 0;
808 }
809 
810 #endif
811 
812 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
813 		struct kfd_node *dev)
814 {
815 	struct mqd_manager *mqd;
816 
817 	if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
818 		return NULL;
819 
820 	mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
821 	if (!mqd)
822 		return NULL;
823 
824 	mqd->dev = dev;
825 
826 	switch (type) {
827 	case KFD_MQD_TYPE_CP:
828 		mqd->allocate_mqd = allocate_mqd;
829 		mqd->free_mqd = kfd_free_mqd_cp;
830 		mqd->is_occupied = kfd_is_occupied_cp;
831 		mqd->get_checkpoint_info = get_checkpoint_info;
832 		mqd->checkpoint_mqd = checkpoint_mqd;
833 		mqd->restore_mqd = restore_mqd;
834 		mqd->mqd_size = sizeof(struct v9_mqd);
835 		mqd->mqd_stride = mqd_stride_v9;
836 #if defined(CONFIG_DEBUG_FS)
837 		mqd->debugfs_show_mqd = debugfs_show_mqd;
838 #endif
839 		if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) {
840 			mqd->init_mqd = init_mqd_v9_4_3;
841 			mqd->load_mqd = load_mqd_v9_4_3;
842 			mqd->update_mqd = update_mqd_v9_4_3;
843 			mqd->destroy_mqd = destroy_mqd_v9_4_3;
844 			mqd->get_wave_state = get_wave_state_v9_4_3;
845 		} else {
846 			mqd->init_mqd = init_mqd;
847 			mqd->load_mqd = load_mqd;
848 			mqd->update_mqd = update_mqd;
849 			mqd->destroy_mqd = kfd_destroy_mqd_cp;
850 			mqd->get_wave_state = get_wave_state;
851 		}
852 		break;
853 	case KFD_MQD_TYPE_HIQ:
854 		mqd->allocate_mqd = allocate_hiq_mqd;
855 		mqd->free_mqd = free_mqd_hiq_sdma;
856 		mqd->update_mqd = update_mqd;
857 		mqd->is_occupied = kfd_is_occupied_cp;
858 		mqd->mqd_size = sizeof(struct v9_mqd);
859 		mqd->mqd_stride = kfd_mqd_stride;
860 #if defined(CONFIG_DEBUG_FS)
861 		mqd->debugfs_show_mqd = debugfs_show_mqd;
862 #endif
863 		mqd->read_doorbell_id = read_doorbell_id;
864 		if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) {
865 			mqd->init_mqd = init_mqd_hiq_v9_4_3;
866 			mqd->load_mqd = hiq_load_mqd_kiq_v9_4_3;
867 			mqd->destroy_mqd = destroy_hiq_mqd_v9_4_3;
868 		} else {
869 			mqd->init_mqd = init_mqd_hiq;
870 			mqd->load_mqd = kfd_hiq_load_mqd_kiq;
871 			mqd->destroy_mqd = destroy_hiq_mqd;
872 		}
873 		break;
874 	case KFD_MQD_TYPE_DIQ:
875 		mqd->allocate_mqd = allocate_mqd;
876 		mqd->init_mqd = init_mqd_hiq;
877 		mqd->free_mqd = kfd_free_mqd_cp;
878 		mqd->load_mqd = load_mqd;
879 		mqd->update_mqd = update_mqd;
880 		mqd->destroy_mqd = kfd_destroy_mqd_cp;
881 		mqd->is_occupied = kfd_is_occupied_cp;
882 		mqd->mqd_size = sizeof(struct v9_mqd);
883 #if defined(CONFIG_DEBUG_FS)
884 		mqd->debugfs_show_mqd = debugfs_show_mqd;
885 #endif
886 		break;
887 	case KFD_MQD_TYPE_SDMA:
888 		mqd->allocate_mqd = allocate_sdma_mqd;
889 		mqd->init_mqd = init_mqd_sdma;
890 		mqd->free_mqd = free_mqd_hiq_sdma;
891 		mqd->load_mqd = kfd_load_mqd_sdma;
892 		mqd->update_mqd = update_mqd_sdma;
893 		mqd->destroy_mqd = kfd_destroy_mqd_sdma;
894 		mqd->is_occupied = kfd_is_occupied_sdma;
895 		mqd->checkpoint_mqd = checkpoint_mqd_sdma;
896 		mqd->restore_mqd = restore_mqd_sdma;
897 		mqd->mqd_size = sizeof(struct v9_sdma_mqd);
898 		mqd->mqd_stride = kfd_mqd_stride;
899 #if defined(CONFIG_DEBUG_FS)
900 		mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
901 #endif
902 		break;
903 	default:
904 		kfree(mqd);
905 		return NULL;
906 	}
907 
908 	return mqd;
909 }
910