1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v12_structs.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v12_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v12_compute_mqd *)mqd; 37 } 38 39 static inline struct v12_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v12_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v12_compute_mqd *m; 48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 49 50 if (!minfo || !minfo->cu_mask.ptr) 51 return; 52 53 mqd_symmetrically_map_cu_mask(mm, 54 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 55 56 m = get_mqd(mqd); 57 m->compute_static_thread_mgmt_se0 = se_mask[0]; 58 m->compute_static_thread_mgmt_se1 = se_mask[1]; 59 m->compute_static_thread_mgmt_se2 = se_mask[2]; 60 m->compute_static_thread_mgmt_se3 = se_mask[3]; 61 m->compute_static_thread_mgmt_se4 = se_mask[4]; 62 m->compute_static_thread_mgmt_se5 = se_mask[5]; 63 m->compute_static_thread_mgmt_se6 = se_mask[6]; 64 m->compute_static_thread_mgmt_se7 = se_mask[7]; 65 66 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 67 m->compute_static_thread_mgmt_se0, 68 m->compute_static_thread_mgmt_se1, 69 m->compute_static_thread_mgmt_se2, 70 m->compute_static_thread_mgmt_se3, 71 m->compute_static_thread_mgmt_se4, 72 m->compute_static_thread_mgmt_se5, 73 m->compute_static_thread_mgmt_se6, 74 m->compute_static_thread_mgmt_se7); 75 } 76 77 static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) 78 { 79 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 80 m->cp_hqd_queue_priority = q->priority; 81 } 82 83 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 84 struct queue_properties *q) 85 { 86 struct kfd_mem_obj *mqd_mem_obj; 87 88 /* 89 * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond 90 * struct MQD size. 91 */ 92 if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj)) 93 return NULL; 94 95 return mqd_mem_obj; 96 } 97 98 static void init_mqd(struct mqd_manager *mm, void **mqd, 99 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 100 struct queue_properties *q) 101 { 102 uint64_t addr; 103 struct v12_compute_mqd *m; 104 105 m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; 106 addr = mqd_mem_obj->gpu_addr; 107 108 memset(m, 0, PAGE_SIZE); 109 110 m->header = 0xC0310800; 111 m->compute_pipelinestat_enable = 1; 112 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 113 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 114 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 115 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 116 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 117 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 118 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 119 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 120 121 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 122 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 123 124 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 125 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 126 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 127 128 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 129 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 130 131 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 132 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 133 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 134 135 /* Set cp_hqd_hq_status0.c_queue_debug_en to 1 to have the CP set up the 136 * DISPATCH_PTR. This is required for the kfd debugger 137 */ 138 m->cp_hqd_hq_status0 = 1 << 14; 139 140 if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) 141 m->cp_hqd_hq_status0 |= 1 << 29; 142 143 if (q->format == KFD_QUEUE_FORMAT_AQL) { 144 m->cp_hqd_aql_control = 145 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 146 } 147 148 if (mm->dev->kfd->cwsr_enabled) { 149 m->cp_hqd_persistent_state |= 150 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 151 m->cp_hqd_ctx_save_base_addr_lo = 152 lower_32_bits(q->ctx_save_restore_area_address); 153 m->cp_hqd_ctx_save_base_addr_hi = 154 upper_32_bits(q->ctx_save_restore_area_address); 155 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 156 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 157 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 158 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 159 } 160 161 *mqd = m; 162 if (gart_addr) 163 *gart_addr = addr; 164 mm->update_mqd(mm, m, q, NULL); 165 } 166 167 static int load_mqd(struct mqd_manager *mm, void *mqd, 168 uint32_t pipe_id, uint32_t queue_id, 169 struct queue_properties *p, struct mm_struct *mms) 170 { 171 int r = 0; 172 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 173 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 174 175 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 176 (uint32_t __user *)p->write_ptr, 177 wptr_shift, 0, mms, 0); 178 return r; 179 } 180 181 static void update_mqd(struct mqd_manager *mm, void *mqd, 182 struct queue_properties *q, 183 struct mqd_update_info *minfo) 184 { 185 struct v12_compute_mqd *m; 186 187 m = get_mqd(mqd); 188 189 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 190 m->cp_hqd_pq_control |= 191 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 192 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 193 194 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 195 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 196 197 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 198 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 199 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 200 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 201 202 m->cp_hqd_pq_doorbell_control = 203 q->doorbell_off << 204 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 205 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 206 m->cp_hqd_pq_doorbell_control); 207 208 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 209 210 /* 211 * HW does not clamp this field correctly. Maximum EOP queue size 212 * is constrained by per-SE EOP done signal count, which is 8-bit. 213 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 214 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 215 * is safe, giving a maximum field value of 0xA. 216 */ 217 m->cp_hqd_eop_control = min(0xA, 218 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 219 m->cp_hqd_eop_base_addr_lo = 220 lower_32_bits(q->eop_ring_buffer_address >> 8); 221 m->cp_hqd_eop_base_addr_hi = 222 upper_32_bits(q->eop_ring_buffer_address >> 8); 223 224 m->cp_hqd_iq_timer = 0; 225 226 m->cp_hqd_vmid = q->vmid; 227 228 if (q->format == KFD_QUEUE_FORMAT_AQL) { 229 /* GC 10 removed WPP_CLAMP from PQ Control */ 230 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 231 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 232 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 233 m->cp_hqd_pq_doorbell_control |= 234 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 235 } 236 if (mm->dev->kfd->cwsr_enabled) 237 m->cp_hqd_ctx_save_control = 0; 238 239 update_cu_mask(mm, mqd, minfo); 240 set_priority(m, q); 241 242 q->is_active = QUEUE_IS_ACTIVE(*q); 243 } 244 245 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 246 { 247 struct v12_compute_mqd *m = (struct v12_compute_mqd *)mqd; 248 249 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 250 } 251 252 static int get_wave_state(struct mqd_manager *mm, void *mqd, 253 struct queue_properties *q, 254 void __user *ctl_stack, 255 u32 *ctl_stack_used_size, 256 u32 *save_area_used_size) 257 { 258 struct v12_compute_mqd *m; 259 struct mqd_user_context_save_area_header header; 260 261 m = get_mqd(mqd); 262 263 /* Control stack is written backwards, while workgroup context data 264 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 265 * Current position is at m->cp_hqd_cntl_stack_offset and 266 * m->cp_hqd_wg_state_offset, respectively. 267 */ 268 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 269 m->cp_hqd_cntl_stack_offset; 270 *save_area_used_size = m->cp_hqd_wg_state_offset - 271 m->cp_hqd_cntl_stack_size; 272 273 /* Control stack is not copied to user mode for GFXv12 because 274 * it's part of the context save area that is already 275 * accessible to user mode 276 */ 277 header.control_stack_size = *ctl_stack_used_size; 278 header.wave_state_size = *save_area_used_size; 279 280 header.wave_state_offset = m->cp_hqd_wg_state_offset; 281 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; 282 283 if (copy_to_user(ctl_stack, &header, sizeof(header))) 284 return -EFAULT; 285 286 return 0; 287 } 288 289 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 290 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 291 struct queue_properties *q) 292 { 293 struct v12_compute_mqd *m; 294 295 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 296 297 m = get_mqd(*mqd); 298 299 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 300 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 301 } 302 303 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 304 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 305 struct queue_properties *q) 306 { 307 struct v12_sdma_mqd *m; 308 309 m = (struct v12_sdma_mqd *) mqd_mem_obj->cpu_ptr; 310 311 memset(m, 0, sizeof(struct v12_sdma_mqd)); 312 313 *mqd = m; 314 if (gart_addr) 315 *gart_addr = mqd_mem_obj->gpu_addr; 316 317 mm->update_mqd(mm, m, q, NULL); 318 } 319 320 #define SDMA_RLC_DUMMY_DEFAULT 0xf 321 322 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 323 struct queue_properties *q, 324 struct mqd_update_info *minfo) 325 { 326 struct v12_sdma_mqd *m; 327 328 m = get_sdma_mqd(mqd); 329 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 330 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 331 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 332 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 333 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 334 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 335 336 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 337 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 338 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 339 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 340 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 341 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 342 m->sdmax_rlcx_doorbell_offset = 343 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 344 345 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum 346 << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) 347 & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; 348 349 m->sdma_engine_id = q->sdma_engine_id; 350 m->sdma_queue_id = q->sdma_queue_id; 351 352 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 353 354 q->is_active = QUEUE_IS_ACTIVE(*q); 355 } 356 357 #if defined(CONFIG_DEBUG_FS) 358 359 static int debugfs_show_mqd(struct seq_file *m, void *data) 360 { 361 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 362 data, sizeof(struct v12_compute_mqd), false); 363 return 0; 364 } 365 366 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 367 { 368 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 369 data, sizeof(struct v12_sdma_mqd), false); 370 return 0; 371 } 372 373 #endif 374 375 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 376 struct kfd_node *dev) 377 { 378 struct mqd_manager *mqd; 379 380 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 381 return NULL; 382 383 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 384 if (!mqd) 385 return NULL; 386 387 mqd->dev = dev; 388 389 switch (type) { 390 case KFD_MQD_TYPE_CP: 391 pr_debug("%s@%i\n", __func__, __LINE__); 392 mqd->allocate_mqd = allocate_mqd; 393 mqd->init_mqd = init_mqd; 394 mqd->free_mqd = kfd_free_mqd_cp; 395 mqd->load_mqd = load_mqd; 396 mqd->update_mqd = update_mqd; 397 mqd->destroy_mqd = kfd_destroy_mqd_cp; 398 mqd->is_occupied = kfd_is_occupied_cp; 399 mqd->mqd_size = sizeof(struct v12_compute_mqd); 400 mqd->get_wave_state = get_wave_state; 401 mqd->mqd_stride = kfd_mqd_stride; 402 #if defined(CONFIG_DEBUG_FS) 403 mqd->debugfs_show_mqd = debugfs_show_mqd; 404 #endif 405 pr_debug("%s@%i\n", __func__, __LINE__); 406 break; 407 case KFD_MQD_TYPE_HIQ: 408 pr_debug("%s@%i\n", __func__, __LINE__); 409 mqd->allocate_mqd = allocate_hiq_mqd; 410 mqd->init_mqd = init_mqd_hiq; 411 mqd->free_mqd = free_mqd_hiq_sdma; 412 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 413 mqd->update_mqd = update_mqd; 414 mqd->destroy_mqd = kfd_destroy_mqd_cp; 415 mqd->is_occupied = kfd_is_occupied_cp; 416 mqd->mqd_size = sizeof(struct v12_compute_mqd); 417 mqd->mqd_stride = kfd_mqd_stride; 418 #if defined(CONFIG_DEBUG_FS) 419 mqd->debugfs_show_mqd = debugfs_show_mqd; 420 #endif 421 mqd->check_preemption_failed = check_preemption_failed; 422 pr_debug("%s@%i\n", __func__, __LINE__); 423 break; 424 case KFD_MQD_TYPE_DIQ: 425 mqd->allocate_mqd = allocate_mqd; 426 mqd->init_mqd = init_mqd_hiq; 427 mqd->free_mqd = kfd_free_mqd_cp; 428 mqd->load_mqd = load_mqd; 429 mqd->update_mqd = update_mqd; 430 mqd->destroy_mqd = kfd_destroy_mqd_cp; 431 mqd->is_occupied = kfd_is_occupied_cp; 432 mqd->mqd_size = sizeof(struct v12_compute_mqd); 433 #if defined(CONFIG_DEBUG_FS) 434 mqd->debugfs_show_mqd = debugfs_show_mqd; 435 #endif 436 break; 437 case KFD_MQD_TYPE_SDMA: 438 pr_debug("%s@%i\n", __func__, __LINE__); 439 mqd->allocate_mqd = allocate_mqd; 440 mqd->init_mqd = init_mqd_sdma; 441 mqd->free_mqd = kfd_free_mqd_cp; 442 mqd->load_mqd = kfd_load_mqd_sdma; 443 mqd->update_mqd = update_mqd_sdma; 444 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 445 mqd->is_occupied = kfd_is_occupied_sdma; 446 mqd->mqd_size = sizeof(struct v12_sdma_mqd); 447 mqd->mqd_stride = kfd_mqd_stride; 448 #if defined(CONFIG_DEBUG_FS) 449 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 450 #endif 451 pr_debug("%s@%i\n", __func__, __LINE__); 452 break; 453 default: 454 kfree(mqd); 455 return NULL; 456 } 457 458 return mqd; 459 } 460