1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v12_structs.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v12_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v12_compute_mqd *)mqd; 37 } 38 39 static inline struct v12_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v12_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v12_compute_mqd *m; 48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 49 50 if (!minfo || !minfo->cu_mask.ptr) 51 return; 52 53 mqd_symmetrically_map_cu_mask(mm, 54 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 55 56 m = get_mqd(mqd); 57 m->compute_static_thread_mgmt_se0 = se_mask[0]; 58 m->compute_static_thread_mgmt_se1 = se_mask[1]; 59 m->compute_static_thread_mgmt_se2 = se_mask[2]; 60 m->compute_static_thread_mgmt_se3 = se_mask[3]; 61 m->compute_static_thread_mgmt_se4 = se_mask[4]; 62 m->compute_static_thread_mgmt_se5 = se_mask[5]; 63 m->compute_static_thread_mgmt_se6 = se_mask[6]; 64 m->compute_static_thread_mgmt_se7 = se_mask[7]; 65 66 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 67 m->compute_static_thread_mgmt_se0, 68 m->compute_static_thread_mgmt_se1, 69 m->compute_static_thread_mgmt_se2, 70 m->compute_static_thread_mgmt_se3, 71 m->compute_static_thread_mgmt_se4, 72 m->compute_static_thread_mgmt_se5, 73 m->compute_static_thread_mgmt_se6, 74 m->compute_static_thread_mgmt_se7); 75 } 76 77 static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) 78 { 79 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 80 } 81 82 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 83 struct queue_properties *q) 84 { 85 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 86 struct kfd_node *node = mm->dev; 87 struct kfd_mem_obj *mqd_mem_obj; 88 89 if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 90 return NULL; 91 92 return mqd_mem_obj; 93 } 94 95 static void init_mqd(struct mqd_manager *mm, void **mqd, 96 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 97 struct queue_properties *q) 98 { 99 uint64_t addr; 100 struct v12_compute_mqd *m; 101 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 102 103 m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; 104 addr = mqd_mem_obj->gpu_addr; 105 106 memset(m, 0, mqd_size); 107 108 m->header = 0xC0310800; 109 m->compute_pipelinestat_enable = 1; 110 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 111 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 112 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 113 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 114 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 115 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 116 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 117 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 118 119 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 120 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 121 122 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 123 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 124 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 125 126 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 127 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 128 129 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 130 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 131 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 132 133 /* Set cp_hqd_hq_status0.c_queue_debug_en to 1 to have the CP set up the 134 * DISPATCH_PTR. This is required for the kfd debugger 135 */ 136 m->cp_hqd_hq_status0 = 1 << 14; 137 138 if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) 139 m->cp_hqd_hq_status0 |= 1 << 29; 140 141 if (q->format == KFD_QUEUE_FORMAT_AQL) { 142 m->cp_hqd_aql_control = 143 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 144 } 145 146 if (mm->dev->kfd->cwsr_enabled) { 147 m->cp_hqd_persistent_state |= 148 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 149 m->cp_hqd_ctx_save_base_addr_lo = 150 lower_32_bits(q->ctx_save_restore_area_address); 151 m->cp_hqd_ctx_save_base_addr_hi = 152 upper_32_bits(q->ctx_save_restore_area_address); 153 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 154 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 155 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 156 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 157 } 158 159 *mqd = m; 160 if (gart_addr) 161 *gart_addr = addr; 162 mm->update_mqd(mm, m, q, NULL); 163 } 164 165 static int load_mqd(struct mqd_manager *mm, void *mqd, 166 uint32_t pipe_id, uint32_t queue_id, 167 struct queue_properties *p, struct mm_struct *mms) 168 { 169 int r = 0; 170 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 171 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 172 173 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 174 (uint32_t __user *)p->write_ptr, 175 wptr_shift, 0, mms, 0); 176 return r; 177 } 178 179 static void update_mqd(struct mqd_manager *mm, void *mqd, 180 struct queue_properties *q, 181 struct mqd_update_info *minfo) 182 { 183 struct v12_compute_mqd *m; 184 185 m = get_mqd(mqd); 186 187 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 188 m->cp_hqd_pq_control |= 189 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 190 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 191 192 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 193 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 194 195 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 196 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 197 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 198 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 199 200 m->cp_hqd_pq_doorbell_control = 201 q->doorbell_off << 202 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 203 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 204 m->cp_hqd_pq_doorbell_control); 205 206 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 207 208 /* 209 * HW does not clamp this field correctly. Maximum EOP queue size 210 * is constrained by per-SE EOP done signal count, which is 8-bit. 211 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 212 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 213 * is safe, giving a maximum field value of 0xA. 214 */ 215 m->cp_hqd_eop_control = min(0xA, 216 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 217 m->cp_hqd_eop_base_addr_lo = 218 lower_32_bits(q->eop_ring_buffer_address >> 8); 219 m->cp_hqd_eop_base_addr_hi = 220 upper_32_bits(q->eop_ring_buffer_address >> 8); 221 222 m->cp_hqd_iq_timer = 0; 223 224 m->cp_hqd_vmid = q->vmid; 225 226 if (q->format == KFD_QUEUE_FORMAT_AQL) { 227 /* GC 10 removed WPP_CLAMP from PQ Control */ 228 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 229 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 230 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 231 m->cp_hqd_pq_doorbell_control |= 232 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 233 } 234 if (mm->dev->kfd->cwsr_enabled) 235 m->cp_hqd_ctx_save_control = 0; 236 237 update_cu_mask(mm, mqd, minfo); 238 set_priority(m, q); 239 240 q->is_active = QUEUE_IS_ACTIVE(*q); 241 } 242 243 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 244 { 245 struct v12_compute_mqd *m = (struct v12_compute_mqd *)mqd; 246 247 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 248 } 249 250 static int get_wave_state(struct mqd_manager *mm, void *mqd, 251 struct queue_properties *q, 252 void __user *ctl_stack, 253 u32 *ctl_stack_used_size, 254 u32 *save_area_used_size) 255 { 256 struct v12_compute_mqd *m; 257 struct mqd_user_context_save_area_header header; 258 259 m = get_mqd(mqd); 260 261 /* Control stack is written backwards, while workgroup context data 262 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 263 * Current position is at m->cp_hqd_cntl_stack_offset and 264 * m->cp_hqd_wg_state_offset, respectively. 265 */ 266 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 267 m->cp_hqd_cntl_stack_offset; 268 *save_area_used_size = m->cp_hqd_wg_state_offset - 269 m->cp_hqd_cntl_stack_size; 270 271 /* Control stack is not copied to user mode for GFXv12 because 272 * it's part of the context save area that is already 273 * accessible to user mode 274 */ 275 header.control_stack_size = *ctl_stack_used_size; 276 header.wave_state_size = *save_area_used_size; 277 278 header.wave_state_offset = m->cp_hqd_wg_state_offset; 279 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; 280 281 if (copy_to_user(ctl_stack, &header, sizeof(header))) 282 return -EFAULT; 283 284 return 0; 285 } 286 287 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 288 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 289 struct queue_properties *q) 290 { 291 struct v12_compute_mqd *m; 292 293 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 294 295 m = get_mqd(*mqd); 296 297 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 298 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 299 } 300 301 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 302 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 303 struct queue_properties *q) 304 { 305 struct v12_sdma_mqd *m; 306 307 m = (struct v12_sdma_mqd *) mqd_mem_obj->cpu_ptr; 308 309 memset(m, 0, sizeof(struct v12_sdma_mqd)); 310 311 *mqd = m; 312 if (gart_addr) 313 *gart_addr = mqd_mem_obj->gpu_addr; 314 315 mm->update_mqd(mm, m, q, NULL); 316 } 317 318 #define SDMA_RLC_DUMMY_DEFAULT 0xf 319 320 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 321 struct queue_properties *q, 322 struct mqd_update_info *minfo) 323 { 324 struct v12_sdma_mqd *m; 325 326 m = get_sdma_mqd(mqd); 327 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 328 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 329 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 330 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 331 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 332 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 333 334 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 335 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 336 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 337 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 338 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 339 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 340 m->sdmax_rlcx_doorbell_offset = 341 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 342 343 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum 344 << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) 345 & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; 346 347 m->sdma_engine_id = q->sdma_engine_id; 348 m->sdma_queue_id = q->sdma_queue_id; 349 350 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 351 352 /* Allow context switch so we don't cross-process starve with a massive 353 * command buffer of long-running SDMA commands 354 * sdmax_rlcx_ib_cntl represent SDMA_QUEUE0_IB_CNTL register 355 */ 356 m->sdmax_rlcx_ib_cntl |= SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK; 357 358 q->is_active = QUEUE_IS_ACTIVE(*q); 359 } 360 361 #if defined(CONFIG_DEBUG_FS) 362 363 static int debugfs_show_mqd(struct seq_file *m, void *data) 364 { 365 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 366 data, sizeof(struct v12_compute_mqd), false); 367 return 0; 368 } 369 370 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 371 { 372 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 373 data, sizeof(struct v12_sdma_mqd), false); 374 return 0; 375 } 376 377 #endif 378 379 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 380 struct kfd_node *dev) 381 { 382 struct mqd_manager *mqd; 383 384 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 385 return NULL; 386 387 mqd = kzalloc_obj(*mqd); 388 if (!mqd) 389 return NULL; 390 391 mqd->dev = dev; 392 393 switch (type) { 394 case KFD_MQD_TYPE_CP: 395 pr_debug("%s@%i\n", __func__, __LINE__); 396 mqd->allocate_mqd = allocate_mqd; 397 mqd->init_mqd = init_mqd; 398 mqd->free_mqd = kfd_free_mqd_cp; 399 mqd->load_mqd = load_mqd; 400 mqd->update_mqd = update_mqd; 401 mqd->destroy_mqd = kfd_destroy_mqd_cp; 402 mqd->is_occupied = kfd_is_occupied_cp; 403 mqd->mqd_size = sizeof(struct v12_compute_mqd); 404 mqd->get_wave_state = get_wave_state; 405 mqd->mqd_stride = kfd_mqd_stride; 406 #if defined(CONFIG_DEBUG_FS) 407 mqd->debugfs_show_mqd = debugfs_show_mqd; 408 #endif 409 pr_debug("%s@%i\n", __func__, __LINE__); 410 break; 411 case KFD_MQD_TYPE_HIQ: 412 pr_debug("%s@%i\n", __func__, __LINE__); 413 mqd->allocate_mqd = allocate_hiq_mqd; 414 mqd->init_mqd = init_mqd_hiq; 415 mqd->free_mqd = free_mqd_hiq_sdma; 416 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 417 mqd->update_mqd = update_mqd; 418 mqd->destroy_mqd = kfd_destroy_mqd_cp; 419 mqd->is_occupied = kfd_is_occupied_cp; 420 mqd->mqd_size = sizeof(struct v12_compute_mqd); 421 mqd->mqd_stride = kfd_mqd_stride; 422 #if defined(CONFIG_DEBUG_FS) 423 mqd->debugfs_show_mqd = debugfs_show_mqd; 424 #endif 425 mqd->check_preemption_failed = check_preemption_failed; 426 pr_debug("%s@%i\n", __func__, __LINE__); 427 break; 428 case KFD_MQD_TYPE_DIQ: 429 mqd->allocate_mqd = allocate_mqd; 430 mqd->init_mqd = init_mqd_hiq; 431 mqd->free_mqd = kfd_free_mqd_cp; 432 mqd->load_mqd = load_mqd; 433 mqd->update_mqd = update_mqd; 434 mqd->destroy_mqd = kfd_destroy_mqd_cp; 435 mqd->is_occupied = kfd_is_occupied_cp; 436 mqd->mqd_size = sizeof(struct v12_compute_mqd); 437 #if defined(CONFIG_DEBUG_FS) 438 mqd->debugfs_show_mqd = debugfs_show_mqd; 439 #endif 440 break; 441 case KFD_MQD_TYPE_SDMA: 442 pr_debug("%s@%i\n", __func__, __LINE__); 443 mqd->allocate_mqd = allocate_mqd; 444 mqd->init_mqd = init_mqd_sdma; 445 mqd->free_mqd = kfd_free_mqd_cp; 446 mqd->load_mqd = kfd_load_mqd_sdma; 447 mqd->update_mqd = update_mqd_sdma; 448 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 449 mqd->is_occupied = kfd_is_occupied_sdma; 450 mqd->mqd_size = sizeof(struct v12_sdma_mqd); 451 mqd->mqd_stride = kfd_mqd_stride; 452 #if defined(CONFIG_DEBUG_FS) 453 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 454 #endif 455 pr_debug("%s@%i\n", __func__, __LINE__); 456 break; 457 default: 458 kfree(mqd); 459 return NULL; 460 } 461 462 return mqd; 463 } 464