1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v12_structs.h" 31 #include "gc/gc_12_0_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v12_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v12_compute_mqd *)mqd; 37 } 38 39 static inline struct v12_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v12_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v12_compute_mqd *m; 48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 49 50 if (!minfo || !minfo->cu_mask.ptr) 51 return; 52 53 mqd_symmetrically_map_cu_mask(mm, 54 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 55 56 m = get_mqd(mqd); 57 m->compute_static_thread_mgmt_se0 = se_mask[0]; 58 m->compute_static_thread_mgmt_se1 = se_mask[1]; 59 m->compute_static_thread_mgmt_se2 = se_mask[2]; 60 m->compute_static_thread_mgmt_se3 = se_mask[3]; 61 m->compute_static_thread_mgmt_se4 = se_mask[4]; 62 m->compute_static_thread_mgmt_se5 = se_mask[5]; 63 m->compute_static_thread_mgmt_se6 = se_mask[6]; 64 m->compute_static_thread_mgmt_se7 = se_mask[7]; 65 66 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 67 m->compute_static_thread_mgmt_se0, 68 m->compute_static_thread_mgmt_se1, 69 m->compute_static_thread_mgmt_se2, 70 m->compute_static_thread_mgmt_se3, 71 m->compute_static_thread_mgmt_se4, 72 m->compute_static_thread_mgmt_se5, 73 m->compute_static_thread_mgmt_se6, 74 m->compute_static_thread_mgmt_se7); 75 } 76 77 static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) 78 { 79 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 80 } 81 82 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 83 struct queue_properties *q) 84 { 85 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 86 struct kfd_node *node = mm->dev; 87 struct kfd_mem_obj *mqd_mem_obj; 88 89 if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 90 return NULL; 91 92 return mqd_mem_obj; 93 } 94 95 static void init_mqd(struct mqd_manager *mm, void **mqd, 96 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 97 struct queue_properties *q) 98 { 99 uint64_t addr; 100 struct v12_compute_mqd *m; 101 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 102 103 m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; 104 addr = mqd_mem_obj->gpu_addr; 105 106 memset(m, 0, mqd_size); 107 108 m->header = 0xC0310800; 109 m->compute_pipelinestat_enable = 1; 110 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 111 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 112 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 113 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 114 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 115 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 116 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 117 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 118 119 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 120 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 121 122 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 123 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 124 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 125 126 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 127 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 128 129 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 130 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 131 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 132 133 /* Set cp_hqd_hq_status0.c_queue_debug_en to 1 to have the CP set up the 134 * DISPATCH_PTR. This is required for the kfd debugger 135 */ 136 m->cp_hqd_hq_status0 = 1 << 14; 137 138 if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) 139 m->cp_hqd_hq_status0 |= 1 << 29; 140 141 if (q->format == KFD_QUEUE_FORMAT_AQL) 142 m->cp_hqd_aql_control = 143 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 144 145 if (mm->dev->kfd->cwsr_enabled) { 146 m->cp_hqd_persistent_state |= 147 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 148 m->cp_hqd_ctx_save_base_addr_lo = 149 lower_32_bits(q->ctx_save_restore_area_address); 150 m->cp_hqd_ctx_save_base_addr_hi = 151 upper_32_bits(q->ctx_save_restore_area_address); 152 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 153 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 154 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 155 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 156 } 157 158 mutex_lock(&mm->dev->kfd->profiler_lock); 159 if (mm->dev->kfd->profiler_process != NULL) 160 m->compute_perfcount_enable = 1; 161 mutex_unlock(&mm->dev->kfd->profiler_lock); 162 163 *mqd = m; 164 if (gart_addr) 165 *gart_addr = addr; 166 mm->update_mqd(mm, m, q, NULL); 167 } 168 169 static int load_mqd(struct mqd_manager *mm, void *mqd, 170 uint32_t pipe_id, uint32_t queue_id, 171 struct queue_properties *p, struct mm_struct *mms) 172 { 173 int r = 0; 174 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 175 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 176 177 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 178 (uint32_t __user *)p->write_ptr, 179 wptr_shift, 0, mms, 0); 180 return r; 181 } 182 183 static void update_mqd(struct mqd_manager *mm, void *mqd, 184 struct queue_properties *q, 185 struct mqd_update_info *minfo) 186 { 187 struct v12_compute_mqd *m; 188 189 m = get_mqd(mqd); 190 191 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 192 m->cp_hqd_pq_control |= 193 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 194 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 195 196 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 197 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 198 199 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 200 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 201 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 202 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 203 204 m->cp_hqd_pq_doorbell_control = 205 q->doorbell_off << 206 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 207 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 208 m->cp_hqd_pq_doorbell_control); 209 210 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 211 212 /* 213 * HW does not clamp this field correctly. Maximum EOP queue size 214 * is constrained by per-SE EOP done signal count, which is 8-bit. 215 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 216 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 217 * is safe, giving a maximum field value of 0xA. 218 */ 219 m->cp_hqd_eop_control = q->eop_ring_buffer_size ? min(0xA, 220 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1) : 0; 221 m->cp_hqd_eop_base_addr_lo = 222 lower_32_bits(q->eop_ring_buffer_address >> 8); 223 m->cp_hqd_eop_base_addr_hi = 224 upper_32_bits(q->eop_ring_buffer_address >> 8); 225 226 m->cp_hqd_iq_timer = 0; 227 228 m->cp_hqd_vmid = q->vmid; 229 230 if (q->format == KFD_QUEUE_FORMAT_AQL) { 231 /* GC 10 removed WPP_CLAMP from PQ Control */ 232 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 233 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 234 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 235 m->cp_hqd_pq_doorbell_control |= 236 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 237 } 238 if (mm->dev->kfd->cwsr_enabled) 239 m->cp_hqd_ctx_save_control = 0; 240 241 update_cu_mask(mm, mqd, minfo); 242 set_priority(m, q); 243 244 q->is_active = QUEUE_IS_ACTIVE(*q); 245 } 246 247 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 248 { 249 struct v12_compute_mqd *m = (struct v12_compute_mqd *)mqd; 250 251 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 252 } 253 254 static int get_wave_state(struct mqd_manager *mm, void *mqd, 255 struct queue_properties *q, 256 void __user *ctl_stack, 257 u32 *ctl_stack_used_size, 258 u32 *save_area_used_size) 259 { 260 struct v12_compute_mqd *m; 261 struct mqd_user_context_save_area_header header; 262 263 m = get_mqd(mqd); 264 265 /* Control stack is written backwards, while workgroup context data 266 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 267 * Current position is at m->cp_hqd_cntl_stack_offset and 268 * m->cp_hqd_wg_state_offset, respectively. 269 */ 270 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 271 m->cp_hqd_cntl_stack_offset; 272 *save_area_used_size = m->cp_hqd_wg_state_offset - 273 m->cp_hqd_cntl_stack_size; 274 275 /* Control stack is not copied to user mode for GFXv12 because 276 * it's part of the context save area that is already 277 * accessible to user mode 278 */ 279 header.control_stack_size = *ctl_stack_used_size; 280 header.wave_state_size = *save_area_used_size; 281 282 header.wave_state_offset = m->cp_hqd_wg_state_offset; 283 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; 284 285 if (copy_to_user(ctl_stack, &header, sizeof(header))) 286 return -EFAULT; 287 288 return 0; 289 } 290 291 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 292 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 293 struct queue_properties *q) 294 { 295 struct v12_compute_mqd *m; 296 297 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 298 299 m = get_mqd(*mqd); 300 301 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 302 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 303 } 304 305 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 306 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 307 struct queue_properties *q) 308 { 309 struct v12_sdma_mqd *m; 310 311 m = (struct v12_sdma_mqd *) mqd_mem_obj->cpu_ptr; 312 313 memset(m, 0, sizeof(struct v12_sdma_mqd)); 314 315 *mqd = m; 316 if (gart_addr) 317 *gart_addr = mqd_mem_obj->gpu_addr; 318 319 mm->update_mqd(mm, m, q, NULL); 320 } 321 322 #define SDMA_RLC_DUMMY_DEFAULT 0xf 323 324 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 325 struct queue_properties *q, 326 struct mqd_update_info *minfo) 327 { 328 struct v12_sdma_mqd *m; 329 330 m = get_sdma_mqd(mqd); 331 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 332 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 333 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 334 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 335 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 336 1 << SDMA0_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; 337 338 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 339 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 340 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 341 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 342 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 343 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 344 m->sdmax_rlcx_doorbell_offset = 345 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 346 347 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum 348 << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) 349 & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; 350 351 m->sdma_engine_id = q->sdma_engine_id; 352 m->sdma_queue_id = q->sdma_queue_id; 353 354 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 355 356 /* Allow context switch so we don't cross-process starve with a massive 357 * command buffer of long-running SDMA commands 358 * sdmax_rlcx_ib_cntl represent SDMA_QUEUE0_IB_CNTL register 359 */ 360 m->sdmax_rlcx_ib_cntl |= SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK; 361 362 q->is_active = QUEUE_IS_ACTIVE(*q); 363 } 364 365 #if defined(CONFIG_DEBUG_FS) 366 367 static int debugfs_show_mqd(struct seq_file *m, void *data) 368 { 369 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 370 data, sizeof(struct v12_compute_mqd), false); 371 return 0; 372 } 373 374 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 375 { 376 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 377 data, sizeof(struct v12_sdma_mqd), false); 378 return 0; 379 } 380 381 #endif 382 383 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, 384 struct kfd_node *dev) 385 { 386 struct mqd_manager *mqd; 387 388 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 389 return NULL; 390 391 mqd = kzalloc_obj(*mqd); 392 if (!mqd) 393 return NULL; 394 395 mqd->dev = dev; 396 397 switch (type) { 398 case KFD_MQD_TYPE_CP: 399 pr_debug("%s@%i\n", __func__, __LINE__); 400 mqd->allocate_mqd = allocate_mqd; 401 mqd->init_mqd = init_mqd; 402 mqd->free_mqd = kfd_free_mqd_cp; 403 mqd->load_mqd = load_mqd; 404 mqd->update_mqd = update_mqd; 405 mqd->destroy_mqd = kfd_destroy_mqd_cp; 406 mqd->is_occupied = kfd_is_occupied_cp; 407 mqd->mqd_size = sizeof(struct v12_compute_mqd); 408 mqd->get_wave_state = get_wave_state; 409 mqd->mqd_stride = kfd_mqd_stride; 410 #if defined(CONFIG_DEBUG_FS) 411 mqd->debugfs_show_mqd = debugfs_show_mqd; 412 #endif 413 pr_debug("%s@%i\n", __func__, __LINE__); 414 break; 415 case KFD_MQD_TYPE_HIQ: 416 pr_debug("%s@%i\n", __func__, __LINE__); 417 mqd->allocate_mqd = allocate_hiq_mqd; 418 mqd->init_mqd = init_mqd_hiq; 419 mqd->free_mqd = free_mqd_hiq_sdma; 420 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 421 mqd->update_mqd = update_mqd; 422 mqd->destroy_mqd = kfd_destroy_mqd_cp; 423 mqd->is_occupied = kfd_is_occupied_cp; 424 mqd->mqd_size = sizeof(struct v12_compute_mqd); 425 mqd->mqd_stride = kfd_mqd_stride; 426 #if defined(CONFIG_DEBUG_FS) 427 mqd->debugfs_show_mqd = debugfs_show_mqd; 428 #endif 429 mqd->check_preemption_failed = check_preemption_failed; 430 pr_debug("%s@%i\n", __func__, __LINE__); 431 break; 432 case KFD_MQD_TYPE_DIQ: 433 mqd->allocate_mqd = allocate_mqd; 434 mqd->init_mqd = init_mqd_hiq; 435 mqd->free_mqd = kfd_free_mqd_cp; 436 mqd->load_mqd = load_mqd; 437 mqd->update_mqd = update_mqd; 438 mqd->destroy_mqd = kfd_destroy_mqd_cp; 439 mqd->is_occupied = kfd_is_occupied_cp; 440 mqd->mqd_size = sizeof(struct v12_compute_mqd); 441 #if defined(CONFIG_DEBUG_FS) 442 mqd->debugfs_show_mqd = debugfs_show_mqd; 443 #endif 444 break; 445 case KFD_MQD_TYPE_SDMA: 446 pr_debug("%s@%i\n", __func__, __LINE__); 447 mqd->allocate_mqd = allocate_mqd; 448 mqd->init_mqd = init_mqd_sdma; 449 mqd->free_mqd = kfd_free_mqd_cp; 450 mqd->load_mqd = kfd_load_mqd_sdma; 451 mqd->update_mqd = update_mqd_sdma; 452 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 453 mqd->is_occupied = kfd_is_occupied_sdma; 454 mqd->mqd_size = sizeof(struct v12_sdma_mqd); 455 mqd->mqd_stride = kfd_mqd_stride; 456 #if defined(CONFIG_DEBUG_FS) 457 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 458 #endif 459 pr_debug("%s@%i\n", __func__, __LINE__); 460 break; 461 default: 462 kfree(mqd); 463 return NULL; 464 } 465 466 return mqd; 467 } 468