1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v11_structs.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v11_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v11_compute_mqd *)mqd; 37 } 38 39 static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v11_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v11_compute_mqd *m; 48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 49 50 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) || 51 !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 m->compute_static_thread_mgmt_se4 = se_mask[4]; 63 m->compute_static_thread_mgmt_se5 = se_mask[5]; 64 m->compute_static_thread_mgmt_se6 = se_mask[6]; 65 m->compute_static_thread_mgmt_se7 = se_mask[7]; 66 67 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 68 m->compute_static_thread_mgmt_se0, 69 m->compute_static_thread_mgmt_se1, 70 m->compute_static_thread_mgmt_se2, 71 m->compute_static_thread_mgmt_se3, 72 m->compute_static_thread_mgmt_se4, 73 m->compute_static_thread_mgmt_se5, 74 m->compute_static_thread_mgmt_se6, 75 m->compute_static_thread_mgmt_se7); 76 } 77 78 static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) 79 { 80 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 81 m->cp_hqd_queue_priority = q->priority; 82 } 83 84 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 85 struct queue_properties *q) 86 { 87 struct kfd_mem_obj *mqd_mem_obj; 88 int size; 89 90 /* 91 * MES write to areas beyond MQD size. So allocate 92 * 1 PAGE_SIZE memory for MQD is MES is enabled. 93 */ 94 if (kfd->shared_resources.enable_mes) 95 size = PAGE_SIZE; 96 else 97 size = sizeof(struct v11_compute_mqd); 98 99 if (kfd_gtt_sa_allocate(kfd, size, &mqd_mem_obj)) 100 return NULL; 101 102 return mqd_mem_obj; 103 } 104 105 static void init_mqd(struct mqd_manager *mm, void **mqd, 106 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 107 struct queue_properties *q) 108 { 109 uint64_t addr; 110 struct v11_compute_mqd *m; 111 int size; 112 113 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; 114 addr = mqd_mem_obj->gpu_addr; 115 116 if (mm->dev->shared_resources.enable_mes) 117 size = PAGE_SIZE; 118 else 119 size = sizeof(struct v11_compute_mqd); 120 121 memset(m, 0, size); 122 123 m->header = 0xC0310800; 124 m->compute_pipelinestat_enable = 1; 125 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 126 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 127 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 128 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 129 130 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 131 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 132 133 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 134 135 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 136 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 137 138 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 139 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 140 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 141 142 if (q->format == KFD_QUEUE_FORMAT_AQL) { 143 m->cp_hqd_aql_control = 144 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 145 } 146 147 if (mm->dev->cwsr_enabled) { 148 m->cp_hqd_persistent_state |= 149 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 150 m->cp_hqd_ctx_save_base_addr_lo = 151 lower_32_bits(q->ctx_save_restore_area_address); 152 m->cp_hqd_ctx_save_base_addr_hi = 153 upper_32_bits(q->ctx_save_restore_area_address); 154 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 155 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 156 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 157 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 158 } 159 160 *mqd = m; 161 if (gart_addr) 162 *gart_addr = addr; 163 mm->update_mqd(mm, m, q, NULL); 164 } 165 166 static int load_mqd(struct mqd_manager *mm, void *mqd, 167 uint32_t pipe_id, uint32_t queue_id, 168 struct queue_properties *p, struct mm_struct *mms) 169 { 170 int r = 0; 171 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 172 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 173 174 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 175 (uint32_t __user *)p->write_ptr, 176 wptr_shift, 0, mms); 177 return r; 178 } 179 180 static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, 181 uint32_t pipe_id, uint32_t queue_id, 182 struct queue_properties *p, struct mm_struct *mms) 183 { 184 return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id, 185 queue_id, p->doorbell_off); 186 } 187 188 static void update_mqd(struct mqd_manager *mm, void *mqd, 189 struct queue_properties *q, 190 struct mqd_update_info *minfo) 191 { 192 struct v11_compute_mqd *m; 193 194 m = get_mqd(mqd); 195 196 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 197 m->cp_hqd_pq_control |= 198 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 199 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 200 201 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 202 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 203 204 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 205 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 206 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 207 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 208 209 m->cp_hqd_pq_doorbell_control = 210 q->doorbell_off << 211 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 212 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 213 m->cp_hqd_pq_doorbell_control); 214 215 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 216 217 /* 218 * HW does not clamp this field correctly. Maximum EOP queue size 219 * is constrained by per-SE EOP done signal count, which is 8-bit. 220 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 221 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 222 * is safe, giving a maximum field value of 0xA. 223 */ 224 m->cp_hqd_eop_control = min(0xA, 225 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 226 m->cp_hqd_eop_base_addr_lo = 227 lower_32_bits(q->eop_ring_buffer_address >> 8); 228 m->cp_hqd_eop_base_addr_hi = 229 upper_32_bits(q->eop_ring_buffer_address >> 8); 230 231 m->cp_hqd_iq_timer = 0; 232 233 m->cp_hqd_vmid = q->vmid; 234 235 if (q->format == KFD_QUEUE_FORMAT_AQL) { 236 /* GC 10 removed WPP_CLAMP from PQ Control */ 237 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 238 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 239 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 240 m->cp_hqd_pq_doorbell_control |= 241 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 242 } 243 if (mm->dev->cwsr_enabled) 244 m->cp_hqd_ctx_save_control = 0; 245 246 update_cu_mask(mm, mqd, minfo); 247 set_priority(m, q); 248 249 q->is_active = QUEUE_IS_ACTIVE(*q); 250 } 251 252 static uint32_t read_doorbell_id(void *mqd) 253 { 254 struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd; 255 256 return m->queue_doorbell_id0; 257 } 258 259 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 260 enum kfd_preempt_type type, 261 unsigned int timeout, uint32_t pipe_id, 262 uint32_t queue_id) 263 { 264 return mm->dev->kfd2kgd->hqd_destroy 265 (mm->dev->adev, mqd, type, timeout, 266 pipe_id, queue_id); 267 } 268 269 static void free_mqd(struct mqd_manager *mm, void *mqd, 270 struct kfd_mem_obj *mqd_mem_obj) 271 { 272 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 273 } 274 275 static bool is_occupied(struct mqd_manager *mm, void *mqd, 276 uint64_t queue_address, uint32_t pipe_id, 277 uint32_t queue_id) 278 { 279 return mm->dev->kfd2kgd->hqd_is_occupied( 280 mm->dev->adev, queue_address, 281 pipe_id, queue_id); 282 } 283 284 static int get_wave_state(struct mqd_manager *mm, void *mqd, 285 void __user *ctl_stack, 286 u32 *ctl_stack_used_size, 287 u32 *save_area_used_size) 288 { 289 struct v11_compute_mqd *m; 290 /*struct mqd_user_context_save_area_header header;*/ 291 292 m = get_mqd(mqd); 293 294 /* Control stack is written backwards, while workgroup context data 295 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 296 * Current position is at m->cp_hqd_cntl_stack_offset and 297 * m->cp_hqd_wg_state_offset, respectively. 298 */ 299 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 300 m->cp_hqd_cntl_stack_offset; 301 *save_area_used_size = m->cp_hqd_wg_state_offset - 302 m->cp_hqd_cntl_stack_size; 303 304 /* Control stack is not copied to user mode for GFXv11 because 305 * it's part of the context save area that is already 306 * accessible to user mode 307 */ 308 /* 309 header.control_stack_size = *ctl_stack_used_size; 310 header.wave_state_size = *save_area_used_size; 311 312 header.wave_state_offset = m->cp_hqd_wg_state_offset; 313 header.control_stack_offset = m->cp_hqd_cntl_stack_offset; 314 315 if (copy_to_user(ctl_stack, &header, sizeof(header))) 316 return -EFAULT; 317 */ 318 return 0; 319 } 320 321 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 322 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 323 struct queue_properties *q) 324 { 325 struct v11_compute_mqd *m; 326 327 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 328 329 m = get_mqd(*mqd); 330 331 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 332 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 333 } 334 335 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 336 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 337 struct queue_properties *q) 338 { 339 struct v11_sdma_mqd *m; 340 341 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr; 342 343 memset(m, 0, sizeof(struct v11_sdma_mqd)); 344 345 *mqd = m; 346 if (gart_addr) 347 *gart_addr = mqd_mem_obj->gpu_addr; 348 349 mm->update_mqd(mm, m, q, NULL); 350 } 351 352 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 353 uint32_t pipe_id, uint32_t queue_id, 354 struct queue_properties *p, struct mm_struct *mms) 355 { 356 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd, 357 (uint32_t __user *)p->write_ptr, 358 mms); 359 } 360 361 #define SDMA_RLC_DUMMY_DEFAULT 0xf 362 363 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 364 struct queue_properties *q, 365 struct mqd_update_info *minfo) 366 { 367 struct v11_sdma_mqd *m; 368 369 m = get_sdma_mqd(mqd); 370 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 371 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 372 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 373 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 374 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 375 376 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 377 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 378 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 379 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 380 m->sdmax_rlcx_doorbell_offset = 381 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 382 383 m->sdma_engine_id = q->sdma_engine_id; 384 m->sdma_queue_id = q->sdma_queue_id; 385 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 386 387 q->is_active = QUEUE_IS_ACTIVE(*q); 388 } 389 390 /* 391 * * preempt type here is ignored because there is only one way 392 * * to preempt sdma queue 393 */ 394 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 395 enum kfd_preempt_type type, 396 unsigned int timeout, uint32_t pipe_id, 397 uint32_t queue_id) 398 { 399 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout); 400 } 401 402 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 403 uint64_t queue_address, uint32_t pipe_id, 404 uint32_t queue_id) 405 { 406 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd); 407 } 408 409 #if defined(CONFIG_DEBUG_FS) 410 411 static int debugfs_show_mqd(struct seq_file *m, void *data) 412 { 413 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 414 data, sizeof(struct v11_compute_mqd), false); 415 return 0; 416 } 417 418 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 419 { 420 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 421 data, sizeof(struct v11_sdma_mqd), false); 422 return 0; 423 } 424 425 #endif 426 427 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 428 struct kfd_dev *dev) 429 { 430 struct mqd_manager *mqd; 431 432 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 433 return NULL; 434 435 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 436 if (!mqd) 437 return NULL; 438 439 mqd->dev = dev; 440 441 switch (type) { 442 case KFD_MQD_TYPE_CP: 443 pr_debug("%s@%i\n", __func__, __LINE__); 444 mqd->allocate_mqd = allocate_mqd; 445 mqd->init_mqd = init_mqd; 446 mqd->free_mqd = free_mqd; 447 mqd->load_mqd = load_mqd; 448 mqd->update_mqd = update_mqd; 449 mqd->destroy_mqd = destroy_mqd; 450 mqd->is_occupied = is_occupied; 451 mqd->mqd_size = sizeof(struct v11_compute_mqd); 452 mqd->get_wave_state = get_wave_state; 453 #if defined(CONFIG_DEBUG_FS) 454 mqd->debugfs_show_mqd = debugfs_show_mqd; 455 #endif 456 pr_debug("%s@%i\n", __func__, __LINE__); 457 break; 458 case KFD_MQD_TYPE_HIQ: 459 pr_debug("%s@%i\n", __func__, __LINE__); 460 mqd->allocate_mqd = allocate_hiq_mqd; 461 mqd->init_mqd = init_mqd_hiq; 462 mqd->free_mqd = free_mqd_hiq_sdma; 463 mqd->load_mqd = hiq_load_mqd_kiq; 464 mqd->update_mqd = update_mqd; 465 mqd->destroy_mqd = destroy_mqd; 466 mqd->is_occupied = is_occupied; 467 mqd->mqd_size = sizeof(struct v11_compute_mqd); 468 #if defined(CONFIG_DEBUG_FS) 469 mqd->debugfs_show_mqd = debugfs_show_mqd; 470 #endif 471 mqd->read_doorbell_id = read_doorbell_id; 472 pr_debug("%s@%i\n", __func__, __LINE__); 473 break; 474 case KFD_MQD_TYPE_DIQ: 475 mqd->allocate_mqd = allocate_mqd; 476 mqd->init_mqd = init_mqd_hiq; 477 mqd->free_mqd = free_mqd; 478 mqd->load_mqd = load_mqd; 479 mqd->update_mqd = update_mqd; 480 mqd->destroy_mqd = destroy_mqd; 481 mqd->is_occupied = is_occupied; 482 mqd->mqd_size = sizeof(struct v11_compute_mqd); 483 #if defined(CONFIG_DEBUG_FS) 484 mqd->debugfs_show_mqd = debugfs_show_mqd; 485 #endif 486 break; 487 case KFD_MQD_TYPE_SDMA: 488 pr_debug("%s@%i\n", __func__, __LINE__); 489 mqd->allocate_mqd = allocate_sdma_mqd; 490 mqd->init_mqd = init_mqd_sdma; 491 mqd->free_mqd = free_mqd_hiq_sdma; 492 mqd->load_mqd = load_mqd_sdma; 493 mqd->update_mqd = update_mqd_sdma; 494 mqd->destroy_mqd = destroy_mqd_sdma; 495 mqd->is_occupied = is_occupied_sdma; 496 mqd->mqd_size = sizeof(struct v11_sdma_mqd); 497 #if defined(CONFIG_DEBUG_FS) 498 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 499 #endif 500 pr_debug("%s@%i\n", __func__, __LINE__); 501 break; 502 default: 503 kfree(mqd); 504 return NULL; 505 } 506 507 return mqd; 508 } 509