1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/uaccess.h> 27 #include "kfd_priv.h" 28 #include "kfd_mqd_manager.h" 29 #include "v11_structs.h" 30 #include "gc/gc_11_0_0_offset.h" 31 #include "gc/gc_11_0_0_sh_mask.h" 32 #include "amdgpu_amdkfd.h" 33 34 static inline struct v11_compute_mqd *get_mqd(void *mqd) 35 { 36 return (struct v11_compute_mqd *)mqd; 37 } 38 39 static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd) 40 { 41 return (struct v11_sdma_mqd *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct mqd_update_info *minfo) 46 { 47 struct v11_compute_mqd *m; 48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 49 bool has_wa_flag = minfo && (minfo->update_flag & (UPDATE_FLAG_DBG_WA_ENABLE | 50 UPDATE_FLAG_DBG_WA_DISABLE)); 51 52 if (!minfo || !(has_wa_flag || minfo->cu_mask.ptr)) 53 return; 54 55 m = get_mqd(mqd); 56 57 if (has_wa_flag) { 58 uint32_t wa_mask = 59 (minfo->update_flag & UPDATE_FLAG_DBG_WA_ENABLE) ? 0xffff : 0xffffffff; 60 61 m->compute_static_thread_mgmt_se0 = wa_mask; 62 m->compute_static_thread_mgmt_se1 = wa_mask; 63 m->compute_static_thread_mgmt_se2 = wa_mask; 64 m->compute_static_thread_mgmt_se3 = wa_mask; 65 m->compute_static_thread_mgmt_se4 = wa_mask; 66 m->compute_static_thread_mgmt_se5 = wa_mask; 67 m->compute_static_thread_mgmt_se6 = wa_mask; 68 m->compute_static_thread_mgmt_se7 = wa_mask; 69 70 return; 71 } 72 73 mqd_symmetrically_map_cu_mask(mm, 74 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 75 76 m->compute_static_thread_mgmt_se0 = se_mask[0]; 77 m->compute_static_thread_mgmt_se1 = se_mask[1]; 78 m->compute_static_thread_mgmt_se2 = se_mask[2]; 79 m->compute_static_thread_mgmt_se3 = se_mask[3]; 80 m->compute_static_thread_mgmt_se4 = se_mask[4]; 81 m->compute_static_thread_mgmt_se5 = se_mask[5]; 82 m->compute_static_thread_mgmt_se6 = se_mask[6]; 83 m->compute_static_thread_mgmt_se7 = se_mask[7]; 84 85 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 86 m->compute_static_thread_mgmt_se0, 87 m->compute_static_thread_mgmt_se1, 88 m->compute_static_thread_mgmt_se2, 89 m->compute_static_thread_mgmt_se3, 90 m->compute_static_thread_mgmt_se4, 91 m->compute_static_thread_mgmt_se5, 92 m->compute_static_thread_mgmt_se6, 93 m->compute_static_thread_mgmt_se7); 94 } 95 96 static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) 97 { 98 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 99 } 100 101 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 102 struct queue_properties *q) 103 { 104 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 105 struct kfd_node *node = mm->dev; 106 struct kfd_mem_obj *mqd_mem_obj; 107 108 if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) 109 return NULL; 110 111 return mqd_mem_obj; 112 } 113 114 static void init_mqd(struct mqd_manager *mm, void **mqd, 115 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 116 struct queue_properties *q) 117 { 118 uint64_t addr; 119 struct v11_compute_mqd *m; 120 u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 121 uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff; 122 123 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; 124 addr = mqd_mem_obj->gpu_addr; 125 126 memset(m, 0, mqd_size); 127 128 m->header = 0xC0310800; 129 m->compute_pipelinestat_enable = 1; 130 131 m->compute_static_thread_mgmt_se0 = wa_mask; 132 m->compute_static_thread_mgmt_se1 = wa_mask; 133 m->compute_static_thread_mgmt_se2 = wa_mask; 134 m->compute_static_thread_mgmt_se3 = wa_mask; 135 m->compute_static_thread_mgmt_se4 = wa_mask; 136 m->compute_static_thread_mgmt_se5 = wa_mask; 137 m->compute_static_thread_mgmt_se6 = wa_mask; 138 m->compute_static_thread_mgmt_se7 = wa_mask; 139 140 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 141 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 142 143 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 144 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 145 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 146 147 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 148 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 149 150 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 151 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 152 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 153 154 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 155 * DISPATCH_PTR. This is required for the kfd debugger 156 */ 157 m->cp_hqd_hq_status0 = 1 << 14; 158 159 /* 160 * GFX11 RS64 CPFW version >= 509 supports PCIe atomics support 161 * acknowledgment. 162 */ 163 if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) 164 m->cp_hqd_hq_status0 |= 1 << 29; 165 166 if (q->format == KFD_QUEUE_FORMAT_AQL) 167 m->cp_hqd_aql_control = 168 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 169 170 if (mm->dev->kfd->cwsr_enabled) { 171 m->cp_hqd_persistent_state |= 172 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 173 m->cp_hqd_ctx_save_base_addr_lo = 174 lower_32_bits(q->ctx_save_restore_area_address); 175 m->cp_hqd_ctx_save_base_addr_hi = 176 upper_32_bits(q->ctx_save_restore_area_address); 177 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 178 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 179 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 180 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 181 } 182 183 mutex_lock(&mm->dev->kfd->profiler_lock); 184 if (mm->dev->kfd->profiler_process != NULL) 185 m->compute_perfcount_enable = 1; 186 mutex_unlock(&mm->dev->kfd->profiler_lock); 187 188 *mqd = m; 189 if (gart_addr) 190 *gart_addr = addr; 191 mm->update_mqd(mm, m, q, NULL); 192 } 193 194 static int load_mqd(struct mqd_manager *mm, void *mqd, 195 uint32_t pipe_id, uint32_t queue_id, 196 struct queue_properties *p, struct mm_struct *mms) 197 { 198 int r = 0; 199 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 200 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 201 202 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 203 (uint32_t __user *)p->write_ptr, 204 wptr_shift, 0, mms, 0); 205 return r; 206 } 207 208 static void update_mqd(struct mqd_manager *mm, void *mqd, 209 struct queue_properties *q, 210 struct mqd_update_info *minfo) 211 { 212 struct v11_compute_mqd *m; 213 214 m = get_mqd(mqd); 215 216 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 217 m->cp_hqd_pq_control |= 218 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 219 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 220 221 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 222 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 223 224 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 225 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 226 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 227 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 228 229 m->cp_hqd_pq_doorbell_control = 230 q->doorbell_off << 231 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 232 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 233 m->cp_hqd_pq_doorbell_control); 234 235 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 236 237 /* 238 * HW does not clamp this field correctly. Maximum EOP queue size 239 * is constrained by per-SE EOP done signal count, which is 8-bit. 240 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 241 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 242 * is safe, giving a maximum field value of 0xA. 243 */ 244 m->cp_hqd_eop_control = min(0xA, 245 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 246 m->cp_hqd_eop_base_addr_lo = 247 lower_32_bits(q->eop_ring_buffer_address >> 8); 248 m->cp_hqd_eop_base_addr_hi = 249 upper_32_bits(q->eop_ring_buffer_address >> 8); 250 251 m->cp_hqd_iq_timer = 0; 252 253 m->cp_hqd_vmid = q->vmid; 254 255 if (q->format == KFD_QUEUE_FORMAT_AQL) { 256 /* GC 10 removed WPP_CLAMP from PQ Control */ 257 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 258 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 259 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ; 260 m->cp_hqd_pq_doorbell_control |= 261 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 262 } 263 if (mm->dev->kfd->cwsr_enabled) 264 m->cp_hqd_ctx_save_control = 0; 265 if (minfo) { 266 if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) 267 m->compute_perfcount_enable = 1; 268 else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) 269 m->compute_perfcount_enable = 0; 270 } 271 272 update_cu_mask(mm, mqd, minfo); 273 set_priority(m, q); 274 275 q->is_active = QUEUE_IS_ACTIVE(*q); 276 } 277 278 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 279 { 280 struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd; 281 282 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 283 } 284 285 static int get_wave_state(struct mqd_manager *mm, void *mqd, 286 struct queue_properties *q, 287 void __user *ctl_stack, 288 u32 *ctl_stack_used_size, 289 u32 *save_area_used_size) 290 { 291 struct v11_compute_mqd *m; 292 struct kfd_context_save_area_header header; 293 294 m = get_mqd(mqd); 295 296 /* Control stack is written backwards, while workgroup context data 297 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 298 * Current position is at m->cp_hqd_cntl_stack_offset and 299 * m->cp_hqd_wg_state_offset, respectively. 300 */ 301 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 302 m->cp_hqd_cntl_stack_offset; 303 *save_area_used_size = m->cp_hqd_wg_state_offset - 304 m->cp_hqd_cntl_stack_size; 305 306 /* Control stack is not copied to user mode for GFXv11 because 307 * it's part of the context save area that is already 308 * accessible to user mode 309 */ 310 header.wave_state.control_stack_size = *ctl_stack_used_size; 311 header.wave_state.wave_state_size = *save_area_used_size; 312 313 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 314 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 315 316 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 317 return -EFAULT; 318 319 return 0; 320 } 321 322 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 323 { 324 struct v11_compute_mqd *m; 325 326 m = get_mqd(mqd); 327 328 memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd)); 329 } 330 331 static void restore_mqd(struct mqd_manager *mm, void **mqd, 332 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 333 struct queue_properties *qp, const void *mqd_src, 334 const void *ctl_stack_src, const u32 ctl_stack_size) 335 { 336 uint64_t addr; 337 struct v11_compute_mqd *m; 338 339 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; 340 addr = mqd_mem_obj->gpu_addr; 341 342 memcpy(m, mqd_src, sizeof(*m)); 343 344 *mqd = m; 345 if (gart_addr) 346 *gart_addr = addr; 347 348 m->cp_hqd_pq_doorbell_control = 349 qp->doorbell_off << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 350 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", m->cp_hqd_pq_doorbell_control); 351 352 qp->is_active = 0; 353 } 354 355 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 356 void *mqd, 357 void *mqd_dst, 358 void *ctl_stack_dst) 359 { 360 struct v11_sdma_mqd *m; 361 362 m = get_sdma_mqd(mqd); 363 364 memcpy(mqd_dst, m, sizeof(struct v11_sdma_mqd)); 365 } 366 367 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 368 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 369 struct queue_properties *qp, 370 const void *mqd_src, 371 const void *ctl_stack_src, 372 const u32 ctl_stack_size) 373 { 374 uint64_t addr; 375 struct v11_sdma_mqd *m; 376 377 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr; 378 addr = mqd_mem_obj->gpu_addr; 379 380 memcpy(m, mqd_src, sizeof(*m)); 381 382 m->sdmax_rlcx_doorbell_offset = 383 qp->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 384 385 *mqd = m; 386 if (gart_addr) 387 *gart_addr = addr; 388 389 qp->is_active = 0; 390 } 391 392 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 393 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 394 struct queue_properties *q) 395 { 396 struct v11_compute_mqd *m; 397 398 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 399 400 m = get_mqd(*mqd); 401 402 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 403 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 404 } 405 406 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 407 enum kfd_preempt_type type, unsigned int timeout, 408 uint32_t pipe_id, uint32_t queue_id) 409 { 410 int err; 411 struct v11_compute_mqd *m; 412 u32 doorbell_off; 413 414 m = get_mqd(mqd); 415 416 doorbell_off = m->cp_hqd_pq_doorbell_control >> 417 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 418 419 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 420 if (err) 421 pr_debug("Destroy HIQ MQD failed: %d\n", err); 422 423 return err; 424 } 425 426 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 427 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 428 struct queue_properties *q) 429 { 430 struct v11_sdma_mqd *m; 431 int size; 432 433 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr; 434 435 if (mm->dev->kfd->shared_resources.enable_mes) 436 size = PAGE_SIZE; 437 else 438 size = sizeof(struct v11_sdma_mqd); 439 440 memset(m, 0, size); 441 *mqd = m; 442 if (gart_addr) 443 *gart_addr = mqd_mem_obj->gpu_addr; 444 445 mm->update_mqd(mm, m, q, NULL); 446 } 447 448 #define SDMA_RLC_DUMMY_DEFAULT 0xf 449 450 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 451 struct queue_properties *q, 452 struct mqd_update_info *minfo) 453 { 454 struct v11_sdma_mqd *m; 455 456 m = get_sdma_mqd(mqd); 457 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 458 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 459 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 460 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 461 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 462 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 463 464 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 465 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 466 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 467 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 468 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 469 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 470 m->sdmax_rlcx_doorbell_offset = 471 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 472 473 m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum 474 << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) 475 & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; 476 477 m->sdma_engine_id = q->sdma_engine_id; 478 m->sdma_queue_id = q->sdma_queue_id; 479 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 480 481 q->is_active = QUEUE_IS_ACTIVE(*q); 482 } 483 484 #if defined(CONFIG_DEBUG_FS) 485 486 static int debugfs_show_mqd(struct seq_file *m, void *data) 487 { 488 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 489 data, sizeof(struct v11_compute_mqd), false); 490 return 0; 491 } 492 493 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 494 { 495 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 496 data, sizeof(struct v11_sdma_mqd), false); 497 return 0; 498 } 499 500 #endif 501 502 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, 503 struct kfd_node *dev) 504 { 505 struct mqd_manager *mqd; 506 507 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 508 return NULL; 509 510 mqd = kzalloc_obj(*mqd); 511 if (!mqd) 512 return NULL; 513 514 mqd->dev = dev; 515 516 switch (type) { 517 case KFD_MQD_TYPE_CP: 518 pr_debug("%s@%i\n", __func__, __LINE__); 519 mqd->allocate_mqd = allocate_mqd; 520 mqd->init_mqd = init_mqd; 521 mqd->free_mqd = kfd_free_mqd_cp; 522 mqd->load_mqd = load_mqd; 523 mqd->update_mqd = update_mqd; 524 mqd->destroy_mqd = kfd_destroy_mqd_cp; 525 mqd->is_occupied = kfd_is_occupied_cp; 526 mqd->mqd_size = sizeof(struct v11_compute_mqd); 527 mqd->get_wave_state = get_wave_state; 528 mqd->mqd_stride = kfd_mqd_stride; 529 mqd->checkpoint_mqd = checkpoint_mqd; 530 mqd->restore_mqd = restore_mqd; 531 #if defined(CONFIG_DEBUG_FS) 532 mqd->debugfs_show_mqd = debugfs_show_mqd; 533 #endif 534 pr_debug("%s@%i\n", __func__, __LINE__); 535 break; 536 case KFD_MQD_TYPE_HIQ: 537 pr_debug("%s@%i\n", __func__, __LINE__); 538 mqd->allocate_mqd = allocate_hiq_mqd; 539 mqd->init_mqd = init_mqd_hiq; 540 mqd->free_mqd = free_mqd_hiq_sdma; 541 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 542 mqd->update_mqd = update_mqd; 543 mqd->destroy_mqd = destroy_hiq_mqd; 544 mqd->is_occupied = kfd_is_occupied_cp; 545 mqd->mqd_size = sizeof(struct v11_compute_mqd); 546 mqd->mqd_stride = kfd_mqd_stride; 547 #if defined(CONFIG_DEBUG_FS) 548 mqd->debugfs_show_mqd = debugfs_show_mqd; 549 #endif 550 mqd->check_preemption_failed = check_preemption_failed; 551 pr_debug("%s@%i\n", __func__, __LINE__); 552 break; 553 case KFD_MQD_TYPE_DIQ: 554 mqd->allocate_mqd = allocate_mqd; 555 mqd->init_mqd = init_mqd_hiq; 556 mqd->free_mqd = kfd_free_mqd_cp; 557 mqd->load_mqd = load_mqd; 558 mqd->update_mqd = update_mqd; 559 mqd->destroy_mqd = kfd_destroy_mqd_cp; 560 mqd->is_occupied = kfd_is_occupied_cp; 561 mqd->mqd_size = sizeof(struct v11_compute_mqd); 562 #if defined(CONFIG_DEBUG_FS) 563 mqd->debugfs_show_mqd = debugfs_show_mqd; 564 #endif 565 break; 566 case KFD_MQD_TYPE_SDMA: 567 pr_debug("%s@%i\n", __func__, __LINE__); 568 mqd->allocate_mqd = allocate_sdma_mqd; 569 mqd->init_mqd = init_mqd_sdma; 570 mqd->free_mqd = free_mqd_hiq_sdma; 571 mqd->load_mqd = kfd_load_mqd_sdma; 572 mqd->update_mqd = update_mqd_sdma; 573 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 574 mqd->is_occupied = kfd_is_occupied_sdma; 575 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 576 mqd->restore_mqd = restore_mqd_sdma; 577 mqd->mqd_size = sizeof(struct v11_sdma_mqd); 578 mqd->mqd_stride = kfd_mqd_stride; 579 #if defined(CONFIG_DEBUG_FS) 580 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 581 #endif 582 /* 583 * To allocate SDMA MQDs by generic functions 584 * when MES is enabled. 585 */ 586 if (dev->kfd->shared_resources.enable_mes) { 587 mqd->allocate_mqd = allocate_mqd; 588 mqd->free_mqd = kfd_free_mqd_cp; 589 } 590 pr_debug("%s@%i\n", __func__, __LINE__); 591 break; 592 default: 593 kfree(mqd); 594 return NULL; 595 } 596 597 return mqd; 598 } 599