1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2018-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v10_structs.h" 31 #include "gc/gc_10_1_0_offset.h" 32 #include "gc/gc_10_1_0_sh_mask.h" 33 #include "amdgpu_amdkfd.h" 34 35 static inline struct v10_compute_mqd *get_mqd(void *mqd) 36 { 37 return (struct v10_compute_mqd *)mqd; 38 } 39 40 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 41 { 42 return (struct v10_sdma_mqd *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct v10_compute_mqd *m; 49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 50 51 if (!minfo || !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 63 pr_debug("update cu mask to %#x %#x %#x %#x\n", 64 m->compute_static_thread_mgmt_se0, 65 m->compute_static_thread_mgmt_se1, 66 m->compute_static_thread_mgmt_se2, 67 m->compute_static_thread_mgmt_se3); 68 } 69 70 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) 71 { 72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 73 } 74 75 static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, 76 struct queue_properties *q) 77 { 78 struct kfd_node *kfd = mm->dev; 79 struct kfd_mem_obj *mqd_mem_obj; 80 81 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 82 &mqd_mem_obj)) 83 return NULL; 84 85 return mqd_mem_obj; 86 } 87 88 static void init_mqd(struct mqd_manager *mm, void **mqd, 89 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 90 struct queue_properties *q) 91 { 92 uint64_t addr; 93 struct v10_compute_mqd *m; 94 95 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 96 addr = mqd_mem_obj->gpu_addr; 97 98 memset(m, 0, sizeof(struct v10_compute_mqd)); 99 100 m->header = 0xC0310800; 101 m->compute_pipelinestat_enable = 1; 102 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 103 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 106 107 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 108 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 109 110 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 111 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 112 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 113 114 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 115 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 116 117 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 118 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 119 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 120 121 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 122 * DISPATCH_PTR. This is required for the kfd debugger 123 */ 124 m->cp_hqd_hq_scheduler0 = 1 << 14; 125 126 if (q->format == KFD_QUEUE_FORMAT_AQL) 127 m->cp_hqd_aql_control = 128 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 129 130 if (mm->dev->kfd->cwsr_enabled) { 131 m->cp_hqd_persistent_state |= 132 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 133 m->cp_hqd_ctx_save_base_addr_lo = 134 lower_32_bits(q->ctx_save_restore_area_address); 135 m->cp_hqd_ctx_save_base_addr_hi = 136 upper_32_bits(q->ctx_save_restore_area_address); 137 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 138 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 139 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 140 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 141 } 142 143 mutex_lock(&mm->dev->kfd->profiler_lock); 144 if (mm->dev->kfd->profiler_process != NULL) 145 m->compute_perfcount_enable = 1; 146 147 mutex_unlock(&mm->dev->kfd->profiler_lock); 148 149 *mqd = m; 150 if (gart_addr) 151 *gart_addr = addr; 152 mm->update_mqd(mm, m, q, NULL); 153 } 154 155 static int load_mqd(struct mqd_manager *mm, void *mqd, 156 uint32_t pipe_id, uint32_t queue_id, 157 struct queue_properties *p, struct mm_struct *mms) 158 { 159 int r = 0; 160 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 161 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 162 163 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 164 (uint32_t __user *)p->write_ptr, 165 wptr_shift, 0, mms, 0); 166 return r; 167 } 168 169 static void update_mqd(struct mqd_manager *mm, void *mqd, 170 struct queue_properties *q, 171 struct mqd_update_info *minfo) 172 { 173 struct v10_compute_mqd *m; 174 175 m = get_mqd(mqd); 176 177 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 178 m->cp_hqd_pq_control |= 179 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 180 181 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 182 183 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 184 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 185 186 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 187 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 188 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 189 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 190 191 m->cp_hqd_pq_doorbell_control = 192 q->doorbell_off << 193 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 194 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 195 m->cp_hqd_pq_doorbell_control); 196 197 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 198 199 /* 200 * HW does not clamp this field correctly. Maximum EOP queue size 201 * is constrained by per-SE EOP done signal count, which is 8-bit. 202 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 203 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 204 * is safe, giving a maximum field value of 0xA. 205 */ 206 m->cp_hqd_eop_control = min(0xA, 207 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 208 m->cp_hqd_eop_base_addr_lo = 209 lower_32_bits(q->eop_ring_buffer_address >> 8); 210 m->cp_hqd_eop_base_addr_hi = 211 upper_32_bits(q->eop_ring_buffer_address >> 8); 212 213 m->cp_hqd_iq_timer = 0; 214 215 m->cp_hqd_vmid = q->vmid; 216 217 if (q->format == KFD_QUEUE_FORMAT_AQL) { 218 /* GC 10 removed WPP_CLAMP from PQ Control */ 219 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 220 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 221 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 222 m->cp_hqd_pq_doorbell_control |= 223 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 224 } 225 if (mm->dev->kfd->cwsr_enabled) 226 m->cp_hqd_ctx_save_control = 0; 227 228 if (minfo) { 229 if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) 230 m->compute_perfcount_enable = 1; 231 else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) 232 m->compute_perfcount_enable = 0; 233 } 234 235 update_cu_mask(mm, mqd, minfo); 236 set_priority(m, q); 237 238 q->is_active = QUEUE_IS_ACTIVE(*q); 239 } 240 241 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 242 { 243 struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; 244 245 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 246 } 247 248 static int get_wave_state(struct mqd_manager *mm, void *mqd, 249 struct queue_properties *q, 250 void __user *ctl_stack, 251 u32 *ctl_stack_used_size, 252 u32 *save_area_used_size) 253 { 254 struct v10_compute_mqd *m; 255 struct kfd_context_save_area_header header; 256 257 m = get_mqd(mqd); 258 259 /* Control stack is written backwards, while workgroup context data 260 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 261 * Current position is at m->cp_hqd_cntl_stack_offset and 262 * m->cp_hqd_wg_state_offset, respectively. 263 */ 264 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 265 m->cp_hqd_cntl_stack_offset; 266 *save_area_used_size = m->cp_hqd_wg_state_offset - 267 m->cp_hqd_cntl_stack_size; 268 269 /* Control stack is not copied to user mode for GFXv10 because 270 * it's part of the context save area that is already 271 * accessible to user mode 272 */ 273 274 header.wave_state.control_stack_size = *ctl_stack_used_size; 275 header.wave_state.wave_state_size = *save_area_used_size; 276 277 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 278 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 279 280 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 281 return -EFAULT; 282 283 return 0; 284 } 285 286 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 287 { 288 struct v10_compute_mqd *m; 289 290 m = get_mqd(mqd); 291 292 memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd)); 293 } 294 295 static void restore_mqd(struct mqd_manager *mm, void **mqd, 296 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 297 struct queue_properties *qp, 298 const void *mqd_src, 299 const void *ctl_stack_src, const u32 ctl_stack_size) 300 { 301 uint64_t addr; 302 struct v10_compute_mqd *m; 303 304 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 305 addr = mqd_mem_obj->gpu_addr; 306 307 memcpy(m, mqd_src, sizeof(*m)); 308 309 *mqd = m; 310 if (gart_addr) 311 *gart_addr = addr; 312 313 m->cp_hqd_pq_doorbell_control = 314 qp->doorbell_off << 315 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 316 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 317 m->cp_hqd_pq_doorbell_control); 318 319 qp->is_active = 0; 320 } 321 322 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 323 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 324 struct queue_properties *q) 325 { 326 struct v10_compute_mqd *m; 327 328 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 329 330 m = get_mqd(*mqd); 331 332 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 333 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 334 } 335 336 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 337 enum kfd_preempt_type type, unsigned int timeout, 338 uint32_t pipe_id, uint32_t queue_id) 339 { 340 int err; 341 struct v10_compute_mqd *m; 342 u32 doorbell_off; 343 344 m = get_mqd(mqd); 345 346 doorbell_off = m->cp_hqd_pq_doorbell_control >> 347 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 348 349 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 350 if (err) 351 pr_debug("Destroy HIQ MQD failed: %d\n", err); 352 353 return err; 354 } 355 356 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 357 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 358 struct queue_properties *q) 359 { 360 struct v10_sdma_mqd *m; 361 362 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 363 364 memset(m, 0, sizeof(struct v10_sdma_mqd)); 365 366 *mqd = m; 367 if (gart_addr) 368 *gart_addr = mqd_mem_obj->gpu_addr; 369 370 mm->update_mqd(mm, m, q, NULL); 371 } 372 373 #define SDMA_RLC_DUMMY_DEFAULT 0xf 374 375 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 376 struct queue_properties *q, 377 struct mqd_update_info *minfo) 378 { 379 struct v10_sdma_mqd *m; 380 381 m = get_sdma_mqd(mqd); 382 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 383 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 384 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 385 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 386 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 387 388 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 389 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 390 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 391 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 392 m->sdmax_rlcx_doorbell_offset = 393 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 394 395 m->sdma_engine_id = q->sdma_engine_id; 396 m->sdma_queue_id = q->sdma_queue_id; 397 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 398 399 q->is_active = QUEUE_IS_ACTIVE(*q); 400 } 401 402 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 403 void *mqd, 404 void *mqd_dst, 405 void *ctl_stack_dst) 406 { 407 struct v10_sdma_mqd *m; 408 409 m = get_sdma_mqd(mqd); 410 411 memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd)); 412 } 413 414 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 415 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 416 struct queue_properties *qp, 417 const void *mqd_src, 418 const void *ctl_stack_src, 419 const u32 ctl_stack_size) 420 { 421 uint64_t addr; 422 struct v10_sdma_mqd *m; 423 424 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 425 addr = mqd_mem_obj->gpu_addr; 426 427 memcpy(m, mqd_src, sizeof(*m)); 428 429 m->sdmax_rlcx_doorbell_offset = 430 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 431 432 *mqd = m; 433 if (gart_addr) 434 *gart_addr = addr; 435 436 qp->is_active = 0; 437 } 438 439 #if defined(CONFIG_DEBUG_FS) 440 441 static int debugfs_show_mqd(struct seq_file *m, void *data) 442 { 443 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 444 data, sizeof(struct v10_compute_mqd), false); 445 return 0; 446 } 447 448 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 449 { 450 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 451 data, sizeof(struct v10_sdma_mqd), false); 452 return 0; 453 } 454 455 #endif 456 457 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 458 struct kfd_node *dev) 459 { 460 struct mqd_manager *mqd; 461 462 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 463 return NULL; 464 465 mqd = kzalloc_obj(*mqd); 466 if (!mqd) 467 return NULL; 468 469 mqd->dev = dev; 470 471 switch (type) { 472 case KFD_MQD_TYPE_CP: 473 pr_debug("%s@%i\n", __func__, __LINE__); 474 mqd->allocate_mqd = allocate_mqd; 475 mqd->init_mqd = init_mqd; 476 mqd->free_mqd = kfd_free_mqd_cp; 477 mqd->load_mqd = load_mqd; 478 mqd->update_mqd = update_mqd; 479 mqd->destroy_mqd = kfd_destroy_mqd_cp; 480 mqd->is_occupied = kfd_is_occupied_cp; 481 mqd->mqd_size = sizeof(struct v10_compute_mqd); 482 mqd->get_wave_state = get_wave_state; 483 mqd->checkpoint_mqd = checkpoint_mqd; 484 mqd->restore_mqd = restore_mqd; 485 mqd->mqd_stride = kfd_mqd_stride; 486 #if defined(CONFIG_DEBUG_FS) 487 mqd->debugfs_show_mqd = debugfs_show_mqd; 488 #endif 489 pr_debug("%s@%i\n", __func__, __LINE__); 490 break; 491 case KFD_MQD_TYPE_HIQ: 492 pr_debug("%s@%i\n", __func__, __LINE__); 493 mqd->allocate_mqd = allocate_hiq_mqd; 494 mqd->init_mqd = init_mqd_hiq; 495 mqd->free_mqd = free_mqd_hiq_sdma; 496 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 497 mqd->update_mqd = update_mqd; 498 mqd->destroy_mqd = destroy_hiq_mqd; 499 mqd->is_occupied = kfd_is_occupied_cp; 500 mqd->mqd_size = sizeof(struct v10_compute_mqd); 501 mqd->mqd_stride = kfd_mqd_stride; 502 #if defined(CONFIG_DEBUG_FS) 503 mqd->debugfs_show_mqd = debugfs_show_mqd; 504 #endif 505 mqd->check_preemption_failed = check_preemption_failed; 506 pr_debug("%s@%i\n", __func__, __LINE__); 507 break; 508 case KFD_MQD_TYPE_DIQ: 509 mqd->allocate_mqd = allocate_mqd; 510 mqd->init_mqd = init_mqd_hiq; 511 mqd->free_mqd = kfd_free_mqd_cp; 512 mqd->load_mqd = load_mqd; 513 mqd->update_mqd = update_mqd; 514 mqd->destroy_mqd = kfd_destroy_mqd_cp; 515 mqd->is_occupied = kfd_is_occupied_cp; 516 mqd->mqd_size = sizeof(struct v10_compute_mqd); 517 #if defined(CONFIG_DEBUG_FS) 518 mqd->debugfs_show_mqd = debugfs_show_mqd; 519 #endif 520 break; 521 case KFD_MQD_TYPE_SDMA: 522 pr_debug("%s@%i\n", __func__, __LINE__); 523 mqd->allocate_mqd = allocate_sdma_mqd; 524 mqd->init_mqd = init_mqd_sdma; 525 mqd->free_mqd = free_mqd_hiq_sdma; 526 mqd->load_mqd = kfd_load_mqd_sdma; 527 mqd->update_mqd = update_mqd_sdma; 528 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 529 mqd->is_occupied = kfd_is_occupied_sdma; 530 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 531 mqd->restore_mqd = restore_mqd_sdma; 532 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 533 mqd->mqd_stride = kfd_mqd_stride; 534 #if defined(CONFIG_DEBUG_FS) 535 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 536 #endif 537 pr_debug("%s@%i\n", __func__, __LINE__); 538 break; 539 default: 540 kfree(mqd); 541 return NULL; 542 } 543 544 return mqd; 545 } 546