1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/printk.h> 25 #include <linux/slab.h> 26 #include <linux/mm_types.h> 27 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "cik_regs.h" 31 #include "cik_structs.h" 32 #include "oss/oss_2_4_sh_mask.h" 33 34 static inline struct cik_mqd *get_mqd(void *mqd) 35 { 36 return (struct cik_mqd *)mqd; 37 } 38 39 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 40 { 41 return (struct cik_sdma_rlc_registers *)mqd; 42 } 43 44 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 45 struct queue_properties *q) 46 { 47 struct cik_mqd *m; 48 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 49 50 if (q->cu_mask_count == 0) 51 return; 52 53 mqd_symmetrically_map_cu_mask(mm, 54 q->cu_mask, q->cu_mask_count, se_mask); 55 56 m = get_mqd(mqd); 57 m->compute_static_thread_mgmt_se0 = se_mask[0]; 58 m->compute_static_thread_mgmt_se1 = se_mask[1]; 59 m->compute_static_thread_mgmt_se2 = se_mask[2]; 60 m->compute_static_thread_mgmt_se3 = se_mask[3]; 61 62 pr_debug("Update cu mask to %#x %#x %#x %#x\n", 63 m->compute_static_thread_mgmt_se0, 64 m->compute_static_thread_mgmt_se1, 65 m->compute_static_thread_mgmt_se2, 66 m->compute_static_thread_mgmt_se3); 67 } 68 69 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd, 70 struct queue_properties *q) 71 { 72 struct kfd_mem_obj *mqd_mem_obj; 73 74 if (q->type == KFD_QUEUE_TYPE_HIQ) 75 return allocate_hiq_mqd(kfd); 76 77 if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd), 78 &mqd_mem_obj)) 79 return NULL; 80 81 return mqd_mem_obj; 82 } 83 84 85 static int init_mqd(struct mqd_manager *mm, void **mqd, 86 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 87 struct queue_properties *q) 88 { 89 uint64_t addr; 90 struct cik_mqd *m; 91 int retval; 92 struct kfd_dev *kfd = mm->dev; 93 94 *mqd_mem_obj = allocate_mqd(kfd, q); 95 if (!*mqd_mem_obj) 96 return -ENOMEM; 97 98 m = (struct cik_mqd *) (*mqd_mem_obj)->cpu_ptr; 99 addr = (*mqd_mem_obj)->gpu_addr; 100 101 memset(m, 0, ALIGN(sizeof(struct cik_mqd), 256)); 102 103 m->header = 0xC0310800; 104 m->compute_pipelinestat_enable = 1; 105 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 106 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 107 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 108 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 109 110 /* 111 * Make sure to use the last queue state saved on mqd when the cp 112 * reassigns the queue, so when queue is switched on/off (e.g over 113 * subscription or quantum timeout) the context will be consistent 114 */ 115 m->cp_hqd_persistent_state = 116 DEFAULT_CP_HQD_PERSISTENT_STATE | PRELOAD_REQ; 117 118 m->cp_mqd_control = MQD_CONTROL_PRIV_STATE_EN; 119 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 120 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 121 122 m->cp_hqd_quantum = QUANTUM_EN | QUANTUM_SCALE_1MS | 123 QUANTUM_DURATION(10); 124 125 /* 126 * Pipe Priority 127 * Identifies the pipe relative priority when this queue is connected 128 * to the pipeline. The pipe priority is against the GFX pipe and HP3D. 129 * In KFD we are using a fixed pipe priority set to CS_MEDIUM. 130 * 0 = CS_LOW (typically below GFX) 131 * 1 = CS_MEDIUM (typically between HP3D and GFX 132 * 2 = CS_HIGH (typically above HP3D) 133 */ 134 m->cp_hqd_pipe_priority = 1; 135 m->cp_hqd_queue_priority = 15; 136 137 if (q->format == KFD_QUEUE_FORMAT_AQL) 138 m->cp_hqd_iq_rptr = AQL_ENABLE; 139 140 *mqd = m; 141 if (gart_addr) 142 *gart_addr = addr; 143 retval = mm->update_mqd(mm, m, q); 144 145 return retval; 146 } 147 148 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd, 149 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 150 struct queue_properties *q) 151 { 152 int retval; 153 struct cik_sdma_rlc_registers *m; 154 struct kfd_dev *dev = mm->dev; 155 156 *mqd_mem_obj = allocate_sdma_mqd(dev, q); 157 if (!*mqd_mem_obj) 158 return -ENOMEM; 159 160 m = (struct cik_sdma_rlc_registers *) (*mqd_mem_obj)->cpu_ptr; 161 162 memset(m, 0, sizeof(struct cik_sdma_rlc_registers)); 163 164 *mqd = m; 165 if (gart_addr) 166 *gart_addr = (*mqd_mem_obj)->gpu_addr; 167 168 retval = mm->update_mqd(mm, m, q); 169 170 return retval; 171 } 172 173 static void uninit_mqd(struct mqd_manager *mm, void *mqd, 174 struct kfd_mem_obj *mqd_mem_obj) 175 { 176 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 177 } 178 179 180 static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, 181 uint32_t queue_id, struct queue_properties *p, 182 struct mm_struct *mms) 183 { 184 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 185 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 186 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1); 187 188 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id, 189 (uint32_t __user *)p->write_ptr, 190 wptr_shift, wptr_mask, mms); 191 } 192 193 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd, 194 uint32_t pipe_id, uint32_t queue_id, 195 struct queue_properties *p, struct mm_struct *mms) 196 { 197 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd, 198 (uint32_t __user *)p->write_ptr, 199 mms); 200 } 201 202 static int __update_mqd(struct mqd_manager *mm, void *mqd, 203 struct queue_properties *q, unsigned int atc_bit) 204 { 205 struct cik_mqd *m; 206 207 m = get_mqd(mqd); 208 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 209 DEFAULT_MIN_AVAIL_SIZE; 210 m->cp_hqd_ib_control = DEFAULT_MIN_IB_AVAIL_SIZE; 211 if (atc_bit) { 212 m->cp_hqd_pq_control |= PQ_ATC_EN; 213 m->cp_hqd_ib_control |= IB_ATC_EN; 214 } 215 216 /* 217 * Calculating queue size which is log base 2 of actual queue size -1 218 * dwords and another -1 for ffs 219 */ 220 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 221 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 222 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 223 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 224 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 225 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 226 227 m->cp_hqd_vmid = q->vmid; 228 229 if (q->format == KFD_QUEUE_FORMAT_AQL) 230 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; 231 232 update_cu_mask(mm, mqd, q); 233 234 q->is_active = (q->queue_size > 0 && 235 q->queue_address != 0 && 236 q->queue_percent > 0 && 237 !q->is_evicted); 238 239 return 0; 240 } 241 242 static int update_mqd(struct mqd_manager *mm, void *mqd, 243 struct queue_properties *q) 244 { 245 return __update_mqd(mm, mqd, q, 1); 246 } 247 248 static int update_mqd_hawaii(struct mqd_manager *mm, void *mqd, 249 struct queue_properties *q) 250 { 251 return __update_mqd(mm, mqd, q, 0); 252 } 253 254 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, 255 struct queue_properties *q) 256 { 257 struct cik_sdma_rlc_registers *m; 258 259 m = get_sdma_mqd(mqd); 260 m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4) 261 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 262 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 263 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 264 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 265 266 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); 267 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); 268 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 269 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 270 m->sdma_rlc_doorbell = 271 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT; 272 273 m->sdma_rlc_virtual_addr = q->sdma_vm_addr; 274 275 m->sdma_engine_id = q->sdma_engine_id; 276 m->sdma_queue_id = q->sdma_queue_id; 277 278 q->is_active = (q->queue_size > 0 && 279 q->queue_address != 0 && 280 q->queue_percent > 0 && 281 !q->is_evicted); 282 283 return 0; 284 } 285 286 static int destroy_mqd(struct mqd_manager *mm, void *mqd, 287 enum kfd_preempt_type type, 288 unsigned int timeout, uint32_t pipe_id, 289 uint32_t queue_id) 290 { 291 return mm->dev->kfd2kgd->hqd_destroy(mm->dev->kgd, mqd, type, timeout, 292 pipe_id, queue_id); 293 } 294 295 /* 296 * preempt type here is ignored because there is only one way 297 * to preempt sdma queue 298 */ 299 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 300 enum kfd_preempt_type type, 301 unsigned int timeout, uint32_t pipe_id, 302 uint32_t queue_id) 303 { 304 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout); 305 } 306 307 static bool is_occupied(struct mqd_manager *mm, void *mqd, 308 uint64_t queue_address, uint32_t pipe_id, 309 uint32_t queue_id) 310 { 311 312 return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->kgd, queue_address, 313 pipe_id, queue_id); 314 315 } 316 317 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd, 318 uint64_t queue_address, uint32_t pipe_id, 319 uint32_t queue_id) 320 { 321 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd); 322 } 323 324 /* 325 * HIQ MQD Implementation, concrete implementation for HIQ MQD implementation. 326 * The HIQ queue in Kaveri is using the same MQD structure as all the user mode 327 * queues but with different initial values. 328 */ 329 330 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd, 331 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr, 332 struct queue_properties *q) 333 { 334 return init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 335 } 336 337 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, 338 struct queue_properties *q) 339 { 340 struct cik_mqd *m; 341 342 m = get_mqd(mqd); 343 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | 344 DEFAULT_MIN_AVAIL_SIZE | 345 PRIV_STATE | 346 KMD_QUEUE; 347 348 /* 349 * Calculating queue size which is log base 2 of actual queue 350 * size -1 dwords 351 */ 352 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 353 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 354 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 355 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 356 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 357 m->cp_hqd_pq_doorbell_control = DOORBELL_OFFSET(q->doorbell_off); 358 359 m->cp_hqd_vmid = q->vmid; 360 361 q->is_active = (q->queue_size > 0 && 362 q->queue_address != 0 && 363 q->queue_percent > 0 && 364 !q->is_evicted); 365 366 return 0; 367 } 368 369 #if defined(CONFIG_DEBUG_FS) 370 371 static int debugfs_show_mqd(struct seq_file *m, void *data) 372 { 373 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 374 data, sizeof(struct cik_mqd), false); 375 return 0; 376 } 377 378 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 379 { 380 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 381 data, sizeof(struct cik_sdma_rlc_registers), false); 382 return 0; 383 } 384 385 #endif 386 387 388 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, 389 struct kfd_dev *dev) 390 { 391 struct mqd_manager *mqd; 392 393 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 394 return NULL; 395 396 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 397 if (!mqd) 398 return NULL; 399 400 mqd->dev = dev; 401 402 switch (type) { 403 case KFD_MQD_TYPE_CP: 404 case KFD_MQD_TYPE_COMPUTE: 405 mqd->init_mqd = init_mqd; 406 mqd->uninit_mqd = uninit_mqd; 407 mqd->load_mqd = load_mqd; 408 mqd->update_mqd = update_mqd; 409 mqd->destroy_mqd = destroy_mqd; 410 mqd->is_occupied = is_occupied; 411 mqd->mqd_size = sizeof(struct cik_mqd); 412 #if defined(CONFIG_DEBUG_FS) 413 mqd->debugfs_show_mqd = debugfs_show_mqd; 414 #endif 415 break; 416 case KFD_MQD_TYPE_HIQ: 417 mqd->init_mqd = init_mqd_hiq; 418 mqd->uninit_mqd = uninit_mqd_hiq_sdma; 419 mqd->load_mqd = load_mqd; 420 mqd->update_mqd = update_mqd_hiq; 421 mqd->destroy_mqd = destroy_mqd; 422 mqd->is_occupied = is_occupied; 423 mqd->mqd_size = sizeof(struct cik_mqd); 424 #if defined(CONFIG_DEBUG_FS) 425 mqd->debugfs_show_mqd = debugfs_show_mqd; 426 #endif 427 break; 428 case KFD_MQD_TYPE_DIQ: 429 mqd->init_mqd = init_mqd_hiq; 430 mqd->uninit_mqd = uninit_mqd; 431 mqd->load_mqd = load_mqd; 432 mqd->update_mqd = update_mqd_hiq; 433 mqd->destroy_mqd = destroy_mqd; 434 mqd->is_occupied = is_occupied; 435 mqd->mqd_size = sizeof(struct cik_mqd); 436 #if defined(CONFIG_DEBUG_FS) 437 mqd->debugfs_show_mqd = debugfs_show_mqd; 438 #endif 439 break; 440 case KFD_MQD_TYPE_SDMA: 441 mqd->init_mqd = init_mqd_sdma; 442 mqd->uninit_mqd = uninit_mqd_hiq_sdma; 443 mqd->load_mqd = load_mqd_sdma; 444 mqd->update_mqd = update_mqd_sdma; 445 mqd->destroy_mqd = destroy_mqd_sdma; 446 mqd->is_occupied = is_occupied_sdma; 447 mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); 448 #if defined(CONFIG_DEBUG_FS) 449 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 450 #endif 451 break; 452 default: 453 kfree(mqd); 454 return NULL; 455 } 456 457 return mqd; 458 } 459 460 struct mqd_manager *mqd_manager_init_cik_hawaii(enum KFD_MQD_TYPE type, 461 struct kfd_dev *dev) 462 { 463 struct mqd_manager *mqd; 464 465 mqd = mqd_manager_init_cik(type, dev); 466 if (!mqd) 467 return NULL; 468 if ((type == KFD_MQD_TYPE_CP) || (type == KFD_MQD_TYPE_COMPUTE)) 469 mqd->update_mqd = update_mqd_hawaii; 470 return mqd; 471 } 472